JP2009216676A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for performing a stress-applied test according to the voltage boosted in stress mode. <P>SOLUTION: In a stress voltage generation circuit 100, when the power source voltage Vcc is boosted into stress mode, a transistor Qn1 comes into ON state. Therefore, current flows in a transistor Qp1, and current of the same magnitude flows also in transistors Qp3-Qp5 constituting a current mirror circuit 400. As a result, a ring oscillator 500 constituted by three inverters INV3-INB5 oscillates and outputs a clock pulse CKP. The clock pulse CKP is applied to a gate terminal of a transistor to which the voltage of the intermediate level between power source voltage Vcc and ground voltage GND is applied in normal mode, thereby performing the stress-applied test. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a stress application mode.

  Conventionally, it is known that even a semiconductor device that has been determined to be a non-defective product in a test immediately after manufacture is present in a proportion that becomes defective due to short-term use. FIG. 8 is a diagram showing the change over time of the defect rate of the semiconductor device. As can be seen from FIG. 8, the defect rate of the semiconductor device is high at the beginning of use, but rapidly decreases in a short period to become a substantially constant value, and then gradually increases due to deterioration over time. A defect until the defect rate decreases from a high value to a constant value is called an initial defect.

  The initial failure is caused by a current flowing or a voltage being applied over a predetermined time to an electrically unstable part such as a wiring pattern constriction or a defect in a gate oxide film produced during the manufacture of a semiconductor device. This is a failure caused by an unstable portion being electrically destroyed. For this reason, it is necessary to find and exclude a semiconductor device having an electrically unstable portion before shipping as a product.

  A semiconductor device that causes such an initial failure is applied with a voltage (voltage stress) higher than the original operating voltage in the thermostatic chamber kept at a high temperature, or a current ( This is determined by a stress application test (burn-in test) in which a current stress is applied. Conditions such as an operating voltage, an operating current, an operating temperature, and an input time used for the stress application test are optimized in consideration of a semiconductor device manufacturing process, a package, and the like.

  FIG. 9A is a circuit diagram illustrating a logic circuit as an example of a logic circuit, and FIG. 9B is a circuit diagram illustrating the logic gate of FIG. 9A at a transistor level. As can be seen from FIGS. 9A and 9B, this logic circuit is a circuit combining a NAND circuit and a NOR circuit. The voltages Vin1 to Vin3 applied to the gate terminals of the transistors are either power supply voltages or ground voltages. For this reason, if the power supply voltage is set higher than that in the normal operation (normal mode), a voltage higher than the voltage in the normal mode can be applied to the gate terminal of the transistor (stress mode). Therefore, by performing a stress application test, it is possible to preliminarily select a semiconductor device that is initially defective with high accuracy.

Patent Document 1 discloses that a state that a gate circuit and a flip-flop circuit can take is reproduced by repeatedly applying and interrupting a voltage, and a burn-in test is performed for each reproduced state. Has been. Patent Document 2 discloses that a burn-in test is performed by applying stress so that a level shifter circuit, a reference voltage generation circuit, and the like are activated in a stress mode.
JP-A-5-60829 JP-A-6-21376

  However, there is a circuit including a transistor in which only a voltage between the power supply voltage and the ground voltage (hereinafter referred to as an intermediate voltage) is applied to the gate terminal in the normal mode. For example, FIG. 10 is a circuit diagram of a conventional differential amplifier circuit. As shown in FIG. 10, this differential amplifier circuit is a circuit that adjusts the output current Iout21 output from the output terminal according to the magnitude relationship between the input voltages Vin21 and Vin22 applied to the two input terminals, respectively. In the normal mode, N-channel transistors Qn21 to Qn28 included in this differential amplifier circuit adjust the output current by applying an intermediate voltage to their gate terminals. However, even if the power supply voltage is increased to perform the stress application test, the increased power supply voltage cannot be applied to the gate terminals of the transistors Qn21 to Qn28. For this reason, there is a problem that a semiconductor device that becomes an initial failure by the stress application test cannot be selected in advance with high accuracy.

  FIG. 11 is a circuit diagram of another conventional differential amplifier. Similarly to the differential amplifier circuit of FIG. 10, this differential amplifier circuit cannot apply the increased power supply voltage to the gate terminals of the N-channel transistors Qn32 and Qn33 even if the power supply voltage is increased. . For this reason, this differential amplifier circuit also has a problem that it is impossible to select in advance with high accuracy a semiconductor device that is initially defective in a stress application test.

  Further, the invention described in Patent Document 1 has a problem that the stress application test becomes complicated and takes time because the voltage must be repeatedly applied and interrupted. In the invention described in Patent Document 2, since it is necessary to generate a stress mode signal for switching between the normal mode and the stress mode, there is a problem that the mode switching becomes complicated.

  Therefore, an object of the present invention is to provide a semiconductor device capable of performing a stress application test according to a boosted voltage in a stress mode.

A first invention is a semiconductor device having a function of switching an operation mode of a circuit under test between a normal mode and a stress mode.
Mode selection means for selecting either a normal mode or a stress mode based on a power supply voltage supplied from the outside;
When a stress mode is selected by the mode selection means, a voltage stress signal based on the power supply voltage is generated, and when the stress test target circuit is operating in a normal mode, the power supply voltage is grounded. And a signal output means for applying the voltage stress signal to a transistor to which the intermediate voltage is applied.

According to a second invention, in the first invention,
The signal output means includes an oscillating means for generating an AC voltage signal when a stress mode is selected by the mode selection means, and outputs the AC voltage signal as the voltage stress signal.

According to a third invention, in the second invention,
The mode selection means includes
A first resistance divider circuit for dividing the power supply voltage by resistance to output a first divided voltage;
Including a first switching element that selects one of a normal mode and a stress mode based on the first divided voltage;
The signal output means further includes predetermined voltage generation means for generating a predetermined voltage when a stress mode is selected by the first switching element,
The oscillating means generates the AC voltage signal based on the predetermined voltage.

According to a fourth invention, in the third invention,
The predetermined voltage generating means includes a current mirror circuit having an odd number of output terminals for outputting a current of the same magnitude,
The oscillating means includes cascaded inverters each having a high level side terminal connected to the output terminal of the current mirror circuit, and a voltage caused by a current output from the current mirror circuit is connected to the high level side of the inverter. And a ring oscillator that generates the AC voltage signal by being applied to the terminal of the circuit.

A fifth invention is the fourth invention,
The number of inverters connected in cascade is adjusted such that the amplitude of the AC voltage signal is the same level as the amplitude of the power supply voltage.

According to a sixth invention, in the fourth invention,
The semiconductor device further includes a voltage switching circuit that switches and outputs a voltage applied to the transistor between the AC voltage signal output from the ring oscillator and an operating voltage signal output in a normal mode,
The voltage switching circuit is
A second resistance divider circuit for dividing the power supply voltage by resistance and outputting a second divided voltage;
A second switching element for providing the AC voltage signal to the transistor when turned on based on the second divided voltage;
And a third switching element that is turned on based on the second divided voltage when the second switching element is in the off state and supplies the operating voltage signal to the transistor.

According to a seventh invention, in the fourth invention,
The mode selection means further includes pull-up means for deactivating the current mirror circuit when the normal mode is selected.

In an eighth aspect based on the first aspect,
The stress test target circuit is an analog circuit.

  According to a ninth invention, in the eighth invention, the transistor is a MOS transistor, and the mode selection means applies the voltage stress signal to a gate terminal of the MOS transistor.

In a tenth aspect based on the first aspect,
The mode selection means and the signal output means are formed on the same substrate as the substrate on which the stress test target circuit is formed.

In an eleventh aspect based on the first aspect,
The stress test target circuit is:
A resistance element formed in a path to be applied with current stress in the stress mode;
A third resistance divider circuit for dividing the power supply voltage by resistance and outputting a third divided voltage;
A third switching element connected in parallel to the resistance element;
The third switching element short-circuits both ends of the resistance element when turned on.

  According to the first aspect, when the stress mode is selected, the voltage stress signal generated based on the power supply voltage can be applied to the transistor of the stress test target circuit. In this case, if the power supply voltage is boosted, the amplitude of the voltage stress signal also increases, so that a sufficiently strong voltage stress can be applied to the transistor to which the intermediate voltage is applied in the normal mode. For this reason, the semiconductor device which becomes an initial failure can be selected in advance with high accuracy.

  According to the second invention, since the voltage stress signal is an AC voltage signal, the voltage changes with time. For this reason, a sufficient voltage stress can be applied by applying an AC voltage signal to the transistor of the stress test target circuit.

  According to the third invention, when the power supply voltage is supplied to the first resistance divider circuit, the first switching element selects either the normal mode or the stress mode according to the supplied power supply voltage. As a result, when the stress mode is selected, an AC voltage signal is generated based on the generated predetermined voltage. Therefore, the semiconductor device can automatically apply voltage stress due to the AC voltage signal to the transistor of the stress test target circuit when it is determined that the semiconductor device is in the stress mode from the magnitude of the power supply voltage.

  According to the fourth aspect of the present invention, when the boosted power supply voltage is applied, the same amount of charge is accumulated in the odd number of parasitic capacitors by the same amount of current output from the current mirror circuit. Is applied to the high level terminal of each of the odd number of inverters of the ring oscillator. For this reason, the ring oscillator oscillates and can output an AC voltage signal. Further, the frequency of the AC voltage signal can be controlled by controlling the current output from the current mirror circuit.

  According to the fifth aspect, the frequency of the AC voltage signal can be controlled so that the amplitude of the AC voltage signal becomes equal to the amplitude of the boosted power supply voltage by adjusting the number of inverters. For this reason, even if the waveform of the AC voltage signal is dull due to the parasitic capacitance of the current mirror circuit, a sufficiently strong voltage stress can be applied to the transistor of the stress test target circuit.

  According to the sixth invention, the voltage switching circuit is provided in each transistor of the stress test target circuit. This voltage switching circuit is automatically switched so as to give an AC voltage signal to the transistor in the stress mode and an operating voltage signal to the transistor in the normal mode according to the applied power supply voltage.

  According to the seventh invention, the pull-up means deactivates the current mirror circuit when the normal mode is selected. In this case, the operation of the current mirror circuit in the normal mode can be stabilized.

  According to the eighth invention, a sufficiently strong voltage stress can be applied to the transistor of the analog circuit to which the intermediate voltage is applied, so that the semiconductor device including the initial defective analog circuit is removed in advance with high accuracy. be able to.

  According to the ninth aspect of the invention, by applying voltage stress to the gate terminal of the MOS transistor of the stress test target circuit, the semiconductor device including a defect that becomes an initial failure in the gate oxide film is removed in advance with high accuracy. Can do.

  According to the tenth aspect, since the mode selection unit and the signal generation unit are formed on the same substrate as the substrate on which the stress test target circuit is formed, an external circuit is not required when performing the stress application test. For example, the stress application test of the semiconductor device can be easily performed.

  According to the eleventh aspect of the invention, when the boosted power supply voltage is applied, the third switching element connected in parallel to the resistance element of the path to which current stress is applied is turned on, and both ends of the resistance element Short circuit. In this case, since a large current flows through a circuit to which current stress is to be applied, a semiconductor device that is initially defective due to electromigration or the like can be selected in advance with high accuracy. The third switching element is automatically switched according to the magnitude of the applied power supply voltage.

<Stress voltage generation circuit>
FIG. 1 is a circuit diagram of a stress voltage generation circuit 100 included in a semiconductor device according to an embodiment of the present invention. As shown in FIG. 1, the stress voltage generation circuit 100 includes a mode switching circuit 200, a pull-up circuit 300, a current mirror circuit 400, and a ring oscillator 500.

  Mode switching circuit 200 includes three resistance elements R1 to R3 and one N-channel transistor Qn1. A power supply voltage Vcc is applied to one end of the resistance element R1, and the other end is connected to one end of the resistance element R2. This connection point is called node NA. The other end of the resistance element R2 is grounded, and the gate terminal of the transistor Qn1 is connected to the node NA. The source terminal of the transistor Qn1 is grounded via the resistance element R3, and the drain terminal is connected to the drain terminal of a P-channel transistor Qp1 described later.

  The pull-up circuit 300 includes one P-channel transistor Qp2 and two inverters INV1 and INV2. The source terminal of the transistor Qp2 is supplied with the power supply voltage Vcc, and the drain terminal is connected to the gate terminal of a transistor Qp1 described later. This connection point is referred to as a node NB. The gate terminal of the transistor Qp2 is connected to the node NA via two cascaded inverters INV1 and INV2. The transistor Qp2 has a function of pulling up the voltage of the node NB to the power supply voltage Vcc, as will be described later.

  In the inverter INV1, the drain terminal of the N-channel transistor is connected to one end of the resistance element, and the power supply voltage Vcc is applied to the other end of the resistance element. The source terminal of the N-channel transistor is grounded and the gate terminal is connected to the node NA. The inverter INV2 is a CMOS (complementary MOS) type inverter composed of a P-channel transistor and an N-channel transistor. A power supply voltage Vcc is applied to the source terminal of the P-channel transistor, and the drain terminal is connected to the drain terminal of the N-channel transistor. The source terminal of the N-channel transistor is grounded, and the gate terminals of the N-channel transistor and the P-channel transistor are connected to the connection point between the resistor element of the previous inverter INV1 and the drain terminal of the N-channel transistor.

  Three P-channel transistors Qp3 to Qp5 are connected in parallel to each other, and form a current mirror circuit 400 together with the transistor Qp1. The transistor Qp1 has a power supply voltage Vcc applied to its source terminal, a drain terminal connected to the drain terminal of the transistor Qn1, and a gate terminal and a drain terminal connected to the node NB. The power supply voltage Vcc is applied to the source terminals of the transistors Qp3 to Qp5, and the drain terminals are connected to the high-level terminals (source terminals of the P-channel transistors) of the three inverters INV3 to INV5, respectively. All gate terminals are connected to the node NB.

  The three inverters INV <b> 3 to INV <b> 5 are CMOS type inverters, which are connected in cascade to form a ring oscillator 500. In each inverter INV3 to INV5, the source terminal of the P-channel transistor is connected to the drain terminal of the transistors Qp3 to Qp5, the drain terminal is connected to the drain terminal of the N-channel transistor, and the source terminal of the N-channel transistor is Grounded. Also, the drain terminal of the P-channel transistor and the drain terminal of the N-channel transistor are connected to become an output terminal, and the gate terminal of the P-channel transistor and the gate terminal of the N-channel transistor of the next stage inverter are connected. Connected to the input terminal. Therefore, the output terminal of the inverter INV5 is connected to the input terminal of the inverter INV4, the output terminal of the inverter INV4 is connected to the input terminal of the inverter INV3, and the output terminal of the inverter INV3 is connected to the input terminal of the inverter INV5. It is connected to a target circuit (hereinafter referred to as “stress test target circuit”).

Next, the operation of the stress voltage generation circuit 100 will be described. The voltage at the node NA is a voltage obtained by resistance-dividing the power supply voltage Vcc by the resistance element R1 and the resistance element R2. That is, when the resistance value of the resistance element R1 is R1, and the resistance value of the resistance element R2 is R2, the voltage at the node NA is expressed by the following equation (1).
V = Vcc * R2 / (R1 + R2) (1)

  In the following description, the power supply voltage in the normal mode is assumed to be 5V, and the power supply voltage in the stress mode is assumed to be 10V. However, this voltage is an example and is not limited thereto. The voltage at the node NA obtained by resistance division is such that the gate-source voltage Vgs of the transistor Qn1 is smaller than the threshold voltage Vth (for example, 0.7 V) in the normal mode and larger than the threshold voltage Vth in the stress mode. Is set.

  First, the case where the stress voltage generation circuit 100 is operated in the normal mode will be described. The voltage at the node NA is applied to the gate terminal of the transistor Qn1. As a result, since the gate-source voltage Vgs of the transistor Qn1 is smaller than the threshold voltage Vthn1, the transistor Qn1 is turned off.

  The voltage at the node NA is also applied to the input terminal of the inverter INV1. In the normal mode, since the gate-source voltage of the N-channel transistor of the inverter INV1 is set to be lower than the threshold voltage, the N-channel transistor is turned off. Therefore, the potential at the connection point between the resistance element and the N-channel transistor becomes the power supply voltage Vcc.

  The inverter INV2 is set so as to be determined as a high level when a power supply voltage Vcc is applied and as a low level when a voltage lower than a power supply voltage Vcc described later is applied. Therefore, in the normal mode, the inverter INV2 outputs a low level voltage based on the input high level voltage.

  When a low level voltage is applied to the gate terminal of the transistor Qp2, the transistor Qp2 is turned on to pull up the voltage at the node NB to the power supply voltage Vcc (high level). As a result, since a high level voltage is applied to the gate terminals of the transistors Qp1, Qp3 to Qp5, the transistor transistors Qp1, Qp3 to Qp5 are turned off and no current flows. For this reason, the ring oscillator 500 does not operate.

  Next, the case where the stress voltage generation circuit 100 is operated in the stress mode will be described. When the power supply voltage Vcc is boosted to 10 V, the voltage at the node NA also increases, and the gate-source voltage Vgs of the transistor Qn1 becomes higher than the threshold voltage Vthn1 as described above. As a result, the transistor Qn1 is turned on, and the ground voltage GND is applied to the drain terminal of the transistor Qp1. The ground voltage GND is also applied to the node NB connected to the drain terminal and the gate terminal of the transistor Qp1.

  On the other hand, the power supply voltage Vcc is applied to the source terminal of the transistor Qp1. Therefore, the gate-source voltage Vgs of the transistor Qp1 is higher than the threshold voltage Vthp1, and the transistor Qp1 is turned on. Therefore, a current flows from the power supply terminal to the ground terminal via transistor Qp1, transistor Qn1, and resistance element R3.

  At this time, the voltage at the node NA is also applied to the input terminal of the inverter INV1. In the stress mode, since the gate-source voltage of the N-channel transistor of the inverter INV1 is set to be higher than the threshold voltage, the N-channel transistor is turned on, and the resistance element and the N-channel transistor are connected from the power supply terminal. A current flows through the transistor to the ground terminal. At this time, a voltage applied to the ON resistance of the N-channel transistor is output to the inverter INV2. As described above, the inverter INV2 is set so that the voltage applied to the on-resistance at this time is determined to be a low level, and therefore outputs a high-level voltage. Accordingly, since a high level voltage is applied to the gate terminal of the transistor Qp2, the transistor Qp2 is turned off.

  Since the voltage at the node NB is simultaneously applied to the gate terminals of the transistors Qp3 to Qp5, the transistors Qp3 to Qp5 are turned on. Further, since the four transistors Qp1, Qp3 to Qp5 form a current mirror circuit, the same current flows in each of the transistors Qp1, Qp3 to Qp5. At this time, the parasitic capacitance C formed in the wiring on the drain terminal side of the transistors Qp3 to Qp5 is charged by the current flowing through the transistors Qp3 to Qp5 until the voltage becomes equal to the power supply voltage Vcc. The charged parasitic capacitance C applies the power supply voltage Vcc to the high level side terminals of the inverters INV3 to INV5.

  The ring oscillator 500 includes three inverters INV3 to INV5 connected in a loop. For example, if the inverter INV5 outputs a high level voltage, the inverter INV4 outputs a low level voltage, and the inverter INV3 is high. Output level voltage. The high level voltage output from the inverter INV3 is given to the stress test target circuit and also fed back to the input terminal of the inverter INV5. The inverters INV3 to INV5 repeat the above-described operation in order, so that the inverter INV3 outputs a low level voltage unlike the previous time. Therefore, the voltage applied to the stress test target circuit is at a low level. Similarly, the ring oscillator 500 generates a clock pulse CKP that alternately repeats a high level voltage and a low level voltage, and outputs the clock pulse CKP to the stress test target circuit.

  In this way, if the three inverters INV3 to INV5 are cascaded in a loop, a clock pulse CKP having a frequency determined based on the delay time of the inverters INV3 to INV5 is generated and output. Although three inverters are used in the ring oscillator 500 of the present embodiment, more inverters may be used as long as it is an odd number. In this case, if the number of inverters included in the ring oscillator 500 is increased, the delay time is increased by the increased number, and accordingly, the frequency of the clock pulse CKP is decreased.

  2A is a waveform diagram of the clock pulse CKP generated by the stress voltage generation circuit 100, and FIG. 2B is a waveform diagram when the frequency of the clock pulse CKP in FIG. 2A is increased. FIG. 2C is an enlarged waveform of a clock pulse showing a problem when the frequency is increased. When the frequency of the clock pulse CKP output from the stress voltage generation circuit 100 is increased as shown in FIGS. 2A to 2B, the voltage applied to the gate terminal of the transistor included in the stress test target circuit is increased. Since the number of times of change increases, a strong stress can be applied to the transistor of the stress test target circuit.

  However, in practice, as shown in FIG. 2C, when the frequency is increased, the waveform of the clock pulse CKP does not become an ideal rectangle because of the parasitic capacitance C, so the voltage of the clock pulse CKP is applied. It takes time to reach the set power supply voltage Vcc. Therefore, the voltage of the clock pulse CKP begins to drop before reaching the applied power supply voltage Vcc. Thus, if the frequency of the clock pulse CKP is too high, there arises a problem that sufficient stress cannot be applied. Therefore, the clock pulse CKP needs to be generated so that the amplitude thereof is the same as that of the power supply voltage Vcc and the frequency is the highest. Such a clock pulse CKP is generated by adjusting the number of inverters included in the ring oscillator 500.

  In addition, since the current mirror circuit 400 can control the current flowing through the transistors Qp3 to Qp5, this can be used to limit the frequency of the AC voltage generated by the ring oscillator 500.

<Voltage switching circuit>
3A is a functional diagram of the voltage switching circuit 600 for switching between the normal mode and the stress mode, and FIG. 3B is a circuit diagram showing a specific circuit of the voltage switching circuit 600 of FIG. 3A. It is. The voltage switching circuit 600 is provided between the output terminal of the stress voltage generation circuit 100 and the gate terminal of each transistor included in the stress test target circuit. In the stress mode, the voltage switching circuit 600 applies the boosted power supply voltage Vcc to the gate terminal of the transistor to which the intermediate voltage has been applied in the normal mode.

  With reference to FIG. 3B, the structure of the voltage switching circuit 600 will be described. The power supply voltage Vcc is applied to one end of the resistance element Ra1, and the other end is grounded through the resistance element Ra2. A connection point (hereinafter referred to as a node NC) between the resistance element Ra1 and the resistance element Ra2 is connected to a gate terminal of the N-channel transistor Qna1 and an input terminal of the inverter INVa. The drain terminal of the transistor Qna1 is connected to the output terminal of the inverter INV3 of the stress voltage generation circuit 100 via the terminal S2, and the source terminal is connected to the gate terminal of the transistor performing the stress application test.

  On the other hand, the output terminal of the inverter INVa is connected to the gate terminal of the N-channel transistor Qna2, and the drain terminal of the transistor Qna2 is connected to a terminal S1 that outputs an intermediate voltage that should be originally applied to the gate terminal of the transistor performing the stress application test. The source terminal is connected to the source terminal of the transistor Qna1. The inverter INVa is set so that the voltage at the node NC in the normal mode is at a low level and the voltage at the node NC in the stress mode is at a high level. The voltage at the node NC obtained by resistance division is set so that the gate-source voltage Vgs of the transistor Qna1 is smaller than the threshold voltage Vtha1 in the normal mode and larger than the threshold voltage Vtha1 in the stress mode. ing.

  Next, the operation of the voltage switching circuit 600 will be described. In the normal mode, since the gate-source voltage Vgs of the transistor Qna1 is smaller than the threshold voltage Vtha1, the transistor Qna1 is turned off. On the other hand, the inverter INVa outputs a high level voltage, and the output high level voltage is applied to the gate terminal of the transistor Qna2. For this reason, the transistor Qna2 is turned on. Therefore, in the normal mode, the intermediate voltage that should be applied from the terminal S1 is applied to the gate terminal of the transistor included in the stress test target circuit.

  On the other hand, in the stress mode, since the power supply voltage is boosted to 10 V, the voltage at the node NC determined by the resistance division becomes high. Therefore, the gate-source voltage Vgs of the transistor Qna1 becomes higher than the threshold voltage Vtha1, and the transistor Qna1 is turned on. On the other hand, the inverter INVa outputs a low level voltage, and the output low level voltage is applied to the gate terminal of the transistor Qna2. For this reason, the transistor Qna2 is turned off. Therefore, the clock pulse CKP output from the stress voltage generation circuit 100 is applied to the gate terminal of the transistor performing the stress application test.

<Current switching circuit>
If current stress is applied to the stress test target circuit, the current density flowing through the wiring increases, and a phenomenon (electromigration) occurs in which metal atoms constituting the wiring move. Electromigration causes an initial failure such that the constriction of the portion where the wiring is constricted becomes large and breaks, or the portion which is in partial contact in the through hole is disconnected and a contact failure occurs.

  4A is a functional diagram of the current switching circuit 700 for switching between the normal mode and the stress mode, and FIG. 4B is a circuit diagram showing a specific circuit of the current switching circuit 700 in FIG. 4A. It is. The current switching circuit 700 is provided so as to be connected in parallel with a resistance element included in a path where current stress is to be applied by a large current. With reference to FIG. 4B, the structure of the current switching circuit 700 will be described. The power supply voltage Vcc is applied to one end of the resistance element Rb1, and the other end is grounded via the resistance element Rb2. A connection point (hereinafter referred to as a node ND) between the resistance element Rb1 and the resistance element Rb2 is connected to the gate terminal of the P-channel transistor Qpb via the inverter INVb. The source terminal of the transistor Qpb is connected to one end of the resistance element Rb3, and the drain terminal is connected to the other end of the resistance element Rb3. Note that INVb is set so that the voltage at the node ND in the normal mode is at a low level and the voltage at the node NC in the stress mode is at a high level.

  Next, the operation of the current switching circuit 700 will be described. When the voltage at the node ND is applied to the input terminal of the inverter INVb in the normal mode, the inverter INVb outputs a high level voltage. The output high level voltage is applied to the gate terminal of the transistor Qpb. For this reason, the transistor Qpb is turned off. Therefore, since the current flowing between the power supply terminal and the ground terminal is determined by the resistance element Rb3, a large current does not flow. For this reason, current stress cannot be applied to the path through which the current flows.

  On the other hand, when the voltage at the node ND is applied to the input terminal of the inverter INVb in the stress mode, the inverter INVb outputs a low level voltage. The output low level voltage is applied to the gate terminal of the transistor Qpb. Therefore, contrary to the normal mode, the transistor Qpb is turned on and the resistance element Rb3 is short-circuited. Therefore, since a large current flows between the power supply terminal and the ground terminal, current stress can be applied to the path through which the current flows.

<Application to differential amplifier circuit>
FIG. 5 is a circuit diagram in the case where voltage switching circuits 611 to 617 and current switching circuits 711 and 712 are provided in the differential amplifier circuit shown in FIG. As shown in FIG. 5, voltage switching circuits 611 to 617 are respectively provided to apply the boosted power supply voltage Vcc to all the gate terminals of transistors Qn21 to Qn28 and Qp21 to Qp25 to which the intermediate voltage is applied. . Here, for example, the voltage switching circuit 611 can simultaneously switch the voltages applied to the gate terminals of the transistors Qn21 to Qn23, and the voltage switching circuit 612 can simultaneously switch the voltages applied to the gate terminals of the transistors Qp22 and Qp23. It is connected to the. Therefore, generally, the number of voltage switching circuits 600 to be installed is smaller than the number of gate terminals of the target transistor.

  Note that the input voltages Vin21 and Vin22 input to the gate terminals of the transistors Qp24 and Qp25 and the bias voltage Vbias input to the gate terminal of the transistor Qn27 are all intermediate voltages generated by the previous circuit. For this reason, the voltage switching circuits 614, 615, and 613 are provided at the gate terminals of the transistors Qp24, Qp25, and Qn27, respectively, similarly to the gate terminals of the other transistors.

  The path to which current stress is applied is a path from the power supply terminal to the ground terminal via the resistor element R21 and the transistor Qn21, and a path from the power supply terminal to the ground terminal via the resistor element R22 and the transistor Qn28. For this reason, current switching circuits 711 and 712 are provided in parallel to the resistors R21 and R22, respectively.

  FIG. 6 is a circuit diagram in the case where a voltage switching circuit and a current switching circuit are provided in the differential amplifier circuit shown in FIG. Voltage switching circuits 621 to 625 are provided at all gate terminals of the transistors Qn31 to Qn33 and Qp31 to Qp35 to which the intermediate voltage is applied, respectively. Here, since the input voltages Vin31 and Vin32 input to the gate terminals of the transistors Qp34 and Qp35 are intermediate voltages generated in the previous circuit, the gates of the transistors Qp34 and Qp35 are the same as the gate terminals of the other transistors. The terminals are also provided with voltage switching circuits 621 and 625, respectively.

  The path to which current stress is applied is a path from the power supply terminal to the ground terminal via the transistor Qp33 and the resistance element R31. For this reason, a current switching circuit 721 is provided in parallel with the resistor R31.

  As described above, by incorporating the stress voltage generation circuit 100 and the voltage switching circuit 600 into a differential amplifier circuit which is an example of a stress test target circuit, a transistor to which a sufficient voltage cannot be applied only by boosting the power supply voltage. The boosted power supply voltage can be directly applied. As a result, an electrically unstable portion can be destroyed by applying voltage stress, so that a differential amplifier circuit that is initially defective can be selected and excluded in advance. Similarly, by incorporating a current switching circuit in the differential amplifier circuit, it is possible to destroy the electrically unstable part by applying current stress, so the differential amplifier circuit that is initially defective is selected and excluded in advance. can do.

  In this embodiment, the differential amplifier circuit has been described as an example. However, the present invention is not limited to the differential amplifier circuit, and may be any circuit including a transistor to which an intermediate voltage lower than the power supply voltage is applied during normal operation. . Further, the transistor to which the intermediate voltage is applied is not limited to the N-channel transistor, and may be a P-channel transistor.

<Modification of stress voltage generation circuit>
FIG. 7 is a circuit diagram showing a stress voltage generation circuit 150 which is a modification of the stress voltage generation circuit 100. As shown in FIG. 7, the stress voltage generation circuit 150 is different from the stress voltage generation circuit 100 in that a predetermined voltage generation circuit 450 is provided instead of the current mirror circuit 400. Therefore, among the components of the stress voltage generation circuit 150, the same components as those of the stress voltage generation circuit 100 are denoted by the same reference numerals, and description thereof is omitted.

  The predetermined voltage generation circuit 450 of the stress voltage generation circuit 150 includes a P-channel transistor Qp1 and an inverter INV6. The power supply voltage Vcc is applied to the source terminal of the P-channel transistor of the inverter INV6, and the drain terminal of the N-channel transistor is connected to the drain terminal. The source terminal of the N-channel transistor is grounded, and the gate terminals of the N-channel transistor and the P-channel transistor are connected to the node NB. The connection point between the drain terminals of the N-channel transistor and the P-channel transistor is connected to the high-level terminals of the three inverters INV3 to INV5 that constitute the ring oscillator 500.

  Next, the operation of the predetermined voltage generation circuit 450 will be described. When the stress voltage generation circuit 150 operates in the normal mode, the voltage at the node NB becomes the power supply voltage Vcc as described above. The inverter INV6 is set to output a low level voltage by determining that a high level voltage is applied when the power supply voltage Vcc is applied. Therefore, when the power supply voltage Vcc is input, the inverter INV6 outputs a low level voltage. Since the output low level voltage is applied to the high level terminals of the inverters INV3 to INV5, the inverters INV3 to INV5 do not operate. For this reason, the ring oscillator 500 does not generate an alternating voltage.

  On the other hand, when the stress voltage generating circuit 150 operates in the stress mode, as described above, the voltage at the node NB is a voltage applied to the resistance element R3 and the on-resistance of the N-channel transistor Qn1. When this voltage is applied to the inverter INV6, the inverter INV6 determines that a low level voltage has been input, and is set to output a high level voltage. Therefore, the inverter INV6 outputs a high level voltage. Since the output high level voltage is applied to the high level terminals of the inverters INV3 to INV5, the inverters INV3 to INV5 operate, generate an AC voltage as a ring oscillator, and apply the AC voltage to the stress test target circuit. Output.

1 is a circuit diagram of a stress voltage generation circuit included in a semiconductor device according to an embodiment of the present invention. (A) is a waveform diagram of a clock pulse generated by the stress voltage generation circuit shown in FIG. 1, (B) is a waveform diagram when the frequency of the clock pulse of (A) is increased, and (C) is a waveform diagram. It is a waveform enlarged view of a clock pulse showing a problem when the frequency is increased. (A) is a functional diagram of a voltage switching circuit that switches between a normal mode and a stress mode, and (B) is a circuit diagram showing a specific circuit of the voltage switching circuit of (A). (A) is a functional diagram of a current switching circuit for switching between a normal mode and a stress mode, and (B) is a circuit diagram showing a specific circuit of the current switching circuit of (A). FIG. 10 is a circuit diagram when a voltage switching circuit and a current switching circuit are provided in the differential amplifier circuit shown in FIG. 9. FIG. 11 is a circuit diagram when a voltage switching circuit and a current switching circuit are provided in the differential amplifier circuit shown in FIG. 10. It is a circuit diagram which shows the modification of a stress voltage generation circuit. It is a figure which shows the time change of the defect rate of a semiconductor device. (A) is a circuit diagram represented using a logic gate as an example of a logic circuit, and (B) is a circuit diagram representing the logic gate of (A) at a transistor level. It is a circuit diagram of the conventional differential amplifier circuit. It is a circuit diagram of another conventional differential amplifier circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100, 150 ... Stress voltage generation circuit 200 ... Mode selection circuit 300 ... Pull-up circuit 400 ... Current mirror circuit 450 ... Predetermined voltage generation circuit 500 ... Ring oscillator 600, 611-616, 621-625 ... Voltage switching circuit 700, 711, 712, 721 ... Current switching circuit

Claims (11)

In a semiconductor device having a function of switching the operation mode of a circuit under test between a normal mode and a stress mode,
Mode selection means for selecting either a normal mode or a stress mode based on a power supply voltage supplied from the outside;
When a stress mode is selected by the mode selection means, a voltage stress signal based on the power supply voltage is generated, and when the stress test target circuit is operating in a normal mode, the power supply voltage is grounded. And a signal output means for applying the voltage stress signal to a transistor to which the intermediate voltage is applied.   2. The signal output means includes an oscillating means for generating an AC voltage signal when a stress mode is selected by the mode selection means, and outputs the AC voltage signal as the voltage stress signal. A semiconductor device according to 1. The mode selection means includes
A first resistance divider circuit for dividing the power supply voltage by resistance to output a first divided voltage;
Including a first switching element that selects one of a normal mode and a stress mode based on the first divided voltage;
The signal output means further includes predetermined voltage generation means for generating a predetermined voltage when a stress mode is selected by the first switching element,
The semiconductor device according to claim 2, wherein the oscillating unit generates the AC voltage signal based on the predetermined voltage. The predetermined voltage generating means includes a current mirror circuit having an odd number of output terminals for outputting a current of the same magnitude,
The oscillating means includes cascaded inverters each having a high level side terminal connected to the output terminal of the current mirror circuit, and a voltage caused by a current output from the current mirror circuit is connected to the high level side of the inverter. 4. The semiconductor device according to claim 3, further comprising a ring oscillator that generates the AC voltage signal by being applied to a terminal.   5. The semiconductor device according to claim 4, wherein the number of cascaded inverters is adjusted such that the amplitude of the AC voltage signal is the same level as the amplitude of the power supply voltage. 6. The semiconductor device further includes a voltage switching circuit that switches and outputs a voltage applied to the transistor between the AC voltage signal output from the ring oscillator and an operating voltage signal output in a normal mode,
The voltage switching circuit is
A second resistance divider circuit for dividing the power supply voltage by resistance and outputting a second divided voltage;
A second switching element for providing the AC voltage signal to the transistor when turned on based on the second divided voltage;
A third switching element that is turned on based on the second divided voltage when the second switching element is in an off state and supplies the operating voltage signal to the transistor. The semiconductor device according to claim 4.   The semiconductor device according to claim 4, wherein the mode selection unit further includes a pull-up unit that deactivates the current mirror circuit when the normal mode is selected.   The semiconductor device according to claim 1, wherein the stress test target circuit is an analog circuit.   9. The semiconductor device according to claim 8, wherein the transistor is a MOS transistor, and the mode selection unit applies the voltage stress signal to a gate terminal of the MOS transistor.   2. The semiconductor device according to claim 1, wherein the mode selection means and the signal output means are formed on the same substrate as the substrate on which the stress test target circuit is formed. The stress test target circuit is:
A resistance element formed in a path to be applied with current stress in the stress mode;
A third resistance divider circuit for dividing the power supply voltage by resistance and outputting a third divided voltage;
A third switching element connected in parallel to the resistance element;
The semiconductor device according to claim 1, wherein the third switching element short-circuits both ends of the resistance element when turned on.

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