JP2009212958A - Zapping method and receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable zapping in a comparatively inexpensive manner and by a comparatively simple configuration in receiving digital compressed image data by a zapping method and a receiver. <P>SOLUTION: In the zapping method of the receiver, there are provided a first tuner 11-1 and a second tuner 11-2 which receive the digital compressed image data, a first decoder for decoding all picture images of the digital compressed image data received by the first tuner, a second decoder which outputs images of the digital compressed image data received by the second tuner and only decodes a reference image required to prepare a given condition for image display, and a control circuit for controlling the first decoder and the second decoder so that the first decoder performs decoding by using the reference image decoded in the second decoder. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a zapping method and a receiving apparatus, and more particularly to a zapping method and a receiving apparatus that switch a channel of received digital compressed image data at high speed.

  In an analog television broadcast receiver, zapping is performed to switch channels at high speed. When the sapping is performed, the display is instantaneously switched from the image of the channel received before the sapping to the image of the channel received after the sapping. However, for example, a digital compressed image data receiving apparatus such as digital television broadcasting cannot output and display an image unless predetermined conditions are met. I can't.

  In the case of digitally compressed image data compressed by the MPEG system defined by ISO / IEC, there are three types of pictures: I, P, and B. The I picture is a reference picture, and the original picture can be constructed with only this I picture. On the other hand, the P picture indicates a difference from the previous I picture or P picture, and image data can be compressed by sending this P picture (difference). The B picture indicates the difference between the preceding and following I pictures and P pictures. For example, in the case of digital compressed image data compliant with the MPEG system, when a channel is switched, MPEG decoding processing, that is, decompression processing cannot be started without an I picture and a P picture. Since the I picture is generally operated so as to arrive every 0.5 seconds, in the worst case, there is a possibility that the MPEG decoding process cannot be started without waiting for 0.5 seconds.

  In digital television broadcasting, a plurality of video streams are time-division-multiplexed into a single MPEG-TS stream, and these video streams are present in the MPEG-TS stream that is distinguished by a number. It takes time to determine. Information used for this discrimination exists in the MPEG-TS stream itself and arrives at regular intervals. Specifically, the arrival of the program index information (PAT) packet is every 0.1 second, and the arrival of the program information (PMT) packet is every 0.1 second. For this reason, in the worst case, there is a possibility that these video streams cannot be identified unless 0.2 second is waited.

  Furthermore, since the broadcast wave of digital television broadcasting is OFDM-modulated, it takes time to synchronize when demodulating the received digital compressed image data. If the initialization time of the OFDM demodulator is, for example, 0.5 seconds, OFDM demodulation cannot be started without waiting for 0.5 seconds.

  Thus, in the case of the above example, a total of 0.5 seconds + 0.1 seconds (maximum value) +0.1 seconds (maximum value) +0.5 seconds (maximum value) + α = 1.2 seconds (maximum value) Without waiting for + α, the predetermined condition is not met. Here, α is a time specific to the receiving apparatus. If the predetermined conditions are not met, MPEG decoding processing cannot be started, and therefore zapping for switching channels at high speed cannot be performed. That is, in the case of digitally compressed image data, it is necessary to prepare for outputting an image at the time of channel switching, and for example, a black screen is displayed during the preparation period until the predetermined condition is met, and the user feels uncomfortable. Will be given.

Patent Document 1, Patent Document 2 and Patent Document 3 propose that two independent tuners are provided in a receiving apparatus, and the influence of display interruption at the time of channel switching is suppressed by switching the tuners.
JP 2003-87668 A JP 2006-191267 A Japanese Patent Laid-Open No. 11-331721

  In the configurations proposed in Patent Documents 1 to 3, since the receiver is provided with two independent tuners, it is necessary to install two systems of hardware such as an MPEG decoder in a television device or the like. As a result, it is necessary to provide a relatively large-capacity memory for use in arithmetic processing, resulting in a problem that the configuration of the receiving apparatus becomes complicated and the cost becomes relatively high. On the other hand, in a personal computer equipped with a tuner, functions such as an MPEG decoder are realized by software. In this case as well, it is necessary to cause the processor to execute processing for two systems. In addition, there is a problem that it is difficult to perform zapping because the load on the processor increases and the processing speed decreases.

  Accordingly, an object of the present invention is to provide a zapping method and a receiving apparatus that enable zapping with a relatively simple and relatively simple configuration when receiving digitally compressed image data.

  According to one aspect of the present invention, there is provided a zapping method in a receiving apparatus having a plurality of tuners for receiving digital compressed image data, wherein the receiving apparatus displays all images only for the digital compressed image data received by the first tuner. A first decoder for decoding, and a second decoder for only decoding a reference image necessary to align predetermined conditions for outputting and displaying the digital compressed image data received by the second tuner. There is provided a zapping method for performing decoding by the first decoder using the reference picture decoded by the second decoder in response to a zapping instruction.

  According to an aspect of the present invention, a first tuner and a second tuner that receive digital compressed image data, a first decoder that decodes all images of the digital compressed image data received by the first tuner, and the second tuner A second decoder that only decodes a reference image necessary to align predetermined conditions for outputting and displaying the digital compressed image data received by the tuner; and the second decoder in response to a zapping instruction There is provided a receiving device including a control circuit for controlling the first decoder and the second decoder so as to perform decoding by the first decoder using the reference image decoded in step (b).

  According to the disclosed zapping method and receiving apparatus, it is possible to perform zapping with a relatively simple and relatively simple configuration when digitally compressed image data is received.

  In the disclosed zapping method and receiving apparatus, a receiving apparatus such as a television apparatus is provided with a plurality of tuners, and a decoder that decodes digitally compressed image data decodes all images for only one tuner (or the first tuner). A full decoder (or first decoder) is connected, and a simple decoder (or second decoder) that decodes only the reference image is connected to the other tuner (or second tuner). The simple decoder has a configuration that performs only the decoding necessary to align predetermined conditions for outputting and displaying an image, and has a simpler hardware configuration and is less expensive than a full decoder. Further, the memory capacity of the memory used by the simple decoder in the arithmetic processing may be smaller than the memory capacity of the memory used by the full decoder in the arithmetic processing.

  If zapping is performed in a state where an image is output and displayed based on the decoding result of the full decoder, the output is switched to the decoding result of the simple decoder, so that the display is switched to the image of the channel after zapping without delay.

  In a personal computer or the like equipped with a tuner, functions such as a decoder are realized by software. In this case, if zapping is performed with the processor executing the decoding process of the full decoder and outputting and displaying the result of the decoding process, the result of the decoding process of the simple decoder being executed in parallel by the processor Since the output is switched, the capacity of the memory used in the arithmetic processing can be kept relatively small, and the increase in the load on the processor can be suppressed, so that zapping can be performed without causing a reduction in processing speed.

  Embodiments of a zapping method and a receiving apparatus according to the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a receiving apparatus according to the first embodiment of the present invention. In the present embodiment, as an example, the present invention is applied to a receiving apparatus of a television apparatus that receives digital compressed image data compressed by the MPEG method such as digital television broadcasting.

  There are three types of image data (hereinafter referred to as pictures) in MPEG compressed image data. The I picture is a reference picture, and the original picture can be constructed with only this I picture. On the other hand, the P picture shows a difference from the previous I picture or P picture and cannot be constructed without the previous I picture or P picture. In general, since there is often a correlation between consecutive images, image data can be compressed by sending this P picture (difference). The B picture indicates the difference between the preceding and following I pictures and P pictures. The B picture has a high compression rate because it is the difference between the preceding and succeeding I pictures or P pictures.

  The receiving apparatus 1 includes tuners 11-1 and 11-2, stream selectors 12 and 13-1, memories 14 and 15, a full MPEG decoder 16, a simple MPEG decoder 17-1, and a CPU or MPU connected as shown in FIG. And the like, a processor 18, an I picture and a P picture (hereinafter simply referred to as I and P pictures) selectors 19 and 20, and memories 21, 22-1, and 23. The memories 14, 15, 21, 22-1, and 23 may be configured by different storage areas of a single memory, or may be configured by separate memories. Two or more memory storage areas may be used as the memories 14, 15, 21, 222-1, 23.

  Each of the tuners 11-1 and 11-2 receives MPEG compressed image data, and when it is adjusted to the selected channel, the tuners 11-1 and 11-2 are selected after the initialization time of the OFDM demodulator in each tuner 11-1 and 11-2 has elapsed. A well-known configuration for outputting an MPEG-TS stream of the selected channel. An MPEG-TS stream is an aggregate of fixed-length MPEG packets that conform to the MPEG standard, and an AV stream or the like is time-division multiplexed therein. The AV stream is a collection of MPEG-TS packets related to audio visual (AV). In the present embodiment, for convenience of explanation, it is assumed that the stream selector 12 selects an AV stream from the MPEG-TS stream output from the tuner 11-1 matched to the selected channel in the initial state. When selecting an AV stream, the stream selector 12 stores a program information packet group included in the MPEG-TS stream in a time-division multiplexed manner and refers to it. The program information packet group includes information on television (TV) programs included in the MPEG-TS stream (for example, the titles and broadcast times of a plurality of programs), and the packet number of the AV stream that is the main body of the program. included. The stream selector 12 extracts AV-related packets (basically digital compressed image data, that is, MPEG compressed image data), and outputs the extracted packets to the full MPEG decoder 16. The full MPEG decoder 16 decodes, that is, expands, the I picture, P picture, and B picture of the MPEG compressed image data, outputs the decompressed image data, and displays it on a display unit (not shown). Specifically, the full MPEG decoder 16 stores the I and P pictures in the memory 21 or the memory 22-1 through the I and P picture selector 19 and also stores the B picture in the memory 23. The full decoding result including the I, P, and B pictures is output to the display unit. In this way, the tuner operation of the system including the tuner whose channel is selected is performed.

  On the other hand, the tuner operation of the tuner system matched to the channel predicted to be selected by zapping is performed as follows. The channel that the user selects next by zapping can be predicted by various methods. For example, in the case of zapping where the user performs an operation of sequentially increasing channel numbers with a remote controller (not shown), the channel number to be selected next is a channel that is larger than the currently selected channel number. In the case of zapping, which can be predicted to be a number and the operation of sequentially decreasing the channel number is performed, the channel number to be selected next is a channel number that is smaller than the currently selected channel number. Predictable to be. It is also possible to learn a selection pattern when a user selects a channel by zapping, and predict a channel number to be selected next by zapping.

  In this embodiment, for convenience of explanation, in the initial state, the stream selector 13-1 selects an AV stream from the MPEG-TS stream output from the tuner 11-2 matched with the channel predicted to be selected by zapping. . When selecting an AV stream, the stream selector 13-1 stores the program information packet group included in the MPEG-TS stream in a time-division multiplexed manner and refers to it. The stream selector 13-1 extracts AV-related packets and outputs them to the simple MPEG decoder 17-1. The simple MPEG decoder 17-1 decodes only the I picture and the P picture of the MPEG compressed image data, that is, decompresses the decompressed image data (that is, I, P picture) via the I, P picture selector 20. And stored in the memory 22-1 or the memory 21.

  When the user performs a zapping operation with the remote controller, a zapping instruction (or signal) from the remote controller is input to the processor 18 via a remote control interface (not shown) having a known configuration. Note that the zapping instruction is not limited to that from the remote controller, and may be any instruction received from the input unit including the operation panel of the receiving device 1. In response to the zapping instruction, the processor 18 outputs a switching instruction (or signal) to the stream selectors 12 and 13-1 and the I and P picture selectors 19 and 20. The stream selectors 12 and 13-1 that have received the switching instruction switch the MPEG-TS streams from the tuners 11-1 and 11-2 to be selected and output. Also, the I / P picture selector 19 that has received the switching instruction switches the reading memory so that the I / P picture used in the full decoding of the full MPEG decoder 16 is read from the memory 22-1. Further, the I / P picture selector 20 that has received the switching instruction switches the writing memory so that the I and P pictures used in the simple decoding of the simple MPEG decoder 17-1 are stored in the memory 21. In this way, every time a zapping instruction is generated, the full MPEG decoder 16 reads from the memory 22-1 or the memory 21 that already stores the I and P pictures already obtained by the simple MPEG decoder 17-1. Since full decoding is performed by reading out the I and P pictures, the full decoding does not wait for the time required to newly obtain the I and P pictures for the channel selected by zapping.

  In this embodiment, the simple MPEG decoder 17-1 decodes only I and P pictures in the MPEG compressed image data. Since it depends on the implementation method of the MPEG decoder, it cannot be generally stated, but in the case of the full MPEG decoder 16, the current image, the previous image (I or P picture), and the subsequent image (P picture) 3 It is necessary to store three images, and the memory is required for three images. However, the simple MPEG decoder 17-1 only needs the preceding and following I pictures or P pictures, and the memory capacity for storing the images is accordingly large. Compared to the case of the full MPEG decoder 16, it is less. Further, since the simple MPEG decoder 17-1 does not need to create a current image from previous and subsequent images, the circuit scale can be reduced. Further, every time a zapping instruction is generated, the I and P picture selector 20 switches the memory for storing the I and P pictures used in the simple decoding of the simple MPEG decoder 17-1, so that the I and P pictures used after zapping are changed. Can always be updated. If the ratio of the data amount of I, P picture and B picture is 1: 1, the processing performance required for decoding only I and P pictures is generally the processing required for decoding I, P and B pictures. About half of the performance is sufficient, and the memory capacity for decoding is about 2/3.

  Since the I picture is generally operated so as to arrive every 0.5 seconds, in the worst case, there is a possibility that full decoding cannot be started without waiting for 0.5 seconds. In digital television broadcasting, a plurality of video streams are time-division-multiplexed into a single MPEG-TS stream, and these video streams are present in the MPEG-TS stream that is distinguished by a number. It takes time to determine. Information used for this discrimination exists in the MPEG-TS stream itself and arrives at regular intervals. Specifically, the arrival of the program index information (PAT) packet is every 0.1 second, and the arrival of the program information (PMT) packet is every 0.1 second. For this reason, in the worst case, there is a possibility that these video streams cannot be identified unless 0.2 second is waited.

  That is, since the packet number of the program index information (PAT) is determined as “0” in the international standard, the processing can be performed on the assumption that the number of this packet is known from the beginning. In this PAT packet, there are the number of programs included in the MPEG-TS packet group, the program number, and the packet number (corresponding to the PMT packet) related to the program. The PMT packet is extracted using the packet number (PMT number) relating to this program. In this PMT packet, the number of the AV packet group, which is the main body of the program, is extracted, and this is extracted to start the extraction of the AV packet. The processing time related to program extraction so far is the worst 0.2 seconds.

  Furthermore, since the broadcast wave of digital television broadcasting is OFDM-modulated, it takes time to synchronize when demodulating the received digital compressed image data. If the initialization time of the OFDM demodulator is, for example, 0.5 seconds, OFDM demodulation cannot be started without waiting for 0.5 seconds.

  In this way, a total of 0.5 seconds + 0.1 seconds (maximum value) +0.1 seconds (maximum value) +0.5 seconds (maximum value) + α = 1.2 seconds (maximum value) + α This means that predetermined conditions for performing full decoding by the decoder 16 are not met. Here, α is a time unique to the receiving apparatus 1.

  FIG. 2 is a diagram for explaining zapping in the present embodiment. As shown in FIG. 2, for example, when channel Ch1 is first selected, if α = 0 for convenience, 1.2 seconds (maximum value) until a predetermined condition for full MPEG decoding is met. In the meantime, for example, a black screen is displayed on the display unit, and then the channel Ch1 screen is displayed. However, since the simple MPEG decoding for, for example, the channel Ch2 after the zapping is performed during the 1.2 seconds, a part of the predetermined conditions (that is, I and P pictures) for performing the full MPEG decoding are prepared. As soon as zapping occurs, the display screen can be switched to the display of the channel Ch2 screen after zapping. If further zapping occurs after this zapping, it can be immediately switched to the display of the screen of channel Ch3 after zapping, for example, 1.2 seconds after the last zapping. Similarly, every time zapping occurs, for example, channels Ch4, Ch5, Ch6, Ch7,. . . Is displayed. In this way, it is possible to prevent a black screen from being displayed every time zapping is performed and to immediately display the channel screen after zapping, so that the user does not feel uncomfortable.

  In this way, if the worst 1.2 seconds are required for MPEG display preparation for each of the two tuners 11-1 and 11-2 in FIG. 2, the tuner 11-2 is ready for MPEG display while the tuner 11-1 is displaying. Is started, MPEG display on the tuner 11-2 becomes possible immediately after 1.2 seconds.

  FIG. 3 is a diagram illustrating zapping in the prior art using a single tuner TU1. In the case of FIG. 3, for example, when channel Ch1 is first selected, if α = 0 for convenience, it takes 1.2 seconds (maximum value) until a predetermined condition for full MPEG decoding is met. For example, a black screen is displayed on the display unit, and then the channel Ch1 screen is displayed. When zapping occurs, a black screen is displayed for 1.2 seconds until a predetermined condition for full MPEG decoding is met again before switching to the display of the screen of channel Ch2 after zapping, for example.

  As can be seen from the comparison between FIG. 2 and FIG. 3, according to the present embodiment, the black screen display that gives the user a sense of incongruity is reduced as much as possible under the precondition that the prediction of the channel selected by zapping is correct. I can do it. Compared with the configuration proposed in Patent Documents 1 to 3, zapping can be performed with a simple and inexpensive hardware configuration.

  Note that the black screen displayed until a predetermined condition for performing full MPEG decoding is met may be a screen of an arbitrary color, and need not be a black screen. Further, nothing may be displayed instead of the black screen. In short, any information other than the image of the selected channel may be displayed until a predetermined condition for performing full MPEG decoding is met.

  FIG. 4 is a block diagram showing the configuration of the receiving apparatus in the second embodiment of the present invention. In this embodiment, as an example, the present invention is applied to a receiving apparatus of a personal computer (PC) that receives digital compressed image data compressed by the MPEG method such as digital television broadcasting. The functions of the full MPEG decoder and the simple MPEG decoder are realized by software. The function of the tuner is realized not by software but by hardware, that is, a tuner.

  The receiving device 31 includes tuners 11-1 to 11 -N (N is an integer of 2 or more), a remote control interface (IF) 42, a processor 43 including a CPU and MPU, and a graphic LSI 44 connected as shown in FIG. A main memory 45, a video RAM 46, a display unit 48, and a PC bus 48 such as PCI or PCI Express.

  The tuners 11-1 to 11 -N are constituted by tuner cards having a known configuration, for example, and are connected to the PC processor 43 via the PC bus 48. The tuners 11-1 to 11 -N are controlled by the processor 43 executing a tuner control program. An instruction from a remote controller (not shown) is sent to the processor 43 via the remote controller IF 42 and the PC bus 48. The instruction is not limited to that from the remote controller, and may be any instruction received from the input unit including the operation panel of the receiving device 31 and the keyboard of the PC.

  The main memory 45 stores various programs and data executed by the processor 43. These various programs include the tuner control program, the stream selector program, a full decode program for realizing the function of the full MPEG decoder, a simple decode program for realizing the function of the simple MPEG decoder, and the like. The processor 43 executes a plurality of programs stored in the main memory 45 in, for example, a Windows (registered trademark) multitasking environment. Image data to be displayed on the display unit 47 is created by the graphic LSI 44 performing graphic processing in accordance with an instruction from the processor 43 and stored in the video RAM 46. The image data stored in the video RAM 46 is displayed on the display unit 47. As the graphic LSI 44, an LSI having a well-known configuration can be used.

  The operation of this embodiment is basically the same as that of the first embodiment except that operations other than the tuner of FIG. 1 are executed by the processor 43 and the graphic LSI 44.

  FIG. 5 is a flowchart for explaining the operation of the receiving apparatus in the second embodiment. In the processing shown in FIG. 5, a tuner control program, a stream selector program, a full decoding program, a zapping preparation program, a simple decoding program, and the like stored in the main memory 45 are executed by the processor 32.

  When the processing of FIG. 5 is started, the tuner control program receives a viewing start instruction (or signal) from the remote controller via the remote controller IF 42 and the PC bus 48 in step S1. As a result, the tuner control program sets the tuners 11-1 to 11 -N, and after 0.5 seconds, the MPEG-TS packet group is sent to the processor 43 via the tuners 11-1 to 11 -N and the PC bus 48. Input to the stream selector program. In step S2, the stream selector program analyzes the MPEG-TS packet group, identifies program selection information in the PAT and PMT packets, extracts the AV packet group number, and extracts the MPEG compressed video packet group. The stream selector program selects, for example, AV stream 1 in step S3. The full decoder program starts full MPEG decoding for the AV stream 1 selected in step S4. Thus, since the AV stream 1 is a program that is currently viewed, it is processed by the full decoder program. The full decoder program stores the I, P, and B pictures obtained by decoding the AV stream 1 in step S5 in the video RAM 46. The full decoding program outputs a moving image composed of I, P, and B pictures stored in the video RAM 46 using the graphic LSI 44 in step S6 and displays it on the display unit 47.

  At the same time as the processing of steps S1 to S6 is performed, preparation for zapping is also performed. This zapping preparation can be realized by executing two or more programs in parallel in a Windows (registered trademark) multitasking environment.

  The zapping preparation program starts preparation for zapping in step S7, predicts a channel to be selected next by the user by zapping, and selects a channel predicted by the tuner control program in step S8 as a tuner 11-n (n = 1 to N). After 0.5 seconds, the MPEG-TS packet group is input to the stream selector program of the processor 43 via the tuner 11-n and the PC bus 48. In step S9, the stream selector program analyzes the MPEG-TS packet group, identifies program selection information in the PAT and PMT packets, extracts the number of the AV packet group, and extracts the MPEG compressed video packet group. The stream selector program selects the AV stream n in step S10. It takes 0.2 seconds (maximum value) to extract this AV stream n. The simple decoder program starts simple MPEG decoding for the AV stream n in step S11. As described above, the AV stream n is a program that is predicted to be viewed next time, not a program that is currently viewed, and thus is processed by the simple decoder program. The simple decoder program stores the I and P pictures obtained by decoding the AV stream 1 in step S12 in the video RAM 46. Since the simple decoding program processes only I and P pictures, only the memory capacity for storing the I and P pictures is required, and the memory capacity of the video RAM 46 can be reduced accordingly. Further, since the simple decoding program processes only I and P pictures, the data processing amount of the processor 43 in the PC is greatly reduced. The degree of reduction in the amount of data processing depends on the frequency of I, P, and B pictures, but in the case of normal MPEG image compressed data, the amount of data of I / P pictures and B pictures depends on the operation of the MPEG encoder. Since the ratio is considered to be 1: 1, in this case, the data processing amount is halved. The zapping preparation program completes preparation for zapping in step S13.

  Next, when the processing in steps S1 to S13 is completed, the tuner control program starts viewing the preparation stream in step S14. The tuner control program receives a zapping instruction (or signal) from the remote controller via the remote controller IF 42 and the PC bus 48 in step S15. As a result, the tuner control program sets the predicted channel to the tuner 11-n, and after 0.5 seconds, the MPEG-TS packet group is input to the stream selector program of the processor 43 via the tuner 11-n and the PC bus 48. Is done. In step S16, the stream selector program analyzes the MPEG-TS packet group, identifies program selection information in the PAT and PMT packets, extracts the number of the AV packet group, and extracts the MPEG compressed video packet group. It should be noted that if the selection information is already confirmed at the stage of preparation for zapping, it is not necessary to actually confirm, and it is only necessary to confirm that the AV stream n is received. The stream selector program selects, for example, the AV stream n in step S3. The full decoder program switches the memory area of the video RAM 46 to be used in order to switch the I and P pictures used for full MPEG decoding in step S18 to the I and P pictures stored in the video RAM 46 at the stage of preparation for zapping.

  If an I / P picture is received when selecting an AV stream n, the AV video stream n is switched after waiting for the decoding of the I / P picture and the updating of the I / P picture in the video RAM 46. Need to do. Otherwise, the I and P pictures in the video RAM 46 cannot be kept up-to-date. Further, even when waiting for the update of the I and P pictures, the waiting time is about 1/30 second. For the human eye, a switching time of about 0.1 seconds can be seen as a sufficiently instantaneous event and does not give the user a sense of incongruity. There is no particular problem.

  The full decoder program starts full MPEG decoding using the I and P pictures stored in the video RAM 46 at the stage of zapping preparation for the AV stream n selected in step S19. The full decoder program stores the I, P, B pictures obtained by decoding the AV stream n in step S20 in the video RAM 46, and also uses the graphic LSI 44 to store the I, P, B pictures stored in the video RAM 46. Is output and displayed on the display unit 47.

  At the same time as the processes of steps S14 to S20 are performed, preparation for the next zapping is also performed. The preparation for the next zapping can be realized by executing two or more programs in parallel in a multi-task environment of Windows (registered trademark).

  The preparation for the next zapping is the same as the zapping preparation in steps S7 to S13, except that the next predicted channel is performed for the AV stream n + 1, for example, and step S25 is performed. It is. That is, steps S21 to S24 and S26 to S28 are the same processes as the above steps S7 to S13, and thus description thereof is omitted. The simple decoding program switches the memory area of the video RAM 46 that stores the I and P pictures obtained by the simple MPEG decoding in step S25 to an unused area that is not used in step S18.

  When the processing in steps S14 to S28 is completed, the tuner control program starts viewing the preparation stream in step S14, and the zapping preparation program starts preparation for the next zapping in step S21. Thereafter, the same processing as described above is repeated.

  Zapping in this embodiment is the same as that shown in FIG. 2 described together with the first embodiment. As can be seen from the comparison between FIG. 2 and FIG. 3, according to the present embodiment, the black screen display that gives the user a sense of incongruity is reduced as much as possible under the precondition that the prediction of the channel selected by zapping is correct. I can do it. In addition, as compared with the case where the configurations proposed in Patent Documents 1 to 3 are realized by software, the capacity of the memory used for the arithmetic processing can be kept relatively small, and an increase in the load on the processor can be suppressed. Zapping can be performed without reducing the processing speed.

  FIG. 6 is a block diagram showing the configuration of the receiving apparatus according to the third embodiment of the present invention. In FIG. 6, the same parts as those in FIG. In the present embodiment, as an example, the present invention is applied to a receiving apparatus of a television apparatus that receives digital compressed image data compressed by the MPEG method such as digital television broadcasting. In the first embodiment, one channel selected by zapping is predicted. However, a plurality of channels may be predicted. In this embodiment, three channels after zapping are predicted as an example. Thus, by setting the number of channels to be predicted to be 2 or more, it is possible to reduce the probability that the channel after zapping is unpredicted. Further, if the predicted channel number is set to the number of channels that can be viewed, the channel after zapping can always be accurately predicted. Note that the channel prediction method after zapping is not particularly limited.

  In FIG. 6, each of the stream selectors 13-1 to 13-3 outputs AV from the MPEG-TS stream output from the corresponding tuners 11-2 to 11-4 adjusted to the channel predicted to be selected by zapping. Select a stream. When selecting an AV stream, each of the stream selectors 13-1 to 13-3 stores a program information packet group included in the MPEG-TS stream in a time-division multiplexed manner and refers to the program information packet group. . Each stream selector 13-1 to 13-3 extracts AV-related packets and outputs them to the corresponding simple MPEG decoders 17-1 to 17-3. Each of the simple MPEG decoders 17-1 to 17-3 decodes only the I picture and the P picture of the MPEG compressed image data, that is, decompresses, and a memory corresponding to the decompressed image data (ie, I, P picture). 22-1 to 22-3.

  When the user performs a zapping operation with the remote controller, a zapping instruction (or signal) from the remote controller is input to the processor 18 via a remote control interface (not shown) having a known configuration. The processor 18 outputs a switching instruction (or signal) to the stream selectors 12, 13-1 to 13-3 and the I and P picture selector 19 in response to the zapping instruction. The stream selectors 12, 13-1 to 13-3 that have received the switching instruction switch the MPEG-TS streams from the tuners 11-1 to 11-4 to be selectively output. The I / P picture selector 19 that has received the switching instruction switches the read memory so that the I / P picture used in the full decoding of the full MPEG decoder 16 is read from one of the memories 21, 222-1 to 22-3. I do. In this way, every time a zapping instruction is generated, the full MPEG decoder 16 stores the memory 22- that already stores the I and P pictures already obtained by any one of the simple MPEG decoders 17-1 to 17-3. Since the I and P pictures are read from any of 1 to 22-3 and full decoding is performed, the full decoding is waited for the time required to newly obtain the I and P pictures for the channel selected by zapping. There is nothing. After the zapping, the processor 18 controls the stream selectors 13-1 to 13-3, and the I and P used in the full decoding of at least the full MPEG decoder 16 among the simple MPEG decoders 17-1 to 17-3. The simple MPEG decoder connected to the memory storing the picture performs simple decoding on the next predicted channel, and thereafter the same processing as described above is repeated.

  FIG. 7 is a diagram for explaining zapping in the third embodiment. As described in conjunction with the first embodiment, a total of 0.5 seconds + 0.1 seconds (maximum value) +0.1 seconds (maximum value) +0.5 seconds (maximum value) + α = 1.2 seconds (maximum value) ) + Α, the predetermined conditions for performing full decoding by the full MPEG decoder 16 are not met.

  As shown in FIG. 7, for example, when channel Ch1 is first selected, if α = 0 for convenience, 1.2 seconds (maximum value) until a predetermined condition for full MPEG decoding is met. In the meantime, for example, a black screen is displayed on the display unit, and then the channel Ch1 screen is displayed. However, a part of a predetermined condition for performing full MPEG decoding by performing simple MPEG decoding for each predicted channel Ch2, Ch3, Ch4, for example, after zapping in 1.2 seconds (ie, I and P pictures) ), The display screen can be switched to the display of the screen of channel Ch2, for example, after zapping as soon as zapping occurs. If further zapping occurs after this zapping, the display can be immediately switched to the display of the channel Ch3 after zapping, for example, 0.4 seconds after the last zapping. Similarly, every time zapping occurs, for example, channels Ch4, Ch5, Ch6, Ch7,. . . Is displayed. In this way, it is possible to prevent a black screen from being displayed every time zapping is performed and to immediately display the channel screen after zapping, so that the user does not feel uncomfortable.

  In this way, if the worst 1.2 seconds are required for MPEG display preparation for each of the four tuners 11-1, 11-2, 11-3, 11-4 in FIG. 7, the tuners 11-1, 11-2 , 11-3, when the tuner 11-4 starts preparing for MPEG display, MPEG display on the tuner 11-4 becomes possible immediately after 1.2 seconds. The total time displayed by the three tuners 11-1, 11-2, 11-3 is 1.2 seconds, and the time displayed for each tuner 11-1, 11-2, 11-3 is 0.4 seconds. is there. In other words, if display and zapping are repeated by the tuners 11-1, 11-2, 11-3, and 11-4 in increments of 0.4 seconds, the tuners 11-1, 11-2, 11-3, and 11-4 are converted to MPEG. The display preparation time can be secured for 1.2 seconds, and MPEG display can be performed immediately without displaying black screens in order.

  In this embodiment, the functions of the full MPEG decoder and the simple MPEG decoder may be realized by software as in the case of the second embodiment.

  FIG. 8 is a block diagram showing the configuration of the receiving apparatus according to the fourth embodiment of the present invention. In the present embodiment, as an example, the present invention is applied to a receiving apparatus of a television apparatus that receives digital compressed image data compressed by the MPEG method such as digital television broadcasting. In FIG. 8, the same parts as those in FIG.

  For convenience, the operation when switching to the state of displaying the image of the channel Ch2 while the image of the channel Ch1 is displayed will be described. Further, as a process after the switching, it is assumed that switching to the state in which the image of the channel Ch1 is displayed again, and switching from the state in which the image of the channel Ch1 is displayed to the state in which the image of the channel Ch2 is displayed is performed again. It shall be possible.

  The receiving device 91 includes tuners 11-1 and 11-2, a full MPEG decoder 16, a simple MPEG decoder 17-1, a processor 18, buffers 51-1 and 51-2, and a switch circuit 52- connected as shown in FIG. 1, 52-2, 53 to 57, 61 to 65, and memories 71-1, 71-2, 72-1, 72-2, 73-1, 73-2.

  Even if the memories 71-1, 71-2, 72-1, 72-2, 73-1, 73-2 are composed of different storage areas of a single memory, they are composed of separate memories. May be. Two or more memory storage areas may be used as the memories 71-1, 71-2, 72-1, 72-2, 73-1, 73-2.

  Buffers 51-1 and 51-2 are connected to the outputs of the two tuners 11-1 and 11-2, and MPEG compressed image data from the tuners 11-1 and 11-2 corresponds to the corresponding buffer 51-. 1, 51-2 are temporarily stored. In order to output MPEG compressed image data from each of the buffers 51-1 and 51-2, the instruction signals c1bf and c2bf from the MPEG decoders 16 and 17-1 are necessary. The instruction signals c1bf and c2bf are provided with a switching circuit 81 for switching because the MPEG decoders 16 and 17-1 are switched when the channels are switched. Based on the control signal c1 from the processor 18, the switch circuit 81 outputs the instruction signal c1bf from the full MPEG decoder 16 or the instruction signal c2bf from the simple MPEG decoder 17-1 as the instruction signal cbf1, and the instruction signal cbf1 The inverted signal is output as the instruction signal cbf2.

  The switch circuits 52-1 and 52-2 output one of the two inputs to the corresponding MPEG decoders 16 and 17-1 based on the control signal c1.

  The full MPEG decoder 16 includes an MPEG decoder 161 that generates an actual MPEG image, and an output circuit 162 that outputs the MPEG-decoded image to a display unit (not shown). In the decoding operation, two systems of B picture memories 71-1 and 71-2 and two systems of I and P picture memories 72-1 and 72-2 are used.

  On the other hand, the simple MPEG decoder 17-1 is composed only of an MPEG decoder that actually generates an MPEG image. Further, since the simple MPEG decoder 17-1 generates only I and P pictures, only the two systems of I and P picture memories 73-1 and 73-2 are used without using the B picture memory.

  A switch circuit 61 is provided in order to switch the two systems of the B picture memories 71-1 and 71-2 and use them in the full MPEG decoder 16. Based on the control signal c11 from the full MPEG decoder 16, the switch circuit 61 outputs one input (data D1 from the full MPEG decoder 16) to one of the B picture memories 71-1 and 71-2.

  Four channels of I and P picture memories 72-1 and 72-2 and I and P picture memories 73-1 and 73-2 are fully used in preparation for switching to display of an image of channel Ch2 while displaying an image of channel Ch1. Switch circuits 62 to 65 are provided for switching between the MPEG decoder 16 and the simplified MPEG decoder 17-1. Based on the control signal c1, the switch circuit 62 outputs one of the data D1 from the full MPEG decoder 16 and the data D2 from the simple MPEG decoder 17-1 to the path on the I and P picture memory 72-1 side, The other is output to the path on the I and P picture memory 72-2 side. Further, the switch circuit 63 outputs one of the outputs of the switch circuit 63 to the I and P picture memory 72-1 and outputs the other to the I and P picture memory 72-2 based on the control signal cIPM1. Based on the control signal c1, the switch circuit 64 outputs one of the data D1 from the full MPEG decoder 16 and the data D2 from the simple MPEG decoder 17-1 to the path on the I and P picture memory 73-1, The other is output to the path on the I and P picture memory 73-2 side. The switch circuit 65 outputs one of the outputs of the switch circuit 65 to the I / P picture memory 73-1 and outputs the other to the I / P picture memory 73-2 based on the control signal cIPM2.

  Since the I and P picture memories connected at the time of channel switching change between the MPEG decoders 16 and 17-1, a switch circuit 82 is provided to perform the switching. The control signals cIPM1 and cIPM2 are generated by the switch circuit 82. Based on the control signal c1, the switch circuit 82 outputs the control signal c1IPM from the full MPEG decoder 16 or the control signal c2IPM from the simple MPEG decoder 17-1 as the control signal cIPM1, and controls the inverted signal of the control signal cIPM1. Output as signal CIPM2.

  Also, it is necessary to output MPEG images from the I and P picture memories 72-1, 72-3, 73-1, 73-2 and B picture memories 71-1, 71-2 storing MPEG images before and after switching. However, switch circuits 53 to 57 for determining which memory the MPEG circuit should be output from by the output circuit 162 and switching the output are provided. The switch circuits 53 to 57 output one of the two inputs based on the control signals c13 to c17 from the full MPEG decoder 16.

  A control signal c1 for performing overall control of channel switching is output from the processor 18 after the end of processing of one screen. When this control signal c1 is switched, control signals cIPM1 and cIPM2 for I and P picture memories are generated, control signals cbf1 and cbf2 for buffers are generated, and an MPEG decoder to which tuners 11-1 and 11-2 are connected 16 and 17-1 are switched, and the memory group to which the data D1 and D2 from the MPEG decoders 16 and 17-1 are output is switched.

  FIG. 9 is a time chart for explaining the operation of the receiving apparatus according to the fourth embodiment. In FIG. 9, BPM1A and BPM1B indicate B picture memories 71-1 and 71-2, IPM1A and IPM1B indicate I and P picture memories 72-1 and 72-2, and IPM2A and IPM2B indicate I and P picture memories, respectively. 73-1 and 73-2 are shown.

  First, the user instructs switching from the channel Ch1 being viewed to the channel Ch2 by a remote control instruction from the remote controller or the like by a channel switching instruction (or zapping instruction). This channel switching instruction (or signal) is input to the full MPEG decoder 16 via the processor 18. In this state, the full MPEG decoder 16 is processing the channel Ch1, and the MPEG decoder 161 decodes the MPEG compressed image data of the channel Ch1 from the tuner 11-1, and the display processing for displaying the image data on the display unit. Is being implemented by the output circuit 162.

  In the MPEG compressed image data, there are an I picture and a P picture, which are basic image information, and a B picture that is not, but first, as shown at the left end of FIG. 9, an I, P picture memory 72-1 (IPM1A) The decoding result of the I picture is stored in the I and P picture memory 72-2 (IPM1B), and then the decoding result of the P picture using the I picture in the I and P picture memory 72-1 (IPM1A) as the reference image is stored. To do. Subsequently, the B picture memory 71-2 (BPM1B) stores the B picture decoded using the I and P picture memories 72-1 and 72-2 (IPM1A and IPM1B) as reference images. Simultaneously with the storage of the B picture, the output circuit 162 selects and outputs the I picture stored in the I / P picture memory 72-1 (IPM 1 A) under the control of the switch circuits 54 to 56. When selecting an I picture stored in the I / P picture memory 72-1 (IPM 1 A), the output circuit 162 converts the image into an RGB format that can be displayed on the display unit because the I picture is a YcbCr format image. Process. The output circuit 162 may further perform image quality improvement processing on the I picture in the YcbCr format.

  The B picture stored in the B picture memory 71-2 (BPM1B) is displayed when the output circuit 162 selects and outputs the I picture stored in the I and P picture memory 72-1 (IPM1A). Displayed in the section. While the B picture stored in the B picture memory 71-2 (BPM1B) is being displayed, the next B picture is stored in the B picture memory 71-1 (BPM1A). By using the B picture memories 71-1 and 71-2 (BPM1A and BPM1B) alternately for display and storage, continuous B picture processing can be realized. The I & P picture memories 72-1 and 72-2 (IPM1A and IPM1B) are alternately used in the same manner, and continuous I / P picture processing is performed, so that continuous MPEG decoding processing can be realized. That is, after storing in the I / P picture memory 72-2 (IPM1B), the I / P picture memory 72-1 (IPM1A) is used for display, and after being used for display, the I / P picture memory 72 is used. -1 (IPM1A) is used as the latest I and P picture storage area. After storage in the I / P picture memory 72-1 (IPM1A), the I / P picture memory 72-2 (IPM1B) is used for display.

  If a channel switching instruction from the user is input to the full MPEG decoder 16 via the processor 18 during such processing, the full MPEG decoder 16 outputs a control signal c1 for performing overall control of channel switching. . However, if the control signal c1 is output immediately, image disturbance or the like may occur, so it is desirable to adjust the output timing. In this embodiment, the output timing is adjusted as follows. Needless to say, the output timing adjustment method is not limited to this. In short, it is only necessary to realize smooth and quick channel switching without causing image disturbance.

  In this embodiment, the adjustment of the output timing of the control signal c1 includes the following steps ST1 to ST5.

  Step ST1: Waiting for the end of the decoding process of the MPEG compressed image data being decoded by the full MPEG decoder 16, the decoding process of the full MPEG decoder 16 is once interrupted. Further, the control signal cbf1 is output, and the output of the MPEG compressed image data from the buffer 51-1 is stopped. The buffer 51-1 temporarily stores the MPEG compressed image data from the tuner 11-1, but the decoding process of the full MPEG decoder 16 is interrupted by stopping the output of the buffer 51-1. Also, the MPEG compressed image data during that time is not lost. The MPEG 5 compressed image data from the tuner 11-1 is sequentially input to the buffer 51-1 even when the output of the buffer 51-1 is stopped. If the decoding process of the full MPEG decoder 16 is not resumed until the storable area in the buffer 51-1 becomes full, the MPEG compressed image data is lost, so an immediate switching process is necessary thereafter.

  Step ST2: Next, the end of the decoding process of the simple MPEG decoder 17-1 is awaited. Since the simple MPEG decoder 17-1 is provided exclusively for processing I pictures or P pictures, there is no need to wait if the I picture and P picture have not arrived. However, if the simple MPEG decoder 17-1 is processing an I picture or P picture, it waits for the end of the processing, outputs the control signal cbf2, stops the output of the buffer 51-2, and then outputs the control signal c1. Output. This prevents the I picture or P picture from becoming incomplete. By waiting for the processing of the simple MPEG decoder 17-1 and outputting the control signal c1, the entire system is switched by controlling the switch circuit group as described above. Basically, the tuner 11-1 (channel Ch1) is connected to the simple MPEG decoder 17-1, and the tuner 11-2 (channel Ch2) is connected to the full MPEG decoder 16. Also, the I and P picture memories 73-1 and 73-2 (IPM2A and IPM2B) are connected to the full MPEG decoder 16, and the I and P picture memories 72-1 and 72-2 (IPM1A and IPM1B) are simplified MPEG decoder 17. -1. As a result, preparation for switching from channel Ch1 to channel Ch2 is completed.

Step ST3: Until the decoding process of the full MPEG decoder 16 is interrupted and the decoding process of the simple MPEG decoder 17-1 is finished, the image data from the output circuit 162 of the full MPEG decoder 16 to which the MPEG decoder 161 has finished the processing. The latest image data is output. If the time between them is long, the latest image data is repeatedly displayed during that time. FIG. 9 shows an example in which the latest image data (BPM1B) is repeatedly displayed twice. The time during which such repeated display is performed is about 1/15 seconds, and even if image data is repeatedly displayed, it appears as a continuous video without any sense of incongruity to human eyes.

  Step ST4: When the control signal c1 is output, the output of the tuner 11-2 (channel Ch2) is connected to the full MPEG decoder 16 capable of full MPEG decoding. The display of the channel Ch2 needs to be started. For this purpose, the control signal cbf2 is output, and the latest image data (BPM1A image in this embodiment) from the tuner 11-2 arrives (the last of the tuner 11-1). When the display of (BPM1B image) ends, MPEG decoding of the BPM1A image of the tuner 11-2 is started. Since one picture (1/30 second) is required until the decoding of the BPM1A image is completed, (the last BPM1B image of the tuner 11-1) is displayed again until then. After the decoding of the BPM1A image is completed, the BPM1A image from the tuner 11-2 is displayed and the BPM1B image is decoded. Thereafter, the same processing is repeated.

  Step ST5: Simultaneously with step ST4, the decoding process of the simple MPEG decoder 17-1 is restarted. For this purpose, the control signal cbf1 is output, and when an I picture or B picture arrives, the I picture or B picture is processed. Also, when a non-I picture or P picture arrives (that is, when a B picture arrives), the MPEG compressed image data is discarded.

  Thereafter, the processes of steps ST1 to ST5 are repeated.

  Although this embodiment has been described with a hardware image, software implementation on a PC is also possible. In that case, the tuners 11-1 and 11-2, the buffers 51-1 and 51-2 are realized by hardware mounted on a peripheral board of the PC, but other circuits (MPEG decoder 161, The output circuit 162, MPEG decoder 17-1, B picture memories 71-1, 71-2, I and P picture memories 72-1, 72-2, 73-1, 73-2, etc.) can be implemented in software. . When software is installed, the output of the buffers 51-1 and 51-2 may be transmitted to a software module on the PC via a general-purpose bus such as a PCI bus.

In addition, this invention also includes the invention attached to the following.
(Appendix 1)
A zapping method in a receiving apparatus having a plurality of tuners for receiving digital compressed image data,
The receiving device decodes all the images only for the digital compressed image data received by the first tuner, and a predetermined decoder for outputting and displaying the digital compressed image data received by the second tuner. A second decoder that only decodes a reference image necessary to meet the conditions;
A zapping method for performing decoding by the first decoder using the reference picture decoded by the second decoder in response to a zapping instruction.
(Appendix 2)
A first tuner and a second tuner for receiving digital compressed image data;
A first decoder for decoding all images of the digital compressed image data received by the first tuner;
A second decoder that performs only decoding of a reference image necessary to satisfy a predetermined condition for outputting and displaying the digital compressed image data received by the second tuner;
A reception circuit comprising: a control circuit that controls the first decoder and the second decoder so as to perform decoding by the first decoder using a reference image decoded by the second decoder in response to a zapping instruction; apparatus.
(Appendix 3)
A first memory for storing an image decoded by the first decoder;
And a second memory for storing an image decoded by the second decoder,
In response to the zapping instruction, the control circuit uses the reference image stored in the second memory to perform decoding by the first decoder and the first memory and the first memory. The receiving device according to attachment 2, wherein the connection between the decoder and the second decoder is switched.
(Appendix 4)
When the zapping instruction is generated during the decoding process by the second decoder, the control circuit waits for the end of the decoding process in the second decoder and then uses the reference image obtained in the decoding process. The receiving apparatus according to appendix 2 or 3, wherein the first decoder and the second decoder are controlled to perform decoding by a decoder.
(Appendix 5)
The receiving device according to any one of appendices 2 to 4, wherein the first decoder and the second decoder are configured by hardware.
(Appendix 6)
The receiving device according to any one of appendices 2 to 4, wherein the functions of the first decoder and the second decoder are realized by software.
(Appendix 7)
Any one of appendices 2 to 6, wherein the first tuner receives digitally compressed image data of a currently selected channel, and the second tuner receives digitally compressed image data of a channel predicted to be selected by zapping. The receiving device according to claim 1.
(Appendix 8)
The digital compressed image data is MPEG compressed image data, the first decoder decodes I pictures, P pictures, and B pictures, and the second decoder decodes only I pictures and P pictures. The receiving device according to claim 1.

  While the present invention has been described with reference to the embodiments, it is needless to say that the present invention is not limited to the above-described embodiments, and various modifications and improvements can be made within the scope of the present invention.

It is a block diagram which shows the structure of the receiver in 1st Example of this invention. It is a figure explaining the zapping in 1st Example. It is a figure explaining the zapping in a prior art. It is a block diagram which shows the structure of the receiver in 2nd Example of this invention. It is a flowchart explaining operation | movement of the receiver in 2nd Example. It is a block diagram which shows the structure of the receiver in 3rd Example of this invention. It is a figure explaining the zapping in 3rd Example. It is a block diagram which shows the structure of the receiver in 4th Example of this invention. It is a time chart explaining operation | movement of the receiver in 4th Example.

Explanation of symbols

1 Receiver 11-1, 11-2 Tuner 12, 13-1 Stream selector 14, 15 Memory 16 Full MPEG decoder 17-1 Simple MPEG decoder 18 Processor 19, 20 Selector 21, 22-1, 23 Memory

Claims (5)

A zapping method in a receiving apparatus having a plurality of tuners for receiving digital compressed image data,
The receiving device decodes all the images only for the digital compressed image data received by the first tuner, and a predetermined decoder for outputting and displaying the digital compressed image data received by the second tuner. A second decoder that only decodes a reference image necessary to meet the conditions;
A zapping method for performing decoding by the first decoder using the reference picture decoded by the second decoder in response to a zapping instruction. A first tuner and a second tuner for receiving digital compressed image data;
A first decoder for decoding all images of the digital compressed image data received by the first tuner;
A second decoder that performs only decoding of a reference image necessary to satisfy a predetermined condition for outputting and displaying the digital compressed image data received by the second tuner;
A reception circuit comprising: a control circuit that controls the first decoder and the second decoder so as to perform decoding by the first decoder using a reference image decoded by the second decoder in response to a zapping instruction; apparatus.   When the zapping instruction is generated during the decoding process by the second decoder, the control circuit waits for the end of the decoding process in the second decoder and then uses the reference image obtained in the decoding process. The receiving apparatus according to claim 2, wherein the first decoder and the second decoder are controlled to perform decoding by a decoder.   The first tuner receives digitally compressed image data of a currently selected channel, and the second tuner receives digitally compressed image data of a channel predicted to be selected by zapping. Receiver.   The digitally compressed image data is MPEG compressed image data, the first decoder decodes I pictures, P pictures, and B pictures, and the second decoder decodes only I pictures and P pictures. The receiving device according to claim 1.

Images