JP2009206243A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a resistance of contact with an electrode in a state that excellent crystallinity of a semiconductor substrate or a semiconductor layer made of a compound semiconductor material having a zinc blende structure such as GaAs and a negative piezoelectric constant e14 is maintained. <P>SOLUTION: On a substrate 101 which is made of semi-insulating GaAs and has a (100) face as a principal face, a semiconductor device has a striped insulation pattern 111 made of an insulator having compressive internal stress and extending in a [0-11] direction and an ohmic electrode 103 formed on the substrate 101 in a region where a conductive region 102 is formed, adjacent to the insulating pattern 111. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device including an ohmic electrode connected to a compound semiconductor having a zinc blende structure such as GaAs.

  A compound semiconductor material having a zinc blende structure such as GaAs is characterized by a high mobility of electrons, and is used as a material for a transistor that operates at high speed. For example, there is an n-type field effect transistor (FET) using a GaAs-based material.

  This field effect transistor will be described. As illustrated in FIG. 7, a semi-insulating GaAs substrate 701 whose main surface is a (100) plane, and a conductive material having a high electron concentration formed in the vicinity of the surface of the GaAs substrate 701. , A source electrode 703 and a drain electrode 704 formed on the GaAs substrate 701 at a predetermined distance, and a gate electrode 705 formed therebetween.

The GaAs substrate 701 has, for example, a p-type residual impurity concentration of about 1 × 10 ¹⁴ cm ⁻³ . In addition, by selective ion implantation using a resist mask or metal mask having a predetermined shape, an n-type impurity (for example, Si) is introduced into the FET formation region, and then activation annealing is performed at about 800 ° C. A conductive region 702 can be formed.

  The source electrode 703 and the drain electrode 704 are formed by, for example, depositing an ohmic electrode layer (for example, AuGe / Ni) made of a metal material that forms ohmic contact, and annealing it to about 350 ° C. A contact region is formed and is electrically connected to the electron gas in the conductive region 702. The gate electrode 705 is formed by successively depositing a metal material (for example, WSi / Au) that forms a Schottky barrier with respect to the GaAs substrate 701 in sequence.

  In this FET, by applying a bias voltage to the gate electrode 705, the electron gas concentration in the portion of the conductive region 702 where the gate electrode 705 is disposed is modulated, and conduction between the source electrode 703 and the drain electrode 704 is prevented. The transistor operation is realized.

Further, another form of field effect transistor will be described. As illustrated in FIG. 8, a semi-insulating GaAs substrate 801 whose main surface is a (100) plane and GaAs formed on the GaAs substrate 801. A channel layer 802 having a thickness of about 2 μm, a Schottky layer 803 having a thickness of about 20 nm made of AI _0.3 Ga _0.7 As, and a conductive region 804 formed in the channel layer 802 in the vicinity of the interface between the Schottky layer 803, A source electrode 805 and a drain electrode 806 formed on the Schottky layer 803 with a predetermined distance therebetween, and a gate electrode 807 formed therebetween are provided.

The GaAs substrate 801 has, for example, a p-type residual impurity concentration of about 1 × 10 ¹⁴ cm ⁻³ . Further, the channel layer 802 and the Schottky layer 803 are formed by sequentially growing (stacking) without introducing impurities by, for example, the MBE method or the MOCVD method. These may have an impurity concentration of about 1 × 10 ¹⁵ cm ⁻³ .

  Further, Si, which is an n-type impurity, is introduced in the vicinity of the interface with the Schottky layer 803 in the channel layer 802 by selective ion implantation using a resist mask or metal mask having a predetermined shape. By conducting the activation annealing at about 0 ° C., a conductive region 804 having a high electron concentration can be formed locally.

  The source electrode 805 and the drain electrode 806 are formed by, for example, depositing an ohmic electrode layer (for example, AuGe / Ni) made of a metal material that forms ohmic contact, and annealing it to about 360 ° C. A contact region is formed and electrically connected to the electron gas in the conductive region 802. The gate electrode 807 is formed by sequentially depositing a metal material (for example, WSi / Au) that forms a Schottky barrier with respect to the GaAs substrate 801 in sequence.

  Also in this FET, by applying a bias voltage to the gate electrode 807, the electron gas concentration of the portion of the conductive region 804 where the gate electrode 807 is disposed is modulated, and conduction between the source electrode 805 and the drain electrode 806 is achieved. Change and transistor operation is realized

Conal E. Murray, "Mechanics of edge effects in anisotropic thin film / substrate systems", Journal of Applied Physics, 100, 103532, pp.1-9, 2006.

  Here, a contact resistance is generated between an electrode such as a source electrode or a drain electrode and a semiconductor substrate or semiconductor device on which the electrode is formed. In the field effect transistor as described above, it is important to reduce the contact resistance while maintaining good crystallinity of the semiconductor substrate and the semiconductor layer.

  In order to reduce the contact resistance, first, it is desirable to perform activation annealing of impurities such as ion-implanted Si at a temperature as high as possible to increase the concentration of the activated impurities. However, such a high temperature treatment disturbs the atomic arrangement of the semiconductor layer (the crystallinity is impaired), leading to deterioration of device characteristics. In particular, in a structure including a Schottky layer and a channel layer, the atomic arrangement at the interface between the Schottky layer made of AIGaAs and the channel layer made of GaAs is disturbed by a high-temperature heat treatment, and the device characteristics are greatly affected.

  The present invention has been made in order to solve the above-described problems, and the semiconductor substrate and the semiconductor layer made of a compound semiconductor material having a zinc blende structure such as GaAs and a negative piezoelectric constant e14 are favorable. The object is to reduce the contact resistance with the electrode while maintaining the crystallinity.

  The semiconductor device according to the present invention is a semiconductor device composed of a compound semiconductor having a zinc blende structure and having a negative piezoelectric constant e14, and is composed of a compound semiconductor and has a main surface of (100). A substrate, a stripe-shaped insulating pattern formed of an insulator having compressive internal stress, extending in the [0-11] direction of the compound semiconductor and formed on the substrate, and a substrate adjacent to the insulating pattern And an ohmic electrode formed thereon.

  In the semiconductor device, the insulating pattern and the ohmic electrode are formed in contact with the substrate. Moreover, the semiconductor layer comprised from the compound semiconductor formed on the board | substrate is provided, and the insulating pattern and the ohmic electrode are formed in contact with the semiconductor layer. In addition, it is good to provide the two insulation patterns formed mutually spaced apart, and the ohmic electrode is arrange | positioned between two insulation patterns.

  The semiconductor device includes a source electrode and a drain electrode configured from ohmic electrodes, and a gate electrode formed between the source electrode and the drain electrode.

  As described above, in the present invention, a compressible material is formed on a substrate composed of a compound semiconductor having a zinc blende structure and having a negative piezoelectric constant e14 and having a main surface of (100). A stripe-shaped insulating pattern formed of an insulator with internal stress and extending in the [0-11] direction is provided, and an ohmic electrode is provided adjacent to the insulating pattern. As a result, according to the present invention, the contact with the electrode while maintaining good crystallinity of a semiconductor substrate or semiconductor layer made of a compound semiconductor material having a zinc blende structure such as GaAs and a negative piezoelectric constant e14. The resistance can be lowered.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following, the crystal direction and crystal plane are described as, for example, [0-11] and (100), but these include equivalent directions and equivalent planes, respectively.

[Embodiment 1]
First, the first embodiment of the present invention will be described. FIG. 1A is a plan view and FIG. 1B is a sectional view showing a partial configuration of a semiconductor device according to the first embodiment of the present invention. The semiconductor device according to the present embodiment includes a substrate 101 made of GaAs which is a compound semiconductor having a zinc blende structure and having a negative piezoelectric constant e14. The substrate 101 is made of, for example, semi-insulating GaAs having a p-type residual impurity concentration of about 1 × 10 ¹⁴ cm ⁻³ , and the main surface is a (100) plane. The normal of the surface of the substrate 101 is the [100] direction. The substrate 101 has a piezoelectric constant e14 of −0.16 C / m ² and a negative e14.

  The semiconductor device according to the present embodiment is made of an insulator with compressive internal stress, and extends in the [0-11] direction of GaAs (compound semiconductor) and is formed on the substrate 101. And a conductive region (electron gas) 102 including a region having a high electron concentration formed in the vicinity of the surface of the substrate 101 adjacent to the insulating pattern 111. In the present embodiment, two insulating patterns 111 are provided at a predetermined distance from each other, and the conductive region 102 is formed near the surface of the substrate 101 between the two insulating patterns 111. . Further, the conductive region 102 is formed to extend in the same direction as the insulating pattern 111 along the insulating pattern 111. As will be described later, the conductive region 102 is formed by a piezoelectric effect due to distortion formed on the surface of the substrate 101 by two insulating patterns 111.

  The insulating pattern 111 can be formed, for example, by depositing a silicon oxide film by a well-known CVD method and processing the deposited silicon oxide film by a known photolithography technique and etching technique. The insulating pattern 111 can also be formed by depositing a silicon oxide film by a sputtering method and processing the deposited silicon oxide film by a known photolithography technique and etching technique. Alternatively, the silicon oxide film may be processed and formed using a well-known lift-off method instead of the etching technique. As is well known, the insulating material formation (deposition) conditions can cause the deposited insulating material to have compressive internal stress, and according to general conditions, the deposited insulating material is It will be in the state provided with compressive internal stress. The insulating pattern 111 is not limited to silicon oxide, and may be made of an insulating material such as silicon nitride or titanium oxide.

  In addition, the semiconductor device in this embodiment includes an ohmic electrode 103 formed on the substrate 101 in a region where the conductive region 102 is formed, which is next to the insulating pattern 111. In this embodiment, as described above, the two insulating patterns 111 are provided, and the ohmic electrode 103 is provided on the substrate 101 between them. In the present embodiment, the insulating pattern 111 and the ohmic electrode 103 are formed on and in contact with the substrate 101.

The insulating pattern 111 is accompanied by (comes with) a compressive internal stress of 1 × 10 ⁹ N / m ² , for example, extends on the substrate 101 in the [0-11] direction, has a thickness of 1 μm, and a width of 1 μm. The two insulating patterns 111 are formed at an interval of 1 μm.

  The ohmic electrode 103 is made of, for example, AuGe / Ni, forms an ohmic contact with the substrate 101, and is electrically connected to the conductive region 102. For example, an ohmic electrode 103 may be formed by forming a Ni film by vapor deposition, forming an AuGe film thereon, and processing the laminated film by a lift-off method. Alternatively, the ohmic electrode 103 may be formed by selectively depositing these metal films at desired locations using a stencil mask or the like. In addition, the ohmic electrode 103 can be electrically connected to the conductive region 102 by performing a heat treatment at 350 ° C., for example, and an ohmic contact can be formed. The ohmic electrode 103 may be made of Ni / Ge.

  In the above description, the ohmic electrode 103 is formed on the substrate 101 between the two insulating patterns 111. However, the present invention is not limited to this. For example, as shown in the sectional view of FIG. 2, the ohmic electrode 203 may be formed on the substrate 101 so as to cross the two insulating patterns 111. Also in this case, the ohmic electrode 203 forms an ohmic contact with the substrate 101 between the two insulating patterns 111 and is electrically connected to the conductive region 102.

  Next, an FET using the ohmic electrode in this embodiment as a source electrode and a drain electrode will be described. As illustrated in the plan view of FIG. 3, this FET first has two striped insulating patterns 311 extending in the [0-11] direction of GaAs and spaced apart from each other on a substrate 301 made of GaAs. Is provided. In addition, this FET includes a source electrode 303 and a drain electrode 304 formed so as to cross the two insulating patterns 311. The substrate 301 is similar to the substrate 101, and the insulating pattern 311 is similar to the insulating pattern 111. The source electrode 303 and the drain electrode 304 are formed in the same manner as the ohmic electrode 203 described above.

  A gate electrode 305 is provided between the source electrode 303 and the drain electrode 304 so as to cross the two insulating patterns 311. In addition, a conductive region 302 having a high electron concentration is formed near the surface of the substrate 301 between the two insulating patterns 311. The gate electrode 305 may be formed by sequentially depositing Au and WSiN selectively at desired locations (gate electrode formation locations). The gate electrode 305 can be composed of WSiN, WSi, WN, or Ti / Pt / Au. For example, the gate electrode 305 is Schottky connected to the substrate 301 between the two insulating patterns 311.

  In this FET, a conductive region 302 is formed between the two insulating patterns 311 due to a piezoelectric effect due to distortion formed on the surface of the substrate 301 by the two insulating patterns 311. As a result, this FET has a low contact resistance (source resistance, drain resistance) between the source electrode 303 and the drain electrode 304, and has excellent transistor characteristics.

  In the above description, the gate electrode 305 is formed so as to cross over two (plural) insulating patterns 311, but the present invention is not limited to this, and between the two insulating patterns 311. A gate electrode 305 may be formed. However, the gate electrode 305 is formed so as to straddle the insulating pattern 311, so that the gate electrode 305 is in contact with the semiconductor layer (substrate 301) in a region where the conductive region 302 serving as a channel is not formed. Therefore, stray capacitance can be reduced, and higher-speed device operation is possible.

  Next, it extends in the [0-11] direction on a substrate made of a compound semiconductor having a zinc blende structure and having a negative piezoelectric constant e14 and having a main surface of (100). The formation of the insulating pattern to be performed will be described in detail with reference to FIG. FIG. 4 shows the difference between the bottom EC of the conduction band and the Fermi energy EF (EC−) in the substrate just below the substrate surface between the two insulating patterns (opening region) and in the substrate just below the insulating pattern (insulating film). EF) shows the location dependence.

  Since the stripe-shaped insulating pattern is accompanied by compressive internal stress, a stretchable strain occurs in the portion of the substrate covered with the insulating pattern as a result of the reaction of the stress of the insulating pattern (Non-Patent Document). 1). Since the piezoelectric constant e14 of the compound semiconductor constituting the substrate is negative and the insulating pattern is formed along the [0-11] direction or a direction equivalent thereto, the insulating pattern is formed by the piezoelectric effect. The electrostatic potential in the substrate at the portion is lowered, that is, the EC is increased (the electron gas surface density is significantly lowered).

  On the other hand, compressive strain occurs in the portion immediately below the opening region in the substrate that is adjacent to the insulating pattern. Due to this compressive strain, the electrostatic potential in the substrate in the open region increases, ie the EC decreases. In particular, an area where EC-EF <0 occurs in the vicinity of the insulating pattern. In this region, the concentration of the electron gas is remarkably high, and a conductive region including a high electron concentration region (COND) and a low electron concentration region is formed in the substrate in accordance with the arrangement of the striped insulating pattern. 1 and 2 schematically show this state. The same applies to FIGS. 5 and 6 used in the description below. 4 schematically shows a conductive region composed of a region having a high electron concentration and a region having a low electron concentration as shown in FIG.

  As described above, according to the present embodiment, by forming the insulating pattern, it is possible to form a region where the electron concentration is increased. In other words, the conductive region can be formed without introducing impurities. Since the conductive region is formed next to the insulating pattern formed extending in the [0-11] direction, it is sufficient to form one insulating pattern, and an ohmic electrode is formed next to the insulating pattern. If formed, the above-described region having a high electron concentration is formed, and a conductive region including a region having a high electron concentration is formed. Therefore, a low contact resistance state can be obtained.

  Here, when the extending direction of the insulating pattern differs by ± 45 ° from [0-11], the above-described effect cannot be obtained. In other words, the direction in which the insulating pattern extends becomes closer to [0-11] than ± 45 ° from [0-11] of the compound semiconductor having a zinc blende structure and having a negative piezoelectric constant e14. The above-described effect can be obtained higher, and the highest effect can be obtained when the extending direction of the insulating pattern matches [0-11].

  As described above, according to the present embodiment, impurities are not introduced by ion implantation or the like, and therefore, the stripe-shaped insulation is not subjected to high-temperature heat treatment such as activation annealing of the implanted ions. In accordance with the arrangement of the pattern 111, the conductive region 102 is locally formed. As a result, according to the present embodiment, the ohmic electrode 103 can be formed in the conductive region 102 without performing a high-temperature treatment such as activation annealing. An excellent ohmic contact with low contact resistance can be formed without causing a decrease.

[Embodiment 2]
Next, a second embodiment of the present invention will be described. FIG. 5 is a plan view (a) and a sectional view (b) showing a partial configuration of the semiconductor device according to the second embodiment of the present invention. The semiconductor device of the present embodiment includes a substrate 501 made of GaAs which is a compound semiconductor having a zinc blende structure and having a negative piezoelectric constant e14. The substrate 501 is made of, for example, semi-insulating GaAs having a p-type residual impurity concentration of about 1 × 10 ¹⁴ cm ⁻³ , and the main surface is a (100) plane. The normal of the surface of the substrate 501 is the [100] direction. The substrate 501 has a piezoelectric constant e14 of −0.16 C / m ² and a negative e14.

The semiconductor device of this embodiment includes a channel layer 502 made of GaAs and having a thickness of about 2 μm formed on a substrate 501 and a Schottky layer 503 made of AI _0.3 Ga _0.7 As and having a thickness of about 20 nm. . The channel layer 502 and the Schottky layer 503 are formed by sequentially growing (stacking) without introducing impurities by, for example, the MBE method or the MOCVD method. These may have an impurity concentration of about 1 × 10 ¹⁵ cm ⁻³ . The channel layer 502 has a piezoelectric constant e14 of −0.16 C / m ² and a negative e14. The Schottky layer 503 has a piezoelectric constant e14 of −0.18 C / m ² and also has a negative e14. Accordingly, the semiconductor multilayer structure including the substrate 501, the channel layer 502, and the Schottky layer 503 has a negative e14.

  In addition, the semiconductor device of the present embodiment is made of an insulator with compressive internal stress, extends in the [0-11] direction of GaAs (compound semiconductor), and is separated from each other on the substrate 501. A conductive region (electron gas) 504 having a high electron concentration formed in the channel layer 502 in the vicinity of the interface between the two stripe-shaped insulating patterns 511 formed in the first layer and the Schottky layer 503 between the two insulating patterns 511; Is provided. As described above, the conductive region 504 is formed by the piezoelectric effect due to the distortion formed in the semiconductor multilayer structure by the two insulating patterns 511.

  The insulating pattern 511 can be formed, for example, by depositing a silicon oxide film by a well-known CVD method and processing the deposited silicon oxide film by a known photolithography technique and etching technique. The insulating pattern 511 can also be formed by depositing a silicon oxide film by a sputtering method and processing the deposited silicon oxide film by a known photolithography technique and etching technique. Alternatively, the silicon oxide film may be processed and formed using a well-known lift-off method instead of the etching technique.

  As is well known, the insulating material formation (deposition) conditions can cause the deposited insulating material to have compressive internal stress, and according to general conditions, the deposited insulating material is It will be in the state provided with compressive internal stress. Note that the insulating pattern 511 is not limited to silicon oxide, and may be made of an insulating material such as silicon nitride or titanium oxide.

Further, the semiconductor device in this embodiment includes an ohmic electrode 505 formed on the Schottky layer 503 between the two insulating patterns 511. In the present embodiment, the ohmic electrode 505 is formed on the Schottky layer 503 so as to cross the two insulating patterns 511. The insulating pattern 511 includes (comes with) compressive internal stress of 1 × 10 ⁹ N / m ² , for example, extends on the Schottky layer 503 in the [0-11] direction, has a thickness of 1 μm, and a width of 1 μm. The two insulating patterns 511 are formed at an interval of 1 μm. In this embodiment mode, the insulating pattern 511 and the ohmic electrode 505 are formed in contact with a Schottky layer (semiconductor layer) 503 formed over the substrate 501.

  The ohmic electrode 505 is made of, for example, AuGe / Ni, forms an ohmic contact with the Schottky layer 503, and is electrically connected to the conductive region 504. For example, an ohmic electrode 505 may be formed by forming a Ni film by vapor deposition, forming an AuGe film thereon, and processing these laminated films by a lift-off method. Alternatively, the ohmic electrode 505 may be formed by selectively depositing these metal films at desired locations using a stencil mask or the like. Further, the ohmic electrode 505 can be electrically connected to the conductive region 504 by performing a heat treatment at 350 ° C., for example, and an ohmic contact can be formed.

  Also in this embodiment, as in the first embodiment described above, the striped insulating pattern 511 is accompanied by compressive internal stress. For this reason, in the semiconductor multilayer structure composed of the channel layer 502 and the Schottky layer 503, stretchable strain is generated as a result of the reaction of the stress of the insulating pattern 511 in the portion covered with the insulating pattern 511. The semiconductor multilayer structure has negative e14, and the insulating pattern 511 is formed along the [0-11] direction or a direction equivalent thereto. As a result, in the region below the insulating pattern 511, the electrostatic potential is reduced by the piezoelectric effect, that is, the electron gas surface density is significantly reduced.

  On the other hand, in the semiconductor multilayer structure between the insulating patterns 511, compressive strain occurs. Due to this compressive strain, the electrostatic potential in the semiconductor multilayer structure in the portion between the insulating patterns 511 increases, and a region having a remarkably high electron gas concentration is formed particularly in the vicinity of the insulating pattern 511. That is, similarly to the first embodiment described above, also in the second embodiment, a conductive region 504 including a region having a high electron concentration and a region having a low electron concentration is formed in the semiconductor multilayer structure in accordance with the arrangement of the insulating pattern 511. The As a result, the conductive region 504 is formed in the channel layer 502 in the vicinity of the interface with the Schottky layer 503 between the two insulating patterns 511.

  As described above, also in the second embodiment, impurities are not introduced by ion implantation or the like, and therefore, the stripe-like insulating pattern 511 is not subjected to high-temperature heat treatment such as activation annealing of the implanted ions. In accordance with the arrangement of the conductive region 504, the conductive region 504 is locally formed. As a result, according to the present embodiment, the ohmic electrode 505 can be formed in the conductive region 504 without performing a high-temperature treatment such as activation annealing. An excellent ohmic contact with low contact resistance can be formed without causing a decrease.

  Next, an FET using the ohmic electrode in this embodiment as a source electrode and a drain electrode will be described with reference to FIG. FIG. 6 is a plan view (a), cross-sectional views (b), and (c) showing the configuration of the FET as the semiconductor device in the present embodiment. This FET first includes four striped insulating patterns 611 extending in the [0-11] direction of GaAs and spaced apart from each other on a substrate 601 made of GaAs. In addition, the FET includes a source electrode 605 and a drain electrode 606 formed so as to cross the four insulating patterns 611. The substrate 601 is the same as the substrate 501 shown in FIG. 5, and the insulating pattern 611 is the same as the insulating pattern 511 shown in FIG. The source electrode 605 and the drain electrode 606 are formed in the same manner as the ohmic electrode 505 described above.

  Further, a gate electrode 607 formed between the source electrode 605 and the drain electrode 606 so as to cross the four insulating patterns 611 is provided, and a channel layer 602 in the vicinity of the interface between the two insulating patterns 611 and the Schottky layer 603 is provided. A conductive region (electron gas) 604 including a region having a high electron concentration and a region having a low electron concentration is formed. The gate electrode 607 may be formed by sequentially depositing Au and WSiN at desired locations (gate electrode formation locations) sequentially. For example, the gate electrode 607 is in Schottky connection with the Schottky layer 603 between the four insulating patterns 611. This FET has a low contact resistance (source resistance, drain resistance) of the source electrode 605 and the drain electrode 606, and has excellent transistor characteristics.

In the above description, the case where the insulating pattern has a compressive internal stress of 1 × 10 ⁹ N / m ² has been described. However, the present invention is not limited to this, and it is also clear from the description using FIG. As such, the insulating pattern only needs to have compressive internal stress. As described above, an insulating material formed by a known manufacturing method such as a sputtering method or a CVD method has compressible internal stress under general manufacturing conditions. Therefore, the insulating pattern is not limited to silicon oxide, and insulating materials such as silicon nitride, titanium oxide, other oxides, and nitrides can be applied.

  In addition, a layer of metal (for example, tungsten) having compressive internal stress may be formed on the insulating pattern in the same manner as the insulating pattern. In general, it is known that the compressive internal stress of a metal such as tungsten is larger than the internal stress of an insulating pattern. For this reason, by forming a metal layer on the insulating pattern, the above-described effects of the present invention can be further increased. For example, it is possible to increase the electron concentration in the conductive region and to reduce the thickness of the insulating pattern for realizing a desired electron concentration. In addition, since the metal layer is formed on the insulating pattern and does not contact the layer below the insulating pattern, for example, as described above, the metal layer is formed on the layer below the insulating pattern. Does not affect the operation.

Here, the decrease in the electrostatic potential in the region where the insulating pattern is formed changes according to a value obtained by multiplying the stress (film stress) provided in the insulating pattern by the film thickness. Film stress × film thickness = 2 × 10 ⁸ N / m ² × 1 μm or more is effective because EC-EF <0 in the compound semiconductor layer near the insulating pattern. When the internal stress of the insulating pattern is larger than film stress × film thickness = 1 × 10 ⁹ N / m ² × 10 μm, the crystal of the semiconductor layer is distorted, crystal defects are induced, and the crystal quality is deteriorated. There is. Accordingly, the film stress × film thickness is preferably smaller than 1 × 10 ⁹ N / m ² × 10 μm.

  In the above description, each electrode is formed after the insulating pattern is formed. However, the present invention is not limited to this. After an ohmic electrode is formed on a compound semiconductor substrate or compound semiconductor layer having a zinc blende structure and a negative piezoelectric constant e14, a region where the ohmic electrode is not formed, for example, an ohmic electrode Next, an insulating pattern may be formed.

  In addition, the present invention is not limited to the semiconductor device having the above-described form, and various changes may be made in the ohmic contact formation method such as the ohmic electrode structure and heating conditions, and the source electrode, drain electrode, and gate electrode formation method. It is needless to say that even when the is added, it is included in the present invention. The present invention is not limited to GaAs, and other compound semiconductors having other zinc blende structures such as InP, InSb, InAs, GaP, GaSb, and AlAs and having a negative piezoelectric constant e14, and mixed crystals thereof. It can also be applied to a semiconductor multilayer structure composed of these. This is clear from the description using FIG.

1A is a plan view illustrating a partial configuration of a semiconductor device according to a first embodiment of the present invention, and FIG. It is sectional drawing which shows a partial structure of the semiconductor device in Embodiment 1 of this invention. It is a top view which shows a partial structure of the semiconductor device (FET) in Embodiment 1 of this invention. Location of difference (EC-EF) between energy EC and Fermi energy EF at the bottom of the conduction band in the substrate immediately below the substrate surface between the two insulating patterns (opening region) and in the substrate immediately below the insulating pattern (insulating film) It is a band figure which shows dependence. It is the top view (a) and sectional drawing (b) which show a partial structure of the semiconductor device in Embodiment 2 of this invention. It is the top view (a), sectional drawing (b), and (c) which show the structure of FET as a semiconductor device in this Embodiment. It is sectional drawing which shows the structural example of the n-type field effect transistor using a GaAs type material. It is sectional drawing which shows the structural example of the n-type field effect transistor using a GaAs type material.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 101 ... Board | substrate, 102 ... Conductive area | region (electron gas), 103 ... Ohmic electrode, 104 ... Insulation pattern.

Claims (5)

In a semiconductor device composed of a compound semiconductor having a sphalerite structure and having a negative piezoelectric constant e14,
A substrate made of the compound semiconductor, the main surface of which is a (100) plane;
A stripe-shaped insulating pattern formed of an insulator with compressive internal stress, extending in the [0-11] direction of the compound semiconductor and formed on the substrate;
An ohmic electrode formed on the substrate adjacent to the insulating pattern. The semiconductor device according to claim 1,
The semiconductor device, wherein the insulating pattern and the ohmic electrode are formed in contact with the substrate. The semiconductor device according to claim 1,
A semiconductor layer composed of the compound semiconductor formed on the substrate;
The semiconductor device, wherein the insulating pattern and the ohmic electrode are formed in contact with the semiconductor layer. The semiconductor device according to any one of claims 1 to 3,
Two insulating patterns formed apart from each other,
The ohmic electrode is disposed between the two insulating patterns. A semiconductor device, wherein: The semiconductor device according to any one of claims 1 to 4,
A source electrode and a drain electrode composed of the ohmic electrode;
A semiconductor device comprising: a gate electrode formed between the source electrode and the drain electrode.

Images