JP2009201311A - Control device for power converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a failure detection system that greatly reduces a delay time of failure detection output. <P>SOLUTION: A power converter 3 is composed by connecting a plurality of semiconductor switching elements 300 between the positive side and the negative side of a DC constant voltage source so as to output a potential level of a DC voltage source by selecting the potential level by a combination of ON-OFF states of the semiconductor switching elements 300. A control device 1 outputs a control command signal to a drive circuit for driving the individual semiconductor switching elements in the power converter. The control device includes a delay function part 21 for generating a delay time with respect to the control command signal, and a discrepancy detection part 400 that compares determination information output, generated by determining whether the switching elements are driven to the ON-side or driven to the OFF-side from an operating state that the drive circuit 200 drives the switching elements corresponding to the control command signal, with output of the delay function part 21 and determines as abnormal operation of the drive circuit 200 or the switching elements 300 themselves when a discrepancy state exceeding a prescribed window time occurs. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a power converter control device, and more particularly to a device that detects a drive abnormality of a semiconductor switch element of a power converter constituted by a semiconductor switch element used for controlling a driving motor in a railway vehicle or the like.

  In power converters such as inverter devices used to control drive motors for railway vehicles, etc., power control is performed for high voltage and large current. May be severely destroyed. Therefore, when the semiconductor switching element operates abnormally, it is necessary to stop the device as soon as possible and avoid damage to the device. For this reason, the control command signal for the drive circuit that drives the semiconductor switching element is compared with the driver operation information that detects the operation state in which the drive circuit drives the switching element to turn on or off, and the drive is performed when a mismatch occurs. An abnormality detection method for determining an abnormal operation of the circuit is adopted.

FIG. 4 shows an example of a system in which this abnormality detection is performed. Although the number of switching elements varies depending on the power converter system, this figure shows a case where there are two switching elements.
The configuration will be described with reference to the drawings. The power converter control device 1 uses the control signal generated by the control signal generator 4 as individual control information PWM0 and PWM1 for the individual IGBTs (insulated gate bipolar transistors) 300 and 310 constituting the power converter 3. This is output to the drive circuits 200 and 210 of the IGBT. Control information PWM0 and PWM1 for the IGBTs 300 and 310 are shaped in the drive circuits 200 and 210, and the semiconductor switching elements IGBT300 and 310 constituting the power converter 3 are driven. Further, the on / off operation state of the IGBTs 300 and 310 is determined in the drive circuits 200 and 210, and the information FB0 and FB1 is fed back to the control device 1 and compared with the control command signal in the mismatch detection units 400 and 410. Detection is taking place. The abnormality detected signal is transmitted to the control signal generating unit 4 via the logical sum function 20, and the generation of the control signal is stopped when the abnormality is detected. The above shows the case where there are two series corresponding to the switching elements. However, even if there are a larger number of series corresponding to the switching elements, the abnormal signals are integrated via the OR function 20 and the control command signal generator 4 The point of stopping is unchanged.

  FIG. 5 is a diagram showing one series corresponding to IGBT 300 in the configuration of the conventional example of FIG. 4 in more detail. This will be described in more detail with reference to the drawings. Inside the control device 1, a control command signal PWMP corresponding to the control of the power converter 3 and corresponding to ON / OFF of the IGBT is output from the control command signal generator 4, and the light control signal PWM 0 is output from the electro-optical converter 5. The signal is transmitted to the drive device 200 via the optical fiber 6. The optical fiber 6 is for obtaining electrical insulation between the power converter 3 which is a high voltage circuit and the control device 1 which is an electronic circuit. In the drive device 200, the control command PWM0 is converted into an electric signal again by the photoelectric converter 7, and is shaped by the waveform shaping circuit 8 into a waveform DS that is electrically matched in the drive circuit. As a result, the IGBT 300 is driven as the drive signal GS. On the other hand, the determination function 10 monitors the drive signal GS to determine whether the IGBT is driven on or off, and the determination information DFB includes the logic inversion function 11, the electro-optical converter 12, the light The feedback signal FB is provided to the mismatch detection unit 400 via the fiber 13, the photoelectric converter 14, and the logic inversion function 15. In the mismatch detection unit 400, when the control command signal PWMP and the feedback signal FB are input to the EOR function 16 for mismatch detection, and the mismatch signal NE is continuously output for more than the delay time output DL of the delay time timer 17, the AND function The abnormality signal DT is output via 18, and the abnormality signal CFD is output by the abnormality detection / holding function 19, which is transmitted via the logical sum function 20 together with other series of abnormality signals to control the control command signal generator 4. Command signal PWMP output is stopped.

  The series corresponding to the IGBT 310 is configured in exactly the same way, and the detected abnormal signal CFD is made into one signal through the OR function 20, and the control command signal of the control command signal generator 4 is stopped.

  FIG. 6 shows operation waveforms of the conventional example. FIG. 6A shows the operation when the control command signal changes from OFF to ON when there is no abnormality in this configuration. Assume that at time A, a signal is output from the control signal generator to switch the IGBT from OFF to ON. In this case, the signal GS changes from OFF to ON at the time after the time Tpg1 due to the operation delay of the circuit from the signal PWMP to the signal GS in FIG. Similarly, the change in the signal FB changes from OFF to ON at time B after time Tgf1 due to the operation delay of the circuit from the signal GS to the signal FB in FIG. Since the signal FB is compared with the signal PWMP by the EOR function 16 for mismatch detection, a signal corresponding to the mismatch appears in the signal NE from the time A to the time B due to the delay of the sum of the time Tpg1 and the time Tgf1. Is before the set time C by the grace time output Tex of the grace time output DL of the grace time timer 17 for the mismatch, it is masked by the AND function 18 and the abnormality detection holding function 19 is not set, and the output CFD is not set. No abnormal signal appears. That is, when there is no abnormality in the configuration, no abnormality signal is output. What is important here is that, in order to avoid false detection, the above-mentioned grace period Tex needs to be set longer than the maximum value expected in the entire range of the use environment conditions for the total time Tpg1 + Tgf1. . It is set in consideration of error, aging, safety factor, etc.

  Similarly (FIG. 6b) shows the operation when the control command signal changes from on to off when there is no abnormality in this configuration. Assume that the signal PWMP is output from the control signal generator 4 to switch the IGBT from on to off at time A, as in FIG. 6A. Similar to (FIG. 6a), the total time of Tpg0 and Tgf0, that is, time A and time, is applied to the EOR function 16 for mismatch detection by the operation delay time of the circuit from the signal PWMP through the signal GS to the signal FB. During B, a signal corresponding to the mismatch appears in the signal NE and is masked because it is before the set time C of the delay time output DL of the delay time output DL of the delay time timer 17 for the mismatch, and the abnormality detection holding function 19 is set. No abnormal signal appears in the output CFD. Here again, it can be seen that in order to avoid erroneous detection, the above-mentioned grace period Tex needs to be set longer than the maximum value in the total range of the total time Tpg0 + Tgf0 use environment conditions.

  FIG. 6C shows a case where the driver circuit output GS is turned on even when the control command signal is turned off and continues longer than the grace time Tex of the grace time timer. When the GS operates abnormally at time A, this is detected by the determination function 10 in FIG. 5, and after an operation delay time Tgf1 of the circuit up to FB, the FB changes from OFF to ON at time B. Since this FB is compared with PWMP by the EOR function 16 for mismatch detection, the mask by the AND function is released at the time C after the lapse of the grace time Tex, the abnormality detection holding function 19 is set, and an abnormal signal appears in the CFD. In this way, an abnormality is detected.

  In the conventional example, the abnormality detection signal CFD is output at the time of abnormality as described above. However, as apparent from the above description, the detection signal cannot be output unless a long time of Tex has elapsed after the abnormality signal appears on the FB. That is, there is a problem that the detection signal is delayed in the case of an abnormality related to damage to the device such as an abnormal operation of the switching element.

  The essence of the above-described conventional abnormality detection system is a system based on the concept of monitoring whether command information on the PWMP has changed as viewed on the FB. Therefore, according to the original purpose, the information generated on the PWMP is transmitted and fed back with an operation delay time. Therefore, the command information as the information source and the time of the feedback signal as a result are matched. Should be compared. That is, the information appearing on the FB is generated on the PWMP before Tpg1 + Tgf1 or Tpg0 + Tgf0 in terms of time due to transmission delay, and the command information before that delay time should be compared with the FB. In the conventional example, the information appearing on the FB is monitored and verified by ignoring that the information generated on the PWMP appears with a delay of Tpg1 + Tgf1 or Tpg0 + Tgf0. For this reason, it is necessary to set a large detection delay time Tex, which is a delay in outputting an abnormal signal.

  An object of the present invention is to provide an abnormality detection method that corrects the above-mentioned unreasonable points and greatly reduces the delay time of abnormality detection output.

  In order to achieve the above object, in the abnormality detection method according to the present invention, the control command signal is converted into a signal having a delay equivalent to the time required for the signal to be transmitted and fed back, and fed back with this. By comparing the signal with the control command signal that is the source of information and the feedback information that appears as a result, the detection delay time is reduced and the delay time of the abnormality detection output is greatly shortened. It was.

  That is, the present invention is configured by connecting a plurality of semiconductor switching elements between the positive side and the negative side of the DC constant voltage source, and the potential of the DC voltage source is determined by the combination of the on / off states of the plurality of semiconductor switching elements. In a power converter that outputs a control command signal to a drive circuit that drives each semiconductor switching element in a power converter that selects and outputs a level, a predetermined delay time is provided for the control command signal. A delay function unit to be generated, and a determination information output for determining whether the drive circuit is driven on or off from the operating state in which the drive circuit is driving the switching element in response to the control command signal When comparing with the output of the delay function unit and a mismatch state occurs for a predetermined grace period or longer, the drive circuit or the switch A power converter control apparatus and a malfunction and determines mismatch detection unit of grayed element itself.

  The present invention is the power converter control device in which the determination information output and the output of the delay function unit are matched and compared based on a delay time generated by the delay function unit.

  In the present invention, the magnitude of the delay time generated by the delay function unit is determined by the determination function unit detecting the operation of the drive circuit corresponding to the output of the control command signal. The time required to reach the mismatch detection unit The average value of the maximum and minimum values among the values that vary depending on the usage environment conditions, and the time until the control command signal reaches the mismatch detection unit via the delay function This is a power converter control device that is set to be approximately the same.

  Further, according to the present invention, the predetermined grace period depends on the use environment condition, since the drive circuit operates after the control command signal is output and the determination function detects and the operation detection signal reaches the mismatch detection unit. This is a power converter control device that is set to ½ or more of the maximum fluctuation amount.

  In addition, the present invention maintains the abnormality detection information even when the inconsistency state disappears after the inconsistency state longer than the predetermined grace period, and the semiconductor switching element in the power converter is detected by the abnormality detection information. It is a power converter control apparatus which outputs the control command which turns off.

  As described above, according to the present invention, information on an abnormality that has occurred in the drive circuit can be received and determined as an abnormality in a short grace period, so that the protection operation against the abnormality can be activated quickly, and system damage due to the abnormality can be minimized. Can be suppressed.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows an example of a system in which this abnormality detection is performed. Although the number of switching elements varies depending on the power converter system, this figure shows a case where there are two switching elements.
The configuration will be described with reference to the drawings. The power converter control device 1 outputs the control signal generated by the control signal generating unit 4 to the individual IGBTs 300 and 310 constituting the power converter 3 as control information PWM0 and PWM1 to the drive circuits 200 and 210 of the individual IGBTs. is doing. The control information for the IGBT is shaped in the drive circuits 200 and 210, and the semiconductor switching elements IGBT 300 and 310 constituting the power converter 3 are driven. Further, the on / off operation state of the IGBT is determined in the drive circuits 200 and 210, and the information FB0 and FB1 is fed back to the control device 1, and the signal DP0 and the control command signal delayed by a predetermined time in the mismatch detection units 400 and 410, Abnormality detection is performed in comparison with DP1. The abnormality detected signal is transmitted to the control signal generating unit 4 via the logical sum function 20, and the generation of the control signal is stopped when the abnormality is detected. The above shows the case where there are two series corresponding to the switching elements. However, even if there are more series corresponding to the switching elements, abnormal signals are integrated via the OR function 20 and the control command signal generation unit 4 is stopped. There is no change in the point of performing.

  FIG. 2 is a diagram showing one series corresponding to IGBT 300 in the configuration of FIG. 1 in more detail. This will be described in more detail with reference to the drawings. Inside the control device 1, a control command signal PWMP corresponding to the control of the power converter 3 and corresponding to ON / OFF of the IGBT 300 is output from the control command signal generator 4, and the electro-optic converter 5 controls the light control signal PWM 0. Is transmitted to the drive device 200 via the optical fiber 6. The optical fiber 6 is used to provide electrical insulation between a power converter that is a high-voltage circuit and a control device that is an electronic circuit. In the drive device 200, the control command is converted again into an electric signal by the photoelectric converter 7, and is shaped into a waveform DS that is electrically matched in the drive device 200 by the waveform shaping circuit 8, and this is converted into the AMP circuit 9. As a result, the IGBT 300 is driven as the drive signal GS. On the other hand, the determination function 10 monitors the signal GS to determine whether the IGBT 300 is driven on or off. The determination information DFB includes the logic inversion function 11, the electro-optic converter 12, the optical fiber 13, and the optical signal. The feedback signal FB is provided to the mismatch detection unit 400 via the electrical converter 14 and the logic inversion function 15. In the mismatch detection unit 400, the signal DP 0 and the signal FB obtained by delaying the control command signal PWMP by a predetermined time by the delay function 21 are input to the EOR function 16 for mismatch detection, and the mismatch signal NE is output from the delay time output DL of the delay time timer 17. If the signal is continuously output as described above, the abnormality signal DT is output via the AND function 18, and the abnormality signal CFD is output by the abnormality detection / holding function 19. At the same time, the output of the control command signal PWMP of the control command signal generator 4 is stopped.

Here, it is defined as follows.
Tpg0 = time until the control command signal PWMP changes from on to off and is transmitted to the drive device 200 and is output as the signal GS Tgf0 = the information is changed to the signal FB after the drive signal GS of the IGBT 300 changes from on to off Time Tpg1 = Time until control command signal PWMP changes from OFF to ON and is transmitted to drive device 200 and is output as signal GS Tgf1 = Time after drive signal GS of IGBT 300 changes from OFF to ON Time until information appears in signal FB

In addition, these times vary depending on the usage environment, for example, ambient temperature, power supply voltage, voltage and current applied to the switching element, etc.
When Tmax = ((Tpg1 + Tgf1) or (Tpg0 + Tgf0)) is defined as the longest time Tmin = ((Tpg1 + Tgf1) or (Tpg0 + Tgf0)), the delay time Tpf of the delay function 21 is as follows: Designed to.
Tpf≈ (Tmax + Tmin) / 2 (1)
The grace time Tex ′ of the grace time timer 17 is
Tex ′> Tmax−Tpf and Tex ′> Tpf−Tmin (2)
Designed with.

  The series corresponding to the IGBT 310 is configured in exactly the same way, and the detected abnormal signal is converted into one signal via the OR function 20, and the control command signal of the control command signal generation unit 4 is stopped.

  FIG. 3 shows an example of operation waveforms of the embodiment of the present invention. FIG. 3A shows the operation when the control command signal PWMP changes from OFF to ON when there is no abnormality in this configuration. Assume that at time A, a signal is output from the control signal generation unit 4 to switch the IGBT 300 from OFF to ON. In this case, the signal GS changes from OFF to ON at the time after the time Tpg1 due to the operation delay of the circuit from the signal PWMP to the signal GS in FIG. Similarly, the change in the signal FB changes from OFF to ON at time B after time Tgf1 due to the operation delay of the circuit from the signal GS to the signal FB in FIG. Since the signal FB is compared with the signal DP0 in which the signal PWMP has been delayed by the time Tpf by the delay circuit 21 by the EOR function 16 for mismatch detection, the total delay time and time of the time Tpg1 and Tgf1 described above are compared. A signal corresponding to the discrepancy appears in the signal NE from the difference in delay time of Tpf, that is, from time B ′ to time B. The signal NE is masked by the AND function 18 because it is included in the setting of the grace time Tex 'of the grace time output DL of the grace time timer 17 for mismatch due to the relationship of the above equations (1) and (2). Therefore, the abnormality detection holding function 19 is not set, and no abnormality signal appears in its output CFD. That is, when there is no abnormality in the configuration, no abnormality signal is output. What is important here is that the above-described grace time Tex ′ for avoiding false detection is designed as shown in Expression (2), so that the time Tex of the above-described conventional example is Tmax, that is, the longest time of (Tpg1 + Tgf1). While it was necessary to set longer, it is greatly shortened.

  Similarly (FIG. 3b) shows the operation when the control command signal PWMP changes from on to off when there is no abnormality in this configuration. It is assumed that the signal PWMP is output from the control signal generation unit 4 to switch the IGBT 300 from on to off at time A as in FIG. In this case as well (FIG. 3a), the signal FB is compared with the signal DP0 in which the signal PWMP is delayed by the time Tpf by the delay circuit 21 by the EOR function 16 for mismatch detection. During the difference between the delay time of Tpg0 and time Tgf0 and the delay time of time Tpf, that is, from time B ′ to time B, a signal corresponding to the discrepancy appears in the signal NE. At this time, as described above, the signal NE is included in the setting of the grace time Tex ′ of the grace time output DL of the grace time timer 17 for the mismatch from the relationship of the above expressions (1) and (2). 18, the abnormality detection holding function 19 is not set, and no abnormality signal appears in its output CFD. Also here, the grace time Tex 'for avoiding erroneous detection is greatly shortened by being designed as shown in Expression (2).

  FIG. 3C shows a case where the driver circuit output GS is turned on and continues longer than the grace time Tex ′ of the grace time timer 17 even though the control command signal PWMP is turned off. When the signal GS operates abnormally at time A, this is detected by the determination function 10 of FIG. 2, and after the operation delay time Tgf1 of the circuit up to the signal FB, the signal FB changes from OFF to ON at time B. Since the signal FB is compared with the signal DP0 by the EOR function 16 for mismatch detection, the mask by the AND function 18 is released at the time C after the lapse time Tex ′ has elapsed, the abnormality detection holding function 19 is set, and the signal CFD is set. An abnormal signal appears in. In this way, an abnormality is detected.

  In this embodiment, as described above, the control command signal PWMP is converted into a signal having a delay equivalent to the time required for the signal to be transmitted and fed back, and this is compared with the fed back signal. As a result, the control command signal that is the source of information and the feedback information that appears as a result are aligned at approximately the same time, and the detection delay time is reduced. Therefore, after the abnormal signal appears in the signal FB, the time Tex ′ is short. After a lapse of time, the abnormality detection signal CFD can be output, and the protection operation of the system can be operated much faster than the conventional example.

The block diagram which shows embodiment of this invention. The block diagram which shows the detail of FIG. The figure which shows the operation | movement waveform by FIG. The block diagram which shows embodiment of a prior art example. The block diagram which shows the detail of FIG. The figure which shows the operation | movement waveform by FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Control apparatus, 3 ... Power converter, 4 ... Control signal generation part, 5, 12 ... Electro-optical converter, 6, 13 ... Optical fiber, 7, 14 ... Photoelectric converter, 8 ... Waveform shaping circuit, 9 ... AMP circuit, 10 ... Determination function, 11, 15 ... Logic inversion function, 16 ... EOR function, 17 ... Delay time timer, 18 ... AND function, 19 ... Abnormality detection holding function, 20 ... OR function, 21,22 ... Delay function, 200, 210... Drive circuit, 300, 310... IGBT, 400, 410.

Claims (5)

A plurality of semiconductor switching elements are connected between a positive side and a negative side of a DC constant voltage source, and a potential level of the DC voltage source is selected and output by a combination of on / off states of the plurality of semiconductor switching elements. In a power converter control device that outputs a control command signal to a drive circuit that drives individual semiconductor switching elements in the power converter,
A delay function unit that generates a predetermined delay time with respect to the control command signal, and the drive circuit is driven on or off from an operating state in which the drive circuit is driving the switching element in response to the control command signal. Compared with the determination information output for determining whether or not the drive circuit is operating and the output of the delay function unit, and when a mismatch occurs for a predetermined delay time or more, it is determined that the drive circuit or the switching element itself is abnormal operation A power converter control device comprising: a detection unit.   The power converter control device according to claim 1, wherein the determination information output and the output of the delay function unit are compared and matched by a delay time generated by the delay function unit.   The magnitude of the delay time generated by the delay function unit is determined by the determination function unit detecting the corresponding operation of the drive circuit after the control command signal is output, and the determination information reaches the mismatch detection unit. The average time of the maximum and minimum values among the values that vary depending on the usage environment conditions, and the time until the control command signal reaches the mismatch detection section via the delay function are almost equal. The power converter control device according to claim 1 to set.   The predetermined delay time is the maximum amount of fluctuation in which the drive circuit operates after the control command signal is output and the determination function detects and the time required for the operation detection signal to reach the mismatch detection unit varies depending on the use environment conditions The power converter control device according to claim 1, wherein the power converter control device is set to ½ or more. When a non-matching normal state longer than the predetermined grace time occurs, even if the non-matching state disappears thereafter, the abnormality detection information is retained and a control command for turning off the semiconductor switching element in the power converter is output based on the abnormality detection information The power converter control device according to claim 1.

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