JP2009200825A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit for reducing noise generated in the resistance voltage dividing circuit of a 2-stage configuration. <P>SOLUTION: A voltage dividing part 1 includes resistors R10-R17 serially connected between an input terminal IN and a grounding terminal AGND and analog switches S10-S17 connected in parallel between the respective connection points and an output terminal O1, and a voltage dividing part 2 includes resistors R20-R25 serially connected between the output terminal O1 and grounding terminal AGND of the voltage dividing part 1 and analog switches S20-S25 connected in parallel between the respective connection points and the output terminal OUT. A switch control part 3 controls the conduction of each of analog switches S10-S17 and analog switches S20-S25 so that the conduction time of the analog switch which outputs the lowest impedance in the view from the grounding potential may become longer than the conduction time of the other analog switches in each of the analog switches S10-S17 and the analog switches S20-S25. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit.

  There is an electronic volume as a semiconductor integrated circuit that digitally adjusts the volume of an audio product.

  As a conventional circuit of such an electronic volume, the input voltage is divided by a resistor connected in series, and a switch connected to each voltage dividing point is controlled by a digital signal for volume setting to obtain a desired divided voltage. An output circuit is used.

  In the case of the electronic volume having the above-described configuration, a transient abnormal voltage is output when the switch is switched, and noise may occur in the reproduced sound.

  When an analog switch having a CMOS transistor configuration is used as a switch, the electric charge accumulated in a parasitic capacitance such as a capacitance (mirror capacitance) formed between the gate and drain of the MOS transistor generates such a transient abnormal voltage. It becomes a factor.

  Conventionally, in order to prevent such noise, it has been proposed to provide two switches connected to each resistance voltage dividing point, and control to switch between the switches with a predetermined time constant (for example, (See Patent Document 1).

  By the way, when the volume adjustment by the resistance voltage dividing circuit and the analog switch is performed finely in multiple stages, the resistance voltage dividing circuit has a two-stage configuration of an upper stage and a lower stage, and the upper stage changes in large increments (for example, in units of -8 db). The lower stage is configured to change the interval between the upper stages in fine increments (for example, in units of -1 db). By adopting such a circuit configuration, it is possible to reduce the number of elements of the semiconductor integrated circuit and to provide a highly accurate divided voltage as compared with the case where the circuit is constituted by a single-stage resistance voltage dividing circuit.

When such a two-stage resistance voltage dividing circuit is used, when switching of the analog switch of the upper-stage resistance voltage dividing circuit and switching of the analog switch of the lower-stage resistance voltage dividing circuit occur simultaneously, the parasitic of the MOS transistor There arises a problem that noise due to the capacitance is generated for four analog switches. In particular, the on / off timing of the analog switch with the highest impedance seen from the ground terminal among the analog switches in the lower stage and the on / off timing of the analog switch with the lowest impedance seen from the ground terminal among the analog switches in the upper stage When the / OFF timing overlaps, it takes time to discharge the charge accumulated in the parasitic capacitance of the upper-stage analog switch, and the noise potential increases.
JP 2001-36361 A (page 4, FIG. 1)

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit capable of reducing noise generated in a two-stage resistance voltage dividing circuit.

  According to one aspect of the present invention, a plurality of first resistors connected in series between an input terminal and a ground potential terminal, each connection point of the plurality of first resistors, and a first voltage dividing output terminal A first voltage dividing means having a first switch group connected in parallel with each other, and a plurality of second voltage connected in series between the first voltage dividing output terminal and the ground potential terminal. A second voltage dividing means comprising: a second resistance group; and a second switch group connected in parallel between each connection point of the plurality of second resistors and a second voltage dividing output terminal; Switch control means for controlling conduction of each switch of the first switch group and the second switch group, and the switch control means is viewed from the ground potential in each of the first switch group and the second switch group. The conduction time of the switch that outputs the lowest impedance The semiconductor integrated circuit and controls to be longer than the time is provided.

  According to the present invention, it is possible to reduce noise generated in a two-stage resistive voltage dividing circuit.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing an example of the configuration of a semiconductor integrated circuit according to an embodiment of the present invention.

  The semiconductor integrated circuit of this embodiment is connected in parallel between resistors R10 to R17 connected in series between the input terminal IN and the ground terminal AGND, and connection points of the resistors R10 to R17 and the output terminal O1. Voltage divider 1 having analog switches S10 to S17, resistors R20 to R25 connected in series between output terminal O1 of voltage divider 1 and ground terminal AGND, and connection points of resistors R20 to R25 Voltage divider 2 having analog switches S20 to S25 connected in parallel with output terminal OUT, analog switches S10 to S17 of voltage divider 1 and analog switches S20 to S25 of voltage divider 2 And a switch control unit 3 that controls the conduction of.

  The switch control unit 3 includes a decoder unit 31 and a conduction control signal generation unit 32.

  The decoder unit 31 selects one of the analog switches S10 to S17 of the voltage dividing unit 1 and one of the analog switches S20 to S25 of the voltage dividing unit 2 according to the setting of the DATA signal input from the input terminal DATA. Decode output signals P10 to P17 and P20 to P25 are output so as to be conducted simultaneously.

  The continuity control signal generator 32 is a switch that outputs the lowest impedance when viewed from the ground potential in each of the analog switches S10 to S17 and the analog switches S20 to S25, that is, the continuity time of the analog switch S10 and the analog switch S20. The delay times are adjusted between the decode output signals P10 and P11 to P17 and between the decode output signals P20 and P21 to P25 so as to be longer than the conduction time of the analog switch, and the conduction control signals Q10, Q11 to Q17 are adjusted. And Q20 and Q21 to Q25 are output.

  FIG. 2 shows an example of a specific circuit configuration of the switch control unit 3.

  The decoder unit 31 decodes the DATA signals D11, D12, and D13 that set the output value of the voltage dividing unit 1 and outputs decoded output signals P10 and P11 to P17, and sets the output value of the voltage dividing unit 2. A decoder 312 that decodes the DATA signals D21, D22, and D23 to output the decoded output signals P20 and P21 to P25.

  FIG. 3 is a truth table showing the input / output relationship between the decoder 311 and the decoder 312.

  FIG. 3A is a truth table of the decoder 311. Here, it is assumed that the amount of attenuation is adjusted by 1 dB in the voltage dividing unit 1. When the amount of attenuation is designated by the DATA signals D11, D12, and D13, any one of the decoded output signals P10 to P17 is set to “1” accordingly. Become.

  FIG. 3B is a truth table of the decoder 312. Here, it is assumed that the amount of attenuation is adjusted by 8 dB in the voltage divider 2, and when the amount of attenuation is designated by the DATA signals D21, D22, and D23, any one of the decoded output signals P20 to P25 is set to “1” accordingly. Become.

  Returning to FIG. 2, the continuity control signal generator 32 delays the decode output signals P11 to P17 and P21 to P25, respectively, and outputs the continuity control signals Q11 to Q17 and Q21 to Q25, and the decode output. A signal obtained by delaying the signal P10 and the decoded output signal P10 by a delay time of 2d by a two-stage delay circuit is input, an OR gate OR1 that outputs a conduction control signal Q10, and a two-stage delay of the decoded output signal P20 and the decoded output signal P20. The circuit includes an OR gate OR2 that receives a signal delayed by a delay time 2d by the circuit and outputs a conduction control signal Q20.

  The conduction control signal generator 32 delays the rise and fall of the conduction control signals Q11 to Q17 and Q21 to Q25 by the delay time d from the decoded output signals P11 to P17 and P21 to P25.

  On the other hand, the conduction control signals Q10 and Q20 rise from the decode output signals P10 and P20 at the same timing as the decode output signals P10 and P20, and the signal rise occurs from the decode output signals P10 and P20. It falls after a delay time of 2d.

  That is, conduction control signals Q10 and Q20 rise earlier than other conduction control signals Q11 to Q17 and Q21 to Q25 by the delay time d and fall later by the delay time d. Therefore, the period in which the conduction control signals Q10 and Q20 are “1” is longer than the period in which the other conduction control signals Q11 to Q17 and Q21 to Q25 are “1”.

  FIG. 4 is a waveform diagram showing an example of changes in conduction control signals Q10 and Q20 and other conduction control signals. Here, an example is shown in which the attenuation is switched from -7 dB to -8 dB by setting the DATA signal, then switched to -7 dB, and then switched again to -8 dB.

  Attenuation amount −7 dB is a period in which the analog switch S17 of the voltage dividing unit 1 is conductive, and the resistors R10 to R16 are connected between the input terminal IN and the output terminal O1 of the voltage dividing unit 1. This is the period during which the resistance value is highest. Therefore, if the timing at which the analog switch S17 is turned off is delayed when the attenuation is switched to −8 dB, a current flows through the resistors R10 to R16, and the level of noise generated at the output terminal OUT becomes the highest. That is, switching the attenuation amount from −7 dB to −8 dB is a setting that may cause the highest level of noise generated at the output terminal OUT.

  When the attenuation amount -7 dB is set for the decoder unit 31, the decode output signals P17 and P20 are '1', and when the attenuation amount -8dB is set, the decode output signals P10 and P21 are '1'. .

  Therefore, the signal levels of the decoded output signals P10, P21, P20, and P10 change as shown in FIG.

  In accordance with the change in the decoded output signal, the conduction control signals Q17, Q21, Q20, and Q10 also change. At this time, the period in which the conduction control signals Q20 and Q10 are “1” is longer than the period in which the conduction control signals Q17 and Q21 are “1”. Therefore, before and after the rise and fall of the conduction control signals Q17 and Q21, the period overlaps with the conduction control signals Q20 and Q10 and '1'.

  Further, a period in which “1” overlaps between the conduction control signal Q20 and the conduction control signal Q10 occurs. That is, a period in which the analog switch S20 and the analog switch S10 are simultaneously conducted occurs.

  Next, the effect of providing a period in which the analog switch S20 and the analog switch S10 are simultaneously turned on at the time of switching the attenuation setting will be described with reference to FIGS.

  For comparison with this embodiment, FIG. 5 does not include the conduction control signal generation unit 32, and directly controls the conduction of the analog switches S10 to S17 and the analog switches S20 to S25 by the output of the decoder unit 31. Is shown as a reference example.

  When the input signal source Vin is connected between the input terminal IN and the ground terminal AGND of the circuit of this reference example, and the attenuation is set to −7 dB by the DATA signal, the analog switch S17 and the analog switch S20 are in a conductive state. Become. At this time, when viewed from the ground terminal AGND, the output terminal O1 of the voltage dividing unit 1 is in the highest impedance state.

  From this state, when the attenuation setting is switched to −8 dB, the analog switch S17 and the analog switch S20 become non-conductive, and instead, the analog switch S10 and the analog switch S21 become conductive.

  At this time, since the switching of the analog switch is performed simultaneously by the decoder unit 31, there may be a transient period in which the analog switch S17 and the analog switch S21 are simultaneously conducted.

  In this case, the charge accumulated in the parasitic capacitance Cp of the analog switch S21 is discharged, and a discharge current is supplied to the ground terminal AGND via the resistor R20, the output terminal O1 of the voltage dividing unit 1, the analog switch S17, and the input terminal IN. Flowing. At this time, since the impedance of the output terminal O1 of the voltage dividing unit 1 viewed from the ground terminal AGND is the highest, the fluctuation of the potential of the output terminal O1 generated by this discharge current, that is, the noise level is the highest. It becomes.

  On the other hand, as shown in FIG. 6, in the case of the present embodiment, when the setting of the attenuation amount from the same −7 dB to −8 dB is switched, as shown in FIG. There is a period in which the analog switch S10 and the analog switch S20 are simultaneously turned on before the analog switch S21 is switched. Since the analog switch S10 and the analog switch S20 are connected to the ground terminal AGND with the lowest impedance, the charges accumulated in the parasitic capacitance Cp of the analog switch S21 pass through the analog switch S20 and the analog switch S10. And discharged to the ground terminal AGND.

  Therefore, the level of noise generated by the discharge current flowing through the analog switch S10 and the analog switch S20 is low.

  FIG. 7 shows a waveform diagram of a simulation result of the circuit operation when the above-described attenuation setting is switched.

  FIG. 7A shows the simulation result of the output noise in the reference example shown in FIG. 5, and FIG. 7B shows the simulation result of the output noise in this embodiment.

  As is apparent from the comparison of the simulation waveforms of the output noise shown in FIGS. 7A and 7B, it can be seen that the output noise level is reduced in this embodiment.

  According to the present embodiment, among the analog switches of the voltage dividing circuit having a two-stage configuration, the conduction period of the analog switch connected to the ground terminal with the lowest impedance is longer than the conduction periods of the other analog switches. Before the other analog switches are switched, the analog switch connected to the ground terminal with the lowest impedance is turned on at the same time. As a result, the charge accumulated in the parasitic capacitance of the analog switch of the two-stage voltage dividing circuit is discharged to the ground terminal through a low impedance path, and the level of output noise generated by the discharge current can be reduced. it can.

1 is a block diagram showing an example of the configuration of a semiconductor integrated circuit according to an embodiment of the present invention. The circuit diagram which shows the example of the circuit structure of the switch control part of the Example of this invention. The figure which shows the example of the input-output relationship of the decoder of the Example of this invention. The wave form diagram which shows the example of the change of the conduction | electrical_connection control signal in the Example of this invention. The reference example for demonstrating the effect of the invention in the Example of this invention. The figure for demonstrating the effect of the invention in the Example of this invention. The simulation waveform diagram for demonstrating the effect of the invention in the Example of this invention.

Explanation of symbols

1, 2 Voltage Divider 3 Switch Controller 31 Decoder 32 Conduction Control Signal Generator 311, 312 Decoder IN, DATA Input Terminal OUT Output Terminal AGND Ground Terminals R10-R17, R20-R25 Resistors S10-S17, S20-S25 Analog Switch OR1, OR2 OR gate O1 Output terminal Cp of voltage divider 1 Parasitic capacitance

Claims (3)

A plurality of first resistors connected in series between the input terminal and the ground potential terminal, and connected in parallel between each connection point of the plurality of first resistors and the first voltage dividing output terminal A first voltage dividing means having a first switch group;
A plurality of second resistors connected in series between the first voltage-dividing output terminal and the ground potential terminal; and connection points of the plurality of second resistors and a second voltage-dividing output terminal. A second voltage dividing means having a second switch group connected in parallel therebetween,
Switch control means for controlling conduction of each switch of the first switch group and the second switch group;
The switch control means includes
In each of the first switch group and the second switch group, control is performed such that the conduction time of the switch that outputs the lowest impedance when viewed from the ground potential is longer than the conduction time of the other switches. Semiconductor integrated circuit. The switch control means includes
A decoder for decoding an input signal for setting an output potential of the second divided voltage output end;
And a conduction control signal generating unit configured to adjust a delay time of an output of the decoder and generate a signal for controlling conduction of each switch of the first switch group and the second switch group. Item 14. The semiconductor integrated circuit according to Item 1. The conduction control signal generating means includes
The continuity of each switch of the first switch group and the second switch group is completed so that the switching of the continuity of the other switches is completed while the switch that outputs the lowest impedance as viewed from the ground potential is conductive. The semiconductor integrated circuit according to claim 2, wherein:

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