JP2009200430A - Display device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device of high quality, in which the current characteristics of a thin-film transistor is improved. <P>SOLUTION: Flat shapes of a polycrystalline silicon layer 4 and an amorphous silicon layer 5 have substantially identical shape, and the amorphous silicon layer 5 has a smaller area than the polycrystalline silicone layer 4 in a first thin-film transistor TFT1, where a channel region has a laminated structure of polycrystalline and amorphous silicones and has a reverse staggered structure. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a display device having a thin film transistor, and more particularly, to a display device with improved current characteristics of the thin film transistor and a method for manufacturing the same.

  In Patent Document 1 below, as a thin film transistor disposed on the back substrate side, a first thin film transistor in which a channel region has a laminated structure of polycrystalline and amorphous silicon and an inverted stagger structure, and a channel region is a single layer amorphous silicon. A structure including a second thin film transistor having a structure and an inverted stagger structure is disclosed.

FIGS. 15A and 15B are schematic views showing an example of the configuration of the thin film transistor disclosed in Patent Document 1, in which FIG. 15A is a plan view, and FIG. 15B is FIG. It is sectional drawing along the AA line of a). 15A and 15B, a gate electrode 2 made of a refractory metal such as molybdenum (Mo) or an alloy thereof is disposed on an insulating substrate 1 such as glass, and an insulating film such as SiO or SiN is formed thereon. Or a gate insulating film 3 made of a laminated film of these. Further, a polycrystalline silicon (p-Si) layer 4 and an amorphous silicon (a-Si) layer 5 are sequentially arranged on the gate insulating film 3 substantially concentrically. An n-type amorphous silicon (n + Si) layer 6 and source / drain electrodes 7 are stacked on the amorphous silicon layer 5. On the other hand, since the polycrystalline silicon layer 4 and the amorphous silicon layer 5 are etched together, the side walls 41 and 51 of both layers exhibit a continuous inclined surface having no step.
JP-A-5-55570

  In the configuration shown in FIGS. 15A and 15B, even when the channel width of the p-Si TFT is increased, a phenomenon that the current does not increase in proportion thereto is observed, which hinders improvement of current characteristics. There was a problem that came.

  In the configuration as described above, since the amorphous silicon layer 5 has a high resistance, it is difficult for current to flow. Most of the current flows from the polycrystalline silicon layer 4 through the n-type amorphous silicon layer 6 to the source / drain. It flows to the electrode 7. However, the contact portion between the polycrystalline silicon layer 4 and the n-type amorphous silicon layer 6 is only the side wall 41 portion of the polycrystalline silicon layer 4, and the necessary current value can be obtained because the contact area is small from the above-mentioned side wall structure. There was a difficult problem. As one of countermeasures, it is conceivable to increase the electrode width of the source / drain electrodes 7, but this is not practical because of layout restrictions.

  An object of the present invention is to provide a display device including a thin film transistor capable of increasing a contact area between a polycrystalline silicon layer and an n-type amorphous silicon layer and obtaining necessary current characteristics, and a method for manufacturing the same. .

In order to achieve the above object, in a display device of the present invention, a channel region has a stacked structure of polycrystalline and amorphous silicon and a first thin film transistor having an inverted stagger structure, and a channel region has a single-layer amorphous silicon structure. In addition, the display device includes a second thin film transistor having an inverted staggered structure on the same insulating substrate, the first thin film transistor including an n-type amorphous silicon layer on the amorphous silicon layer in the channel region and an n-type amorphous silicon layer. Source / drain electrodes on the amorphous silicon layer,
The amorphous silicon layer and the polycrystalline silicon layer laminated with the amorphous silicon layer have a substantially similar planar shape perpendicular to the lamination direction, and the upper amorphous silicon layer is the lower polycrystalline silicon layer. The area is smaller than that of the crystalline silicon layer.

The display device of the present invention includes a first thin film transistor in which a channel region has a stacked structure of polycrystalline and amorphous silicon and an inverted stagger structure, and a channel region having a single-layer amorphous silicon structure and an inverted staggered structure. A second thin film transistor provided on the same insulating substrate;
The first thin film transistor includes an n-type amorphous silicon layer on the amorphous silicon layer in the channel region and a source / drain electrode disposed on the n-type amorphous silicon layer,
The polycrystalline silicon layer has an inclined side wall that has a slope different from the side wall of the amorphous silicon layer and spreads from the lower end of the side wall to the bottom, and passes through the side wall of the amorphous silicon layer from the inclined side wall. It is characterized in that it is in contact with the n-type amorphous silicon layer in a region extending over.

  Furthermore, in the method for manufacturing a display device according to the present invention, in the manufacturing of the first thin film transistor, a dimension of a resist pattern covering the amorphous silicon layer stacked on the polycrystalline silicon layer is specified, and the amorphous An island-like amorphous silicon layer having a smaller area than that of the resist pattern is formed by controlling the amount of side etching when the porous silicon layer is dissolved.

  Furthermore, in the method for manufacturing a display device of the present invention, an etching stopper layer is disposed on the polycrystalline silicon layer in the manufacture of the first thin film transistor.

  The area of the amorphous silicon layer stacked on the polycrystalline silicon layer is smaller than that of the polycrystalline silicon layer, and the polycrystalline silicon layer, the n-type amorphous silicon layer, and the source / drain electrodes By increasing the contact area, desired current characteristics can be ensured and the voltage can be reduced.

  The present invention can be applied to liquid crystal display devices, organic EL display devices, and other display devices using various display principles.

  Hereinafter, a display device and a manufacturing method thereof according to the present invention will be described with reference to examples.

  FIG. 1 is a schematic plan view showing an embodiment of a display device according to the present invention. In FIG. 1, a display area 101 on an insulating substrate 1 and peripheral circuits such as an RGB switch 102 and a shift register 103 are incorporated outside the display area 101. The display area 101 has a single-layer amorphous silicon structure and a reverse stagger structure. The peripheral circuit of the peripheral circuit is constituted by a first thin film transistor TFT1 having a channel structure of a laminated structure of polycrystalline and amorphous silicon and an inverted staggered structure. The first thin film transistor TFT1 is applied to a peripheral circuit, but can also be applied to a pixel region.

  FIGS. 2A and 2B are schematic views showing an example of the configuration of the first thin film transistor TFT1, FIG. 2A is a plan view, and FIG. 2B is a cross-sectional view taken along line BB in FIG. It is sectional drawing along a line. 2A and 2B, a gate electrode 2 having a film thickness of about 50 to 150 nm made of a refractory metal such as molybdenum (Mo) or an alloy thereof is disposed on an insulating substrate 1 such as glass, and the top thereof is covered. The insulating film such as SiO or SiN or a laminated film of these is covered with a gate insulating film 3 having a thickness of about 100 to 300 nm. Further, a polycrystalline silicon (p-Si) layer 4 having a thickness of about 50 to 300 nm and an amorphous silicon (a-Si) layer 5 having a thickness of about 100 to 300 nm are substantially concentric on the gate insulating film 3. They are arranged sequentially. An n-type amorphous silicon (n + Si) layer 6 and source / drain electrodes 7 are stacked on the amorphous silicon layer 5.

  With the configuration as described above, the amorphous silicon layer 5 has a smaller area than the polycrystalline silicon layer 4. That is, the polycrystalline silicon layer 4 has a top surface 42 composed of a top surface central portion 43 and a top surface peripheral portion 44. The top surface central portion 43 is a portion where the bottom surface 52 of the amorphous silicon layer 5 is laminated substantially concentrically, and the top surface peripheral portion 44 is continuous with the top surface central portion 43 to form the amorphous silicon layer 5. This represents a region extending and projecting further outward from the outer periphery of the side wall 53, and the outer edge of the peripheral edge 44 of the top surface is connected to the side wall 45 having a hem shape.

  In the first embodiment, the top surface peripheral edge portion 44 is disposed over the entire outer periphery of the side wall 53 of the amorphous silicon layer 5, which is the same as the extending direction of the source / drain electrode 7. It may be provided only in the direction.

Further, the protruding width W _R is set in the same direction as the extending direction of the source / drain electrode 7 and is set to about 50 nm in the first embodiment.

In this configuration, the contact surface between the polycrystalline silicon layer 4 and the n-type amorphous silicon layer 6 extends over a wide range from the side wall 45 to the top surface peripheral portion 44, so that the current characteristics can be improved.

Next, FIG. 3 is a chart showing the dependence of the on-current value of the first thin film transistor TFT1 on the contact area between the polycrystalline silicon layer 4 and the n-type amorphous silicon layer 6. Here, the channel width and the channel length are constant.
As is apparent from FIG. 3, the current value of the current characteristic increases depending on the contact area.

  Next, FIGS. 4 to 8 are process diagrams for explaining an embodiment of the manufacturing method of the display device of the present invention. Each figure (a) shows the first thin film transistor TFT1 (peripheral circuit region arrangement), and each figure. FIG. 4B shows a manufacturing process of the second thin film transistor TFT2 (pixel region arrangement). In these drawings, the same symbols are assigned to the same parts as those described above.

  First, as shown in FIG. 4, a refractory metal such as molybdenum (Mo) or an alloy thereof is formed on an insulating substrate 1 such as glass by sputtering to a thickness of about 50 to 150 nm, and then by photolithography and etching. A pattern is formed to form the gate electrode 2. Thereafter, an insulating film such as SiO or SiN or a laminated film thereof is formed to a thickness of about 100 to 300 nm so as to cover the gate electrode 2 to form the gate insulating film 3.

  Next, an amorphous silicon (a-Si) layer is formed on the gate insulating film 3 to a thickness of about 50 to 300 nm by CVD to form a semiconductor layer 46.

  Next, after dehydrogenating the semiconductor layer 46, the semiconductor layer 46 is crystallized by a pulse or continuous wave laser 47 or the like to form the first polycrystalline silicon layer 40. At this time, crystallization is not performed in the pixel region shown in FIG. 4B, but it may be crystallized.

  Next, as shown in FIG. 5, first, in the peripheral circuit portion shown in FIG. 5A, the first polycrystalline silicon layer 40 is processed into an island shape larger than the required transistor size by photolithography. The island-shaped center is made substantially concentric with the gate electrode 2. On the other hand, the semiconductor layer 46 is removed by etching in the pixel region shown in FIG. However, when the pixel transistor is also formed of polycrystalline silicon, it is processed into an island shape.

  Next, as shown in FIG. 6, a hydrogenated amorphous silicon (a-Si) layer is formed to a thickness of about 100 to 300 nm on the entire surface by CVD to form a semiconductor layer 55. Next, after a resist film is formed on the surface of the semiconductor layer 55, the resist film is processed to form a resist pattern 8 having specifications described later. One of the specifications of the resist pattern 8 is a formation position. In the peripheral circuit portion shown in FIG. 6A, the position is substantially concentric with the island-shaped primary polycrystalline silicon layer 40, and FIG. The pixel region shown in FIG. 2 is arranged substantially concentrically with the gate electrode 2.

  Further, the resist pattern 8 is formed in such a manner that the dimension after etching of the island-shaped primary polycrystalline silicon layer 40 becomes the required transistor size in the peripheral circuit portion. On the other hand, in the pixel region, a resist pattern 82 having the same or different dimensions as the peripheral circuit portion is formed.

  Next, as shown in FIG. 7, the semiconductor layer 55 made of a hydrogenated amorphous silicon (a-Si) layer is dissolved until it becomes smaller than the resist pattern 8 by, for example, a secco etching method, and an island-like amorphous material is obtained. A quality silicon layer 5 is formed. The amount of side etching in this step is preferably about 0.5 μm to 5.0 μm.

In this melting step, there is a possibility that the grain boundary portion of the first polycrystalline silicon layer 40 may be etched. However, if the crystallization is performed while scanning the above-described continuous wave laser, the grain boundary is formed in a certain direction. Therefore, even if the grain boundary is etched, the TFT characteristics are not affected.
Next, the first polycrystalline silicon layer 40 is etched by dry etching to form a polycrystalline silicon layer 4 having a size larger than that of the amorphous silicon layer 5. Thereby, an amorphous silicon layer 5 smaller than the polycrystalline silicon layer 4 is disposed.

Next, after removing the resist pattern 8, a P ⁺ doped amorphous silicon layer for forming an n-type amorphous silicon layer (n + layer) 6 is formed with a thickness of about 10 to 50 nm by CVD. . Further, a metal such as aluminum (Al) to be the source / drain electrode 7 is formed thereon with a thickness of about 300 to 500 nm by sputtering.

  At that time, in consideration of prevention of Al film diffusion and reduction of contact resistance, it is also possible to form a refractory metal such as titanium (Ti) or Mo or an alloy thereof as a barrier metal above and below the Al layer. is there. The thickness of the barrier metal layer may be about 30 to 100 nm.

Thereafter, source / drain electrodes 7 are formed by photolithography and etching. In addition, in order to form a channel of the semiconductor layer, the P ⁺ doped amorphous silicon layer is also etched at this time to form an n-type amorphous silicon layer (n + layer) 6 (see FIG. 8).

  Next, FIG. 9 to FIG. 13 are process diagrams for explaining another embodiment of the display device manufacturing method of the present invention. Each figure (a) shows the first thin film transistor TFT1 (peripheral circuit region arrangement), and FIG. Each figure (b) shows the manufacturing process of 2nd thin-film transistor TFT2 (pixel area arrangement | positioning), respectively. In these drawings, the same symbols are assigned to the same parts as those described above.

  First, as shown in FIG. 9, a refractory metal such as molybdenum (Mo) or an alloy thereof is formed on an insulating substrate 1 such as glass by sputtering to a thickness of about 50 to 150 nm, and then photolithography / etching is performed. A pattern is formed to form the gate electrode 2. Thereafter, an insulating film such as SiO or SiN or a laminated film thereof is formed to a thickness of about 100 to 300 nm so as to cover the gate electrode 2 to form the gate insulating film 3.

  Next, an amorphous silicon (a-Si) layer is formed on the gate insulating film 3 to a thickness of about 50 to 300 nm by CVD to form a semiconductor layer 46.

  Next, after dehydrogenating the semiconductor layer 46, the semiconductor layer 46 is crystallized by a pulse or continuous wave laser 47 or the like to form the first polycrystalline silicon layer 40. At this time, crystallization is not performed in the pixel region shown in FIG. 9B, but it may be crystallized.

  Next, as shown in FIG. 10, the first polycrystalline silicon layer 40 is first processed into an island shape in the peripheral circuit portion shown in FIG. The center of the island shape is substantially concentric with the gate electrode 2. On the other hand, the semiconductor layer 46 is removed by etching in the pixel region shown in FIG.

Next, in the peripheral circuit portion, the surface of the first polycrystalline silicon layer 40 is covered with an etching stopper layer 9. The etching stopper layer 9 is formed by performing O ₂ plasma treatment or by forming a SiO film with a thickness of about several to 10 nm.

Next, as shown in FIG. 11, a hydrogenated amorphous silicon (a-Si) layer is formed to a thickness of about 100 to 300 nm on the entire surface by CVD to form a semiconductor layer 55.
Next, after a resist film is formed on the surface of the semiconductor layer 55, the resist film is processed to form a resist pattern 8 having specifications described later. One of the specifications of the resist pattern 8 is a formation position. In the peripheral circuit portion shown in FIG. 11A, the position is substantially concentric with the island-shaped primary polycrystalline silicon layer 40, and FIG. The pixel region shown in FIG. 2 is arranged substantially concentrically with the gate electrode 2.

  Further, the resist pattern 8 has a size of 0.1 mm in the peripheral circuit portion after the etching of the semiconductor layer 55, as compared with the previously formed primary polycrystalline silicon layer 40 and the completed polycrystalline silicon layer 4. A resist pattern 81 having such a size as to be reduced by about 5 μm to 5 μm is formed.

  On the other hand, in the pixel region, a resist pattern 82 having the same or different dimensions as the peripheral circuit portion is formed.

  Next, as shown in FIG. 12, the semiconductor layer 55 made of a hydrogenated amorphous silicon (a-Si) layer is processed by dry etching to form an island-shaped amorphous silicon layer 5. In this step, the etching stopper layer 9 acts as an etching stopper, thereby preventing the first polycrystalline silicon layer 40 from being etched.

  Next, after removing the resist pattern 8, the etching stopper layer 9 in the exposed portion of the surface of the first polycrystalline silicon layer 40 is removed with HF or the like.

Next, a P ⁺ doped amorphous silicon layer for forming the n-type amorphous silicon layer (n + layer) 6 is formed by CVD to a thickness of about 10 to 50 nm. Further, a metal such as aluminum (Al) to be the source / drain electrode 7 is formed thereon with a thickness of about 300 to 500 nm by sputtering.

At that time, in consideration of prevention of Al film diffusion and reduction of contact resistance, it is also possible to form a refractory metal such as titanium (Ti) or Mo or an alloy thereof as a barrier metal above and below the Al layer. is there. The thickness of the barrier metal layer may be about 30 to 100 nm.
Thereafter, source / drain electrodes 7 are formed by photolithography and etching. Further, in order to form a channel of the semiconductor layer, the P ⁺ doped amorphous silicon layer is also etched at this time to form an n-type amorphous silicon layer (n + layer) 6 (see FIG. 13).

  FIG. 14 is a schematic cross-sectional view showing another embodiment of the display device according to the present invention, and the same reference numerals are given to the same parts as those described above. In FIG. 14, reference numeral 48 indicates an inclined side wall of the polycrystalline silicon layer 4. The inclined side wall 48 has a configuration in which the lower end of the side wall 53 of the amorphous silicon layer 5 starts from the lower end and spreads at a different inclination angle from the side wall 53. The n-type amorphous silicon layer 6 is in contact with such an inclined side wall 48 having a flared shape.

With the above-described configuration, a display device including a high-quality thin film transistor with improved current characteristics and a manufacturing method thereof can be provided.

It is a schematic plan view which shows one Example of the display apparatus by this invention. 2A and 2B are schematic views showing the structure of an example of a thin film transistor according to the present invention. FIG. 2A is a plan view, and FIG. 2B is a cross-sectional view taken along line BB in FIG. 4 is a chart showing the contact area dependence of the on-current value of a thin film transistor for explaining a display device according to the present invention. FIG. 4A is a schematic cross-sectional view of a peripheral circuit portion, and FIG. 4B is a schematic cross-sectional view of an image region, illustrating a method for manufacturing a display device according to the present invention. FIG. 5A is a schematic cross-sectional view of a peripheral circuit portion, and FIG. 5B is a schematic cross-sectional view of an image region, illustrating a method for manufacturing a display device according to the present invention. FIG. 6A is a schematic cross-sectional view of a peripheral circuit portion, and FIG. 6B is a schematic cross-sectional view of an image region, illustrating a method for manufacturing a display device according to the present invention. FIG. 7A is a schematic cross-sectional view of a peripheral circuit portion, and FIG. 7B is a schematic cross-sectional view of an image region, illustrating a method for manufacturing a display device according to the present invention. FIG. 8A is a schematic cross-sectional view of a peripheral circuit portion, and FIG. 8B is a schematic cross-sectional view of an image region, illustrating a method for manufacturing a display device according to the present invention. FIG. 9A is a schematic cross-sectional view of a peripheral circuit portion, and FIG. 9B is a schematic cross-sectional view of an image region. FIG. 10A is a schematic cross-sectional view of a peripheral circuit section, and FIG. 10B is a schematic cross-sectional view of an image region, illustrating a method for manufacturing a display device according to the present invention. FIG. 11A is a schematic cross-sectional view of a peripheral circuit section, and FIG. 11B is a schematic cross-sectional view of an image region, illustrating a method for manufacturing a display device according to the present invention. FIG. 12A is a schematic cross-sectional view of a peripheral circuit portion, and FIG. 12B is a schematic cross-sectional view of an image region, illustrating a method for manufacturing a display device according to the present invention. FIG. 13A is a schematic cross-sectional view of a peripheral circuit section, and FIG. 13B is a schematic cross-sectional view of an image region, illustrating a method for manufacturing a display device according to the present invention. It is a schematic cross section which shows the other Example of the display apparatus by this invention. FIG. 15A is a schematic plan view illustrating a configuration of a conventional display device, and FIG. 15B is a schematic cross-sectional view taken along line AA in FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Insulating substrate, 2 ... Gate electrode, 3 ... Gate insulating film, 4 ... Polycrystalline silicon layer, 42 ... Top surface, 43 ... Top surface center part, 44 ... -Top surface peripheral edge, 45 ... sidewall, 48 ... inclined sidewall, 5 ... amorphous silicon layer, 52 ... bottom surface, 53 ... sidewall, 6 ... n-type amorphous Silicon layer, 7 ... source / drain electrodes, 8 ... resist pattern, 9 ... etching stopper layer, TFT1 ... first thin film transistor, TFT2 ... second thin film transistor.

Claims (8)

A first thin film transistor whose channel region has a stacked structure of polycrystalline and amorphous silicon and has an inverted stagger structure, and a second thin film transistor whose channel region has a single layer amorphous silicon structure and has an inverted stagger structure, are formed over the same insulating substrate. With a display device
The first thin film transistor includes an n-type amorphous silicon layer on the amorphous silicon layer in the channel region, and further includes a source / drain electrode on the n-type amorphous silicon layer, and the amorphous silicon layer The polycrystalline silicon layer laminated with the amorphous silicon layer has a substantially similar planar shape perpendicular to the lamination direction, and the upper amorphous silicon layer has a smaller area than the lower polycrystalline silicon layer. A display device characterized by comprising:   The polycrystalline silicon layer is formed by laminating the amorphous silicon layer at the center of the top surface, extending further outward from the outer periphery of the amorphous silicon layer and continuing to the center of the top surface and the top surface. 2. The display device according to claim 1, further comprising a side wall connected to an outer edge of the surface peripheral portion, and continuously contacting the n-type amorphous silicon layer from the side wall to the top surface peripheral portion.   The display device according to claim 1, wherein the peripheral edge portion of the top surface is disposed so as to surround an outer periphery of the amorphous silicon layer.   The display device according to any one of claims 1 to 3, wherein the side wall is an inclined surface having a flared shape.   5. The display device according to claim 1, wherein an etching stopper layer is interposed in a laminated portion of the amorphous silicon layer and the polycrystalline silicon layer in the channel region. A first thin film transistor whose channel region has a stacked structure of polycrystalline and amorphous silicon and has an inverted stagger structure, and a second thin film transistor whose channel region has a single layer amorphous silicon structure and has an inverted stagger structure, are formed over the same insulating substrate. With a display device
The first thin film transistor includes an n-type amorphous silicon layer on the amorphous silicon layer in the channel region and a source / drain electrode disposed on the n-type amorphous silicon layer,
The polycrystalline silicon layer has an inclined side wall that has a slope different from the side wall of the amorphous silicon layer and spreads from the lower end of the side wall to the bottom, and passes through the side wall of the amorphous silicon layer from the inclined side wall. A display device, wherein the display device is in contact with the n-type amorphous silicon layer in a region extending over. A first thin film transistor whose channel region has a stacked structure of polycrystalline and amorphous silicon and has an inverted stagger structure, and a second thin film transistor whose channel region has a single layer amorphous silicon structure and has an inverted stagger structure, are formed over the same insulating substrate. A method of manufacturing a display device provided for
Forming a first thin film transistor gate electrode on an insulating substrate; covering the gate electrode; and forming a gate insulating film;
Forming an amorphous silicon layer on the gate insulating film;
Processing the amorphous silicon layer to form a polycrystalline silicon layer;
Processing the polycrystalline silicon layer into an island shape by a process including etching;
Covering the island-shaped polycrystalline silicon layer with a hydrogenated amorphous silicon layer;
Forming an island-shaped resist pattern on the hydrogenated amorphous silicon layer, substantially concentrically with the island-shaped polycrystalline silicon layer and having a smaller area than the island-shaped polycrystalline silicon layer;
Processing the hydrogenated amorphous silicon layer into an island shape that is substantially concentric with the resist pattern and smaller in area than the resist pattern;
Processing the island-shaped polycrystalline silicon layer into a shape that is substantially concentric with the island-shaped hydrogenated amorphous silicon layer and has a peripheral edge protruding from the hydrogenated amorphous silicon layer;
Removing the resist pattern;
Forming a P ⁺ doped amorphous silicon layer on the surface including the island-shaped hydrogenated amorphous silicon layer;
Forming a metal film for source / drain electrodes on the surface of the P ⁺ doped amorphous silicon layer;
A method of manufacturing a display device, comprising: processing the P ⁺ doped amorphous silicon layer and the metal film for source / drain electrodes to form a source / drain electrode and an n-type amorphous silicon layer. A first thin film transistor whose channel region has a stacked structure of polycrystalline and amorphous silicon and has an inverted stagger structure, and a second thin film transistor whose channel region has a single layer amorphous silicon structure and has an inverted stagger structure, are formed over the same insulating substrate. A method of manufacturing a display device provided for
Forming a first thin film transistor gate electrode on an insulating substrate; covering the gate electrode; and forming a gate insulating film;
Forming an amorphous silicon layer on the gate insulating film;
Processing the amorphous silicon layer to form a polycrystalline silicon layer;
Processing the polycrystalline silicon layer into an island shape by a process including etching;
Covering the island-shaped polycrystalline silicon layer with an etching stopper layer;
Covering the island-shaped polycrystalline silicon layer covered with the etching stopper layer with a hydrogenated amorphous silicon layer;
Forming an island-shaped resist pattern on the hydrogenated amorphous silicon layer, substantially concentrically with the island-shaped polycrystalline silicon layer and having a smaller area than the island-shaped polycrystalline silicon layer;
Processing the hydrogenated amorphous silicon layer into islands with the resist pattern;
Removing the resist pattern;
Removing the remaining etching stopper layer except for the portion covered with the island-shaped hydrogenated amorphous silicon layer of the island-shaped polycrystalline silicon layer covered with the etching stopper layer;
Forming a P ⁺ doped amorphous silicon layer on the surface including the island-shaped hydrogenated amorphous silicon layer;
Forming a metal film for source / drain electrodes on the surface of the P ⁺ doped amorphous silicon layer;
A method of manufacturing a display device, comprising: processing the P ⁺ doped amorphous silicon layer and the metal film for source / drain electrodes to form a source / drain electrode and an n-type amorphous silicon layer.