JP2009188897A - Communication system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To synchronize between a source device and a sync device. <P>SOLUTION: A packet-generating circuit 3 generates a video packet including video data, adds a count value Csource(t) of clocks CLKp1 of pixel data, with a timing to send the video packet to a sync device 11 to a header part of the video packet as a time stamp value and transmits the video packet to the sync device 11. A packet-processing circuit 14 extracts the count value Csource(t) from the header part of the received video packet and outputs the extracted count value to a clock-generating circuit 18. The clock generating circuit 18 performs an insertion processing or a thinning processing on a clock CLKp2 from a PLL circuit 26, with a timing other than an effective pixel region in the video data so that by having the differential value between the count value Csource(t) and count value Ccount(t) of clocks CLKp3 of pixel data substantially converge to zero, the clock CLKp3 of pixel data in the sync device 11 is generated and output. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a communication system for transmitting video and audio data (hereinafter referred to as AV data) between video and audio devices (hereinafter referred to as AV devices), and in particular, packet transmission of uncompressed video data and audio data. The present invention relates to a communication system.

  Uncompressed video data is divided into a plurality of horizontal scanning lines (also referred to as horizontal lines), and each scanning line has a plurality of pixel data. Here, the product of the number of pixels per scanning line, the number of scanning lines per frame or field, and the required refresh rate (which is the frame rate or field frequency) is defined as a clock for pixel data. An AV device that receives uncompressed video data, for example, uses a single reference clock to generate an audio clock and a pixel data clock (hereinafter referred to as a PLL (Phase Locked Loop) circuit). It is configured with. However, since not all the frequency divider parameters of the PLL circuit can actually be realized, the PLL circuit cannot be used to generate both an accurate audio clock and pixel data clock, and therefore The video included in the received AV stream cannot be accurately synchronized with the audio.

  According to the video synchronization method according to the prior art described in Patent Document 1, in order to generate a clock of pixel data synchronized with an audio clock using a divider parameter that can be realized by the PLL circuit, for example, scanning is performed. Change video parameters such as the number of pixels per line or the number of scan lines per frame.

JP 2006-74740 A.

  However, in the video synchronization method according to the prior art, since video parameters such as the number of pixels per scanning line or the number of scanning lines per frame are changed, uncompressed AV data is transmitted from the source device to the sink device. When displaying, the following problems occurred. That is, for example, when the source device and the sink device are connected to each other over the network, for example, when the content of AV data is switched between the commercial and the program and the video parameter is changed, the source device to the sink device There is a problem that it is necessary to notify the information of the changed video parameter, and it is necessary to perform complicated control. In addition, there is a problem that the video parameters can be changed or not guaranteed in each device. Further, when the specifications such as the accuracy of the clock frequency are different between the source device and the sink device, there is a possibility that the AV data cannot be normally reproduced in the sink device.

  The object of the present invention is to solve the above-mentioned problems, and in a communication system in which AV data is packet-transmitted between a source device such as an AV device and a sink device, a frequency such as a clock of pixel data in uncompressed video data. Provides a communication system with a simpler configuration compared to the prior art that can synchronize the clock between the source device and the sink device without affecting the viewed image even when the image changes There is to do.

A communication system according to a first aspect of the present invention is a communication system for packet-transmitting video data from a source device to a sink device.
The source device is
A transmission counter that counts a clock of pixel data in the video data and outputs a signal indicating a first count value;
A video packet in a predetermined packet format including the video data is generated, and the first count value at the timing of sending the video packet to the sink device is added as a time stamp value to the header of the video packet. Packet generating means for transmitting to the sink device,
The sink device
Packet processing means for receiving the video packet, extracting the first count value from a header portion of the received video packet, and outputting a signal indicating the extracted first count value;
Subtraction for calculating the difference value between the signal indicating the first count value from the packet processing means and the signal indicating the second count value output from the reception counter and outputting the difference signal indicating the difference value Means,
Clock generating means for generating and outputting a clock based on the differential signal;
Synchronization signal generating means for generating and outputting a horizontal synchronization signal and a vertical synchronization signal of the video data based on a clock of pixel data in the sink device;
Based on the horizontal synchronizing signal and the vertical synchronizing signal from the synchronizing signal generating means, timing other than the effective pixel area of the video data is detected, and the difference value is converged to substantially zero at the detected timing. A clock control unit that generates and outputs a clock of pixel data in the sink device by performing either a predetermined insertion process or a predetermined decimation process on the clock from the clock generation unit;
And a reception counter that counts a clock of pixel data output from the clock control means and outputs a signal indicating the second count value to the subtraction means.

  In the communication system, the timing other than the effective pixel region is a timing within a horizontal blanking period or a vertical blanking period of the video data.

A communication system according to a second invention is a communication system for packet-transmitting video data from a source device to a sink device.
The source device is
Based on a clock control data signal transmitted from the sink device, a clock adjusting unit that adjusts the frequency of the pixel data clock in the video data and generates and outputs the clock of the adjusted pixel data;
A transmission counter that counts the clock of pixel data after adjustment from the clock adjustment means and outputs a signal indicating a first count value;
A video packet in a predetermined packet format including the video data is generated, and the first count value at the timing of sending the video packet to the sink device is added as a time stamp value to the header of the video packet. Packet generating means for transmitting to the sink device,
The sink device
Packet processing means for receiving a video packet from the source device, extracting the first count value from a header portion of the received video packet, and outputting a signal indicating the extracted first count value; ,
Subtraction for calculating the difference value between the signal indicating the first count value from the packet processing means and the signal indicating the second count value output from the reception counter and outputting the difference signal indicating the difference value Means,
Clock generation means for generating and outputting a clock of pixel data in the sink device based on the difference signal;
Synchronization signal generation means for generating and outputting a horizontal synchronization signal and a vertical synchronization signal of the video data based on a clock of pixel data output from the clock generation means;
A reception counter that counts a clock of pixel data output from the clock generation means and outputs a signal indicating the second count value to the subtraction means;
Clock control means for generating the clock control data signal based on the difference value and transmitting it to the clock adjustment means of the source device,
Based on the clock control data signal transmitted from the clock control means of the sink device, the clock adjustment means of the source device is configured to adjust the pixel data in the video data so that the difference value converges to substantially zero. The clock frequency is adjusted to generate a clock for the adjusted pixel data.

  In the communication system, the clock control means determines whether or not the difference value from the subtraction means has substantially converged to zero, and the difference value from the subtraction means has substantially converged to zero. When not, the clock control data signal is generated.

  According to the communication system of the first invention, the clock control means of the sink device detects timings other than the effective pixel area of the video data based on the horizontal synchronization signal and the vertical synchronization signal from the synchronization signal generation means, Pixel data in the sink device is obtained by performing either predetermined insertion processing or predetermined thinning-out processing on the clock from the clock generation means so that the difference value converges to substantially zero at the detected timing. Therefore, the clock of the pixel data in the sink device can be synchronized with the clock of the pixel data in the video data without affecting the image viewed by the user. Thereby, underflow and overflow of video data in the sink device can be prevented.

  According to the communication system of the second invention, the clock control means of the sink device generates a clock control data signal based on the difference value and transmits it to the clock adjustment means of the source device to adjust the clock of the source device. The means adjusts the frequency of the pixel data clock in the video data based on the clock control data signal transmitted from the clock control means of the sink device so that the difference value substantially converges to zero, Since the clock of the subsequent pixel data is generated and output, clock synchronization can be established between the source device and the sink device without affecting the image viewed by the user. Thereby, underflow and overflow of video data in the sink device can be prevented.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

First embodiment.
FIG. 1 is a block diagram showing the configuration of the wireless communication system according to the first embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of the clock generation circuit 18 of FIG. 1, and FIG. 3 is a timing chart showing an example of the operation of the clock controller 21.

  In the wireless communication system according to the present embodiment, the source device 1 counts the pixel data clock CLKp1 in the video data and outputs a signal indicating the first count value Csource (t), and the video data A video packet Pvideo having a predetermined packet format is generated, and the first count value Csource (t) at the timing of sending the video packet Pvideo to the sink device 11 is added as a time stamp value to the header portion of the video packet Pvideo. A packet generation circuit 3 that transmits to the sink device 11 is provided. The sink device 11 includes a packet processing circuit 14, a subtractor 22, a clock generation circuit 28, a synchronization signal generation circuit 19, a clock controller 21, and a reception counter 27. Here, the packet processing circuit 14 receives the video packet Pvideo, extracts the first count value Csource (t) from the header portion of the received video packet Pvideo, and extracts the extracted first count value Csource (t ) Is output. Further, the subtracter 22 is a difference value between a signal indicating the first count value Csource (t) from the packet processing circuit 14 and a signal indicating the second count value Ccount (t) output from the reception counter 27. D (t) is calculated and a difference signal indicating the difference value D (t) is output. Further, the clock generation circuit 28 generates and outputs a clock based on the difference signal. Furthermore, the synchronization signal generation circuit 19 generates and outputs a horizontal synchronization signal HSYNC and a vertical synchronization signal VSYNC of video data based on the pixel data clock CLKp3 in the sink device 11. Then, the clock controller 21 detects timings other than the effective pixel area of the video data based on the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC from the synchronization signal generation circuit 19, and at the detected timing, the difference value D (t ) Of the pixel data in the sink device 11 by performing either a predetermined insertion process or a predetermined decimation process on the clock CLKp2 from the clock generation circuit 28 so that it substantially converges to zero. Is generated and output. The reception counter 27 counts the clock CLKp3 of the pixel data output from the clock controller 21 and outputs a signal indicating the second count value Ccount (t) to the subtractor 22.

  Furthermore, in the present embodiment, the timing other than the effective pixel region is a timing within a horizontal blanking period or a vertical blanking period of video data.

  In FIG. 1, the source device 1 includes a video playback device 2 such as a DVD player, a packet generation circuit 3, a transmission counter 4, a wireless communication circuit 5, and an antenna 6. On the other hand, the sink device 11 includes an antenna 12, a wireless communication circuit 13, a packet processing circuit 14, a video data processing circuit 15, a buffer memory 16, a display 17, a clock generation circuit 18, and a synchronization signal generation circuit 19. And is configured.

  First, the operation of the source device 1 will be described. In FIG. 1, a video reproduction device 2 reproduces video data from a recording medium such as a DVD and outputs the video data to the packet generation circuit 3, and a clock CLKp1 (for example, 2200 pixels per horizontal line) of pixel data in the video data. X horizontal line number 1125 x field frequency 60 Hz = 148.5 MHz) is output to the transmission counter 4. The transmission counter 4 counts using the pixel data clock CLKp1. The count value Csource (t) of the transmission counter 4 is added to the header portion of the packet Pvideo as a time stamp value at each timing when the video data packet Pvideo is sent from the wireless communication circuit 5 to the sink device 11 in the packet generation circuit 3. Is done. The packet generation circuit 3 generates a data signal of a video data packet Pvideo in a predetermined packet format including the video data from the video playback device 2 and outputs the data signal to the wireless communication circuit 5. Further, the wireless communication circuit 5 digitally modulates the wireless carrier signal in accordance with the input data signal, and wirelessly transmits the modulated wireless signal to the antenna 12 of the sink device 11 via the antenna 6.

  Next, the operation of the sink device 11 will be described. In FIG. 1, a radio signal transmitted from the antenna 6 of the source device 1 is received by the antenna 12 and then input to the radio communication circuit 13. The wireless communication circuit 13 demodulates the received wireless signal into a digital signal, and then outputs it to the packet processing circuit 14. The packet processing circuit 14 outputs the packet Pvideo transmitted from the source device 1 to the synchronization signal generation circuit 19 and extracts the count value Csource (t) added to the header of the packet Pvideo to the clock generation circuit 18. Output. Further, the packet processing circuit 14 demultiplexes the video data and outputs it to the video data processing circuit 15. As will be described later in detail with reference to FIG. 3, the clock generation circuit 18 generates a clock CLKp3 of pixel data based on the count value Csource (t) and the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC from the synchronization signal generation circuit 19. And output to the video data processing circuit 15 and the synchronization signal generation circuit 19. The video data processing circuit 15 converts the input video data into a video signal by executing a predetermined packet decoding process or the like based on the clock CLKp3 of the pixel data from the clock generation circuit 18, and then converts it into a buffer memory. The image is output to the display 17 via 16 and displayed. On the other hand, the synchronization signal generation circuit 19 uses the pixel data clock CLKp3 from the clock generation circuit 18 as a base clock, and transmits the positional information of the transmitted pixel data stored in the header of the packet Pvideo from the packet processing circuit 14 ( For example, the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC are generated based on the horizontal pixel position and the vertical pixel position) and output to the display 17 and the clock generation circuit 18.

  In FIG. 2, the clock generation circuit 18 includes a subtracter 22, a clock generation circuit 28, a clock controller 21, and a reception counter 27, and receives a count value Csource (t) and a horizontal synchronization signal HSYNC. The pixel data clock CLKp3 is generated based on the vertical synchronization signal VSYNC. Here, the clock generation circuit 28 includes a filter 23, a D / A converter 24, a VCXO 25, and a PLL circuit 26.

  The clock generation circuit 18 operates as follows. In FIG. 2, first, the count value Csource (t) output from the source device 1 is input to the subtractor 22. The subtractor 22 calculates a difference value D (t) between the input count value Csource (t) and the count value Ccount (t) from the reception counter 27, and generates a signal indicating the difference value D (t). Then, the data is output to the filter 23 and the clock controller 21. The filter 23 is composed of, for example, LPF, and smoothes the signal indicating the difference value D (t) and outputs the smoothed signal Dav (t) to the D / A converter 24. The D / A converter 24 converts the smoothed signal Dav (t) into an analog voltage and controls the oscillation frequency of the VCXO 25. The VCXO 25 outputs a reference clock CLKref (for example, having a frequency of 27 MHz) to the PLL circuit 26. The PLL circuit 26 generates a clock CLKp2 based on the reference clock CLKref and outputs it to the clock controller 21.

  The difference value D (t) calculated by the subtracter 22 indicates a synchronization state between the pixel data clock CLKp1 in the source device 1 and the pixel data clock CLKp3 in the sink device 11. Specifically, when the pixel data clock CLKp1 and the pixel data clock CLKp3 are synchronized, the difference value D (t) substantially converges to zero, and the pixel data clock CLKp1 becomes the pixel data clock. The difference value D (t) increases when the frequency is higher than CLKp3, and the difference value D (t) decreases when the pixel data clock CLKp1 has a lower frequency than the pixel data clock CLKp3.

  In FIG. 2, the clock controller 21 detects the value of the difference value D (t) at a predetermined timing based on the signal indicating the difference value D (t) from the subtractor 22. The clock controller 21 detects the horizontal blanking period and the vertical blanking period of the image based on the horizontal synchronizing signal HSYNC and the vertical synchronizing signal VSYNC from the synchronizing signal generation circuit 19. Further, based on the detected difference value D (t), the clock controller 21 performs a thinning process or insertion for the clock CLKp2 at a timing within the horizontal blanking period or the vertical blanking period that is a timing other than the effective pixel region of the image. By performing the processing, the pixel data clock CLKp3 is generated so that the difference value D (t) substantially converges to zero. For example, when the number of pixels per horizontal line is 2200 and the number of horizontal lines is 1125, the number of pixels per horizontal line in the effective pixel area is 1920 and the number of horizontal lines is 1080.

  Specifically, when the clock controller 21 detects that the difference value D (t) continuously decreases a predetermined number of times (hereinafter, referred to as a first case), the horizontal blanking with respect to the clock CLKp2. At a timing within the period or the vertical blanking period, a thinning process is performed in which the clock CLKp2 is paused a number of times proportional to the magnitude of the difference value D (t), and the clock CLKp3 is generated. Further, when the clock controller 21 detects that the difference value D (t) continuously increases a predetermined number of times (hereinafter, referred to as a second case), the clock controller 21 performs a horizontal blanking period or vertical with respect to the clock CLKp2. Insertion processing for adding an inverted clock of the clock CLKp2 to the clock CLKp2 by the number of times proportional to the magnitude of the difference value D (t) is performed at the timing within the blanking period, and the clock CLKp3 is generated. Further, the clock controller 21 does not apply the time change of the difference value D (t) to the first and second cases, and when the difference value D (t) has substantially converged to zero, the clock CLKp2 As clock CLKp3. The clock controller 21 outputs a clock CLKp3 of the generated pixel data to the synchronization signal generation circuit 19, the video data processing circuit 15, and the reception counter 27. The reception counter 27 counts using the clock CLKp3 of the pixel data and outputs the count value Ccount (t) to the subtracter 22.

  An example of the operation of the clock controller 21 will be described with reference to FIG. In FIG. 3, when the clock controller 21 detects that the difference value D (t) has decreased continuously a predetermined number of times, the clock controller 21 performs the above-described thinning process on the clock CLKp2 at timings t1 and t2 within the horizontal blanking period. Is performed to generate a clock CLKp3 of pixel data. In FIG. 3, when the clock controller 21 detects that the difference value D (t) has increased continuously a predetermined number of times, the clock controller 21 detects the difference from the clock CLKp2 at timings t3, t4 and t4 within the vertical blanking period. Thus, the pixel data clock CLKp3 is generated by performing the above insertion processing.

  As described above in detail, according to the wireless communication system according to the present embodiment, the clock controller 21 is based on the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC within the horizontal blanking period or the vertical blanking period of the video data. Or a decimation process or a clock for stopping the clock CLKp2 with respect to the clock CLKp2 from the PLL circuit 26 so that the difference value D (t) converges to substantially zero at the detected timing. A clock CLKp3 of pixel data in the sink device 11 is generated by performing an insertion process for adding an inverted clock of the clock CLKp2 to CLKp2. Furthermore, the clock controller 21 performs an insertion process and a thinning process based on the magnitude of the difference value D (t). Thus, even when the clock CLKp2 from the PLL circuit 26 is not synchronized with the clock CLKp1 of the pixel data in the video data in the source device 1, the synchronization is performed in the unit of the horizontal blanking period or the unit of the vertical blanking period. The pixel data clock CLKp3 in the device 11 can be synchronized with the pixel data clock CLKp1 in the video data. That is, clock synchronization can be established between the source device 1 and the sink device 11 without affecting the image viewed by the user. Thereby, underflow and overflow of the video data in the buffer memory 16 of the sink device 11 can be prevented.

  In the present embodiment, the configuration of the clock generation circuit 18 is not limited to the configuration illustrated in FIG. 2, and may be another circuit configuration that outputs the reference clock CLKref to the PLL circuit 26.

  In the present embodiment, the wireless communication system in which the source device 1 and the sink device 11 are connected via the wireless communication line has been described. However, the present invention is not limited to this, and the source device 1 and the sink device 11 are connected to the wired communication line. It may be a wired communication system connected via

Second embodiment.
FIG. 4 is a block diagram showing a configuration of a radio communication system according to the second embodiment of the present invention, and FIG. 5 is a block diagram showing a configuration of the clock generation circuit 18A of FIG.

  In FIG. 4, the wireless communication system according to the present embodiment includes a source device 1 and a sink device 11A. Here, compared with the sink device 11 (FIG. 1) according to the first embodiment, the sink device 11A replaces the clock generation circuit 18 with a pixel based on the video data accumulation amount Db in the buffer memory 16. A clock generation circuit 18A for generating a data clock CLKp3 is provided.

  The accumulated amount Db of the video data in the buffer memory 16 is similar to the difference value D (t) from the subtractor 22, and the pixel data clock CLKp1 in the source device 1 and the pixel data clock CLKp3 in the sink device 11A. Shows the synchronization state between. Specifically, when the pixel data clock CLKp1 and the pixel data clock CLKp3 are synchronized, the accumulation amount Db does not increase or decrease, and the pixel data clock CLKp1 has a higher frequency than the pixel data clock CLKp3. When the pixel data clock CLKp1 has a lower frequency than the pixel data clock CLKp3, the accumulation amount Db decreases.

  In the clock generation circuit 18A of FIG. 5, the clock controller 21A detects the video data accumulation amount Db in the buffer memory 16 at a predetermined timing. Further, the clock controller 21A detects the horizontal blanking period and the vertical blanking period of the image based on the horizontal synchronizing signal HSYNC and the vertical synchronizing signal VSYNC from the synchronizing signal generating circuit 19. Furthermore, the clock controller 21A performs a thinning process or an insertion process for the clock CLKp2 at a timing within the horizontal blanking period or the vertical blanking period that is a timing other than the effective pixel area of the image, based on the detected accumulation amount Db. Thus, the pixel data clock CLKp3 is generated so that the accumulation amount Db does not substantially increase or decrease. Thereby, the difference value D (t) converges to substantially zero.

  Specifically, when the clock controller 21A detects that the accumulation amount Db has continuously decreased a predetermined number of times (hereinafter referred to as the third case), the timing within the horizontal blanking period or the vertical blanking period. Thus, a thinning process is performed in which the clock CLKp2 is paused a number of times proportional to the amount of video data stored in the buffer memory 16, and the clock CLKp3 is generated. Further, when the clock controller 21A detects that the accumulation amount Db continuously increases a predetermined number of times (hereinafter referred to as a fourth case), the clock controller 21A performs buffering at a timing within the horizontal blanking period or the vertical blanking period. Insertion processing for adding an inverted clock of the clock CLKp2 to the clock CLKp2 by the number of times proportional to the amount of video data stored in the memory 16 is performed to generate the clock CLKp3. Furthermore, when the time change of the accumulation amount Db does not apply to the third and fourth cases, the clock controller 21A uses the clock CLKp2 as it is as the clock CLKp3. The clock controller 21A outputs a clock CLKp3 of the generated pixel data to the synchronization signal generation circuit 19, the video data processing circuit 15, and the reception counter 27. The reception counter 27 counts using the clock CLKp3 of the pixel data and outputs the count value Ccount (t) to the subtracter 22.

  As described above in detail, according to the wireless communication system according to the present embodiment, the clock controller 21A can determine whether the video data is within the horizontal blanking period or the vertical blanking period based on the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC. The clock signal CLKp2 from the PLL circuit 26 at the above timing is thinned out or the clock signal CLKp2 is stopped so that the difference value D (t) converges to substantially zero. An insertion process for adding an inverted clock of the clock CLKp2 is performed to generate a clock CLKp3 of pixel data in the sink device 11A. Further, the clock controller 21A detects the accumulation amount Db of the video data in the buffer memory 16, and performs an insertion process and a thinning process based on the detected accumulation amount Db. Thus, even when the clock CLKp2 from the PLL circuit 26 is not synchronized with the clock CLKp1 of the pixel data in the video data, the pixels in the sink device 11A are in units of the horizontal blanking period or vertical blanking period. The data clock CLKp3 can be synchronized with the pixel data clock CLKp1 in the video data. In other words, clock synchronization can be established between the source device 1 and the sink device 11A without affecting the image viewed by the user. Thereby, underflow and overflow of video data in the buffer memory 16 of the sink device 11A can be prevented.

  In the present embodiment, the configuration of the clock generation circuit 18 </ b> A is not limited to the configuration shown in FIG. 5, and may be another circuit configuration that outputs the reference clock CLKref to the PLL circuit 26.

  In the present embodiment, the wireless communication system in which the source device 1 and the sink device 11A are connected via the wireless communication line has been described. However, the present invention is not limited to this, and the source device 1 and the sink device 11A are connected to the wired communication line. It may be a wired communication system connected via

Third embodiment.
FIG. 6 is a block diagram showing a configuration of a wireless communication system according to the third embodiment of the present invention, and FIG. 7 is a block diagram showing a configuration of the clock generation circuit 18B of FIG.

  In FIG. 6, the source device 1 </ b> A includes a video reproduction device 2, a packet generation circuit 3, a transmission counter 4, a wireless communication circuit 5 </ b> A, an antenna 6, and a clock adjustment circuit 7. On the other hand, the sink device 11B includes an antenna 12, a wireless communication circuit 13A, a packet processing circuit 14, a video data processing circuit 15, a buffer memory 16, a display 17, a clock generation circuit 18B, and a synchronization signal generation circuit 19. And is configured.

  In this embodiment, the source device 1A adjusts the frequency of the pixel data clock CLKp1 in the video data based on the clock control data signal Sd transmitted from the sink device 11B, and the adjusted pixel data clock CLKp4. A clock adjustment circuit 7 that generates and outputs the signal, a transmission counter 4 that counts the clock CLKp4 of the pixel data after adjustment from the clock adjustment circuit 7 and outputs a signal indicating the first count value Csource (t), and video A video packet Pvideo of a predetermined packet format including data is generated, and the first count value Csource (t) at the timing of transmitting the video packet to the sink device 11B is added to the header portion of the video packet Pvideo as a time stamp value. Packet generation circuit 3 to be transmitted to sink device 11B It is characterized in that was example. On the other hand, the sink device 11B includes a packet processing circuit 14, a subtractor 22, a clock generation circuit 28, a synchronization signal generation circuit 19, a reception counter 27, and a clock controller 21B. Here, the packet processing circuit 14 receives the video packet Pvideo from the source device 1A, extracts the first count value Csource (t) from the header portion of the received video packet Pvideo, and extracts the extracted first A signal indicating the count value Csource (t) is output. Further, the subtracter 22 is a difference value between a signal indicating the first count value Csource (t) from the packet processing circuit 14 and a signal indicating the second count value Ccount (t) output from the reception counter 27. D (t) is calculated and a difference signal indicating the difference value D (t) is output. Further, the clock generation circuit 28 generates and outputs a clock CLKp2 of pixel data in the sink device 11B based on the difference signal. Furthermore, the synchronization signal generation circuit 19 generates and outputs a horizontal synchronization signal HSYNC and a vertical synchronization signal VSYNC of video data based on the pixel data clock CLKp2 output from the clock generation circuit 28. The reception counter 27 counts the pixel data clock CLKp2 output from the clock generation circuit 28 and outputs a signal indicating the second count value Ccount (t) to the subtractor 22. Furthermore, the clock controller 21B generates a clock control data signal Sd based on the difference value D (t) and transmits it to the clock adjustment circuit 7 of the source device 1A. Here, based on the clock control data signal Sd transmitted from the clock controller 21B of the sink device 11B, the clock adjustment circuit 7 of the source device 1A performs video so that the difference value D (t) converges to substantially zero. The frequency of the pixel data clock CLKp1 in the data is adjusted to generate the adjusted pixel data clock CLKp4.

  Further, the clock controller 21B determines whether or not the difference value D (t) from the subtracter 22 has substantially converged to zero, and the difference value D (t) from the subtractor 22 is substantially zero. The clock control data signal Sd is generated when it has not converged to.

  First, the operation of the source device 1A will be described. In FIG. 6, the video reproduction device 2 reproduces video data from a recording medium such as a DVD and outputs it to the packet generation circuit 3, and outputs a clock CLKp <b> 1 of pixel data in the video data to the clock adjustment circuit 7. Based on the clock control data signal Sd from the sink device 11B, the clock adjustment circuit 7 adjusts the frequency of the clock CLKp1 of the pixel data as will be described later, and generates the clock CLKp4 of the adjusted pixel data as a transmission counter 4 and a packet generator. Output to circuit 3. The transmission counter 4 counts using the adjusted pixel data clock CLKp4. The count value Csource (t) of the transmission counter 4 is added to the header portion of the packet Pvideo as a time stamp value at each timing when the video data packet Pvideo is sent from the wireless communication circuit 5A to the sink device 11B in the packet generation circuit 3. Is done. The packet generation circuit 3 generates a data signal of a video data packet Pvideo in a predetermined packet format including the video data from the video playback device 2, and outputs the data signal to the wireless communication circuit 5A. Further, the wireless communication circuit 5A digitally modulates the wireless carrier signal in accordance with the input data signal, and wirelessly transmits the modulated wireless signal to the antenna 12 of the sink device 11B via the antenna 6. On the other hand, a radio signal transmitted from the antenna 12 of the sink device 11B is received by the antenna 6 and then input to the radio communication circuit 5A. The radio communication circuit 5A demodulates the received radio signal into a digital signal, extracts the clock control data signal Sd, and outputs the clock control data signal Sd to the clock adjustment circuit 7.

  Next, the operation of the sink device 11B will be described. In FIG. 6, a radio signal transmitted from the antenna 6 of the source device 1A is received by the antenna 12, and then input to the radio communication circuit 13A. The wireless communication circuit 13A demodulates the received wireless signal into a digital signal and then outputs it to the packet processing circuit 14. The packet processing circuit 14 outputs the packet Pvideo transmitted from the source device 1A to the synchronization signal generation circuit 19, extracts the count value Csource (t) added to the header of the packet Pvideo, and sends it to the clock generation circuit 18B. Output. Further, the packet processing circuit 14 demultiplexes the video data and outputs it to the video data processing circuit 15. The clock generation circuit 18B generates a clock CLKp2 of pixel data based on the count value Csource (t) and outputs it to the video data processing circuit 15 and the synchronization signal generation circuit 19 as will be described in detail later with reference to FIG. To do. Further, the clock generation circuit 18B generates a clock control data signal Sd based on the difference value D (t) between the count value Ccount (t) and the count value Csource (t) of the clock CLKp2 of the pixel data, and wirelessly Output to the communication circuit 13A. In response to this, the wireless communication circuit 13A digitally modulates the wireless carrier signal in accordance with the input clock control data signal Sd, and wirelessly directs the modulated wireless signal to the antenna 6 of the source device 1A via the antenna 12. Send.

  In FIG. 6, the video data processing circuit 15 performs a predetermined packet decoding process or the like on the input video data based on the clock CLKp2 of the pixel data from the clock generation circuit 18B. After the conversion, the image is output to the display 17 via the buffer memory 16 to display the image. In addition, the synchronization signal generation circuit 19 uses the pixel data clock CLKp2 from the clock generation circuit 18B as a base clock, and transmits the positional information of the transmitted pixel data stored in the header of the packet Pvideo from the packet processing circuit 14 ( For example, the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC are generated and output to the display 17 based on the position of the horizontal pixel and the position of the vertical pixel.

  In FIG. 7, a clock generation circuit 18B includes a filter 23, a D / A converter 24, a VCXO 25, a PLL circuit 26, a clock generation circuit 28, a subtractor 22, a clock controller 21B, and a reception counter 27. And is configured.

  Here, the clock generation circuit 18B operates as follows. In FIG. 7, first, the count value Csource (t) output from the source device 1 </ b> A is input to the subtracter 22. The subtractor 22 calculates a difference value D (t) between the input count value Csource (t) and the count value Ccount (t) from the reception counter 27, and generates a signal indicating the difference value D (t). Then, the data is output to the filter 23 and the clock controller 21B. The filter 23 is composed of, for example, LPF, and smoothes the signal indicating the difference value D (t) and outputs the smoothed signal Dav (t) to the D / A converter 24. The D / A converter 24 converts the smoothed signal Dav (t) into an analog voltage and controls the oscillation frequency of the VCXO 25. The VCXO 25 outputs a reference clock CLKref (for example, having a frequency of 27 MHz) to the PLL circuit 26. The PLL circuit 26 generates a clock CLKp2 based on the reference clock CLKref and outputs it to the synchronization signal generation circuit 19 and the video data processing circuit 15 as a clock for pixel data.

  The difference value D (t) calculated by the subtracter 22 indicates a synchronization state between the adjusted pixel data clock CLKp4 in the source device 1A and the pixel data clock CLKp2 in the sink device 11C. Specifically, when the pixel data clock CLKp4 and the pixel data clock CLKp2 are synchronized, the difference value D (t) converges to zero, and the pixel data clock CLKp4 is higher than the pixel data clock CLKp2. When having a frequency, the difference value D (t) increases, and when the pixel data clock CLKp4 has a lower frequency than the pixel data clock CLKp2, the difference value D (t) decreases.

  In FIG. 7, the clock controller 21B of the sink device 11B detects the difference value D (t) at a predetermined timing based on a signal indicating the difference value D (t). Furthermore, the clock controller 21B determines whether or not the difference value D (t) has substantially converged to zero by determining whether or not the difference value D (t) has increased or decreased a predetermined number of times. Judge whether or not. When the difference value D (t) has not substantially converged to zero, the clock controller 21B generates a clock control data signal Sd indicating that the difference value D (t) has increased or decreased, and the wireless communication circuit 13A, the antennas 12 and 6, and the wireless communication circuit 5A, and then transmitted to the clock adjustment circuit 7 of the source device 1A.

  In response to the clock control data signal Sd transmitted from the sink device 11B, the clock adjustment circuit 7 of the source device 1A, when the difference value D (t) continuously increases a predetermined number of times, Control is performed to lower the frequency of CLKp1, and a clock CLKp4 of pixel data after adjustment is generated. On the other hand, the clock adjustment circuit 7 of the source device 1A controls to increase the frequency of the clock CLKp1 of the pixel data when the difference value D (t) continuously decreases a predetermined number of times, and after the adjustment A clock CLKp4 for pixel data is generated. When the clock adjustment circuit 7 has not received the clock control data signal Sd from the sink device 11B (that is, when the difference value D (t) has substantially converged to zero), the clock adjustment circuit 7 Without adjusting the frequency of the clock CLKp1, it is directly output as the clock CLKp4. Thus, the clock adjustment circuit 7 adjusts the frequency of the pixel data clock CLKp1 so that the difference value D (t) converges to substantially zero, and generates the adjusted pixel data clock CLKp4. The clock adjustment circuit 7 adjusts the frequency of the clock CLKp1 of the pixel data by adjusting the frequency division parameter of the PLL circuit.

  As described above in detail, according to the wireless communication system according to the present embodiment, the clock controller 21B determines whether or not the difference value D (t) from the subtractor 22 has substantially converged to zero. Thus, it is determined whether or not the pixel data clock CLKp4 after adjustment in the source device 1A is synchronized with the pixel data clock CLKp2 in the sink device 11B. Furthermore, the clock controller 21B indicates that the difference value D (t) has increased or decreased when the adjusted pixel data clock CLKp4 in the source device 1A and the pixel data clock CLKp2 in the sink device 11B are not synchronized. A clock control data signal Sd is generated and output to the clock adjustment circuit 7 of the source device 1A. On the other hand, the clock adjustment circuit 7 adjusts the frequency of the clock CLKp1 of the pixel data based on the clock control data signal Sd so that the difference value D (t) converges to substantially zero, and the adjusted pixel data The clock CLKp4 is generated. Thereby, even when the clock CLKp2 of the pixel data from the PLL circuit 26 of the sink device 11B is not synchronized with the clock CLKp1 of the pixel data in the video data in the source device 1A, the adjustment is synchronized with the clock CLKp2 of the pixel data. The clock CLKp4 of the subsequent pixel data can be generated to synchronize the clock between the source device 1A and the sink device 11B. Thus, clock synchronization is performed between the source device 1A and the sink device 11C without affecting the image viewed by the user, and underflow and overflow of the video data in the buffer memory 16 of the sink device 11B can be prevented.

  In the present embodiment, the clock controller 21B generates and transmits the clock control data signal Sd indicating that the difference value D (t) has increased or decreased to the source device 1A, but the present invention is not limited to this. The clock controller 21B receives the clock control data signal Sd indicating the difference value D (t), the clock control data signal Sd indicating that the accumulation amount of the video data in the buffer memory 16 has increased or decreased, or the video data in the buffer memory 16 Generating a signal indicating the synchronization state of the pixel data clock between the pixel data clock CLKp4 in the source device 1A and the pixel data clock CLKp2 in the sink device 11B, such as a clock control data signal Sd indicating the accumulated amount of What is necessary is just to transmit to the source apparatus 1A.

  The clock controller 21B generates the clock control data signal Sd and transmits it to the clock adjustment circuit 7 of the source device 1A when the difference value D (t) has not substantially converged to zero. Is not limited to this. The clock controller 21B may always generate the clock control data signal Sd and send it to the clock adjustment circuit 7 of the source device 1A.

  Furthermore, in the present embodiment, the configuration of the clock generation circuit 18B is not limited to the configuration shown in FIG. 7, and may be another circuit configuration that outputs the reference clock CLKref to the PLL circuit 26.

  Furthermore, in the present embodiment, the wireless communication system in which the source device 1A and the sink device 11B are connected via a wireless communication line has been described. However, the present invention is not limited to this, and the source device 1A and the sink device 11B are connected to each other. It may be a wired communication system connected via a wired communication line.

Fourth embodiment.
FIG. 8 is a block diagram showing a configuration of a wireless communication system according to the fourth embodiment of the present invention, and FIG. 9 is a block diagram showing a configuration of the clock generation circuit 18C of FIG.

  In FIG. 8, the wireless communication system according to the present embodiment includes a source device 1A and a sink device 11C. Here, the sink device 11C is based on the accumulation amount Db of the video data in the buffer memory 16 in place of the clock generation circuit 18B, as compared with the sink device 11B according to the third embodiment (FIG. 6). The clock generation circuit 18C for determining whether or not the clock CLKp4 of the adjusted pixel data in the source device 1A and the clock CLKp2 of the pixel data in the sink device 11B are synchronized is provided.

  The accumulated amount Db of the video data in the buffer memory 16 is similar to the difference value D (t) from the subtracter 22, and the pixel data clock CLKp4 after adjustment in the source device 1 and the pixel data in the sink device 11C. A synchronization state with the clock CLKp2 is shown. Specifically, when the pixel data clock CLKp4 and the pixel data clock CLKp2 are synchronized, the accumulation amount Db does not increase or decrease, and the difference value D (t) from the subtractor 22 is substantially zero. It has converged. When the pixel data clock CLKp4 has a higher frequency than the pixel data clock CLKp2, the accumulation amount Db increases and the difference value D (t) does not converge to zero. Further, when the pixel data clock CLKp4 has a lower frequency than the pixel data clock CLKp2, the accumulation amount Db decreases and the difference value D (t) does not converge to zero.

  In FIG. 9, the clock controller 21C detects the video data accumulation amount Db in the buffer memory 16 at a predetermined timing. Further, the clock controller 21C determines whether or not the difference value D (t) has substantially converged to zero by determining whether or not the accumulated amount Db has increased or decreased continuously for a predetermined number of times. to decide. When the difference value D (t) has not substantially converged to zero, the clock controller 21B generates a clock control data signal Sd indicating the difference value D (t) and outputs it to the wireless communication circuit 13A.

  In response to the clock control data signal Sd from the sink device 11B, the clock adjustment circuit 7 of the source device 1A lowers the frequency of the clock CLKp1 of the pixel data when the accumulation amount Db continuously increases a predetermined number of times. In this way, the clock CLKp4 of the adjusted pixel data is generated. On the other hand, the clock adjustment circuit 7 of the source device 1A controls to increase the frequency of the clock CLKp1 of the pixel data when the accumulation amount Db decreases continuously a predetermined number of times, so that the adjusted pixel data A clock CLKp4 is generated. Further, when the clock adjustment circuit 7 does not receive the clock control data signal Sd from the sink device 11B (that is, when the accumulation amount Db does not increase or decrease continuously for a predetermined number of times), the pixel data Without adjusting the frequency of the clock CLKp1, the clock CLKp1 is output as it is. As a result, the clock adjustment circuit 7 makes the increase / decrease amount of the accumulated amount Db substantially zero (that is, the adjusted pixel data clock CLKp4 in the source device 1 and the pixel data clock CLKp2 in the sink device 11C). Are substantially synchronized so that the difference value D (t) converges to substantially zero), and the frequency of the pixel data clock CLKp1 is adjusted to generate the adjusted pixel data clock CLKp4.

  As described above in detail, according to the wireless communication system according to the present embodiment, the clock controller 21C, based on the video data storage amount Db in the buffer memory 16, adjusts the clock CLKp4 of the adjusted pixel data in the source device 1A. And whether or not the clock CLKp2 of the pixel data in the sink device 11B is substantially synchronized. Further, when the clock CLKp4 of the adjusted pixel data in the source device 1A and the clock CLKp2 of the pixel data in the sink device 11B are not synchronized, the lock controller 21B displays the clock control data signal Sd indicating the difference value D (t). Is output to the clock adjustment circuit 7 of the source device 1A. On the other hand, the clock adjustment circuit 7 adjusts the frequency of the clock CLKp1 of the pixel data based on the clock control data signal Sd so that the difference value D (t) converges to substantially zero, and the adjusted pixel data The clock CLKp4 is generated. Thereby, even when the clock CLKp2 of the pixel data from the PLL circuit 26 of the sink device 11C is not synchronized with the clock CLKp1 of the pixel data in the video data in the source device 1A, the adjustment is synchronized with the clock CLKp2 of the pixel data. The clock CLKp4 of the subsequent pixel data can be generated to synchronize the clock between the source device 1A and the sink device 11C. Thus, clock synchronization is performed between the source device 1A and the sink device 11C without affecting the image viewed by the user, and underflow and overflow of video data in the buffer memory 16 of the sink device 11C can be prevented.

  In this embodiment, the clock controller 21C generates and transmits a clock control data signal Sd indicating that the accumulated amount Db of the video data in the buffer memory 16 has increased or decreased to the source device 1A. Not limited to. The clock controller 21C receives the clock control data signal Sd indicating that the difference value D (t) has increased or decreased, the clock control data signal Sd indicating the difference value D (t), or the amount of video data stored in the buffer memory 16. The source device generates a signal indicating the synchronization state of the pixel data clock between the pixel data clock CLKp4 in the source device 1A and the pixel data clock CLKp2 in the sink device 11C, such as the clock control data signal Sd indicating Db. What is necessary is just to transmit to 1A.

  The clock controller 21B generates the clock control data signal Sd and transmits it to the clock adjustment circuit 7 of the source device 1A when the difference value D (t) has not substantially converged to zero. Is not limited to this. The clock controller 21B may always generate the clock control data signal Sd and send it to the clock adjustment circuit 7 of the source device 1A.

  Furthermore, in the present embodiment, the configuration of the clock generation circuit 18C is not limited to the configuration shown in FIG. 9, and may be another circuit configuration that outputs the reference clock CLKref to the PLL circuit 26.

  Furthermore, in the present embodiment, the wireless communication system in which the source device 1A and the sink device 11C are connected via a wireless communication line has been described. However, the present invention is not limited to this, and the source device 1A and the sink device 11C are connected. It may be a wired communication system connected via a wired communication line.

  In the first and second embodiments, the synchronization signal generation circuit 19 generates a horizontal signal based on the pixel data clock CLKp3 in the sink device 11 or 11A and the positional information of the transmitted pixel data stored in the header of the packet Pvideo. Although the synchronization signal HSYNC and the vertical synchronization signal VSYNC are generated, the present invention is not limited to this, and based on the clock CLKp3 of pixel data and the synchronization flag (for example, the field start point flag) stored in the header of the packet Pvideo. The synchronization signal HSYNC and the vertical synchronization signal VSYNC may be generated. In the third and fourth embodiments, the synchronization signal generation circuit 19 is based on the pixel data clock CLKp2 in the sink device 11B or 11C and the positional information of the transmitted pixel data stored in the header of the packet Pvideo. Thus, the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC are generated. However, the present invention is not limited to this, and is based on the clock CLKp2 of pixel data and the synchronization flag (for example, the field start point flag) stored in the header of the packet Pvideo. Thus, the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC may be generated.

  In the third and fourth embodiments, the clock adjustment circuit 7 adjusts the frequency of the clock CLKp1 of the pixel data by adjusting the frequency division parameter of the PLL circuit. However, the present invention is not limited to this, and the VCXO is not limited to this. The frequency of the clock CLKp1 of the pixel data may be adjusted by using and adjusting the frequency of the reference clock.

  As described above in detail, according to the communication system according to the first invention, the clock control means of the sink device is based on the horizontal synchronization signal and the vertical synchronization signal from the synchronization signal generating means, and the effective pixel area of the video data. Any other timing is detected, and at the detected timing, either a predetermined insertion process or a predetermined decimation process is performed on the clock from the clock generation means so that the difference value converges to substantially zero. Thus, the pixel data clock in the sink device is generated and output, so that the pixel data clock in the sink device can be synchronized with the pixel data clock in the video data without affecting the image viewed by the user. it can. Thereby, underflow and overflow of video data in the sink device can be prevented.

  According to the communication system of the second invention, the clock control means of the sink device generates a clock control data signal based on the difference value and transmits it to the clock adjustment means of the source device to adjust the clock of the source device. The means adjusts the frequency of the pixel data clock in the video data based on the clock control data signal transmitted from the clock control means of the sink device so that the difference value substantially converges to zero, Since the clock of the subsequent pixel data is generated and output, clock synchronization can be established between the source device and the sink device without affecting the image viewed by the user. Thereby, underflow and overflow of video data in the sink device can be prevented.

  The communication system according to the present invention can be used for a wireless communication system compliant with a wireless communication standard such as wireless HD (Wireless High-Definition).

1 is a block diagram illustrating a configuration of a wireless communication system according to a first embodiment of the present invention. FIG. 2 is a block diagram illustrating a configuration of a clock generation circuit 18 in FIG. 1. 3 is a timing chart showing an example of the operation of the clock controller 21 of FIG. It is a block diagram which shows the structure of the radio | wireless communications system which concerns on the 2nd Embodiment of this invention. FIG. 5 is a block diagram showing a configuration of a clock generation circuit 18A of FIG. It is a block diagram which shows the structure of the radio | wireless communications system which concerns on the 3rd Embodiment of this invention. FIG. 7 is a block diagram showing a configuration of a clock generation circuit 18B of FIG. It is a block diagram which shows the structure of the radio | wireless communications system which concerns on the 4th Embodiment of this invention. It is a block diagram which shows the structure of the clock generation circuit 18C of FIG.

Explanation of symbols

1, 1A ... Source device,
2 ... Video playback device,
3 ... packet generation circuit,
4 ... transmission counter,
5, 5A, 13, 13A ... wireless communication circuit,
6,12 ... antenna,
7: Clock adjustment circuit,
11, 11A, 11B, 11C ... sink devices,
14 ... Packet processing circuit,
15 ... Video data processing circuit,
16 ... Buffer memory,
17 ... Display,
18, 18A, 18B, 18C, 28... Clock generation circuit,
19 ... Synchronization signal generating circuit,
21, 21A, 21B, 21C ... clock controller,
22 ... subtractor,
23 ... Filter,
24 ... D / A converter,
25 ... VCXO,
26 ... PLL circuit,
27: Reception counter.

Claims (4)

In a communication system for packet transmission of video data from a source device to a sink device,
The source device is
A transmission counter that counts a clock of pixel data in the video data and outputs a signal indicating a first count value;
A video packet in a predetermined packet format including the video data is generated, and the first count value at the timing of sending the video packet to the sink device is added as a time stamp value to the header of the video packet. Packet generating means for transmitting to the sink device,
The sink device
Packet processing means for receiving the video packet, extracting the first count value from a header portion of the received video packet, and outputting a signal indicating the extracted first count value;
Subtraction for calculating the difference value between the signal indicating the first count value from the packet processing means and the signal indicating the second count value output from the reception counter and outputting the difference signal indicating the difference value Means,
Clock generating means for generating and outputting a clock based on the differential signal;
Synchronization signal generating means for generating and outputting a horizontal synchronization signal and a vertical synchronization signal of the video data based on a clock of pixel data in the sink device;
Based on the horizontal synchronizing signal and the vertical synchronizing signal from the synchronizing signal generating means, timing other than the effective pixel area of the video data is detected, and the difference value is converged to substantially zero at the detected timing. A clock control unit that generates and outputs a clock of pixel data in the sink device by performing either a predetermined insertion process or a predetermined decimation process on the clock from the clock generation unit;
A communication system comprising: a reception counter that counts a clock of pixel data output from the clock control means and outputs a signal indicating the second count value to the subtraction means.   2. The communication system according to claim 1, wherein the timing other than the effective pixel region is a timing within a horizontal blanking period or a vertical blanking period of the video data. In a communication system for packet transmission of video data from a source device to a sink device,
The source device is
Based on a clock control data signal transmitted from the sink device, a clock adjusting unit that adjusts the frequency of the pixel data clock in the video data and generates and outputs the clock of the adjusted pixel data;
A transmission counter that counts the clock of pixel data after adjustment from the clock adjustment means and outputs a signal indicating a first count value;
A video packet in a predetermined packet format including the video data is generated, and the first count value at the timing of sending the video packet to the sink device is added as a time stamp value to the header of the video packet. Packet generating means for transmitting to the sink device,
The sink device
Packet processing means for receiving a video packet from the source device, extracting the first count value from a header portion of the received video packet, and outputting a signal indicating the extracted first count value; ,
Subtraction for calculating the difference value between the signal indicating the first count value from the packet processing means and the signal indicating the second count value output from the reception counter and outputting the difference signal indicating the difference value Means,
Clock generation means for generating and outputting a clock of pixel data in the sink device based on the difference signal;
Synchronization signal generation means for generating and outputting a horizontal synchronization signal and a vertical synchronization signal of the video data based on a clock of pixel data output from the clock generation means;
A reception counter that counts a clock of pixel data output from the clock generation means and outputs a signal indicating the second count value to the subtraction means;
Clock control means for generating the clock control data signal based on the difference value and transmitting it to the clock adjustment means of the source device,
Based on the clock control data signal transmitted from the clock control means of the sink device, the clock adjustment means of the source device is configured to adjust the pixel data in the video data so that the difference value converges to substantially zero. A communication system, wherein a clock frequency of the pixel data after adjustment is generated by adjusting a frequency of the clock.   The clock control means determines whether or not the difference value from the subtraction means has substantially converged to zero, and when the difference value from the subtraction means has not substantially converged to zero, 4. The communication system according to claim 3, wherein a clock control data signal is generated.

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