JP2009188779A - Superconductive output circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain an output interface circuit which can output data at highspeed, and can output data having a broad pulse width concerning a superconductive output circuit. <P>SOLUTION: In the superconductive output circuit provided with an output driver of a superconductive single flux quantum circuit which generates a level logic, the superconductive output circuit comprises two output drivers and an output compositing circuit for compositing output waveforms from the two output drivers, and has a pair of series circuits which comprises a Josephson junction having a hysteresis in which the output compositing circuit separates the two output drivers, and a resistance. Also, a bias current source for supplying a DC offset current is provided in the series circuit. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a superconducting output circuit, and in particular, a configuration for increasing the output speed or widening the pulse width in an output interface circuit used in a superconducting AD converter using a superconducting SFQ (single magnetic flux quantum) circuit or a superconducting digital circuit in general. It is about.

  A superconducting analog / digital circuit using a single flux quantum (SFQ) has a feature that it operates at a higher speed and with lower power consumption than a semiconductor circuit. As its application, research and development has been energetically aimed at application to ultra-high-speed processors, network router switches, AD converters, and the like.

In the SFQ logic circuit, logic operation and signal processing using SFQ pulses are performed at high speed, but it is necessary to finally transfer data after ultra-high speed signal processing to a semiconductor circuit / element in a room temperature environment.
For this purpose, it is necessary to convert from pulse logic to level logic which is a voltage output, and for this purpose, an interface with a room temperature semiconductor circuit / element is required.

  As described above, in order to construct a system using an SFQ circuit, development of an interface with a room temperature semiconductor, in particular, an output interface is one of important technologies in addition to the performance of the SFQ circuit main body.

Thus, various circuits including DC drive and AC drive have been researched and developed as output interface circuits (output drivers or output gates).
For example,
(A) DC-driven SQUID type in which SQUIDs with hysteresis are connected in series with magnetic coupling input (for example, see Non-Patent Document 1 or Non-Patent Document 2),
(B) AC-driven stack type in which junctions with hysteresis are connected in series and parallel (for example, see Non-Patent Document 3), or
(C) A DC-driven DC latch type (see, for example, Patent Document 1) provided with a self-reset circuit has been proposed.

FIG. 15 is a circuit configuration diagram of a conventional SQUID type driver, in which an output voltage is increased by serially connecting SQUIDs having a magnetic field coupling input and no hysteresis. In this configuration method, the input to the SQUID type driver is sequentially distributed and input to the SQUID at the previous stage, and is currently an output driver with a repetition rate of 10 GHz and a low error rate.
In this case, a damping resistor having a small resistance value is connected in parallel to the Josephson junction constituting the SQUID so that the McCamber coefficient is 1 so that there is no hysteresis.

This SQUID type driver is currently operating at a critical current density of 10 kA / cm ² and can be sufficiently operated at a critical current density of 40 kA / cm ² by improving the process technology, thereby Operation at twice the speed, ie 20 GHz repetition frequency, is expected.

  FIG. 16 is a circuit configuration diagram of a conventional AC-driven stacked driver, in which a Josephson junction and resistor series connection circuit having n + 1 hysteresis and a series connection circuit of n Josephson junction and resistance having hysteresis are shown. An AC bias ACBias is applied to a parallel connection circuit.

When the SFQ signal is input, the Josephson junction J ₁ adjacent to the input terminal of the left series connection circuit consisting of n + 1 Josephson junctions and resistors switches to a voltage state, and current flows in the right series connection circuit. Flowing.

At this time, all the Josephson junctions in the right series connection circuit are switched to a voltage state, and the current flows again in the left series connection circuit that is reset to the superconducting state, so that the left series connection circuit The Josephson junction, which was still in the superconducting state, becomes a voltage state. As a result, a current flows through the load circuit, and an output voltage is generated in the load circuit.
In this circuit, since the Josephson junction having hysteresis is used, the voltage once generated is maintained. Therefore, in order to stop the voltage state, the AC bias ACBias needs to be once reduced to zero.

This AC-driven stack type driver has been confirmed to operate at a repetition frequency of 5 GHz by operating at a critical current density of 2.5 kA / cm ² .
Further, when the Josephson junction is composed of an Nb system, an output of about 2.8 mV is ideally obtained with one Josephson junction, but an output of about 2 mV is obtained because of an output loss.

  FIG. 17 is a circuit configuration diagram of a conventional DC-driven latch-type driver, which is a series connection circuit of a Josephson junction and a resistor having two hysteresis, and a series connection circuit of a Josephson junction and a resistor having one hysteresis. A DC bias DCBias is applied to the parallel connection circuit, and a self-reset circuit including a series connection circuit of an inductor L and a resistor R is provided on the output side.

When SFQ signal is inputted, becomes a voltage state Josephson junction J ₁ adjacent to the input terminal of the series connection circuit of left and switch, the Josephson junction current flows on the right side of the series circuit is a voltage state To do. Thereafter, a current flows again through the left series connection circuit that has been reset and is in the superconducting state, and the Josephson junction that was still in the superconducting state in the left series connection circuit becomes a voltage state. As a result, a current flows through the load circuit, and an output voltage is generated in the load circuit.

  At this time, the left and right Josephson junctions are switched to be in a voltage state, but a current flows through the reset circuit according to the time constant LR of the self-reset circuit, the voltage state is released, and the initial state is restored.

Also in this case, operation at a critical current density of 2.5 kA / cm ² and operation at a repetition frequency of ˜5 GHz has been confirmed. In the case of this DC-driven latch type driver, it is not necessary to once make the bias current zero, so that the operation becomes simple.
In this DC-driven latch type driver, from the viewpoint of stability of circuit operation, at present, there is only one Josephson junction on the right side, that is, the output side.
O. A. Mukhanov et al. , IEEE Trans. on Appl. Superconductivity, Vol. 7, no. 2, pp. 2826-2831 Hashimoto et al., Proceedings of the 2006 IEICE General Conference H. Suzuki et al. , IEEE Trans. on Electron Devices, Vol. 37, no. 11, pp. 2399-2405, 1990 JP 2005-260364 A

  However, it was difficult to say that the performance of each of the output interface circuits described above was sufficient. For example, the SFQ circuit can be operated at 40 GHz even if the standard 2 μm process rule is used at present, but as described above, the output driver is limited to the operation of 5 to 10 GHz, and the logic using the SFQ pulse is used. There was a problem that the operation speed was slower than that of the circuit.

Therefore, in order to output data at a rate of 40 GHz, it is necessary to perform serial-parallel conversion to lower the data rate and output, for example, 5 GHz × 8.
However, in this case, there is a problem that the scale of the output interface circuit is increased, the number of output signal lines is increased, and heat inflow to the low temperature environment is increased.

As described above, if the critical current density constituting the circuit is increased, the operation speed can be increased. If the critical current density is quadrupled, the operation speed is approximately doubled.
However, in order to increase the critical current density, it is necessary to develop a microfabrication technique. In the case of the above-described AC-driven stack driver or DC-driven DC latch driver, the current operating speed of 5 GHz is critical. It is very difficult to achieve 40 GHz by increasing the current density.
Note that the AC-driven output driver also has problems such as punch through associated with the characteristics of the Josephson junction.

  In the case of the above SQUID type driver, it is easier to set the operation speed to 40 GHz than the AC driven stack type driver or the DC driven DC latch type driver. Since 100 Josephson junctions are required, there is a problem that the circuit configuration becomes large, which is not realistic.

In addition to the operating speed, the output voltage amplitude and pulse width of the superconducting output driver are not sufficient to drive the semiconductor circuit.
For example, in order to drive a semiconductor circuit composed of GaAs MESFETs, a pulse width of 60 psec is necessary if a voltage of 2 mV and a hold time of 40 psec are taken into consideration.
However, since the current pulse output from the superconducting SFQ circuit is not a rectangular wave but a sawtooth wave, the current situation is that a sufficient pulse width is not obtained.

  As described above, the high-speed operation which is a problem in the conventional output interface circuit has an essential problem that the operation speed has to be slower than that of the SFQ circuit in order to obtain a voltage output. Data rate (output frequency) was limited.

  Therefore, an object of the present invention is to realize an output interface circuit that can output data at a high speed or can output data having a wide pulse width.

  According to one aspect of the present invention, there is provided a superconducting output circuit including an output driver of a superconducting single flux quantum circuit that generates level logic, and combines two output drivers and output waveforms from the two output drivers. An output synthesizing circuit, and the output synthesizing circuit has a pair of series circuits composed of a Josephson junction and a resistor having hysteresis for separating the two output drivers, and supplies a DC offset current to the series circuit. A superconducting output circuit having a bias current source is provided.

  According to the disclosed superconducting output circuit, problems such as high-speed data rate, which were regarded as problems, can be solved by synthesizing the output waveforms of the two output drivers, and a higher data rate (frequency) and wider pulse width can be achieved. A superconducting output interface circuit that generates the output signal can be realized, and as a result, the system can be simplified and stabilized.

Here, an embodiment of the present invention will be described with reference to FIGS.
FIG. 1 is a principle configuration diagram of a superconducting output circuit according to an embodiment of the present invention, in which a pair of output drivers 11 ₁ and 11 ₂ and output waveforms from the pair of output drivers 11 ₁ and 11 ₂ are synthesized. It is composed of a synthesis circuit 12 and a load circuit 15.

The synthesizing circuit 12 includes a pair of separating series circuits 13 ₁ and 13 ₂ and a DC bias source 14, and each of the series circuits 13 ₁ and 13 ₂ includes resistors r ₁ and r ₂ and Josephson junction J ₁ , is composed of a J _2, each Josephson junction J _1, J _2, damping resistors R _1, R ₂ for adjusting the hysteresis, respectively are connected.

The resistors r ₁ and r ₂ are small resistors of about 5Ω and are connected to suppress the formation of the superconducting loop. The resistors r ₁ and r ₂ are connected to each Josephson from the DC bias source 14. A DC offset current I _Bias smaller than the critical current of the Son junctions J ₁ and J ₂ is supplied through the connection point of the pair of series circuits for separation 13 ₁ and 13 ₂ .

The damping resistors R ₁ and R ₂ are connected to adjust the hysteresis characteristics of the Josephson junctions J ₁ and J ₂ , and the McCamber coefficient is sufficiently larger than 1, for example, 5 to 100 To.
When the McCamber coefficient is less than 5, it is not desirable because the resistance when the voltage state is reached is small and the hysteresis is small.

The output of the synthesis circuit 12 is input to a semiconductor circuit such as a semiconductor amplifier in a room temperature environment or a low temperature environment, an LN modulator, a semiconductor laser, or a superconducting photosensor.
The impedance of the load circuit 15 is often terminated at 50Ω including the impedance of the transmission line (cable).

Next, the operating principle of the superconducting output circuit will be described.
As shown in FIG. 2 (a), for example, when the signal A consisting of SFQ pulses to the output driver 11 ₁ is input, the output driver 11 ₁ is switched output current I ₁ flows, the load circuit 15 resistance Therefore, I ₁ tries to flow to the other driver 11 ₂ at first.
However, as shown in FIG. 2 (b), the current of I ₁ + I _Bias / 2 flows through the Josephson junction J ₂ constituting the separating series circuit 13 ₂ and switches to a voltage state to prevent backflow. and the current is supplied to the load circuit 15 as I _out.

Next, as shown in FIG. 3 (c), when the signal B is inputted consisting SFQ pulses delayed by π to output driver 11 _2, output driver 11 ₂ to switch the Josephson junction J _2, FIG. 3 ( As shown in d), the state is reset and becomes a superconducting state.

As shown in FIG. 4E, when the Josephson junction J ₂ is reset and the current I ₂ flows, this time, I ₂ + I _Bias / 2 is _added to the Josephson junction J ₁ constituting the separating series circuit 13 _1. and current flows to prevent backflow by becoming voltage state by the switch, current is supplied to the load circuit 15 as I _out.

Next, as shown in FIG. 4 (f), by repeating the operation from FIG. 2 (a) again, each of the output driver 11 ₁ and the output driver 11 ₂ can perform the original operation. .

FIG. 5 is an explanatory diagram of the result of frequency synthesis. As the synthesized signal C, an output having a frequency (output data rate) twice that of the signal A or the signal B is obtained.
As described above, in order to shift the output timing of the signals A and B by π, one SFQ pulse signal may be converted into two parallel outputs by serial-parallel conversion using a DEMUX (demultiplexer) or shift register. .

  The superconducting output circuit according to the embodiment of the present invention can obtain an output of double frequency (output data rate) when the phase is shifted by π. By shifting about the pulse width, the pulse width can be widened.

FIG. 6 is an explanatory diagram of the result of the pulse width synthesis. As the synthesized signal C, a wide pulse width signal is obtained in which the overlapping portions of the pulse waveforms of the signal A and the signal B have a substantially flat output.
In order to shift the output timings of the signal A and the signal B by about the pulse width of the output signal, one SFQ pulse signal is divided into two identical signals by a splitter circuit, and one signal is delayed using a delay circuit. The output timing difference with the other signal is set to be about the pulse width of the output signal.

In addition, since some leakage current flows through the Josephson junctions J ₁ and J ₂ constituting the separating series circuits 13 ₁ and 13 ₂ even when they are in a voltage state, a plurality of Josephson junctions J ₁ and J ₂ are used. Song junctions may be connected in series.
FIG. 7 shows that each series circuit for separation 13 ₁ , 13 ₂ is composed of two Josephson junctions J ₁₁ , J _21, Josephson junctions J ₁₂ , J ₂₂ and one resistor r ₁ , r _2. It is.

Based on the above, the superconducting output circuit according to the first embodiment of the present invention will now be described with reference to FIGS.
FIG. 8 is a conceptual configuration diagram of the superconducting output circuit according to the first embodiment of the present invention. The DEMUX 21 converts the input signal into series-parallel conversion into two parallel outputs, and the converted parallel outputs are output drivers 23. _1, 23 Josephson transmission line for transmitting the ₂ (JTL) 22 _1, 22 _2, made of the output driver 23 _1, 23 ₂ of the output waveform to the synthesis circuit 24.
Although the delay circuit 25 is provided in the drawing, the delay circuit 25 is not necessary if the distribution timing by the DEMUX 21 is accurate.

FIG. 9 is a specific circuit configuration diagram of the interface unit of the superconducting output circuit according to the first embodiment of the present invention. As an output driver in the superconducting output circuit of FIG. 1, the DC-driven latch driver shown in FIG. Here, the buffer circuit is omitted.
Here, since the pair of output drivers need to have a symmetrical structure, r ₁ = r ₂ , the critical current densities of the Josephson junction J ₁ and the Josephson junction J ₂ are the same, and R ₁ = R ₂ is set.

  FIG. 10 is an explanatory diagram of a simulation result of the operation of the superconducting output circuit according to the first embodiment of the present invention. Here, by using an input signal of 5 GHz as the input signals A and B, an output signal of 10 GHz is obtained. It was confirmed.

  Thus, in the first embodiment of the present invention, the operation speed itself of each circuit remains 5 GHz, and by devising the circuit configuration, an output of 10 GHz with a double data rate can be obtained.

  Therefore, when the repetition frequency of each output driver is set to 20 GHz by improving the process technology to increase the critical current density of each Josephson junction, the 40 GHz SFQ pulse signal is deviated from each other by DEMUX. The output is converted into two parallel outputs of 20 GHz and input to each output driver, whereby the same 40 GHz output as that of the SFQ output circuit can be obtained from the synthesis circuit.

Next, the superconducting output circuit according to the second embodiment of the present invention will be described with reference to FIG. 11. The conceptual configuration of the superconducting output circuit is the same as that of the first embodiment, except that the configuration of the output driver is different. Therefore, only a specific circuit configuration diagram of the interface unit is shown.
FIG. 11 is a specific circuit configuration diagram of the interface unit of the superconducting output circuit according to the second embodiment of the present invention. As an output driver in the superconducting output circuit of FIG. 1 described above, the AC-driven stacked driver shown in FIG. Is used.
Also here, the buffer circuit is omitted.

  In the second embodiment, an AC-driven stack type driver in which a plurality of Josephson junctions are connected on the output side is used, so that the output voltage is increased in proportion to the number of connected Josephson junctions. For example, when two Nb Josephson junctions are connected, an output of about 4 mV can be obtained even if the output loss is subtracted, which is sufficient to drive a semiconductor circuit composed of GaAs MESFETs. is there.

Next, a superconducting output circuit according to a third embodiment of the present invention will be described with reference to FIGS.
FIG. 12 is a conceptual configuration diagram of the superconducting output circuit according to the third embodiment of the present invention. The splitter circuit 26 divides the SFQ pulse output after signal processing such as computation into the same signal, and outputs each of the divided parallel outputs. driver 23 _1, 23 ₂ Josephson transmission line for transmitting the (JTL) 22 _1, 22 _2, one delay circuit for shifting the order of the pulse width input timing of the output 25, the output driver 23 _1, 23 ₂ of the output waveform And a synthesis circuit 24 for synthesizing the signals.

FIG. 13 is a specific circuit configuration diagram of the interface unit of the superconducting output circuit according to the third embodiment of the present invention. The basic circuit configuration is the same as the circuit configuration shown in FIG. The critical current of J ₁ is made smaller than the critical current of Josephson junction J ₂ .
Accordingly, in order to make the offset current applied to the Josephson junction J ₁ from the bias current source smaller than the current applied to the Josephson junction J ₂ , r ₁ > r ₂ is set.
Also here, the buffer circuit is omitted.

FIG. 14 is an explanatory diagram of the simulation result of the operation of the superconducting output circuit according to the third embodiment of the present invention. Here, as the input signals A and B, an input signal having a half width of 60 psec and 5 GHz is used, and the delay time is set. The result is 30 psec.
As shown in the figure, it was confirmed that an output signal C having a wide pulse width was obtained.

The operation in this case, first, the output driver 11 signal A consisting of SFQ pulses ₁ is input, the output driver 11 ₁ is switched output current I ₁ flows, because the load circuit 15 have a resistance I ₁ initially tries to flow to the other driver 11 _two.
However, when a current of I ₁ + I _Bias flows through the Josephson junction J ₂ constituting the separating series circuit 13 ₂ and switches to a voltage state to prevent a backflow, the current flows to the load circuit 15 as I _out. Supplied.

Next, when the signal B is inputted consisting SFQ pulses delayed 30psec to the output driver 11 _2, the Josephson junction J ₂ is reset to the superconducting state output driver 11 ₂ is switched.
At this time, the current I ₂ from the output driver 11 _2, flows into the Josephson junction J _1, which current I ₁ is flowing in the opposite direction together with I _Bias, the critical current density of Josephson junctions J ₁ is relatively small Therefore, the current I ₁ is gradually switched in a state where the current I ₁ is flowing, so that a voltage state is obtained, the back flow of the current I ₂ is prevented, and the current is supplied to the load circuit 15 as a current I _out having a wide pulse width.

Thus, in the third embodiment of the present invention, by devising the circuit configuration, it is possible to obtain an output in which the pulse width is expanded with the conventional technique.
Therefore, when the repetition frequency of each output driver is set to 20 GHz by improving the critical current density of each Josephson junction by improving the process technology, the SFQ pulse signal of 20 GHz is divided by the splitter circuit, and one output Is input with a delay of about half the half width of the pulse waveform, an output of 20 GHz with a wide pulse width is obtained from the synthesis circuit.

  Although the embodiments and examples of the present invention have been described above, the present invention is not limited to the configurations and conditions described in the embodiments and examples, and various modifications can be made. For example, in the above-described third embodiment, a DC-driven latch-type driver is used as an output driver. However, similarly to the second embodiment, an AC-driven stack-type driver may be used.

  Further, in the above-described Example 1 and Example 3, in order to obtain a reliable operation, the output side Josephson junction is made one, but if the process technology is improved and the variation of the elements is reduced, A plurality of Josephson junctions can be connected in series, and in this case, an output voltage proportional to the number of connections can be obtained.

  In each of the above embodiments, the SFQ output circuit and the semiconductor circuit are described as interface circuits. However, by using the interface circuit having such an output driver configuration, high-speed and stable operation is possible. A superconducting A / D converter or a superconducting digital circuit can be configured.

It is a principle block diagram of the superconducting output circuit of the embodiment of the present invention. It is explanatory drawing to the middle of the operation | movement principle of the superconducting output circuit of embodiment of this invention. It is explanatory drawing to the middle after FIG. 2 of the principle of operation of the superconducting output circuit of embodiment of this invention. It is explanatory drawing after FIG. 3 of the principle of operation of the superconducting output circuit of embodiment of this invention. It is explanatory drawing of the result of the frequency synthesis | combination in embodiment of this invention. It is explanatory drawing of the result of the pulse width synthesis | combination in embodiment of this invention. It is a circuit block diagram at the time of comprising the series circuit for isolation | separation by two Josephson junctions. It is a notional block diagram of the superconducting output circuit of Example 1 of this invention. It is a concrete circuit block diagram of the interface part of the superconducting output circuit of Example 1 of this invention. It is explanatory drawing of the simulation result of operation | movement of the superconducting output circuit of Example 1 of this invention. It is a concrete circuit block diagram of the interface part of the superconducting output circuit of Example 2 of this invention. It is a notional block diagram of the superconducting output circuit of Example 3 of the present invention. It is a concrete circuit block diagram of the interface part of the superconducting output circuit of Example 3 of this invention. It is explanatory drawing of the simulation result of operation | movement of the superconducting output circuit of Example 3 of this invention. It is a circuit block diagram of the conventional SQUID type driver. It is a circuit block diagram of the conventional AC drive stack type driver. It is a circuit block diagram of the conventional DC drive latch type driver.

Explanation of symbols

11 ₁ , 11 ₂ output driver 12 synthesis circuit 13 ₁ , 13 ₂ separation series circuit 14 DC bias source 15 load circuit 21 DEMUX
22 ₁ , 22 ₂ Josephson transmission line 23 ₁ , 23 ₂ output driver 24 synthesis circuit 25 delay circuit 26 splitter circuit

Claims (10)

A superconducting output circuit comprising an output driver of a superconducting single flux quantum circuit that generates level logic, comprising two output drivers and an output synthesizing circuit that synthesizes output waveforms from the two output drivers, A superconducting output circuit having a pair of series circuits composed of a Josephson junction having a hysteresis and a resistor for separating the two output drivers, and a bias current source for supplying a DC offset current to the series circuit. 2. The superconducting output circuit according to claim 1, further comprising signal input means for inputting a signal having a phase difference of .pi. To the two output circuits and outputting a signal having a data rate twice that of the input signal. 3. A superconducting output circuit according to claim 2, wherein said signal input means comprises either a demultiplexer or a shift register. The distribution means for distributing the output of the superconducting single-flux quantum circuit in two and the timing difference between the signals input to the output drivers after shifting the divided outputs are shifted by a timing within the pulse width of the input signal. The superconducting output circuit according to claim 1, further comprising a signal input means. 5. The superconducting output circuit according to claim 4, wherein the signal input means includes a splitter circuit and a delay circuit. 6. The superconducting output circuit according to claim 1, wherein each of the output drivers is a DC drive latch type driver having a self-reset function by connecting a resistor and an inductance in series. 6. The superconducting output circuit according to claim 1, wherein each of the output drivers is an AC driven stack type driver having two or more output-side Josephson junctions. The superconducting output circuit according to any one of claims 1 to 7, wherein a DC offset current supplied to the series circuit is supplied via a connection point of the pair of DC circuits. The superconducting output circuit according to any one of claims 1 to 8, wherein a Mcson bar coefficient of a Josephson junction constituting each series circuit is 5 or more. The superconducting output circuit according to any one of claims 1 to 9, wherein the Josephson junction constituting each series circuit comprises a series circuit of a plurality of Josephson junctions.

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