US10158363B1 - Josephson and/or gate - Google Patents
Josephson and/or gate Download PDFInfo
- Publication number
- US10158363B1 US10158363B1 US15/811,000 US201715811000A US10158363B1 US 10158363 B1 US10158363 B1 US 10158363B1 US 201715811000 A US201715811000 A US 201715811000A US 10158363 B1 US10158363 B1 US 10158363B1
- Authority
- US
- United States
- Prior art keywords
- logical
- input
- bias
- storage
- quantizing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 claims description 15
- 230000004907 flux Effects 0.000 claims description 7
- 230000005540 biological transmission Effects 0.000 claims description 4
- 230000001902 propagating effect Effects 0.000 claims description 4
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000004513 sizing Methods 0.000 description 3
- 230000004044 response Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002887 superconductor Substances 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/195—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/195—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices
- H03K19/1954—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices with injection of the control current
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
Abstract
A Josephson AND/OR gate circuit makes efficient use of Josephson junction (JJ) and inductor components to provide two-input, two-output AND/OR logical functions. The circuit includes four logical input storage loops that each contain one of two logical decision JJs that are configured such that they trigger to provide the OR and AND signals, respectively. Functional asymmetry is provided in the topologically symmetrical AND/OR gate circuit by a bias storage loop that includes both of the logical decision JJs and that is initialized to store a directional Φ0 of current at system start-up.
Description
The present invention relates generally to quantum and classical digital superconducting circuits, and specifically to a Josephson AND/OR gate.
In the field of digital logic, extensive use is made of well known and highly developed complimentary metal-oxide semiconductor (CMOS) technology. As CMOS has begun to approach maturity as a technology, there is an interest in alternatives that may lead to higher performance in terms of speed, power dissipation computational density, interconnect bandwidth, and the like. An alternative to CMOS technology comprises superconductor based single flux quantum circuitry, utilizing superconducting Josephson junctions (JJs), with typical signal power of around 4 nanowatts (nW), at a typical data rate of 20 gigabits per second (Gb/s) or greater, and operating temperatures of around 4 kelvins.
An AND/OR gate is a logical gate having at least two logical inputs and at least two logical outputs, one of the logical outputs representing the AND logical function and another of the outputs representing the OR logical function. The AND output of the AND/OR gate returns an asserted output signal if and only if all of the logical inputs are asserted. The OR output returns an asserted output signal if any one of the logical inputs is asserted.
One example provides a superconducting AND/OR gate circuit. A first logical input is configured to provide a first input single flux quantum (SFQ) pulse to first and second quantizing storage loops. A second logical input is configured to provide a second input SFQ pulse to third and fourth quantizing storage loops. A DC bias input is configured to provide an initializing SFQ pulse to a fifth quantizing storage loop. A first logical decision Josephson junction (JJ) common to the first, fourth, and fifth quantizing storage loops is configured to assert a first logical output based on the first and second logical inputs both being asserted and to de-assert the first logical output based on either or both of the first or second logical inputs being de-asserted. A second logical decision JJ common to the second, third, and fifth quantizing storage loops is configured to assert a second logical output based on either or both of the first or second logical inputs being asserted and to de-assert the second logical output based on the first and second logical inputs both being de-asserted.
Another example provides a method of determining logical AND and OR values based on SFQ pulse inputs. An initializing current is established in a bias storage loop comprising first and second logical decision JJs in a reciprocal quantum logic (RQL) AND/OR gate. Positive SFQ pulses are provided to assert one or both logical inputs of the RQL AND/OR gate, thereby placing currents in quantizing logical input storage loops in the RQL AND/OR gate and causing one or both logical decision JJs to be triggered. A logical OR assertion signal propagates from an OR output of the RQL AND/OR gate based on one or both logical inputs being asserted. A logical AND assertion signal can also propagate from an AND output of the RQL AND/OR gate based on both logical inputs being asserted.
Another example provides a superconducting gate circuit, which includes a first input configured to provide a first input pulse and a second input configured to provide a second input pulse. The circuit further includes a first storage loop comprising a first quantizing storage inductor interconnecting a first input JJ and a first logical decision JJ, a second storage loop comprising a second quantizing storage inductor interconnecting the first input JJ and a second logical decision JJ, a third storage loop comprising a third quantizing storage inductor interconnecting a second input JJ and the second logical decision JJ, a fourth storage loop comprising a fourth quantizing storage inductor interconnecting the second input JJ and the first logical decision JJ, and a bias storage loop comprising the first and second logical decision JJs. A logical AND output in the circuit is configured to be asserted based on positive input pulses being provided to both the first and second logical inputs. A logical OR output in the circuit is configured to be asserted based on a positive input pulse being provided to at least one of the first and second logical inputs.
This disclosure relates generally to logical gate circuits for use in superconducting systems. A two-input, two-output superconducting gate can be configured to provide two logic functions, such as two different logic functions, in response to a pair of inputs. As an example, the two logic functions can correspond to a logic-AND operation and a logic-OR operation on the respective pair of inputs. As an example, the inputs can each be provided via a Josephson transmission line (JTL), such as in a reciprocal quantum logic (RQL) superconducting circuit.
Storage loops 106-1, 106-2, 106-3, 106-4, 106-5 can be quantizing storage loops, by which it is meant that storage elements therein are sized large enough such that stored current alone, even with the AC bias, is insufficient trigger Josephson junctions at either end, such as JJs 108-1 and 108-2. The quantizing nature of the storage loops permits them to stably store a full Φ0 of current for an arbitrary amount of time until some condition is met.
First logical decision Josephson junction (JJ) 108-1 is common to (i.e., shared by) first and fourth logical input storage loops 106-1, 106-4, as well as bias storage loop 106-5. First logical decision JJ 108-1 triggers based on logical inputs A and B both being asserted. The assertion or de-assertion of output AO is based on the triggering of first logical decision JJ 108-1. For example, output AO can propagate a positive SFQ pulse corresponding to an asserted output logic state when both A and B are asserted, and a negative SFQ pulse corresponding to a de-asserted output logic state when either or both of A or B are de-asserted.
Second logical decision JJ 108-2 is common to (i.e., shared by) second and third logical input storage loops 106-2, 106-3, as well as bias storage loop 106-5. Second logical decision JJ 108-2 triggers based on either or both of logical inputs A or B being asserted. The assertion or de-assertion of output OO is based on the triggering of second logical decision JJ 108-2. For example, output OO can propagate a positive SFQ pulse corresponding to an asserted output logic state when either or both of A or B are asserted, and a negative SFQ pulse corresponding to a de-asserted output logic state when both A and B are de-asserted.
Bias storage loop 106-5 includes both first logical decision JJ 108-1 and second logical decision JJ 108-2. Output stage 102 includes two output Josephson transmission lines (JTLs) 110, 114 to amplify the outputs of logical decision JJs 108-1, 108-2. AND output JTL 110 corresponds to AND output AO, while OR output JTL 114 corresponds to OR output OO. The triggering of logical decision JJs 108-1, 108-2 can be based not only on inputs A and B, but also on bias signals 112, 116 provided to output stage 102, e.g., to output JTLs 110, 114, respectively. Bias signals 112, 116 can provide both AC and DC bias. Thus, for example, bias signals 112, 116 can act as a clock to AND/OR gate 100, causing the evaluation of the inputs A and B to produce the outputs AO, OO at certain points in time according to the AC component of bias signals 112, 116.
The storage inductors Lstoraa, Lstorba, Lstorao, Lstorbo, and Lstorbias can be quantizing storage inductors, by which it is meant that they are sized large enough such that stored current alone, even with the AC bias, is insufficient trigger Josephson junctions at either end, e.g., b2 a_0, b2 b_0, b0_1, b0_0 as they pertain in pairs to any corresponding loop. The quantizing nature of the storage loops permits them to stably store a full Φ0 of current for an arbitrary amount of time until some condition is met.
A first storage loop comprises first input JJ b2 a_0, first storage inductor Lstoraa, and first logical decision JJ b0_1. A second storage loop comprises first input JJ b2 a_0, second storage inductor Lstorao, and second logical decision JJ b0_0. A third storage loop comprises second input JJ b2 b_0, third storage inductor Lstorbo, and second logical decision JJ b0_0. A fourth storage loop comprises second input JJ b2 b_0, fourth storage inductor Lstorba, and first logical decision JJ b0_1. A first output JTL, associated with the logical AND output, consists of first logical decision JJ b0_1, inductors FL4_1, L2_1, and FL5_1, and first output JJ b1_1. A second output JTL, associated with the logical OR output, consists of second logical decision JJ b0_0, inductors FL4_0, L2_0, and FL5_0, and second output JJ b1_0.
An inductor, bias inductor Lstorbias, is connected between the two logical decision JJs, b0_0 and b0_1, to establish the fifth storage loop, a bias storage loop, that is initialized to a certain state at system start-up. Bias inductor Lstorbias can be slightly smaller than inductors that in a different topology (not shown) might be placed between the upper connections of logical decision JJs b0_1, b0_0 and a low-voltage node (e.g., a ground node), yielding an overall more efficient gate. At startup of the operation of circuit 200, bias inductor Lstorbias can be initialized with application of one Φ0 of current 202. Such application can be achieved either directly, via a transformer coupling to a DC current 204, as shown in FIG. 2B , or indirectly, via transformer and quantizing JJ 206, as shown in FIG. 2C , or by any other suitable mechanism. In the variation of circuit 200 shown in FIG. 2C , bias inductor Lstorbias is split into two inductors, bias inductors Lstorbias1 and Lstorbias2, in series with and separated by quantizing JJ bquant, which is connected in parallel with a transformer coupling to a DC bias so as to provide the aforementioned initializing current. This current 202 is shown in FIG. 2A as flowing from the AND side of the gate, b0_1, towards the OR side of the gate, b0_0.
With regard to component sizings, as an example, input inductors FL6 a_0 and FL6 b_0 can be sized to provide about 8.5 picohenries (pH) of inductance Storage inductors Lstoraa, Lstorba, Lstorao, Lstorbo, and Lstorbias can all be sized, for example, to provide about 35 pH of inductance. Output JTL inductors FL4_1 and FL5_1 can be sized such that their inductances sum to about 14 pH, for example. Similarly, output JTL inductors FL4_0 and FL5_0 can be sized such that their inductances sum to about 14 pH. Bias input inductors L2_1 and L2_0 in the output JTLs can be sized to provide appropriate bias current. The given example component sizings can be scaled proportionately. The AC components of bias signals bias_1 and bias_0 can be the same or about the same phase. By “about,” it is meant within tolerances acceptable for circuit functioning as described herein, e.g., ±10%.
When the AC bias provided by bias lines bias_0 and bias_1 is sufficiently positive, these currents 202 and 304 cause second logical decision JJ b0_0 to trigger, as shown in FIG. 3C . This will drive an SFQ pulse 308 towards second output JJ b1_0, which will then trigger and propagate the pulse 310 out of the logical OR output oo, as shown in FIG. 3D . Additionally, the Φ0 of current 202 stored in bias inductor Lstorbias (not shown in FIG. 3C or 3D ) is removed, and a Φ0 of current 312 is placed into the loop formed by second logical decision JJ b0_0, second storage inductor Lstorao, and first input JJ b2 a_0 flowing towards first input JJ b2 a_0.
The above sequence illustrates the result of providing an assertion SFQ pulse 302 on second logical input bi alone: an assertion SFQ pulse 310 on output oo alone. However, an assertion SFQ pulse on first logical input ai alone will not generate an assertion SFQ pulse on output ao alone despite the apparent topological symmetry of circuit 200 with respect to its upper and lower halves. Directional initializing bias current 202 engenders a functional asymmetry that realizes the correct logical functioning of OR and AND outputs oo and ao, respectively. Logical decision JJs b0_1 and b0_0 each effectively operate as a 2-of-3 majority gate with respect to currents in the three storage loops connected to each of them—b0_1 being connected to storage inductors Lstoraa, Lstroba, and Lstorbias, and b0_0 being connected to storage inductors Lstorbo, Lstorao, and Lstorbias. After initialization of bias current 202, second logical decision JJ b0_0, corresponding to the OR output, sees bias current 202 as a positive current on one of its three storage-loop inputs, while first logical decision JJ b0_1, corresponding to the AND output, sees bias current 202 as a negative current on one of its three storage-loop inputs. As a consequence of this functional asymmetry, an assertion SFQ pulse on first logical input ai alone will also generate an assertion SFQ pulse on output oo and not on output ao.
Following from the circuit state established in the previously described sequence, FIG. 3E shows the application of a second positive SFQ input pulse via the first logical input ai to establish current 314. This triggers first input JJ b2 a_0, as shown in FIG. 3F , which removes the Φ0 of current 312 from the second storage loop containing second storage inductor Lstorao and places an SFQ 316 into the first storage loop comprising first input JJ b2 a_0, first storage inductor Lstoraa, and first logical decision JJ b0_1, flowing from first input JJ b2 a_0 to first logical decision JJ b0_1. Now when the AC bias provided by bias lines bias_0 and bias_1 is sufficiently positive, first logical decision JJ b0_1 receives two Φ0 of positive current and triggers, as shown in FIG. 3G , driving an SFQ 318 towards first output JJ b1_1, which will then trigger to assert the logical AND output ao by propagating a pulse out that output (not shown). Additionally, it will also destroy current 306 (first generated in FIG. 3B ) with an equal and opposite current, and put one Φ0 of current 320 into bias inductor Lstorbias flowing from first logical decision JJ b0_1 to second logical decision JJ b0_0, restoring this loop to its initial state (i.e., as with current 202 shown in FIGS. 2A and 3A ).
Logical AND output ao is deasserted when one of the inputs is deasserted via the application of a negative SFQ pulse. Applied to either logical input, this pulse will look similar to the initial input application but the direction of the current is reversed, negatively triggering (“untriggering”) the respective input JJ and putting current into the internal storage loops in the opposite direction. Following from the circuit state established in the previously described sequence, FIG. 3H shows the state of the circuit after first input JJ b2 a_0 has been untriggered to take it from a 2π superconducting phase to a zero superconducting phase following the application of a negative SFQ pulse to first logical input ai. A negative current 322 is established in the first storage loop between input JJ b2 a_0, first storage inductor Lstoraa, and first logical decision JJ b0_1. Another negative current 324 is likewise established in the second storage loop between input JJ b2 a_0, second storage inductor Lstorao, and second logical decision JJ b0_0.
Then, during the negative portion of the AC cycle (i.e., when the AC bias provided by bias lines bias_0 and bias_1 is sufficiently negative), the AC bias plus the stored currents will sum to untrigger first logical decision JJ b0_1 and deassert logical AND output ao. This will leave the circuit in the state shown in FIG. 3I , which is the same state as the state shown in FIG. 3D after output pulse 310 has exited circuit 200, storage loop currents 324 and 326 in FIG. 3I corresponding to storage loop currents 312 and 306 in FIG. 3D , respectively. The application of a second negative SFQ pulse (not shown) to deassert second logical input bi untriggers second input JJ b2 b_0, resulting in the state shown in FIG. 3J , with negative current 328 in third storage loop between second input JJ b2 b_0, third storage inductor Lstorbo, and second logical decision JJ b0_0. During the negative portion of the AC clock cycle (i.e., when the AC bias provided by bias lines bias_0 and bias_1 is sufficiently negative), the bias plus the two stored currents untrigger second logical decision JJ b0_0. This untriggering drives a negative SFQ pulse towards second output JJ b1_0, which itself untriggers, propagating a negative output pulse out of logical OR output oo to deassert that output. Additionally, this will put one Φ0 of current into the loop including bias inductor Lstorbias flowing from first logical decision JJ b0_1 to second logical decision JJ b0_0, corresponding to initial current 202 in FIGS. 2A and 3A , restoring the circuit to its original state.
The above-described circuits can provide a single storage inductor Lstorbias, or two such storage inductors Lstorbias1, Lstorbias2 in series, rather than two separate storage inductors connected to a low-voltage rail (e.g., ground), to perform the same function more efficiently. The improved efficiency of the described AND/OR logic gates can result in denser circuits. The above-described circuits further avoid the need for transformer couplings between storage inductors, permitting the circuit to have a simplified layout that is scalable to smaller process nodes. The described circuit designs can also use a full Φ0 flux bias current, which is easier to introduce than a fraction of a Φ0 where a Josephson junction is used to quantize the flux bias, given that a full Φ0 of current is the natural output of a Josephson junction. The above examples are also capable of storing at least one Φ0 of current in any of the storage inductors in the storage loops, and in some cases can store 2Φ0.
One or both logical decision JJs then trigger 408. For example, a first logical decision JJ can trigger based on both the logical inputs being asserted, and/or a second logical decision JJ can trigger based on one or both the logical inputs being asserted. The second logical decision JJ may trigger further based on the presence of the current established 402 in the bias storage loop. The first logical decision JJ may trigger further based on the absence of the current established 402 in the bias storage loop. The first and second logical decision JJs can be configured to so trigger, for example, by making them common to multiple of the logical input storage loops, by providing appropriate biasing, and/or by appropriate component sizing.
A logical OR assertion signal, generated as a result of the second logical decision JJ triggering, can then propagate 410 from an OR output of the RQL AND/OR gate based on one or both logical inputs being asserted. A logical AND assertion signal, generated as a result of the first logical decision JJ triggering, can then propagate 410 from an OR output of the RQL AND/OR gate based on both logical inputs being asserted. Each of these assertion signals can be, for example, a single SFQ pulse.
What have been described above are examples of the invention. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the invention, but one of ordinary skill in the art will recognize that many further combinations and permutations of the invention are possible. Accordingly, the invention is intended to embrace all such alterations, modifications, and variations that fall within the scope of this application, including the appended claims. Additionally, where the disclosure or claims recite “a,” “an,” “a first,” or “another” element, or the equivalent thereof, it should be interpreted to include one or more than one such element, neither requiring nor excluding two or more such elements. As used herein, the term “includes” means includes but not limited to, and the term “including” means including but not limited to. The term “based on” means based at least in part on.
Claims (20)
1. A superconducting AND/OR gate circuit comprising:
a first logical input configured to provide a first input single flux quantum (SFQ) pulse to first and second quantizing storage loops;
a second logical input configured to provide a second input SFQ pulse to third and fourth quantizing storage loops;
a DC bias input configured to provide an initializing SFQ pulse to a fifth quantizing storage loop,
a first logical decision Josephson junction (JJ) common to the first, fourth, and fifth quantizing storage loops, configured to assert a first logical output based on the first and second logical inputs both being asserted and to de-assert the first logical output based on either or both of the first or second logical inputs being de-asserted;
a second logical decision JJ common to the second, third, and fifth quantizing storage loops, configured to assert a second logical output based on either or both of the first or second logical inputs being asserted and to de-assert the second logical output based on the first and second logical inputs both being de-asserted.
2. The circuit of claim 1 , further comprising first and second output Josephson transmission lines (JTLs) configured to amplify the first and second logical outputs, respectively.
3. The circuit of claim 2 , further comprising bias inputs to the output JTLs configured to induce respective bias currents in the logical decision JJs based on bias signals.
4. The circuit of claim 3 , wherein the assertion of the first and second logical outputs is further based on the bias currents.
5. The circuit of claim 1 , wherein each storage loop is configured to store a superconducting current based on the assertion of inputs.
6. The circuit of claim 1 , wherein
the first quantizing storage loop comprises a first quantizing storage inductor interconnecting a first input JJ and the first logical decision JJ,
the second quantizing storage loop comprises a second quantizing storage inductor interconnecting the first input JJ and the second logical decision JJ,
the third quantizing storage loop comprises a third quantizing storage inductor interconnecting a second input JJ and the second logical decision JJ, and
the fourth quantizing storage loop comprises a fourth quantizing storage inductor interconnecting the second input JJ and the first logical decision JJ.
7. The circuit of claim 6 , wherein the fifth quantizing storage loop comprises a bias inductor interconnecting the first logical decision JJ and the second logical decision JJ.
8. The circuit of claim 7 , wherein the bias inductor is transformer-coupled to the DC bias input.
9. The circuit of claim 6 , wherein the fifth quantizing storage loop comprises a series arrangement interconnecting the first logical decision JJ and the second logical decision JJ, the series arrangement comprising a parallel arrangement interconnecting a first bias inductor and a second bias inductor, the parallel arrangement comprising a quantizing JJ and an inductor that is transformer-coupled to the DC bias input.
10. A method of determining logical AND and OR values based on SFQ pulse inputs, the method comprising:
establishing an initializing current in a bias storage loop comprising first and second logical decision Josephson junctions (JJs) in a reciprocal quantum logic (RQL) AND/OR gate;
providing positive SFQ pulses to assert one or both logical inputs of the RQL AND/OR gate;
placing currents in quantizing logical input storage loops in the RQL AND/OR gate;
triggering one or both logical decision JJs;
propagating a logical OR assertion signal from an OR output of the RQL AND/OR gate based on one or both logical inputs being asserted.
11. The method of claim 10 , wherein the logical OR assertion signal is generated as a result of the second logical decision JJ triggering.
12. The method of claim 11 , wherein the second logical decision JJ triggering is further based on the presence of the current established in the bias storage loop.
13. The method of claim 10 , further comprising:
propagating a logical AND assertion signal from an AND output of the RQL AND/OR gate based on both logical inputs being asserted.
14. The method of claim 13 , wherein the logical AND assertion signal is generated as a result of the first logical decision JJ triggering.
15. The method of claim 14 , wherein the first logical decision JJ triggering is further based on the absence of current in the bias storage loop.
16. The method of claim 10 , wherein the triggering of the one or both logical decision JJs is based on an AC bias provided by at least one bias lines being sufficiently positive.
17. The method of claim 10 , wherein the RQL AND/OR gate comprises no more than six JJs and no more than fourteen inductors.
18. A superconducting gate circuit comprising:
a first input configured to provide a first input pulse;
a second input configured to provide a second input pulse;
a first storage loop comprising a first quantizing storage inductor interconnecting a first input Josephson junction (JJ) and a first logical decision JJ;
a second storage loop comprising a second quantizing storage inductor interconnecting the first input JJ and a second logical decision JJ;
a third storage loop comprising a third quantizing storage inductor interconnecting a second input JJ and the second logical decision JJ;
a fourth storage loop comprising a fourth quantizing storage inductor interconnecting the second input JJ and the first logical decision JJ;
a bias storage loop comprising the first and second logical decision JJs;
a logical AND output configured to be asserted based on positive input pulses being provided to both the first and second logical inputs; and
a logical OR output configured to be asserted based on a positive input pulse being provided to at least one of the first and second logical inputs.
19. The circuit of claim 18 , wherein the logical AND and logical OR outputs are configured to be asserted further based on the presence or absence of current in the bias storage loop.
20. The circuit of claim 18 , wherein the bias storage loop further comprises an inductor interconnecting the first and second logical decision JJs, the inductor being configured to initialize the bias storage loop to hold one Φ0 of current at startup.
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/811,000 US10158363B1 (en) | 2017-11-13 | 2017-11-13 | Josephson and/or gate |
PCT/US2018/056316 WO2019094162A1 (en) | 2017-11-13 | 2018-10-17 | Josephson and/or gate |
CA3077219A CA3077219C (en) | 2017-11-13 | 2018-10-17 | Josephson and/or gate |
KR1020207012934A KR102291321B1 (en) | 2017-11-13 | 2018-10-17 | josephson AND/OR gate |
AU2018364957A AU2018364957B2 (en) | 2017-11-13 | 2018-10-17 | Josephson AND/OR gate |
JP2020517893A JP6894048B2 (en) | 2017-11-13 | 2018-10-17 | Josephson AND / OR Gate |
EP18799635.0A EP3711165B1 (en) | 2017-11-13 | 2018-10-17 | Superconducting and/or gate and method for determining logical and/or values based on single flux quantum pulse inputs |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/811,000 US10158363B1 (en) | 2017-11-13 | 2017-11-13 | Josephson and/or gate |
Publications (1)
Publication Number | Publication Date |
---|---|
US10158363B1 true US10158363B1 (en) | 2018-12-18 |
Family
ID=64172591
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/811,000 Active US10158363B1 (en) | 2017-11-13 | 2017-11-13 | Josephson and/or gate |
Country Status (7)
Country | Link |
---|---|
US (1) | US10158363B1 (en) |
EP (1) | EP3711165B1 (en) |
JP (1) | JP6894048B2 (en) |
KR (1) | KR102291321B1 (en) |
AU (1) | AU2018364957B2 (en) |
CA (1) | CA3077219C (en) |
WO (1) | WO2019094162A1 (en) |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10389361B1 (en) * | 2018-02-01 | 2019-08-20 | Northrop Grumman Systems Corporation | Four-input josephson gates |
US10554207B1 (en) * | 2018-07-31 | 2020-02-04 | Northrop Grumman Systems Corporation | Superconducting non-destructive readout circuits |
US10615783B2 (en) * | 2018-07-31 | 2020-04-07 | Northrop Grumman Systems Corporation | RQL D flip-flops |
US10650319B2 (en) | 2015-02-06 | 2020-05-12 | Northrop Grumman Systems Corporation | Flux control of qubit under resonant excitation |
US10756712B2 (en) | 2017-11-13 | 2020-08-25 | Northrop Grumman Systems Corporation | RQL phase-mode flip-flop |
US10769344B1 (en) * | 2019-07-22 | 2020-09-08 | Microsoft Technology Licensing, Llc | Determining timing paths and reconciling topology in a superconducting circuit design |
US11201608B2 (en) | 2020-04-24 | 2021-12-14 | Northrop Grumman Systems Corporation | Superconducting latch system |
US11380835B2 (en) | 2019-07-22 | 2022-07-05 | Microsoft Technology Licensing, Llc | Determining critical timing paths in a superconducting circuit design |
WO2024023577A1 (en) * | 2022-07-27 | 2024-02-01 | Imec Vzw | Sfq-based pulse-conserving logic gates |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20210149521A (en) | 2020-06-02 | 2021-12-09 | 삼성전자주식회사 | Memory system and operating method of the same |
Citations (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3094685A (en) | 1957-09-30 | 1963-06-18 | Ibm | Non-destructive readout system |
US4956642A (en) | 1987-11-24 | 1990-09-11 | Research Development Corporation Of Japan | Superconducting analog to digital converter |
US5233243A (en) | 1991-08-14 | 1993-08-03 | Westinghouse Electric Corp. | Superconducting push-pull flux quantum logic circuits |
US6310488B1 (en) | 1998-12-02 | 2001-10-30 | Hitachi, Ltd. | Superconductive single flux quantum logic circuit |
US20030011398A1 (en) | 2001-06-15 | 2003-01-16 | Herr Quentin P. | Combinational logic using asynchronous single-flux quantum gates |
US20030016069A1 (en) | 2001-06-15 | 2003-01-23 | Hitachi, Ltd. | Superconducting single flux quantum circuit |
US6734699B1 (en) | 1999-07-14 | 2004-05-11 | Northrop Grumman Corporation | Self-clocked complementary logic |
US6756925B1 (en) | 2003-04-18 | 2004-06-29 | Northrop Grumman Corporation | PSK RSFQ output interface |
US7129869B2 (en) | 2003-08-28 | 2006-10-31 | Hitachi, Ltd. | Superconductor semiconductor integrated circuit |
US7227480B2 (en) | 2005-06-22 | 2007-06-05 | Hitachi, Ltd. | Current steering type single flux quantum circuit |
US20090153180A1 (en) | 2007-12-13 | 2009-06-18 | Herr Quentin P | Single flux quantum circuits |
US7786748B1 (en) | 2009-05-15 | 2010-08-31 | Northrop Grumman Systems Corporation | Method and apparatus for signal inversion in superconducting logic gates |
US7903456B2 (en) | 2006-02-23 | 2011-03-08 | Hypres, Inc. | Superconducting circuit for high-speed lookup table |
US7944253B1 (en) | 2005-10-04 | 2011-05-17 | Hypres, Inc. | Digital programmable frequency divider |
US20110133770A1 (en) | 2008-05-29 | 2011-06-09 | John Xavier Przybysz | Method and apparatus for controlling qubits with single flux quantum logic |
US8489163B2 (en) | 2011-08-12 | 2013-07-16 | Northrop Grumman Systems Corporation | Superconducting latch system |
US8611974B2 (en) | 2008-06-03 | 2013-12-17 | D-Wave Systems Inc. | Systems, methods and apparatus for superconducting demultiplexer circuits |
US20160164505A1 (en) | 2014-12-09 | 2016-06-09 | Northrop Grumman Systems Corporation | Josephson current source systems and method |
US9455707B2 (en) | 2014-07-08 | 2016-09-27 | Northrop Grumman Systems Corporation | Superconductive gate system |
US9543959B1 (en) | 2015-10-21 | 2017-01-10 | Microsoft Technology Licensing, Llc | Phase-mode based superconducting logic |
US9595970B1 (en) | 2016-03-24 | 2017-03-14 | Northrop Grumman Systems Corporation | Superconducting cell array logic circuit system |
US9646682B1 (en) | 2016-05-27 | 2017-05-09 | Northrop Grumman Systems Corporation | Reciprocal quantum logic (RQL) sense amplifier |
US9712172B2 (en) | 2015-10-07 | 2017-07-18 | Microsoft Technology Licensing, Llc | Devices with an array of superconducting logic cells |
US9812192B1 (en) | 2016-09-02 | 2017-11-07 | Northrop Grumman Systems Corporation | Superconducting gate memory circuit |
US20170359072A1 (en) * | 2016-06-08 | 2017-12-14 | Auburn University | Superconducting quantum logic and applications of same |
US9876505B1 (en) | 2016-09-02 | 2018-01-23 | Northrop Grumman Systems Corporation | Superconducting isochronous receiver system |
US9905900B2 (en) | 2015-05-01 | 2018-02-27 | Northrop Grumman Systems Corporation | Superconductor circuits with active termination |
US9917580B2 (en) | 2015-02-06 | 2018-03-13 | Northrop Grumman Systems Corporation | Superconducting single-pole double-throw switch system |
US9972380B2 (en) | 2016-07-24 | 2018-05-15 | Microsoft Technology Licensing, Llc | Memory cell having a magnetic Josephson junction device with a doped magnetic layer |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2688011B2 (en) * | 1994-12-16 | 1997-12-08 | 工業技術院長 | Unit circuit for building asynchronous superconducting logic circuits |
US5963351A (en) * | 1996-08-23 | 1999-10-05 | Conductus, Inc. | Digital optical receiver with instantaneous Josephson clock recovery circuit |
CN101626233B (en) * | 2009-08-03 | 2011-07-20 | 杭州电子科技大学 | Resistive superconductive asynchronous bilinear logic universal gate circuit |
CN101626234B (en) * | 2009-08-03 | 2011-04-06 | 杭州电子科技大学 | Resistive superconductive asynchronous bilinear logic AND gate circuit |
-
2017
- 2017-11-13 US US15/811,000 patent/US10158363B1/en active Active
-
2018
- 2018-10-17 EP EP18799635.0A patent/EP3711165B1/en active Active
- 2018-10-17 AU AU2018364957A patent/AU2018364957B2/en active Active
- 2018-10-17 CA CA3077219A patent/CA3077219C/en active Active
- 2018-10-17 WO PCT/US2018/056316 patent/WO2019094162A1/en unknown
- 2018-10-17 KR KR1020207012934A patent/KR102291321B1/en active IP Right Grant
- 2018-10-17 JP JP2020517893A patent/JP6894048B2/en active Active
Patent Citations (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3094685A (en) | 1957-09-30 | 1963-06-18 | Ibm | Non-destructive readout system |
US4956642A (en) | 1987-11-24 | 1990-09-11 | Research Development Corporation Of Japan | Superconducting analog to digital converter |
US5233243A (en) | 1991-08-14 | 1993-08-03 | Westinghouse Electric Corp. | Superconducting push-pull flux quantum logic circuits |
US6310488B1 (en) | 1998-12-02 | 2001-10-30 | Hitachi, Ltd. | Superconductive single flux quantum logic circuit |
US6734699B1 (en) | 1999-07-14 | 2004-05-11 | Northrop Grumman Corporation | Self-clocked complementary logic |
US6608518B2 (en) | 2001-06-15 | 2003-08-19 | Hitachi, Ltd. | Superconducting single flux quantum circuit |
US20030016069A1 (en) | 2001-06-15 | 2003-01-23 | Hitachi, Ltd. | Superconducting single flux quantum circuit |
US20030011398A1 (en) | 2001-06-15 | 2003-01-16 | Herr Quentin P. | Combinational logic using asynchronous single-flux quantum gates |
US6756925B1 (en) | 2003-04-18 | 2004-06-29 | Northrop Grumman Corporation | PSK RSFQ output interface |
US7129869B2 (en) | 2003-08-28 | 2006-10-31 | Hitachi, Ltd. | Superconductor semiconductor integrated circuit |
US7227480B2 (en) | 2005-06-22 | 2007-06-05 | Hitachi, Ltd. | Current steering type single flux quantum circuit |
US7944253B1 (en) | 2005-10-04 | 2011-05-17 | Hypres, Inc. | Digital programmable frequency divider |
US7903456B2 (en) | 2006-02-23 | 2011-03-08 | Hypres, Inc. | Superconducting circuit for high-speed lookup table |
US7977964B2 (en) | 2007-12-13 | 2011-07-12 | Northrop Grumman Systems Corporation | Single flux quantum circuits |
US7724020B2 (en) | 2007-12-13 | 2010-05-25 | Northrop Grumman Systems Corporation | Single flux quantum circuits |
US20090153180A1 (en) | 2007-12-13 | 2009-06-18 | Herr Quentin P | Single flux quantum circuits |
US20110133770A1 (en) | 2008-05-29 | 2011-06-09 | John Xavier Przybysz | Method and apparatus for controlling qubits with single flux quantum logic |
US7969178B2 (en) | 2008-05-29 | 2011-06-28 | Northrop Grumman Systems Corporation | Method and apparatus for controlling qubits with single flux quantum logic |
US8138784B2 (en) | 2008-05-29 | 2012-03-20 | Northrop Grumman Systems Corporation | Method and apparatus for controlling qubits with single flux quantum logic |
US8611974B2 (en) | 2008-06-03 | 2013-12-17 | D-Wave Systems Inc. | Systems, methods and apparatus for superconducting demultiplexer circuits |
US7786748B1 (en) | 2009-05-15 | 2010-08-31 | Northrop Grumman Systems Corporation | Method and apparatus for signal inversion in superconducting logic gates |
US8489163B2 (en) | 2011-08-12 | 2013-07-16 | Northrop Grumman Systems Corporation | Superconducting latch system |
US9455707B2 (en) | 2014-07-08 | 2016-09-27 | Northrop Grumman Systems Corporation | Superconductive gate system |
US20160164505A1 (en) | 2014-12-09 | 2016-06-09 | Northrop Grumman Systems Corporation | Josephson current source systems and method |
US9780765B2 (en) | 2014-12-09 | 2017-10-03 | Northrop Grumman Systems Corporation | Josephson current source systems and method |
US9917580B2 (en) | 2015-02-06 | 2018-03-13 | Northrop Grumman Systems Corporation | Superconducting single-pole double-throw switch system |
US9905900B2 (en) | 2015-05-01 | 2018-02-27 | Northrop Grumman Systems Corporation | Superconductor circuits with active termination |
US9712172B2 (en) | 2015-10-07 | 2017-07-18 | Microsoft Technology Licensing, Llc | Devices with an array of superconducting logic cells |
US9543959B1 (en) | 2015-10-21 | 2017-01-10 | Microsoft Technology Licensing, Llc | Phase-mode based superconducting logic |
US9887700B2 (en) | 2015-10-21 | 2018-02-06 | Microsoft Technology Licensing, Llc | Phase-mode based superconducting logic |
US9595970B1 (en) | 2016-03-24 | 2017-03-14 | Northrop Grumman Systems Corporation | Superconducting cell array logic circuit system |
US9646682B1 (en) | 2016-05-27 | 2017-05-09 | Northrop Grumman Systems Corporation | Reciprocal quantum logic (RQL) sense amplifier |
US20170359072A1 (en) * | 2016-06-08 | 2017-12-14 | Auburn University | Superconducting quantum logic and applications of same |
US9972380B2 (en) | 2016-07-24 | 2018-05-15 | Microsoft Technology Licensing, Llc | Memory cell having a magnetic Josephson junction device with a doped magnetic layer |
US9812192B1 (en) | 2016-09-02 | 2017-11-07 | Northrop Grumman Systems Corporation | Superconducting gate memory circuit |
US9876505B1 (en) | 2016-09-02 | 2018-01-23 | Northrop Grumman Systems Corporation | Superconducting isochronous receiver system |
Non-Patent Citations (2)
Title |
---|
Likharev, K.K. et al.: "RSFQ Logic/Memory Family: A New Josephson-Junction Technology for Sub-Terahertz-Clock-Frequency Digital Systems," IEEE Transactions on Applied Superconductivity, vol. 1 No. 1, Mar. 1991. |
U.S. Office Action corresponding to U.S. Appl. No. 15/886,652, dated May 24, 2018. |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10650319B2 (en) | 2015-02-06 | 2020-05-12 | Northrop Grumman Systems Corporation | Flux control of qubit under resonant excitation |
US11010686B2 (en) | 2015-02-06 | 2021-05-18 | Northrop Grumman Systems Corporation | Flux control of qubit under resonant excitation |
US10756712B2 (en) | 2017-11-13 | 2020-08-25 | Northrop Grumman Systems Corporation | RQL phase-mode flip-flop |
US10389361B1 (en) * | 2018-02-01 | 2019-08-20 | Northrop Grumman Systems Corporation | Four-input josephson gates |
US10554207B1 (en) * | 2018-07-31 | 2020-02-04 | Northrop Grumman Systems Corporation | Superconducting non-destructive readout circuits |
US10615783B2 (en) * | 2018-07-31 | 2020-04-07 | Northrop Grumman Systems Corporation | RQL D flip-flops |
US11159168B2 (en) * | 2018-07-31 | 2021-10-26 | Northrop Grumman Systems Corporation | Superconducting non-destructive readout circuits |
US10769344B1 (en) * | 2019-07-22 | 2020-09-08 | Microsoft Technology Licensing, Llc | Determining timing paths and reconciling topology in a superconducting circuit design |
US11380835B2 (en) | 2019-07-22 | 2022-07-05 | Microsoft Technology Licensing, Llc | Determining critical timing paths in a superconducting circuit design |
US11201608B2 (en) | 2020-04-24 | 2021-12-14 | Northrop Grumman Systems Corporation | Superconducting latch system |
WO2024023577A1 (en) * | 2022-07-27 | 2024-02-01 | Imec Vzw | Sfq-based pulse-conserving logic gates |
US20240039541A1 (en) * | 2022-07-27 | 2024-02-01 | Imec Vzw | SFQ-based Pulse-conserving Logic Gates |
Also Published As
Publication number | Publication date |
---|---|
KR20200066674A (en) | 2020-06-10 |
EP3711165A1 (en) | 2020-09-23 |
AU2018364957B2 (en) | 2021-02-25 |
WO2019094162A1 (en) | 2019-05-16 |
CA3077219C (en) | 2022-11-01 |
CA3077219A1 (en) | 2019-05-16 |
AU2018364957A1 (en) | 2020-04-09 |
EP3711165B1 (en) | 2023-09-13 |
KR102291321B1 (en) | 2021-08-20 |
JP2020535753A (en) | 2020-12-03 |
JP6894048B2 (en) | 2021-06-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10158363B1 (en) | Josephson and/or gate | |
JP7047111B2 (en) | 4-input Josephson gate | |
US10615783B2 (en) | RQL D flip-flops | |
US10084454B1 (en) | RQL majority gates, and gates, and or gates | |
US10171087B1 (en) | Large fan-in RQL gates | |
US10158348B1 (en) | Tri-stable storage loops | |
US10103735B1 (en) | Two-input two-output superconducting gate |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FEPP | Fee payment procedure |
Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |