JP2009181094A - Substrate for electrooptical device, electrooptical device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a substrate for electrooptical device capable of reliably preventing pads from being short-circuited with each other via a guard ring without drastically deteriorating a function as the guard ring even when connecting a wiring substrate and pads with an anisotropic conductive material, to provide an electrooptical device, and to provide an electronic apparatus. <P>SOLUTION: Although when connecting the flexible printed circuit substrate 90 to a pad formation region 12 of a first substrate 10 used for various kinds of electrooptical devices with the anisotropic conductive material, a conductive particle may break through an insulation film 70 to electrically connect to a second conductive layer 8s, the pads 102 are prevented from being short-circuited with each other via the guard ring 5a, even if the second conductive layer 8s of the guard ring 5 is electrically connected with a conductive pattern 91 of the flexible printed circuit substrate 90, since the second conductive layer 8s is divided by position corresponding to the pads 102 in the edge region 1z, and is made to be in an electrically floating state. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an electro-optical device substrate used in an electro-optical device such as a liquid crystal device or an organic electroluminescence (hereinafter referred to as organic EL (Electro-Luminescence) device), an electro-optical device using the electro-optical device substrate, and the electro-optical device. The present invention relates to an electronic device including an optical device.

  Typical examples of the electro-optical device include a liquid crystal device and an organic EL device. The substrate for the electro-optical device used in the electro-optical device is a large substrate until the middle of the manufacturing process, The large substrate is cut out by a scribing process at the final stage. At that time, in order to prevent the mechanical damage of dicing and the influence of static electricity from reaching the pixel area and the drive circuit formed inside the electro-optical device substrate, the large-sized substrate is cut out as the electro-optical device substrate. A guard ring made of a metal material is disposed along the scribe line. The guard ring also exhibits a function of preventing moisture that has entered from the cut surface from entering the inside.

  Here, a plurality of pads are formed along the edge of the substrate on the electro-optical device substrate, and a flexible wiring substrate (FPC (Flexible Printed Circuit) substrate) is connected to the pads. For this reason, as shown in FIGS. 11A and 11B, the guard ring 5 includes a pad forming region 12 in which a plurality of pads 102 are arranged and a substrate edge 1y (cut portion in the scribing process). It is formed so as to pass through the sandwiched edge region 1z. The substrate of the electro-optical device substrate is, for example, a P-type semiconductor substrate 1 such as single crystal silicon, and a P-type well region 1x having an impurity concentration higher than that of the semiconductor substrate 1 is formed on the surface thereof. Yes. Further, on the surface of the semiconductor substrate 1, a thick field oxide film 1i for element isolation and a thin silicon dioxide film 2c are formed. A first interlayer insulating film 71 is formed on the field oxide film 1i and the silicon dioxide film 2c, and first conductive layers 6e and 6s are formed on the first interlayer insulating film 71. A second interlayer insulating film 72 is formed on the first conductive layers 6e and 6s, and second conductive layers 8e and 8s are formed on the second interlayer insulating film 72. An insulating film 70 made of a silicon nitride film 73 and a silicon dioxide film 74 is formed on the second conductive layers 8e and 8s, and an opening 70b is formed in the insulating film 70.

  The second conductive layer 8 e is electrically connected to the first conductive layer 6 e as a wiring through a via hole 72 e formed in the second interlayer insulating film 72, and is exposed from the opening 70 b of the insulating film 70. The part that is present is used as the pad 102. The second conductive layer 8 s is electrically connected to the first conductive layer 6 s through the via hole 72 s formed in the second interlayer insulating film 72, and the first conductive layer 6 s is connected to the first interlayer insulating film 71. And electrically connected to the P-type well region 1x through a via hole 71s formed in the silicon dioxide film 2c. Here, the second conductive layer 8 s and the first conductive layer 6 s extend along the outer peripheral edge of the semiconductor substrate 1 through the edge region 1 z and constitute the guard ring 5 (see Patent Document 1).

  According to the electro-optical device substrate configured as described above, since the guard ring 5 is covered with the thick insulating film 70, the flexible wiring substrate 90 in which the conductive pattern 91 is formed on the resin base material 92 is used as the pad 102. Short circuit when connecting can be prevented.

  However, as shown in FIG. 11C, when the anisotropic conductive material 95 in which the conductive particles 96 are dispersed in the resin matrix 97 is used when the pad 102 and the flexible wiring substrate 90 are connected, the conductive particles 96 breaks through the insulating film 70 and is connected to the guard ring 5, and the pads 102 are short-circuited via the guard ring 5.

On the other hand, when forming the guard ring 5, only the first conductive layer 6s is formed in the edge region 1z without forming the second conductive layer 8s, and the first conductive layer 6s and the first conductive layer 6s are separated from the edge region 1z. A configuration in which the two conductive layers 8s are electrically connected has been proposed (see Patent Document 2).
JP 2000-66241 A JP-A-1-15954

  However, when a structure in which the second conductive layer 8s is not formed at all in the edge region 1z as in the configuration disclosed in Patent Document 2, moisture intrusion from the side surface is prevented over a wide region corresponding to the pad formation region 12. It becomes an impossible structure.

  In view of the above problems, an object of the present invention is to provide a pad via a guard ring without significantly reducing the function as a guard ring even when the wiring board and the pad are connected by an anisotropic conductive material. An object of the present invention is to provide a substrate for an electro-optical device and an electro-optical device that can reliably prevent short-circuiting each other.

  In order to solve the above-described problems, in the present invention, a pixel region in which a plurality of pixels each including a pixel electrode and a pixel transistor are arranged, and a pad formation region in which a plurality of pads are arranged along the substrate edge are formed on a substrate. An electro-optical device substrate having a conductive substrate electrically connected to the pad by an anisotropic conductive material is connected to the substrate. A guard ring is formed extending along an outer peripheral edge on the substrate through an edge region sandwiched between the pad forming region and the substrate edge, and the pad region is formed from the pad to the substrate edge in the edge region. The uppermost conductive layer that constitutes the uppermost layer of the guard ring is left on the virtual extension line that faces, and both sides sandwiching the extension line are cut off portions of the uppermost conductive layer.

  In the present invention, when the guard ring is formed along the outer peripheral edge of the substrate, the guard ring is also formed in the edge region sandwiched between the pad forming region and the substrate edge portion. The uppermost conductive layer that constitutes the uppermost layer of the guard ring is left on the virtual extension line toward the part, but the uppermost conductive layer is interrupted on both sides of the extension line. For this reason, since the uppermost conductive layer of the guard ring is opposed to the pad on a one-to-one basis, when the wiring board and the pad are connected by an anisotropic conductive material, the conductive particles are the uppermost conductive layer of the guard ring. Even when electrically connected to each other, it is possible to avoid a situation in which the conductive patterns of the wiring board and the pads are short-circuited via the guard ring. In the edge region, the uppermost conductive layer of the guard ring is interrupted, but the guard ring is partially formed, so that the function as the guard ring is not significantly deteriorated. For this reason, when the electro-optical device substrate is cut out from the large substrate, the mechanical damage of dicing and the influence of static electricity do not reach the pixel region and the drive circuit formed inside the electro-optical device substrate. Further, the guard ring can prevent moisture that has entered from the cut surface from entering inside.

  In another embodiment of the present invention, a pixel region including a plurality of pixels each including a pixel electrode and a pixel transistor and a pad forming region in which a plurality of pads are arrayed along the substrate edge are provided on the substrate. An electro-optical device substrate on which a wiring substrate having a conductive pattern electrically connected to the pad by an anisotropic conductive material is connected, wherein the pad is formed on the substrate. A guard ring is formed extending along an outer peripheral edge on the substrate through an edge region sandwiched between the region and the substrate edge, and a virtual extension from the pad toward the substrate edge in the edge region The uppermost conductive layer constituting the uppermost layer of the guard ring is left on both sides of the line, and the extended line is cut off at the uppermost conductive layer.

  In the present invention, when the guard ring is formed along the outer peripheral edge of the substrate, the guard ring is also formed in the edge region sandwiched between the pad forming region and the substrate edge portion. The uppermost conductive layer constituting the uppermost layer of the guard ring is left on both sides of the virtual extension line toward the part, but the uppermost conductive layer is interrupted on the extension line. For this reason, since the uppermost conductive layer of the guard ring is opposed to the pad on a one-to-one basis, even if the conductive particles break through the insulating film when the wiring board and the pad are connected with an anisotropic conductive material, the guard is guarded. There is no electrical connection with the uppermost conductive layer of the ring. For this reason, the situation where the conductive patterns of the wiring board and the pads are short-circuited via the guard ring can be avoided. In the edge region, the uppermost conductive layer of the guard ring is interrupted, but the guard ring is partially formed, so that the function as the guard ring is not significantly deteriorated. For this reason, when the electro-optical device substrate is cut out from the large substrate, the mechanical damage of dicing and the influence of static electricity do not reach the pixel region and the drive circuit formed inside the electro-optical device substrate. Further, the guard ring can prevent moisture that has entered from the cut surface from entering inside. Furthermore, as for the uppermost conductive layer left on both sides of the virtual extension line from the pad toward the substrate edge, a structure fixed to a predetermined potential can be adopted as in the guard ring other than the edge region.

  In the present invention, it is possible to adopt a configuration in which the portion divided by the discontinuous portion in the uppermost conductive layer formed in the edge region is in an electrically floating state.

  In the present invention, the guard ring is formed by a plurality of conductive layers stacked with an interlayer insulating film interposed therebetween, and the edge region includes one or more of the plurality of conductive layers including the uppermost conductive layer. It is preferable that the discontinuous portion is formed in the upper conductive layer, and the other conductive layers extend continuously without interruption in the edge region. With this configuration, among the conductive layers constituting the guard ring, the upper conductive layer is interrupted in the edge region, but the lower conductive layer is continuous in the edge region. It is possible to prevent damage and static electricity from reaching the inside and to prevent moisture that has entered from the cut surface from entering the inside.

  In the present invention, it is possible to adopt a configuration in which the uppermost conductive layer is covered with an insulating film in the edge region. In this case, in the insulating film, the layer directly covering the surface of the uppermost conductive layer is preferably a moisture-resistant insulating film. If comprised in this way, the penetration | invasion of the water | moisture content from the surface can be prevented with a moisture-resistant insulating film. Further, since the guard ring has a structure in direct contact with the moisture-resistant insulating film, it is possible to prevent moisture that has entered from the cut surface from entering inside.

  In the present invention, in the edge region, the uppermost conductive layer may have a structure in which the surface is exposed from the insulating film and is in direct contact with the anisotropic conductive material. That is, in the present invention, since the conductive patterns of the wiring board and the pads are prevented from being short-circuited via the guard ring, it is not necessary to cover the surface of the uppermost conductive layer with the insulating film. Therefore, it is not necessary to form an extra insulating film in the pixel region. Therefore, unnecessary reflection or attenuation of light in the pixel region can be prevented, and a high-quality image can be displayed.

  The present invention can be applied to electro-optical devices such as liquid crystal devices, organic EL devices, and digital light processing devices (hereinafter referred to as DLP (Digital Light Processing) devices). In other words, each of these electro-optical devices includes an electro-optic device that includes a pixel region in which a plurality of pixels each including a pixel electrode and a pixel transistor are arranged, and a pad formation region in which a plurality of pads are arranged along the substrate edge. Since it is provided on the device substrate, even when the wiring substrate and the pad are connected by an anisotropic conductive material, the pads are prevented from being short-circuited via the guard ring formed along the outer peripheral edge of the substrate. Can do.

  When these electro-optical devices are configured as a liquid crystal device, for example, the liquid crystal is held between the electro-optical device substrate to which the present invention is applied and the substrate disposed on the electro-optical device substrate. . When the electro-optical device is configured as an organic EL device, the substrate for the electro-optical device to which the present invention is applied has a configuration in which a functional layer for an organic EL element is formed on the pixel electrode.

  An electro-optical device to which the present invention is applied is used as a direct-view display unit or the like in an electronic apparatus such as a mobile phone or a mobile computer. When the electro-optical device to which the present invention is applied is a liquid crystal device, the electro-optical device can also be used as a light valve of a projection display device (electronic apparatus).

  Embodiments of the present invention will be described below. In the drawings to be referred to in the following description, the scales of the layers and the members are different from each other in order to make the layers and the members large enough to be recognized on the drawings. Further, in the following description, as much as possible, the same reference numerals are given to the corresponding portions so that the correspondence with the conventional example described with reference to FIG. 11 can be easily understood. In the field-effect transistor, the source and the drain are switched depending on the applied voltage, but in the following description, for convenience of explanation, the side to which the pixel electrode is connected will be described as the drain.

[Embodiment 1]
(overall structure)
FIG. 1 is a block diagram showing an electrical configuration of an element substrate used in an electro-optical device (liquid crystal device) according to Embodiment 1 of the present invention. FIGS. 2A and 2B are plan views of the electro-optical device according to the first embodiment of the present invention as viewed from the side of the counter substrate together with each component formed thereon, and HH thereof. It is a cross-sectional view.

  As shown in FIG. 1, the electro-optical device 100 of the present embodiment is a liquid crystal device, and a plurality of pixels 100 a are included in a pixel region 10 b of an electro-optical device substrate (first substrate 10) used in the electro-optical device 100. It is formed in a matrix. In each of the plurality of pixels 100a, a pixel electrode 9a and a field effect transistor 30a (pixel transistor) for pixel switching for controlling the pixel electrode 9a are formed. In the first substrate 10, a data line driving circuit 101 and a scanning line driving circuit 104 are formed in the outer region of the pixel region 10b. Here, the data line 6a extending from the data line driving circuit 101 is electrically connected to the source of the field effect transistor 30a, and the data line driving circuit 101 supplies image signals to the data line 6a in a line sequential manner. To do. The scanning line 3a extending from the scanning line driving circuit 104 is electrically connected to the gate of the field effect transistor 30a, and the scanning line driving circuit 104 sequentially supplies scanning signals to the scanning line 3a sequentially and exclusively. The pixel electrode 9a is electrically connected to the drain of the field effect transistor 30a. In the electro-optical device 100, the pixel electrode 9a is supplied from the data line 6a by turning on the field effect transistor 30a for a certain period. The image signal is written into the liquid crystal capacitor 50a of each pixel 100a at a predetermined timing.

  An image signal of a predetermined level written in the liquid crystal capacitor 50a is held for a certain period between a pixel electrode 9a formed on the first substrate 10 and a common electrode on a counter substrate described later. A storage capacitor 60 is formed between the pixel electrode 9a and the common electrode, and the voltage of the pixel electrode 9a is held, for example, for a time that is three orders of magnitude longer than the time when the source voltage is applied. As a result, the charge retention characteristic is improved, and the electro-optical device 100 capable of performing display with a high contrast ratio is realized. In this embodiment, when the storage capacitor 60 is configured, the capacitor line 3b is formed so as to be parallel to the scanning line 3a. However, the storage capacitor 60 may be formed between the previous scanning line 3a. In this embodiment, a liquid crystal device adopting a TN (Twisted Nematic) mode or a VAN (Vertically Aligned Nematic) mode will be described as an example of the electro-optical device 100. However, in the case of an FFS (Fringe Field Switching) mode liquid crystal device, The electrodes are formed on the first substrate 10 like the pixel electrodes 9a.

  The electro-optical device 100 shown in FIGS. 2A and 2B is a reflective active matrix liquid crystal device. In this electro-optical device 100, a sealing material 107 is provided in a rectangular frame shape on a first substrate 10 (electro-optical device substrate) as an element substrate, and the first substrate 10 is opposed to the sealing material 107. It is bonded to the second substrate 20 as a substrate through a predetermined gap. The second substrate 20 and the sealing material 107 have substantially the same contour, and the liquid crystal layer 50 is held in a region surrounded by the sealing material 107. In addition, an inter-substrate conducting portion (not shown) for electrical connection between the first substrate 10 and the second substrate 20 is disposed at a corner portion of the sealing material 107. Although illustration is omitted, a part of the sealing material 107 is cut off, and the cut-off part is used to fill the liquid crystal in the region surrounded by the sealing material 107, and after filling the liquid crystal, the cut-off part. Is closed with a sealing material.

  In the first substrate 10, a data line driving circuit 101 and a plurality of pads 102 are arranged along one side (edge 1 y) of the first substrate 10 in the outer region of the pixel region 10 b, and FIG. ), A flexible wiring board 90 for electrical connection with an external circuit is connected so as to cover the edge 1y from the pad forming region 12. In the first substrate 10, the scanning line driving circuit 104 is formed in the outer region of the pixel region 10 b along two sides adjacent to the edge 1 y where the pads 102 are arranged. Note that peripheral circuits such as a precharge circuit and an inspection circuit may be formed on the first substrate 10. As will be described in detail later, pixel electrodes 9a are formed in a matrix on the first substrate 10, and an alignment film (not shown) is formed on the surface of the pixel electrodes 9a.

  On the second substrate 20, a light shielding film 23 b is formed in a region facing the data line driving circuit 101 and the scanning line driving circuit 104. The light shielding film 23 b is formed on the data line driving circuit 101 and the scanning line driving circuit 104. While preventing light from entering, it functions as a frame. A common electrode 21 made of an ITO (Indium Tin Oxide) film is formed on the second substrate 20, and an alignment film (not shown) is formed on the surface of the pixel electrode 9a. Here, if the light shielding film 23 b is connected to the common electrode 21, the light shielding film 23 b can be held at the same potential as the common electrode 21. On the second substrate 20, a light shielding film (not shown) called a black matrix or black stripe may be formed in a region facing the vertical and horizontal boundary regions of the pixel electrode 9 a of the first substrate 10. The light shielding film is formed from the same light shielding material as the light shielding film 23b. Further, when the electro-optical device 100 is configured as a liquid crystal device for color display, a color halter for each color is formed on the second substrate 20.

  When the electro-optical device 100 having such a configuration is manufactured, the first substrate 10 and the second substrate 20 are in the state of a large substrate until the middle of the manufacturing process, and the bonding process or liquid crystal filling is performed in the state of the large substrate. After performing the process, the large substrate is cut out by a scribing process. At that time, in a large-sized substrate, mechanical dicing damage and static electricity do not reach the pixel region 10b and the driving circuit (the data line driving circuit 101 and the scanning line driving circuit 104) formed inside the first substrate 10. In a region cut out as the first substrate 10, a guard ring 5 made of a metal material is formed along a scribe line. The guard ring 5 also exhibits a function of preventing moisture from entering the inside from the cut surface.

  For this reason, the guard ring extends along the entire outer peripheral edge of the first substrate 10 through the edge region 1z sandwiched between the pad forming region 12 and the edge 1y. The configuration of the guard ring 5 and the pad 102 will be described later with reference to FIG.

  In this embodiment, the semiconductor substrate 1 is used as a base material of the first substrate 10, and a structure in which a reinforcing substrate made of glass or ceramic is bonded to the back surface of the semiconductor substrate 1 to increase the strength is adopted. There is also.

(Detailed pixel configuration)
FIGS. 3A and 3B are respectively a plan view of one adjacent pixel and a cross-sectional view of one pixel of the electro-optical device 100 according to Embodiment 1 of the present invention. 3B is a cross-sectional view taken along the line XX ′ in FIG. 3A. In FIG. 3A, the scanning line 3a and the conductive film formed simultaneously with the scanning line 3a are indicated by thick solid lines, and data The first conductive layer such as the line 6a is indicated by a thick dashed line, the second conductive layer such as the drain electrode is indicated by a two-dot chain line, the field oxide film removal region is indicated by a short dotted line, and the pixel electrode 9a is indicated by a long dotted line. It is.

  In FIG. 3A, on the first substrate 10, a plurality of pixels 100a are arranged in a matrix corresponding to the intersections of the data lines 6a and the scanning lines 3a, and each of the plurality of pixels 100a has light reflectivity. The pixel electrode 9a is formed. On the first substrate 10, a capacitor line 3b is formed in parallel with the scanning line 3a.

  In the first substrate 10 shown in FIG. 3B, a P-type semiconductor substrate 1 such as single crystal silicon is used as the base material, and the surface of the semiconductor substrate 1 has an impurity concentration higher than that of the semiconductor substrate 1. A high P-type well region 1x is formed. The well region 1x can employ a configuration formed in each of the plurality of pixels 100a. In this embodiment, the well region 1x is formed as a common well region for all the pixels 100a. However, the well region 1x in the pixel region 10b and the well region in which the data line driving circuit 101, the scanning line driving circuit 104, and the like are formed may be separated as necessary.

  A field oxide film 1g made of a LOCOS (Local Oxidation of Silicon) film having a thickness of 500 to 700 nm is formed on the surface of the semiconductor substrate 1 by selective thermal oxidation. Two openings 1t and 1u are formed. A gate insulating film 2a is formed in one opening 1t, and a scanning line 3a made of polysilicon or metal silicide passes as a gate electrode on the gate insulating film 2a. The gate insulating film 2a is a silicon dioxide film formed by thermal oxidation and has a thickness of 40 to 80 nm. The scanning line 3a is formed to a thickness of 100 to 200 nm when formed of a polysilicon film, and is formed to a thickness of 100 to 300 nm when formed of a refractory metal silicide film. On the surface of the semiconductor substrate 1, a source region 1f and a drain region 1e made of an N-type doped region having an impurity concentration higher than that of the well region 1x are formed on both sides of the scanning line 3a. With reference to FIG. The field effect transistor 30a described above is configured. The source region 1f and the drain region 1e are formed in a self-aligned manner by ion implantation of N-type impurities using the scanning line 3a as a mask.

  A P-type doped region 1h is formed on the substrate surface of the other opening 1u formed in the field oxide film 1g. The surface of the P-type doped region 1h is simultaneously formed with the gate insulating film 2a by thermal oxidation. A dielectric film 2b made of the formed silicon dioxide film is formed. A capacitor line 3b made of polysilicon, metal silicide, or the like passes through the dielectric film 2b. The capacitor line 3b is formed simultaneously with the scanning line 3a. In this way, the storage capacitor 60 is constituted by the capacitor line 3b, the dielectric film 2b, and the P-type doped region 1h.

  A first interlayer insulating film 71 is formed on the scanning line 3a, the capacitor line 3b, and the field oxide film 1g. On the first interlayer insulating film 71, a data line 6a made of a metal film mainly composed of aluminum and A drain electrode 6b is formed as the first conductive layer. Data line 6a and drain electrode 6b are electrically connected to source region 1f and drain region 1e via via holes 71a and 71b formed in first interlayer insulating film 71 and gate insulating film 2a. The drain electrode 6b is also electrically connected to the P-type doped region 1h constituting the storage capacitor 60 through the via hole 71c formed in the first interlayer insulating film 71 and the gate insulating film 2a. The via holes 71a, 71b, 71c are simultaneously formed by the same process. The data line 6a and the drain electrode 6b are made of a conductive film formed simultaneously. For example, a Ti film (lower layer) having a thickness of 10 to 60 nm, a TiN film (intermediate layer) having a thickness of about 100 nm, and a thickness of 30 are formed. It is composed of a laminated film composed of a Ti film (upper layer) of ˜60 nm.

  A second interlayer insulating film 72 is formed on the data line 6a and the drain electrode 6b. For the second interlayer insulating film 72, for example, an insulating film such as a silicon dioxide film made of LTO (Low Temperature Oxide) is formed, and then a planarizing film made of SOG (Spin On Glass) is applied, and after a flattening process such as etch back. It is configured by forming an insulating film such as LTO again.

  On the second interlayer insulating film 72, a light shielding film 8a made of a layer such as aluminum and a relay electrode 8b are formed as a second conductive layer. The relay electrode 8b is formed on the second interlayer insulating film 72. The drain electrode 6b is electrically connected through the via hole 72a. The light shielding film 8a prevents light incident from the second substrate 20 side from entering the field effect transistor 30a. The relay electrode 8b is formed in an island shape in a region overlapping the drain electrode 6b, while the light shielding film 8a is formed so as to surround the relay electrode 8b with a gap 8n between the relay electrode 8b and the relay electrode 8b. Yes.

  Above the light shielding film 8a and the relay electrode 8b, a silicon nitride film 73 as a moisture-resistant insulating film is formed with a thickness of 100 to 500 nm, and a silicon dioxide film 74 made of LTO is formed thereon. The insulating film 70 composed of the silicon nitride film 73 and the silicon dioxide film 74 functions as a third interlayer insulating film. The silicon nitride film 73 and the silicon dioxide film 74 are each formed by a low pressure CVD method or the like. The thickness of the insulating film 70 is 800 to 1200 nm, and the surface of the insulating film 70 is planarized by a CMP (Chemical Mechanical Polishing) method or the like. As the moisture resistant insulating film, a silicon oxynitride film can be used instead of the silicon nitride film 73.

  A light-reflective pixel electrode 9a made of an aluminum film or the like is formed on the insulating film 70. In the insulating film 70, a via hole 70a is formed at an overlapping portion of the pixel electrode 9a and the relay electrode 8b. Yes. A conductive film formed by a CVD method or the like is embedded as a connection plug 4a inside the via hole 70a, and the pixel electrode 9a is electrically connected to the relay electrode 8b via the connection plug 4a. In this way, the pixel electrode 9a is electrically connected to the drain region 1e of the field effect transistor 30a via the connection plug 4a, the relay electrode 8b, and the drain electrode 6b.

(Configuration of guard ring and pad)
4A and 4B are a plan view schematically showing the vicinity of the pad formation region of the first substrate used in the electro-optical device 100 according to Embodiment 1 of the present invention, and regions other than the edge region, respectively. FIG. 4B is a cross-sectional view schematically showing a state in which the first substrate is cut so as to cross the guard ring, and FIG. 4B corresponds to the C1-C1 ′ cross-sectional view of FIG. FIGS. 5A, 5B, and 5C each cut the first substrate along a line passing through the pad toward the edge of the substrate in the electro-optical device 100 according to the first embodiment of the present invention. A cross-sectional view schematically showing the state of the substrate, a cross-sectional view schematically illustrating a state in which the first substrate is cut along a line that passes between the pads and toward the edge of the substrate, and a flexible wiring board is provided on the first substrate 10. FIGS. 5A and 5B are explanatory views when connected by an anisotropic conductive material, respectively, and are A1-A1 ′ cross-sectional views of FIG. 4A and B1-B1 of FIG. 4A. 'Corresponds to a cross-sectional view. 5C corresponds to the A1-A1 ′ cross-sectional view of FIG.

  As shown in FIG. 4A, in the first substrate 10, a pad formation region 12 in which a plurality of pads 102 are arranged is formed along the edge 1y (cut portion in the scribe process). 5 extends along the outer peripheral edge of the first substrate 10 so as to pass through the edge region 1z sandwiched between the pad forming region 12 and the edge 1y.

  In configuring the pad 102 and the guard ring 5, in this embodiment, as shown in FIG. 4B and FIGS. 5A and 5B, a P-type well is formed on the surface of the semiconductor substrate 1. A region 1x is formed, and on the semiconductor substrate 1, a thick field oxide film 1i for element isolation and a thin silicon dioxide film 2c are formed. The silicon dioxide film 2c is a thermal oxide film formed simultaneously with the gate insulating film 2a and the dielectric film 2b described with reference to FIG.

  A first interlayer insulating film 71 is formed on the field oxide film 1 i and the silicon dioxide film 2 c, and first conductive layers 6 e and 6 s are formed on the first interlayer insulating film 71. The first conductive layers 6e and 6s are conductive films formed simultaneously with the data lines 6a and the drain electrodes 6b described with reference to FIG. 3B. Of the first conductive layers 6e and 6s, the first conductive layers 6e and 6s are the first conductive layers 6e and 6s. The layer 6e constitutes a wiring.

  A second interlayer insulating film 72 is formed on the first conductive layers 6e and 6s, and second conductive layers 8e and 8s are formed on the second interlayer insulating film 72. The second conductive layers 8e and 8s are conductive films formed simultaneously with the relay electrode 8a and the light shielding film 8b shown in FIG.

  On the second conductive layers 8e and 8s, an insulating film 70 made of a silicon nitride film 73 and a silicon dioxide film 74 as a moisture-resistant insulating film is formed, and an opening 70b is formed in the insulating film 70. ing. The opening 70b is a hole formed simultaneously with the via hole 70a shown in FIG.

  The second conductive layer 8 e is electrically connected to the first conductive layer 6 e as a wiring through a via hole 72 e formed in the second interlayer insulating film 72, and is exposed from the opening 70 b of the insulating film 70. The part that is present is used as the pad 102.

  The second conductive layer 8s is electrically connected to the first conductive layer 6s through a via hole 72s formed in the second interlayer insulating film 72. The first conductive layer 6s includes the first interlayer insulating film 71 and The P-type well region 1x is electrically connected through a via hole 71s formed in the silicon dioxide film 2c. The via holes 72e and 72s are formed simultaneously with the via hole 72a shown in FIG. 3B, and the via hole 71s is a contact hole formed simultaneously with the via holes 71a, 71b and 71c shown in FIG.

  Here, the first conductive layer 6 s extends continuously in the edge region 1 z and extends along the outer peripheral edge of the semiconductor substrate 1. The via hole 71s is formed along the first conductive layer 6s. For this reason, the via hole 71 s also extends continuously in the edge region 1 z and extends along the outer peripheral edge of the semiconductor substrate 1, similarly to the first conductive layer 6 s. The second conductive layer 8s extends along the outer peripheral edge of the semiconductor substrate 1 through the edge region 1z, and the via hole 72s also extends along the outer peripheral edge of the semiconductor substrate 1 along the second conductive layer 8s. It is extended. Thus, in this embodiment, the guard ring 5 extending along the outer peripheral edge of the first substrate 10 is formed by the first conductive layer 6s and the second conductive layer 8s. For this reason, when the first substrate 10 is cut out from the large substrate by the scribing process, mechanical damage and static electricity of dicing are stopped by the guard ring 5, and the pixel region 10 b and the driving circuit ( It does not reach the data line driving circuit 101 and the scanning line driving circuit 104). Moreover, the water | moisture content which penetrate | invaded from the cutting | disconnection part is stopped with the guard ring 5, and does not penetrate | invade inside. Therefore, due to the invading water, the field effect transistor 30a formed in the pixel region 10b is deteriorated, the pixel electrode 9a is deteriorated, the drive circuit (the data line drive circuit 101 and the scan drive circuit 104) is deteriorated, and the liquid crystal layer 50 is deteriorated. Etc., and delamination does not occur.

  In constructing such a guard ring 5, in this embodiment, as shown in FIGS. 4A and 5A, the first conductive layer 6s and the via hole 71s extend continuously in the edge region 1z. is doing. In contrast, the second conductive layer 8s is formed on a virtual extension line (A1-A1 ′ line in FIG. 4A) from the pad 102 toward the edge 1y of the first substrate 10 in the edge region 1z. However, on both sides of the extension line, as shown in FIG. 5B, the second conductive layer 8s is not formed. Therefore, both sides of a virtual extension line from the pad 102 toward the edge 1y of the first substrate 10 in the edge region 1z are discontinuous portions 8t of the second conductive layer 8s. Further, as shown in FIG. 5A, in the edge region 1z, via holes 72s (see FIG. 4D) are formed in the second interlayer insulating film 72 on a virtual extension line from the pad 102 toward the edge 1y of the first substrate 10. b)) is not formed. Therefore, only the first conductive layer 6s and the via hole 71s are formed at the position corresponding to the discontinuous portion 8t of the second conductive layer 8s, and the portion divided for each pad 102 in the second conductive layer 8s is electrically It is in a floating state.

(Main effects of this form)
When the first substrate 10 of this embodiment is used in the electro-optical device 100, the pad forming region 12 has a film-like anisotropic conductive film (Anisotropic Conductive Film) or paste as shown in FIG. The flexible wiring board 90 is connected by an anisotropic conductive material 95 made of an anisotropic conductive agent. On the flexible wiring substrate 90, a conductive pattern 91 electrically connected to the pad 102 is formed on the resin base material 92 so as to overlap with an extension line of the pad 102. In the anisotropic conductive material 95, conductive particles 96 are dispersed in the resin matrix 97. Accordingly, when the first substrate 10 is crimped while heating the flexible wiring substrate 90 with the anisotropic conductive material 95 sandwiched between the first substrate 10 and the flexible wiring substrate 90, the first substrate 10 and the flexible wiring The substrate 90 is fixed by a resin matrix 97 of an anisotropic conductive material 95, and the pad 102 and the conductive pattern 91 are electrically connected.

  Here, the flexible wiring substrate 90 is disposed so as to extend from the pad forming region 12 toward the edge 1y of the first substrate 10, and the first substrate 10 and the flexible wiring substrate 90 are anisotropic in the edge region 1z. It is fixed with a conductive material 95. At this time, the conductive particles 96 may break through the insulating film 70 and be electrically connected to the second conductive layer 8s. In this embodiment, the second conductive layer 8s is located at a position corresponding to the pad 102 in the edge region 1z. Since the via hole 72s is not formed in the second interlayer insulating film 72 on the lower side of the divided second conductive layer 8s, the divided second conductive layer 8s is in an electrically floating state. It is in. Therefore, even if the second conductive layer 8s of the guard ring 5 and the conductive pattern 91 of the flexible wiring board 90 are electrically connected, the pads 102 are short-circuited via the guard ring 5 or the well region 1x. Don't be.

  Further, on the lower layer side of the second conductive layer 8s, the first conductive layer 6s extends continuously in the edge region 1z. However, in the edge region 1z, the second interlayer insulating film is located above the first conductive layer 6s. 72 and the insulating film 70, the second conductive layer 8s is formed. Therefore, even if the conductive particles 96 may break through the insulating film 70, the second conductive layer 8s and the second interlayer insulating film 72 are broken through. Thus, it is not electrically connected to the first conductive layer 6s.

  Therefore, according to the present embodiment, even when the flexible wiring board 90 and the pad 102 are connected by the anisotropic conductive material 95, the pad 102 is interposed via the guard ring 5 formed along the outer peripheral edge of the first substrate 10. It is possible to reliably prevent short-circuiting each other.

  Further, since the first conductive layer 6 s and the second conductive layer 8 s are formed in the edge region 1 z, the surface thereof is higher than the pad 102. For this reason, since the flexible wiring board 90 is firmly connected even in the edge region 1z, a problem such as peeling of the flexible wiring board 90 does not occur.

  Further, in this embodiment, the silicon nitride film 74 is directly laminated on the second conductive layer 8s in the edge region 1z. For this reason, moisture hardly enters from the surface side, and moisture hardly enters from the side surface at the edge 1y of the scribed first substrate 10. Moreover, in the edge region 1z, although the second conductive layer 8s is interrupted, it is partially formed and the first conductive layer 6s is formed continuously, so that the function as the guard ring 5 is greatly increased. It has not declined. Therefore, according to the present embodiment, it is possible to prevent moisture from entering from the surface side of the first substrate 10 and moisture from entering from the side surface (cut surface).

[Modification of Embodiment 1]
In the first embodiment, the second conductive layer 8s is divided in the edge region 1z, while the first conductive layer 6s is continuously extended. In the edge region 1z, the via hole 72s is formed in the second interlayer insulating film 72. Although a configuration in which the via hole 71s is not formed in the first interlayer insulating film 71 may be employed in the edge region 1z.

  In the first embodiment, the second conductive layer 8s is divided in the edge region 1z and the first conductive layer 6s is continuously extended. However, the second conductive layer 8s and the first conductive layer are extended in the edge region 1z. Both 6s may be divided. In such a case, if a configuration is adopted in which the via hole 71s is formed in the first interlayer insulating film 71 in the edge region 1z while the via hole 72s is not formed in the second interlayer insulating film 72 in the edge region 1z. The divided second conductive layer 8s can be brought into an electrically floating state. In the edge region 1z, a via hole 72s is formed in the second interlayer insulating film 72. On the other hand, if the edge region 1z does not form the via hole 71s in the first interlayer insulating film 71, the divided first region is formed. The two conductive layers 8s and the first conductive layer 6s can be in an electrically floating state. In the edge region 1z, the divided second conductive layer 8s can be obtained even when the configuration in which neither the formation of the via hole 71s to the first interlayer insulating film 71 nor the formation of the via hole 72s to the second interlayer insulating film 72 is employed. In addition, the first conductive layer 6s can be in an electrically floating state.

[Embodiment 2]
(Pad and guard ring configuration)
6A and 6B are a plan view schematically showing the vicinity of the pad formation region of the first substrate used in the electro-optical device 100 according to Embodiment 2 of the present invention, and regions other than the edge region, respectively. FIG. 6B is a cross-sectional view schematically showing a state in which the first substrate is cut so as to cross the guard ring, and FIG. 6B corresponds to the C2-C2 ′ cross-sectional view of FIG. FIGS. 7A, 7B, and 7C each show a cut of the first substrate along a line passing through the pad toward the edge of the substrate in the electro-optical device 100 according to the second embodiment of the present invention. A cross-sectional view schematically showing the state of the substrate, a cross-sectional view schematically illustrating a state in which the first substrate is cut along a line that passes between the pads and toward the edge of the substrate, and a flexible wiring board is different from the first substrate. FIGS. 7A and 7B are explanatory views when they are connected by an isotropic conductive material, respectively. FIGS. 7A and 7B are cross-sectional views taken along the line A2-A2 ′ of FIG. 6A and B2-B2 ′ of FIG. It corresponds to a sectional view. FIG. 7C corresponds to the A2-A2 ′ sectional view of FIG. Since the basic configuration of this embodiment is the same as that of Embodiment 1, common portions are denoted by the same reference numerals and description thereof is omitted.

  As shown in FIG. 6A, in this embodiment as well, in the first substrate 10, a plurality of pads 102 are arranged along the edge portion 1y (cut portion in the scribe process) as in the first embodiment. The pad forming region 12 is formed, and the guard ring 5 extends along the outer peripheral edge of the first substrate 10 so as to pass through the edge region 1z sandwiched between the pad forming region 12 and the edge 1y. In the configuration of the pad 102 and the guard ring 5, as in the first embodiment, as shown in FIGS. 6B, 7A, and 7B, the first interlayer insulating film 71 is also formed in this embodiment. First conductive layers 6e and 6s are formed thereon, and second conductive layers 8e and 8s are formed on the second interlayer insulating film 72. An insulating film 70 made of a silicon nitride film 73 and a silicon dioxide film 74 as a moisture-resistant insulating film is formed on the second conductive layers 8e and 8s. In the second conductive layer 8e, an insulating film is formed. A portion exposed from the opening 70 b of the 70 is used as the pad 102. The second conductive layer 8s is electrically connected to the first conductive layer 6s through a via hole 72s formed in the second interlayer insulating film 72. The first conductive layer 6s includes the first interlayer insulating film 71 and The P-type well region 1x is electrically connected through a via hole 71s formed in the silicon dioxide film 2c.

  Here, the first conductive layer 6 s extends continuously in the edge region 1 z and extends along the outer peripheral edge of the semiconductor substrate 1. Similarly to the first conductive layer 6 s, the via hole 71 s extends continuously in the edge region 1 z and extends along the outer peripheral edge of the semiconductor substrate 1. The second conductive layer 8s extends along the outer peripheral edge of the semiconductor substrate 1 through the edge region 1z, and the via hole 72s also extends along the outer peripheral edge of the semiconductor substrate 1 along the second conductive layer 8s. It is extended. Thus, in this embodiment, the guard ring 5 extending along the outer peripheral edge of the first substrate 10 is formed by the first conductive layer 6s and the second conductive layer 8s.

  In the guard ring 5 configured as described above, in this embodiment, the first conductive layer 6s and the via hole 71s extend continuously in the edge region 1z. On the other hand, the second conductive layer 8s is disposed on both sides of a virtual extension line (A2-A2 ′ line in FIG. 6A) from the pad 102 toward the edge 1y of the first substrate 10 in the edge region 1z. Although formed, it is not formed on a virtual extension line from the pad 102 toward the edge 1 y of the first substrate 10. For this reason, a virtual extension line from the pad 102 toward the edge 1y of the first substrate 10 in the edge region 1z is a discontinuous portion 8t of the second conductive layer 8s. Therefore, only the first conductive layer 6s and the via hole 71s are formed at a position corresponding to the discontinuous portion 8t of the second conductive layer 8s. Note that via holes 72 s are formed in the second interlayer insulating film 72 on both sides of a virtual extension line from the pad 102 toward the edge 1 y of the first substrate 10, and are formed in a state of being divided into such regions. The second conductive layer 8s is electrically connected to the well 1x via the via hole 72s, the first conductive layer 6s, and the via hole 71s. Therefore, the second conductive layer 8s is fixed at a constant potential also in the edge region 1z.

(Main effects of this form)
Also in this embodiment, when the first substrate 10 is used for the electro-optical device 100, the flexible wiring is formed in the pad forming region 12 by the anisotropic conductive material 95 as shown in FIG. The substrate 90 is connected. At this time, the conductive particles 96 may break through the insulating film 70, but the second conductive layer 8 s is divided at each position corresponding to the pad 102 in the edge region 1 z and overlaps the conductive pattern 91 of the flexible wiring board 90. Is a discontinuous portion 8t of the second conductive layer 8s. Therefore, even if the conductive particles 96 break through the insulating film 70, the same effects as in the first embodiment are obtained, such as the pads 102 are not short-circuited via the guard ring 5 or the well region 1x.

  In the edge region 1z, although the second conductive layer 8s is interrupted, the second conductive layer 8s is partially formed and connected to the first conductive layer 6s via the via hole 72s. Does not drop significantly.

[Modification of Embodiment 2]
In the second embodiment, the second conductive layer 8s is divided at the edge region 1z, while the first conductive layer 6s is continuously extended to form the via hole 72s in the second interlayer insulating film 72, and the first interlayer Although both the formation of the via hole 71 s with respect to the insulating film 71 is performed, a configuration in which the formation of the via hole 72 s with respect to the second interlayer insulating film 72 and / or the formation of the via hole 71 s with respect to the first interlayer insulating film 71 is not employed. Good.

  In the first embodiment, the second conductive layer 8s is divided in the edge region 1z and the first conductive layer 6s is continuously extended. However, the second conductive layer 8s and the first conductive layer are extended in the edge region 1z. Both 6s may be divided. In such a case, both the formation of the via hole 72 s for the second interlayer insulating film 72 and the formation of the via hole 71 s for the first interlayer insulating film 71 may be performed. The formation of the via hole 72 s for the second interlayer insulating film 72 may be performed. Alternatively, a configuration in which the via hole 71 s is not formed in the first interlayer insulating film 71 may be employed.

[Embodiment 3]
FIGS. 8A, 8B and 8C are plan views schematically showing the vicinity of the pad formation region of the first substrate used in the electro-optical device 100 according to Embodiment 3 of the present invention. Sectional drawing which shows a mode that the 1st board | substrate was cut | disconnected along the line which goes to the edge part of a board | substrate through, and a mode which cut | disconnected the 1st board | substrate along the line which goes to the edge part of a board | substrate through between pads 8 (b) and 8 (c) respectively correspond to the A3-A3 'sectional view of FIG. 8 (a) and the B3-B3' sectional view of FIG. 8 (a). To do. Since the basic configuration of this embodiment is the same as that of Embodiment 1, common portions are denoted by the same reference numerals and description thereof is omitted.

  As shown in FIGS. 8A, 8 </ b> B, and 8 </ b> C, in this embodiment as well, as in the first embodiment, along the edge 1 y of the first substrate 10 (the cut portion in the scribe process). A pad forming region 12 in which a plurality of pads 102 are arranged is formed, and the guard ring 5 is formed on the outer peripheral edge of the first substrate 10 so as to pass through the edge region 1z sandwiched between the pad forming region 12 and the edge 1y. Extending along. In forming such a guard ring 5, the first conductive layer 6s extends continuously in the edge region 1z, while the second conductive layer 8s extends from the pad 102 in the edge region 1z. 8 is left on a virtual extension line (A3-A3 ′ line in FIG. 8A) toward the edge 1y of the substrate 10, but the second conductive layer 8s is interrupted on both sides of the extension line. A portion 8t is formed. In the edge region 1 z, no via hole is formed in the second interlayer insulating film 72 on a virtual extension line from the pad 102 toward the edge 1 y of the first substrate 10.

  In the first substrate 10 configured as described above, the insulating film 70 is formed so as to cover the second conductive layer 8s in the first embodiment, but in this embodiment, an insulating film is formed on the second conductive layer 8s. Not formed. In the pixel region 10b described with reference to FIG. 3B, only the silicon dioxide film 74 is formed. Other configurations are the same as those of the first embodiment.

  In such a configuration, when the first substrate 10 and the flexible wiring substrate 90 are connected by the anisotropic conductive material 95, the second conductive layer 8s and the flexible wiring substrate 90 are connected to each other through the conductive particles 96 in the edge region 1z. In this embodiment, the second conductive layer 8s is divided at each position corresponding to the pad 102 in the edge region 1z, and the divided second conductive layer is connected to the conductive pattern 91. On the lower layer side of 8s, the via hole 72s (see FIG. 4B) is not formed in the second interlayer insulating film 72. For this reason, the divided second conductive layer 8s is in an electrically floating state. Therefore, even if the second conductive layer 8s of the guard ring 5 and the conductive pattern 91 of the flexible wiring board 90 are electrically connected, the pads 102 are short-circuited via the guard ring 5 or the well region 1x. Don't be.

  In addition, no insulating film is formed on the second conductive layer 8s, and no silicon nitride film is formed in the pixel region 10b. For this reason, since the light transmittance in the pixel region 10b can be improved, a bright image can be displayed. That is, since the refractive index of the silicon nitride film is larger than the refractive index of the liquid crystal, when the silicon nitride film is formed in the pixel region 10b, the reflectance in the visible light region changes greatly due to the variation in the film thickness. However, in this embodiment, since it is not necessary to form a silicon nitride film on the second conductive layer 8s, it is not necessary to form a silicon nitride film in the pixel region 10b. Can be displayed. Such a configuration can also be applied to the second embodiment.

[Embodiment 4]
As described in the first to third embodiments, the present invention can be applied not only to a liquid crystal device but also to an organic EL device and a digital light processing device (hereinafter referred to as a DLP (Digital Light Processing) device). An example in which the present invention is applied to an organic EL device will be briefly described. In the following description, the same reference numerals are given to the corresponding parts as much as possible so that the correspondence with the first to third embodiments can be easily understood.

  FIG. 9 is a block diagram showing an electrical configuration of an electro-optical device (organic EL device) according to Embodiment 4 of the present invention. The electro-optical device 100 shown in FIG. 9 is a top emission type organic EL device, and on the first substrate 10, a plurality of scanning lines 3a and a plurality of data lines extending in a direction intersecting the scanning lines 3a. 6a and a plurality of power supply lines 3e extending in parallel to the scanning line 3a. In the first substrate 10, a plurality of pixels 100a are arranged in a matrix in a rectangular pixel region 10b. A data line driving circuit 101 and a scanning line driving circuit 104 are formed in the outer area of the pixel area 10b. The data line 6 a is connected to the data line driving circuit 101, and the scanning line 3 a is connected to the scanning line driving circuit 104. Each of the pixel regions 10b is supplied from a switching field effect transistor 30b to which a scanning signal is supplied to the gate electrode through the scanning line 3a, and from the data line 6a through the switching field effect transistor 30b. A storage capacitor 60 for holding the pixel signal to be driven, a field effect transistor 30c for driving to which the pixel signal held by the storage capacitor 60 is supplied to the gate electrode, and the power line 3e via the field effect transistor 30c. A pixel electrode 9a (anode layer) into which a drive current flows from the power supply line 3e when electrically connected to the organic EL element 80 and an organic EL element 80 in which an organic functional layer is sandwiched between the pixel electrode 9a and the cathode layer 85 are configured. is doing.

  According to this configuration, when the scanning line 3a is driven and the switching field effect transistor 30b is turned on, the potential of the data line 6a at that time is held in the storage capacitor 60, and the charge held in the storage capacitor 60 is Accordingly, the on / off state of the driving field effect transistor 30c is determined. Then, a current flows from the power supply line 3e to the pixel electrode 9a through the channel of the driving field effect transistor 30c, and further a current flows to the counter electrode layer through the organic functional layer. As a result, the organic EL element 80 emits light according to the amount of current flowing therethrough.

  In the configuration shown in FIG. 9, the power supply line 3e is parallel to the scanning line 3a, but a configuration in which the power supply line 3e is parallel to the data line 6a may be adopted. In the configuration shown in FIG. 9, the storage capacitor 60 is configured using the power supply line 3e. However, a capacitor line may be formed separately from the power supply line 3e, and the storage capacitor 60 may be configured by the capacitor line. Good.

  Even when the electro-optical device 100 having such a configuration is manufactured, the first substrate 10 is in a state of a large substrate until the middle of the manufacturing process, and is cut out from the large substrate by a scribing process. At this time, in order to prevent mechanical damage and static electricity from dicing from reaching the pixel region 10b and the driving circuit (the data line driving circuit 101 and the scanning line driving circuit 104) formed inside the first substrate 10, the first substrate 10 In a region cut out as one substrate 10, a guard ring 5 made of a metal material is disposed along a scribe line. Further, the guard ring 5 is formed for the purpose of preventing moisture from entering from the cut surface. For this reason, the guard ring 5 is formed so as to extend along the outer peripheral edge of the first substrate 10 through the edge region 1z sandwiched between the pad forming region 12 and the edge 1y.

  Also when such a guard ring 5 is configured, as in the first and third embodiments, the uppermost layer of the guard ring 5 is located on a virtual extension line from the pad 102 toward the edge 1y of the first substrate 10 in the edge region 1z. However, the conductive film is cut off on both sides of the extension line. Alternatively, as in the second embodiment, the conductive film constituting the uppermost layer of the guard ring 5 is left on both sides of a virtual extension line from the pad 102 toward the edge 1y of the first substrate 10 in the edge region 1z. A configuration is adopted in which the conductive film constituting the uppermost layer of the guard ring 5 is interrupted on the line. Therefore, even when the flexible wiring board and the pad 102 are connected by an anisotropic conductive material, the pads 102 are reliably short-circuited via the guard ring 5 formed along the outer peripheral edge of the first substrate 10. Can be prevented.

[Other embodiments]
In the above embodiment, the guard ring 5 is formed of two conductive layers. However, the guard ring may be formed of a plurality of conductive layers stacked with an interlayer insulating film interposed therebetween. In this case, in the edge region 1z, a discontinuous portion is formed in one or more upper conductive layers including the uppermost conductive layer (uppermost conductive layer) among the plurality of conductive layers, and the other conductive layers are What is necessary is just to employ | adopt the structure extended continuously without interrupting in the area | region 1z.

[Example of mounting on electronic equipment]
Among the electro-optical devices 100 according to the present invention, the reflective liquid crystal devices according to the first to third embodiments are the projection type display device (liquid crystal projector / electronic device) shown in FIG. ) And (c) can be used for portable electronic devices, and the organic EL device according to Embodiment 4 is used for the portable electronic devices shown in FIGS. 10 (b) and 10 (c). it can.

  A projection display device 1000 shown in FIG. 10A includes a polarized light illumination device 800 including a light source unit 810, an integrator lens 820, and a polarization conversion element 830 arranged along the system optical axis L, and the polarized light illumination device 800. The polarization beam splitter 840 that reflects the emitted S-polarized light beam by the S-polarized light beam reflection surface 841 and the blue light (B) component of the light reflected from the S-polarized light beam reflection surface 841 of the polarization beam splitter 840 are separated. And a dichroic mirror 843 that reflects and separates the red light (R) component of the luminous flux after the blue light is separated. In addition, the projection display apparatus 1000 includes three electro-optical devices 100 (reflection type liquid crystal devices 100R, 100G, and 100B) on which each color light is incident. Further, the projection display apparatus 1000 combines the light modulated by the three reflective liquid crystal devices 100R, 100G, and 100B by the dichroic mirrors 842 and 843 and the polarization beam splitter 840, and then combines the combined light with the screen 860. Project to.

  A cellular phone 3000 shown in FIG. 10B includes a plurality of operation buttons 3001, scroll buttons 3002, and the electro-optical device 100 as a display unit. By operating the scroll button 3002, the screen displayed on the electro-optical device 100 is scrolled. A personal digital assistant (PDA) 4000 shown in FIG. 10C includes a plurality of operation buttons 4001, a power switch 4002, and the electro-optical device 100 as a display unit, and when the power switch 4002 is operated. Various kinds of information such as an address book and a schedule book are displayed on the electro-optical device 100.

  Furthermore, if a color hole is formed on the second substrate 20 or the like, the electro-optical device 100 capable of color display can be formed. Further, if the electro-optical device 100 in which the color halter is formed, a single-plate projection display device can be configured.

[Other configurations]
In the first to fourth embodiments, a semiconductor substrate is used as the base material of the first substrate 10 (electro-optical device substrate). As the base material, an electro-optical device using a glass substrate, a metal substrate, or a ceramic substrate. The present invention may be applied to 100. In the first to fourth embodiments, since the semiconductor substrate is used as the base material of the first substrate 10, the electro-optical device 100 is configured as a reflective liquid crystal device or a top emission type organic EL device. If a translucent substrate such as a quartz substrate or a glass substrate is used as the base material 10, the electro-optical device 100 can be configured as a transmissive or transflective liquid crystal device or a bottom emission organic EL device. In forming the guard ring 5 on the first substrate 10 (electro-optical device substrate) in the optical device, the present invention may be applied. Even in such a configuration, the electro-optical device 100 can be used as a light valve of a direct-view display device or a transmission projection device in various electronic devices.

1 is a block diagram showing an electrical configuration of an element substrate used in an electro-optical device (liquid crystal device) according to Embodiment 1 of the invention. (A), (b) is the top view which looked at the electro-optical apparatus based on Embodiment 1 of this invention from the opposing board | substrate side with each component formed on it, respectively, and its HH 'cross section FIG. FIGS. 4A and 4B are a plan view and a cross-sectional view of one pixel adjacent to each other of the electro-optical device according to the first embodiment of the present invention. (A), (b) is the top view which shows typically the pad formation area vicinity of the 1st board | substrate used for the electro-optical apparatus based on Embodiment 1 of this invention, respectively, and guard rings in area | regions other than an edge area | region. It is sectional drawing which shows typically a mode that the 1st board | substrate was cut | disconnected so that may be crossed. (A), (b), and (c) each show a state in which the first substrate is cut along a line passing through the pad toward the edge of the substrate in the electro-optical device according to the first embodiment of the present invention. Schematic cross-sectional view, cross-sectional view schematically showing a state in which the first substrate is cut along a line that passes between the pads and toward the edge of the substrate, and the flexible wiring substrate is anisotropically conductive on the first substrate It is explanatory drawing when it connects with a material. (A), (b) is a plan view schematically showing the vicinity of the pad formation region of the first substrate used in the electro-optical device according to the second embodiment of the present invention, and guard rings in regions other than the edge region. It is sectional drawing which shows typically a mode that the 1st board | substrate was cut | disconnected so that may be crossed. (A), (b), and (c) each show a state in which the first substrate is cut along a line passing through the pad toward the edge of the substrate in the electro-optical device according to the second embodiment of the present invention. Schematic cross-sectional view, cross-sectional view schematically showing a state in which the first substrate is cut along a line that passes between the pads and toward the edge of the substrate, and the flexible wiring substrate is anisotropically conductive on the first substrate It is explanatory drawing when it connects with a material. (A), (b), (c) is a plan view schematically showing the vicinity of the pad formation region of the first substrate used in the electro-optical device according to Embodiment 3 of the present invention, and the substrate passes through the pad. Sectional drawing which shows a mode that the 1st board | substrate was cut | disconnected along the line which goes to the edge of this, and a mode that the 1st board | substrate was cut | disconnected along the line which goes to the edge of a board | substrate through between pads FIG. FIG. 6 is a block diagram showing an electrical configuration of an electro-optical device (organic EL device) according to a fourth embodiment of the present invention. It is explanatory drawing of the electronic device using the electro-optical apparatus which concerns on this invention. (A), (b), (c) is a plan view schematically showing the vicinity of the pad formation region of the first substrate used in the conventional electro-optical device, and is a line passing through the pad toward the edge of the substrate. It is sectional drawing which shows a mode that the 1st board | substrate was cut | disconnected along, and explanatory drawing when a flexible wiring board is connected to the 1st board | substrate with the anisotropic electrically conductive material.

Explanation of symbols

1 ... Semiconductor substrate, 1y ... Edge of substrate, 1z ... Edge region, 5 ... Guard ring, 6s ... First conductive layer, 8s ... Second conductive layer (top conductive layer), 9a ... Pixel electrode, 10... First substrate (electro-optical device substrate), 10 b... Pixel region, 12... Pad formation region, 20 .. Second substrate, 30 a, 30 b, 30 c. Pixel transistor), 50 ... Liquid crystal layer, 70 ... Insulating film, 73 ... Silicon nitride film (moisture resistant insulating film), 90 ... Flexible wiring board, 95 ... Anisotropic conductive material, 100 ... Electro-optical Device, 100a ... Pixel, 102 ... Pad

Claims (11)

A pixel region having a plurality of pixels each including a pixel electrode and a pixel transistor, and a pad forming region in which a plurality of pads are arrayed along a substrate edge are provided on the substrate. A substrate for an electro-optical device to which a wiring board having a conductive pattern electrically connected to the pad by a conductive conductive material is connected,
On the substrate, a guard ring is formed that extends along an outer peripheral edge on the substrate through an edge region sandwiched between the pad forming region and the substrate edge,
In the edge region, an uppermost conductive layer constituting the uppermost layer of the guard ring is left on a virtual extension line from the pad toward the substrate edge, and both sides sandwiching the extension line are interrupted by the uppermost conductive layer. A substrate for an electro-optical device, characterized by being a part. A pixel region having a plurality of pixels each including a pixel electrode and a pixel transistor, and a pad forming region in which a plurality of pads are arrayed along a substrate edge are provided on the substrate. A substrate for an electro-optical device to which a wiring board having a conductive pattern electrically connected to the pad by a conductive conductive material is connected,
On the substrate, a guard ring is formed that extends along an outer peripheral edge on the substrate through an edge region sandwiched between the pad forming region and the substrate edge,
In the edge region, the uppermost conductive layer constituting the uppermost layer of the guard ring is left on both sides of a virtual extension line from the pad toward the substrate edge, and the uppermost conductive layer is interrupted on the extension line. A substrate for an electro-optical device, characterized by being a part.   3. The electro-optical device substrate according to claim 1, wherein a portion of the uppermost conductive layer formed in the edge region and divided by the interrupted portion is in an electrically floating state. The guard ring is formed by a plurality of conductive layers stacked with an interlayer insulating film interposed therebetween,
In the edge region, the discontinuous portion is formed in one or more upper conductive layers including the uppermost conductive layer among the plurality of conductive layers, and the other conductive layers are continuous without being interrupted in the edge region. The substrate for an electro-optical device according to claim 1, wherein the substrate for an electro-optical device is extended.   4. The electro-optical device substrate according to claim 1, wherein the uppermost conductive layer is covered with an insulating film in the edge region. 5.   6. The electro-optical device substrate according to claim 5, wherein in the insulating film, the layer directly covering the surface of the uppermost conductive layer is a moisture-resistant insulating film.   5. The uppermost conductive layer in the edge region has a surface exposed from an insulating film and is in direct contact with the anisotropic conductive material. 2. The substrate for an electro-optical device according to 1.   An electro-optical device comprising the electro-optical device substrate according to claim 1.   9. The electro-optical device according to claim 8, wherein a liquid crystal is held between the electro-optical device substrate and a substrate disposed on the electro-optical device substrate.   9. The electro-optical device according to claim 8, wherein a functional layer for an organic electroluminescence element is formed on the pixel electrode.   An electronic apparatus comprising the electro-optical device according to claim 8.

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