JP2009177278A - A/d converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an A/D converter capable of simplifying a circuit configuration. <P>SOLUTION: Each of comparison operation circuits CP1-CP4 serially connected in four stages has a function of comparing a supplied input voltage with reference voltages R1-R4 in order, and outputs a bit 00 when the reference voltage supplied at the point of time at which the size relation of both changes is R1, a bit 01 when it is R2, a bit 10 when it is R3 and a bit 11 when it is R4. The voltage of analog signals to be a conversion object is supplied as the input voltage of the comparison operation circuit CP1 of the first stage. In each comparison operation circuit, a voltage 4×e, where a difference voltage e of the reference voltage supplied at the point of time at which the size relation changes and the input voltage is multiplied by four, is supplied as the input voltage of the comparison operation circuit of the next stage, and cascade operations are successively performed in the comparison operation circuits CP1-CP4 of four stages. After inverting the bits output from the comparison operation circuits CP2 and CP4 of the even-numbered stages, respective bit streams are output as the value of 8 bits expressing a digital value after conversion. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an A / D converter, and in particular, sequentially compares an analog signal voltage to be converted with an analog reference signal whose voltage increases stepwise, and outputs a bit string corresponding to the comparison result. The present invention relates to an A / D converter that uses a comparison arithmetic circuit connected in multiple stages.

  With the spread of technology for handling information as digital data, A / D converters that play a role in converting analog data into digital data have come to be used in various technical fields. For example, in a solid-state imaging device, an analog signal indicating the received light intensity at the pixel position is output from each pixel constituting the image sensor. To create imaging data based on these analog signals, each analog signal is generated. It is necessary to convert the signal into a digital signal, and in order to perform such conversion, a general solid-state imaging device includes an A / D converter.

  A general A / D converter includes a comparison operation circuit that compares the magnitude relationship between an input voltage and a reference voltage. While increasing the reference voltage applied to the comparison operation circuit stepwise, the magnitude relationship is increased. The method of recognizing the change timing of the signal and outputting a bit string corresponding to the change timing as converted digital data is adopted. For example, Patent Documents 1 and 2 below disclose basic A / D converters using such a comparison operation circuit.

Usually, the conversion accuracy is improved by connecting such comparison operation circuits in multiple stages. That is, the “residual component corresponding to the difference between the input voltage and the reference voltage (a component that does not satisfy the step width of the step-like reference voltage)” in the preceding comparison operation circuit is amplified via the amplifier circuit, A method of applying as an input voltage to the comparison operation circuit is employed. Patent Documents 3 and 4 below disclose A / D converters in which a plurality of comparison operation circuits are cascade-connected via an amplifier circuit. Further, in Patent Document 5 below, after the residual component output from the comparison operation circuit is amplified, it is again provided as an input signal to the same comparison operation circuit, and the signal is circulated to the same comparison operation circuit. Thus, a cyclic A / D converter is disclosed in which a single comparison operation circuit can execute processing equivalent to that of a device using substantially multiple stages of comparison operation circuits.
Japanese Patent Laid-Open No. 6-77830 JP-A-8-213908 Japanese Patent Laid-Open No. 11-214997 JP 2000-78011 A JP 2007-36580 A

  As described above, the conventional general A / D converter using the comparison arithmetic circuit connected in multiple stages increases the reference voltage stepwise and recognizes the timing when the magnitude relationship with the input signal changes. In addition, a bit string corresponding to the change timing is output, and a difference voltage serving as a residual component is output to the subsequent stage. However, the difference voltage output to the subsequent stage is not the difference from the “reference voltage at the timing when the magnitude relationship changes” but the difference from the “reference voltage at the timing immediately before the magnitude relationship changes”. The difference voltage obtained for the determination of the magnitude relationship cannot be used as it is. For this reason, in the conventional A / D converter, the circuit configuration for outputting the differential voltage to the subsequent stage has to be complicated.

  Accordingly, an object of the present invention is to provide an A / D converter that can further simplify the circuit configuration.

(1) The first aspect of the present invention is:
A comparison operation circuit that compares the magnitude relationship between the input voltage and a predetermined reference voltage, outputs a bit indicating the comparison result, and outputs a difference voltage between the input voltage and the reference voltage;
An amplifier circuit for amplifying the differential voltage output from the comparison operation circuit;
With
The comparison operation circuit is cascaded in a plurality of stages with the amplification circuit interposed so that the differential voltage output from the comparison operation circuit of the previous stage is amplified by the amplification circuit and then input to the comparison operation circuit of the subsequent stage. ,
When an analog signal to be converted is supplied to the first-stage comparison operation circuit, an A / D converter that obtains converted digital data as a bit output string from each comparison operation circuit,
The comparison operation circuit outputs a difference voltage related to the reference voltage that was given when the magnitude relationship between the input voltage and the reference voltage changed,
Bit inversion means for performing logic inversion on the bit output from the even-numbered comparison operation circuit is further provided.

(2) According to a second aspect of the present invention, in the A / D converter according to the first aspect described above,
By gradually increasing the voltage, a plurality of reference voltages are generated in order, and a reference voltage generation circuit is provided that gives this to the comparison operation circuit at a predetermined timing,
The comparison operation circuit recognizes the timing when the magnitude relationship between the input voltage and the reference voltage has changed, and outputs a specific bit associated with the change timing.

(3) According to a third aspect of the present invention, in the A / D converter according to the second aspect described above,
The comparison operation circuit obtains a difference voltage between the input voltage and the reference voltage, a storage circuit that temporarily holds the difference voltage, a sign determination circuit that determines the sign of the difference voltage, and a determination result of the sign determination circuit And a control circuit that outputs a specific bit based on the timing at which the signal changes, and the storage circuit outputs a difference voltage that is held when the determination result of the sign determination circuit changes. is there.

(4) According to a fourth aspect of the present invention, in the A / D converter according to the second or third aspect described above,
The comparison operation circuit is configured to be provided with an input voltage from 0 to Vmax in the full range of voltage width,
Of the (2 ⁿ +1) voltage R (0), R (1), R (2),..., R (2 ⁿ ) obtained by dividing the full range by 2 ⁿ (However, R (0) = 0, R (2 ⁿ ) = Vmax), ²ⁿ reference voltages R (1), R (2),..., R (2 ⁿ ) are generated in this order. ,
When the comparison operation circuit changes the magnitude relationship (i = 1, 2,..., 2 ⁿ ) when comparing the input voltage with the i-th reference voltage R (i) (i = 1, 2,..., 2 ⁿ ), A differential voltage with respect to the th reference voltage R (i) and an n-bit bit string corresponding to the binary representation of the value (i−1),
The amplifier circuit amplifies the differential voltage by ²ⁿ times.

(5) According to a fifth aspect of the present invention, in the A / D converter according to the first to fourth aspects described above,
K sets (K is a natural number of 2 or more) comparison operation circuits and (K-1) sets of amplification circuits are provided, and the difference output from the k-th (k = 1 to K-1) comparison operation circuits is provided. The comparison operation circuit and the amplification circuit are alternately connected so that the voltage is amplified by the kth amplification circuit and then input to the (k + 1) th comparison operation circuit,
The bit inversion means is constituted by an inverter circuit provided on the bit output line from the even-numbered comparison operation circuit.

(6) According to a sixth aspect of the present invention, in the A / D converter according to the first to fourth aspects described above,
A set of comparison operation circuits and a set of amplification circuits are provided so that the differential voltage output from the set of comparison operation circuits is amplified by the amplification circuit and then input to the same comparison operation circuit again. In order to realize a cascade connection of a plurality of stages by a set of comparison operation circuits themselves,
Bit inversion means performs logic inversion on the even-numbered bit output from the comparison operation circuit.

(7) According to a seventh aspect of the present invention, in the A / D converter according to the sixth aspect described above,
A selector that selectively outputs a signal applied to the first input terminal and a signal applied to the second input terminal is provided, and an analog signal to be converted is input to the first input terminal of the selector. Connect the signal line to be supplied, connect the output terminal of the selector to the input terminal for the input voltage of the comparison operation circuit, connect the output terminal for the differential voltage of the comparison operation circuit to the input terminal of the amplification circuit, The output terminal is connected to the second input terminal of the selector, and the selector selectively outputs the signal given to the first input terminal at the beginning when the analog signal to be converted is given, and the circuit is circulated from the amplifier circuit. After the signal is given, the signal given to the second input terminal is selectively outputted.

  The A / D converter according to the present invention is the same as the conventional A / D converter in that the comparison operation circuit is connected in multiple stages, but the difference voltage output to the subsequent stage is “ Since the difference from the “reference voltage at the changed timing” is used, the difference voltage obtained for determining the magnitude relation can be output to the subsequent stage as it is, and the circuit configuration can be simplified. become. In addition, the problem caused by outputting the difference from the “reference voltage at the timing when the magnitude relationship changes” to the subsequent stage is solved by performing logical inversion on the bit output from the even-numbered comparison operation circuit. Therefore, it is completely the same as the conventional A / D converter in that a correct conversion result can be obtained.

  Hereinafter, the present invention will be described based on the illustrated embodiments.

<<< §1. Basic Configuration of Conventional A / D Converter (Part 1) >>>
Here, for convenience of explanation, the basic configuration and operation principle of a conventional general A / D converter using a comparison arithmetic circuit connected in multiple stages will be briefly described. FIG. 1 is a block diagram showing the basic configuration of such a conventional A / D converter.

  In the figure, CP1 to CP4 are comparison operation circuits each having the same configuration, compare the magnitude relationship between the input voltage Vin and the reference voltage R, and output 1 bit based on the comparison result. It has a function of outputting a voltage difference as an output voltage Vout. For example, the comparison operation circuit CP1 compares the magnitude relationship between the input voltage Vin (1) and the reference voltage R, performs a 1-bit output B1 based on the comparison result, and outputs the difference voltage (Vin (1) and R). Is output as the output voltage Vout (1).

  On the other hand, each of A1 to A3 is an amplifier circuit that amplifies the input voltage by a factor of two (reference symbol X2 indicates that the amplification factor is two), and as illustrated, between the comparison operation circuits CP1 to CP4. Is inserted. The input terminal of each amplifier circuit is connected to the output terminal for the differential voltage of the comparison operation circuit located in the previous stage, and the output terminal of each amplification circuit is the input terminal for the input voltage of the comparison operation circuit located in the subsequent stage. It is connected to the. Therefore, for example, the amplifier circuit A1 doubles the output voltage Vout (1) from the comparison operation circuit CP1 located in the previous stage, and the amplified voltage is input to the comparison operation circuit CP2 located in the subsequent stage. It fulfills the function of supplying as Vin (2).

  Similarly, the amplifier circuit A2 doubles the output voltage Vout (2) from the comparison operation circuit CP2 located in the previous stage, and the amplified voltage is compared with the input voltage Vin to the comparison operation circuit CP3 located in the subsequent stage. The amplifier circuit A3 performs the function of supplying as (3), and the amplifier circuit A3 amplifies the output voltage Vout (3) from the comparison operation circuit CP3 located in the previous stage by a factor of 2, and the comparison operation circuit CP4 located in the subsequent stage. In contrast, the function of supplying the input voltage Vin (4) is achieved.

  FIG. 2 is a diagram showing a general processing operation of each of the comparison operation circuits CP1 to CP4 shown in FIG. Here, in order to mean “kth comparison operation circuit”, the comparison operation circuit is denoted by a symbol CPk. As described above, the first function of the comparison operation circuit CPk is to compare the magnitude relationship between the input voltage Vin (k) and the predetermined reference voltage R and to output the bit B indicating the comparison result. The second function is to output the difference voltage between the input voltage Vin (k) and the reference voltage R as the output voltage Vout (k). In FIG. 1, the reference voltage is indicated by a symbol R, but actually, the reference voltage R changes with time and takes a plurality of voltage values. In the example shown here, as shown in FIG. 2, the reference voltage takes two values R0 and R1, and the input voltage Vin (k) is compared with the two reference voltages R0 and R1. Will be.

  However, normally, since the reference voltage R0 is set to the ground potential and the input voltage Vin (k) is set to be equal to or higher than the ground potential, the comparison process regarding the magnitude relationship with the reference voltage R0 can be omitted. Therefore, in practice, the comparison of the magnitude relationship in the comparison operation circuit CPk only needs to be performed for the reference voltage R1. The right half of FIG. 2 shows specific processing contents of the comparison operation circuit CPk executed based on the comparison result. That is, when Vin (k) <R1, the output bit B = 0 is output (first function), and the difference voltage Vout (k) = Vin (k) −R0 is output (second function). ). On the other hand, when Vin (k) ≧ R1, the output bit B = 1 is output (first function), and a differential voltage Vout (k) = Vin (k) −R1 is output (second function). ).

  FIG. 3 is a diagram illustrating a specific processing operation of such a comparison operation circuit CPk. In the figure, R0 is the ground potential, R2 is the voltage value of the full range Vmax, R1 is an intermediate potential, and the bar graph indicates the magnitude of the input voltage Vin (k). As described above, the processing operation of the comparison operation circuit CPk is divided into two types based on the magnitude relationship between the input voltage Vin (k) and the reference voltage R1.

  FIG. 3A shows the processing operation when Vin (k) <R1. In this case, output bit B = 0 is output (“0” in the frame indicates the value of this output bit B), and a differential voltage of Vout (k) = Vin (k) −R0 is output. Here, since R0 is the ground potential and the voltage value is 0, Vout (k) = Vin (k), and as shown in the figure, the input voltage Vin (k) is output as the differential voltage Vout (k) as it is. Will be.

  On the other hand, FIG. 3B shows the processing operation when Vin (k) ≧ R1. In this case, output bit B = 1 is output (“1” in the frame indicates the value of this output bit B), and a differential voltage of Vout (k) = Vin (k) −R1 is output. As shown in the drawing, a difference voltage corresponding to the residual obtained by subtracting the reference voltage R1 from the input voltage Vin (k) is output as Vout (k).

  Next, a specific processing operation in which four sets of comparison operation circuits included in the A / D converter shown in FIG. 1 are linked will be described with reference to FIG. CP1 to CP4 shown in FIG. 4 correspond to the comparison operation circuits CP1 to CP4 shown in FIG. 1, and specific processing operations in the respective comparison operation circuits are shown. Here, for the sake of convenience, the following description will be made assuming specific voltage values (anonymous number) of ground potential R0 = 0, full range R2 = 100, and reference voltage R1 = 50.

  Now, it is assumed that a signal having a voltage corresponding to the voltage value “66” is given to the A / D converter as an analog signal to be converted. In this case, the input voltage supplied to the first-stage comparison operation circuit CP1 is Vin (1) = 66. Since the reference voltage R1 = 50, the comparison operation circuit CP1 executes the “processing operation in the case of Vin (k) ≧ R1” shown in FIG. 2, the output bit B1 = 1 is output, and Vout Based on the equation (1) = Vin (1) −R1, a differential voltage d of d = 66−50 = 16 is output as the output voltage Vout (1). This difference voltage d is amplified twice by the amplifier circuit A1, and is supplied as the input voltage Vin (2) to the second comparison operation circuit CP2. In the example shown in the figure, since d = 16, 2 · d = 32 is given to the comparison operation circuit CP2 in the second stage (the dashed line in the figure indicates that twice the difference voltage d is in the subsequent stage. Indicating that it will be sent).

  Thus, the input voltage applied to the second-stage comparison operation circuit CP2 is Vin (2) = 32. Since the reference voltage R1 = 50, the comparison operation circuit CP2 executes the “processing operation when Vin (k) <R1” shown in FIG. 2, and the output bit B2 = 0 is output. Based on the equation (2) = Vin (2) −R0, the difference voltage d of Vin (2) = 32 is output as it is as the output voltage Vout (2). The difference voltage d is amplified twice by the amplifier circuit A2, and is supplied as the input voltage Vin (3) to the third-stage comparison operation circuit CP3. In the example shown in the figure, since d = 32, 2 · d = 64 is given to the third-stage comparison operation circuit CP3.

  Subsequently, an input voltage Vin (3) = 64 is applied to the third-stage comparison operation circuit CP3. Since the reference voltage R1 = 50, the comparison operation circuit CP3 executes the “processing operation in the case of Vin (k) ≧ R1” shown in FIG. 2, the output bit B3 = 1 is output, and Vout Based on the equation (3) = Vin (3) −R1, a differential voltage d of d = 64−50 = 14 is output as the output voltage Vout (3). The difference voltage d is amplified twice by the amplifier circuit A3, and is supplied as the input voltage Vin (4) to the fourth comparison operation circuit CP4. In the example shown in the figure, since d = 14, 2 · d = 28 is supplied to the fourth-stage comparison operation circuit CP4.

  Thus, the input voltage supplied to the fourth-stage comparison operation circuit CP4 is Vin (4) = 28. Since the reference voltage R1 = 50, the comparison operation circuit CP4 executes the “processing operation in the case of Vin (k) <R1” shown in FIG. 2, the output bit B4 = 0 is output, and Vout Based on the arithmetic expression (4) = Vin (4) −R0, the differential voltage d of Vin (4) = 28 is output as it is as the output voltage Vout (4). In the example shown here, the fourth-stage comparison operation circuit CP4 is the final stage. However, when the fifth-stage comparison operation circuit continues, this difference voltage d is amplified twice by the amplification circuit. And supplied to the fifth-stage comparison operation circuit.

  Thus, as a digital output from the A / D converter, a bit string “1010” in which output bits B1, B2, B3, and B4 are arranged in this order is obtained. This is a digital value corresponding to the analog voltage value “66” when the full range R2 = 100.

<<< §2. Basic configuration of conventional A / D converter (2) >>
As described above, in §1, the basic operation of the A / D converter shown in FIG. 1 has been described. The A / D converter shown in FIG. 1 is a very simple example in which a comparison result in 1-bit units is output from one comparison operation circuit. Usually, a plurality of bits are output from one comparison operation circuit. In general, a unit comparison result is output. FIG. 5 is a block diagram showing a basic configuration of a conventional general A / D converter that outputs a comparison result in units of 2 bits from one comparison operation circuit. The comparison operation circuits CP1 to CP4 have a function of comparing the magnitude relationship between the input voltage Vin and the reference voltage R, outputting 2 bits based on the comparison result, and outputting the difference between the two voltages as the output voltage Vout. . For example, the comparison operation circuit CP1 compares the magnitude relationship between the input voltage Vin (1) and the reference voltage R, performs 2-bit outputs B1 and B2 based on the comparison result, and compares the difference voltage (Vin (1) with (Difference from R) is output as the output voltage Vout (1). Similarly, 2-bit outputs B3 and B4 are obtained from the comparison operation circuit CP2, 2-bit outputs B5 and B6 are obtained from the comparison operation circuit CP3, and 2-bit outputs B7 and B8 are obtained from the comparison operation circuit CP4. Is obtained.

  On the other hand, each of A1 to A3 is an amplifying circuit that amplifies the input voltage by 4 times (reference X4 indicates that the amplification magnification is 4 times). The points where the respective amplifier circuits A1 to A3 are interposed between the respective comparison operation circuits CP1 to CP4 are the same as in the above example. For example, the amplifier circuit A1 amplifies the output voltage Vout (1) from the comparison operation circuit CP1 located in the preceding stage by a factor of 4, and the amplified voltage is compared with the input voltage Vin ( 2) fulfills the function of supplying.

  FIG. 6 is a diagram showing a general processing operation of each of the comparison operation circuits CP1 to CP4 shown in FIG. Here, in order to mean “kth comparison operation circuit”, the comparison operation circuit is denoted by a symbol CPk. As described above, the first function of the comparison operation circuit CPk is to compare the magnitude relationship between the input voltage Vin (k) and the predetermined reference voltage R, and to output the comparison result as 2-bit data. The second function is to output the difference voltage between the input voltage Vin (k) and the reference voltage R as the output voltage Vout (k). In the figure, 2-bit data output by the first function is shown as a left output bit BL and a right output bit BR. Thus, in order to output the comparison result as 2-bit data, four different comparison results must be obtained.

  Therefore, in the example shown here, four voltages R0, R1, R2, and R3 are used as the reference voltage R. As will be described later, the reference voltage R is given by a signal whose voltage increases stepwise with time. The step-like signal shown in the block of the comparison operation circuit CPk in FIG. 6 shows the waveform of such a reference signal. Therefore, the input voltage Vin (k) given to the comparison operation circuit CPk is first compared with the reference voltage R0 (in fact, since R0 is the ground potential, it is impossible that Vin (k) <R0. This comparison operation can be omitted), followed by comparison with the reference voltage R1, then with the reference voltage R2, and finally with the reference voltage R3. However, if there is a change in the magnitude relationship in comparison with any of the reference voltages, the subsequent comparison operation becomes unnecessary.

  (1) to (4) shown in the lower half of FIG. 6 show specific processing contents of the comparison operation circuit CPk executed based on each comparison result. As described above, if the comparison process with the ground potential R0 is omitted, the comparison with the reference voltage R1 is performed as the first comparison process. As a result, as shown in FIG. 6A, when Vin (k) <R1, output bits BL = 0 and BR = 0 are output (first function), and Vout (k) = Vin A differential voltage of (k) −R0 is output (second function). In this case, the magnitude relationship changes in comparison with the reference voltage R1. Therefore, thereafter, the comparison operation with the reference voltages R2 and R3 is unnecessary.

  When no change in the magnitude relationship has occurred by comparison with the reference voltage R1 (that is, when R1 ≦ Vin (k)), comparison with the reference voltage R2 is performed as the second comparison process. . As a result, as shown in FIG. 6 (2), when R1 ≦ Vin (k) <R2, output bits BL = 0 and BR = 1 are output (first function), and Vout (k) = A difference voltage of Vin (k) -R1 is output (second function). In this case, the magnitude relationship changes in comparison with the reference voltage R2. Therefore, thereafter, the comparison operation with the reference voltage R3 is unnecessary.

  If no change in the magnitude relationship has occurred by comparison with the reference voltage R2 (that is, when R2 ≦ Vin (k)), comparison with the reference voltage R3 is performed as a third comparison process. As a result, as shown in FIG. 6 (3), when R2 ≦ Vin (k) <R3, output bits BL = 1 and BR = 0 are output (first function), and Vout (k) = A difference voltage Vin (k) -R2 is output (second function). In this case, the magnitude relationship changes in comparison with the reference voltage R3.

  Finally, when no change in the magnitude relationship occurs even by comparison with the reference voltage R3, that is, when R3 ≦ Vin (k), the input voltage Vin (k) is not less than the voltage R3 and not more than the full range Vmax. That is the voltage within the range. Accordingly, as shown in FIG. 6 (4), output bits BL = 1 and BR = 1 are output (first function), and a differential voltage Vout (k) = Vin (k) −R3 is output ( Second function).

  FIG. 7 is a diagram illustrating a specific processing operation of such a comparison operation circuit CPk. In the figure, R0 is a ground potential, R4 is a voltage value of the full range Vmax, R1 to R3 are potentials at intermediate positions obtained by dividing R0 to R4 into four equal parts, and the bar graph indicates the magnitude of the input voltage Vin (k). It shows. As described above, the processing operation of the comparison operation circuit CPk is divided into four types based on the magnitude relationship between the input voltage Vin (k) and the reference voltages R1, R2, and R3.

  FIG. 7A shows the processing operation when Vin (k) <R1. In this case, output bits BL = 0 and BR = 0 are output, and a difference voltage Vout (k) = Vin (k) −R0 is output. Here, since R0 is the ground potential and the voltage value is 0, Vout (k) = Vin (k), and as shown in the figure, the input voltage Vin (k) is output as the differential voltage Vout (k) as it is. Will be.

  On the other hand, FIG. 7B shows the processing operation when R1 ≦ Vin (k) <R2. In this case, BL = 0 and BR = 1 are output, and a differential voltage Vout (k) = Vin (k) −R1 is output. As shown in the drawing, a difference voltage corresponding to the residual obtained by subtracting the reference voltage R1 from the input voltage Vin (k) is output as Vout (k).

  FIG. 7C shows the processing operation when R2 ≦ Vin (k) <R3. In this case, BL = 1 and BR = 0 are output, and a differential voltage Vout (k) = Vin (k) −R2 is output. As shown in the drawing, a difference voltage corresponding to the residual obtained by subtracting the reference voltage R2 from the input voltage Vin (k) is output as Vout (k).

  FIG. 7D shows the processing operation when R3 ≦ Vin (k) ≦ R4. In this case, BL = 1 and BR = 1 are output, and a differential voltage Vout (k) = Vin (k) −R3 is output. As shown in the drawing, a difference voltage corresponding to the residual obtained by subtracting the reference voltage R3 from the input voltage Vin (k) is output as Vout (k).

  Next, a specific processing operation in which four sets of comparison operation circuits included in the A / D converter shown in FIG. 5 are linked will be described with reference to FIG. CP1 to CP4 shown in FIG. 8 correspond to the comparison operation circuits CP1 to CP4 shown in FIG. 5, and specific processing operations in the respective comparison operation circuits are shown. Here, for the sake of convenience, the following explanation is made assuming specific voltage values (anonymous number) of ground potential R0 = 0, full range R4 = 100, reference voltage R1 = 25, reference voltage R2 = 50, and reference voltage R3 = 75. To do.

  Now, it is assumed that a signal having a voltage corresponding to the voltage value “66” is given to the A / D converter as an analog signal to be converted. In this case, the input voltage supplied to the first-stage comparison operation circuit CP1 is Vin (1) = 66. For this reason, in the comparison with the reference voltages R1 and R2, the magnitude relationship of “input voltage> reference voltage” is maintained, but by the comparison with the reference voltage R3, the change in magnitude relationship of “input voltage <reference voltage” is maintained. (Reverse) will occur. Therefore, in the comparison operation circuit CP1, the processing operation shown in FIG. 7C is executed, B1 = 1 and B2 = 0 are output, and the difference voltage Vout (1) = Vin (1) −R2 is output. Is output. Specifically, a differential voltage d of d = 66−50 = 16 is output as the output voltage Vout (1). The difference voltage d is amplified four times by the amplifier circuit A1, and is supplied as the input voltage Vin (2) to the second comparison operation circuit CP2. In the example shown in the figure, since d = 16, 4 · d = 64 is given to the second-stage comparison operation circuit CP2 (the one-dot chain line in the figure indicates that four times the difference voltage d is in the subsequent stage. Indicating that it will be sent).

  Thus, the input voltage applied to the second-stage comparison operation circuit CP2 is Vin (2) = 64. For this reason, in the comparison with the reference voltages R1 and R2, the magnitude relationship of “input voltage> reference voltage” is maintained, but by the comparison with the reference voltage R3, the change in magnitude relationship of “input voltage <reference voltage” is maintained. (Reverse) will occur. Therefore, in the comparison operation circuit CP2, the processing operation shown in FIG. 7C is executed, B3 = 1 and B4 = 0 are output, and the difference voltage Vout (2) = Vin (2) −R2 is output. Is output. Specifically, a differential voltage d of d = 64−50 = 14 is output as the output voltage Vout (2). The difference voltage d is amplified four times by the amplifier circuit A2, and is supplied as the input voltage Vin (3) to the third-stage comparison operation circuit CP3. In the example shown in the figure, since d = 14, 4 · d = 56 is supplied to the third-stage comparison operation circuit CP3.

  Thus, the input voltage Vin (3) = 56 is applied to the third-stage comparison operation circuit CP3. For this reason, in the comparison with the reference voltages R1 and R2, the magnitude relationship of “input voltage> reference voltage” is maintained, but by the comparison with the reference voltage R3, the change in magnitude relationship of “input voltage <reference voltage” is maintained. (Reverse) will occur. Therefore, in the comparison operation circuit CP3, the processing operation shown in FIG. 7C is executed, B5 = 1 and B6 = 0 are output, and the difference voltage Vout (3) = Vin (3) −R2 is output. Is output. Specifically, a differential voltage d of d = 56−50 = 6 is output as the output voltage Vout (3). The difference voltage d is amplified four times by the amplifier circuit A3, and is supplied as the input voltage Vin (4) to the fourth comparison operation circuit CP4. In the illustrated example, since d = 6, 4 · d = 24 is given to the fourth-stage comparison operation circuit CP4.

  When an input voltage of Vin (4) = 24 is applied to the final fourth comparison operation circuit CP4, a change in the magnitude relationship of “input voltage <reference voltage” occurs in comparison with the reference voltage R1. become. In the example shown here, the comparison operation with the reference voltage R0 is omitted. However, if the initial state in the comparison operation circuit at each stage is set to “input voltage> reference voltage”, the reference voltage is set. Even if the comparison operation with R1 is the first comparison operation in the comparison operation circuit CP4, if the result of “input voltage <reference voltage” is obtained, the magnitude relationship has changed. Therefore, in the comparison operation circuit CP4, the processing operation shown in FIG. 7A is executed, B7 = 0 and B8 = 0 are output, and the difference voltage Vout (4) = Vin (4) −R0. Is output. Specifically, a differential voltage d of d = 24−0 = 24 is output as the output voltage Vout (4). In the example shown here, the fourth-stage comparison operation circuit CP4 is the final stage. However, when the fifth-stage comparison operation circuit continues, this difference voltage d is amplified by a factor of 4 by the amplification circuit. In this case, 4 · d = 96 is supplied to the fifth-stage comparison operation circuit.

  Thus, as a digital output from the A / D converter, a bit string “10101000” in which output bits B1 to B8 are arranged in this order is obtained. This is a digital value corresponding to the analog voltage value “66” when the full range R4 = 100.

  As described above, the A / D converter shown in FIG. 5 is an example in which a comparison result in units of 2 bits is output from one comparison operation circuit. Of course, a comparison result in units of 3 bits or more is output. An A / D converter having such a configuration is also used.

<<< §3. Basic configuration of conventional A / D converter (Part 3) >>>
Here, a conventional example of a cyclic A / D converter as disclosed in Patent Document 5 will be briefly described. In the example described in §1 and §2, four sets of comparison operation circuits CP1 to CP4 are connected in multiple stages. Here, the four sets of comparison operation circuits CP1 to CP4 are all physically separate and independent components. However, since the processing operations are the same in all cases, the apparatus proposed based on the idea of realizing such multi-stage connection by using a single comparison operation circuit is a cyclic A / D. It is a converter. In this cyclic A / D converter, after the residual component output from the comparison operation circuit is amplified, it is again supplied to the same comparison operation circuit as an input signal, and the signal is made to cycle through the same comparison operation circuit. As a result, it is possible to execute processing equivalent to that of a device using a multistage comparison operation circuit by a single comparison operation circuit.

  FIG. 9 is a block diagram showing a basic configuration of a conventional cyclic A / D converter that outputs a comparison result in a general 2-bit unit. In other words, the A / D converter shown in FIG. 9 is obtained by replacing the cascade-connected A / D converter shown in FIG. 5 with a cyclic type. In FIG. 9, the comparison operation circuit CPk is a single comparison operation circuit, but fulfills the function of combining the four sets of comparison operation circuits CP1 to CP4 shown in FIG. The function of the comparison operation circuit CPk itself is exactly the same as that of the four sets of comparison operation circuits CP1 to CP4 shown in FIG. 5, and the input voltage Vin (k) and the reference voltage R (the voltages R0, R1 stepwise with time). , R2 and R3), and outputs 2-bit data BL and BR indicating the comparison results according to the equations shown in FIGS. A process of outputting the differential voltage as the output voltage Vout (k) is performed. Similarly, the amplifier circuit Ak in FIG. 9 also functions as the three sets of amplifier circuits A1 to A3 shown in FIG. 5, and performs a process of amplifying the output voltage Vout (k) from the comparison operation circuit CPk by four times. Do.

  In the cyclic A / D converter shown in FIG. 9, the output voltage of the amplifier circuit Ak is applied to the selector S. The selector S includes two input terminals, and has a function of selectively outputting a signal given to the first input terminal and a signal given to the second input terminal. As shown in the figure, a signal line for supplying an analog signal (voltage V) to be converted is connected to the first input terminal of the selector S, and the output terminal of the amplifier circuit Ak is connected to the second input terminal. Amplified signal circulated from is provided.

  The input voltage Vin (k) of the comparison operation circuit CPk can be switched in two ways by the selection operation of the selector S. Therefore, at the beginning when the analog signal to be converted is given, if the selector S selectively outputs the signal given to the first input terminal, the input voltage Vin (k) of the comparison operation circuit CPk. Is the voltage V of the analog signal to be converted, and the comparison operation circuit CPk functions as the first comparison operation circuit CP1 shown in FIG. On the other hand, after the cyclic signal is supplied from the amplifier circuit Ak, if the selector S selectively outputs the signal given to the second input terminal, the comparison operation circuit CPk is shown in FIG. It functions as a comparison operation circuit CP2 for the second and subsequent stages.

  In this way, if the cyclic processing is performed four times using the comparison operation circuit CPk, processing substantially equivalent to the A / D converter shown in FIG. 5 can be executed. In this case, since the comparison operation circuit CPk outputs 2-bit data at each cycle, if this is arranged four times to form 8-bit data, the data is converted into an analog signal to be converted. The digital data corresponding to the voltage V.

  FIG. 10 is a block diagram showing an example in which the cyclic A / D converter shown in FIG. 9 is extended to an A / D converter that outputs a comparison result in units of 3 bits. The comparison operation circuit CPk has a function of outputting the comparison result as data B1, B2, B3 in units of 3 bits at every cycle. Therefore, eight voltages R0 to R7 are used as the reference voltage R. The step-like signal shown in the block of the comparison operation circuit CPk in FIG. 10 shows the waveform of such a reference signal. Here, R0 is a ground potential, and R1 to R7 are intermediate potentials obtained by dividing the full range Vmax (= R8) into eight equal parts (the comparison with the full range R8 is unnecessary, so the reference voltage is up to R7). ) Further, the amplifier circuit Ak executes a process of amplifying the output voltage Vout (k) from the comparison operation circuit CPk by 8 times.

FIG. 11 shows an example in which the cyclic A / D converter shown in FIGS. 9 and 10 is extended to an A / D converter that outputs a comparison result in units of n bits expressed by an arbitrary number n. FIG. The comparison operation circuit CPk has a function of outputting the comparison result as data B1, B2,. For this purpose, 2 ⁿ kinds of voltages R (0) to R (2 ⁿ −1) are used as the reference voltage R. Here, R (0) is a ground potential, and R (1) to R (2 ⁿ −1) are intermediate potentials obtained by equally dividing the full range Vmax (= R (2 ⁿ )) by 2 ⁿ (full range). Since no comparison with R (2 ⁿ ) is required, the reference voltage is up to R (2 ⁿ −1)). The amplifier circuit Ak executes a process of amplifying the output voltage Vout (k) from the comparison operation circuit CPk by ²ⁿ times. Here, for convenience of reference, the i-th reference voltage is indicated by parenthesized reference R (i), but R (0), R (1), R (2),... Is the same as the reference voltages R0, R1, R2,.

  FIG. 12 is a block diagram showing a specific configuration example of a comparison operation circuit included in a conventional general A / D converter. In the description so far, the comparison operation circuit CPk is shown as one block. However, in actuality, the comparison operation circuit CPk is realized, for example, with a configuration as shown in FIG. That is, in the illustrated example, the comparison operation circuit CPk is configured by the difference circuit 10, the storage circuit 11, the sign determination circuit 12, and the control circuit 13. A reference voltage generation circuit 20 shown in FIG. 12 is a circuit for generating a reference voltage R that has been described as a voltage that increases stepwise.

  The difference circuit 10 is a circuit for obtaining a difference voltage between the input voltage Vin (k) and the reference voltage R, and the obtained difference voltage is given to the storage circuit 11 and the sign determination circuit 12. The memory circuit 11 temporarily holds this differential voltage. The sign determination circuit 12 determines the sign of the difference voltage (in other words, the magnitude relationship between the input voltage Vin (k) and the reference voltage R is determined). The control circuit 13 supplies the reference voltage R generated by the reference voltage generation circuit 20 to the difference circuit 10 and also specifies specific bits B1, B2, B3,... Based on the timing when the determination result is changed by the sign determination circuit 12. Is output. What bits are output when the timing changes are as already described in some examples. Further, the storage circuit 11 outputs the held differential voltage as the output voltage Vout (k) according to the determination result by the sign determination circuit 12.

<<< §4. Problems of the prior art and basic technical idea of the present invention >>>
Here, the problems of the conventional A / D converter described in §1 to §3 will be described, and the basic technical idea of the present invention effective for solving the problems will be described. As described above, the comparison operation circuit CPk is supplied with the reference voltage R that increases stepwise, and it is determined whether or not the magnitude relationship with the input voltage Vin (k) has changed. Let's take a closer look at the process of determining the change in magnitude.

  FIG. 13 is a time chart showing an example of such a change determination process. In the figure, the horizontal axis indicates the time t, the vertical axis indicates the voltage V, and the step-like waveform indicates the reference voltage R generated by the reference voltage generation circuit 20. Here, the reference voltage R is assumed to increase stepwise at a predetermined time interval, and the voltage step (vertical step width in the figure) is assumed to be constant. Also, the comparison determination of the magnitude relationship is executed at a predetermined cycle, and t (i-3), t (i-2), etc. shown on the time axis indicate the timing of this comparison determination. Shall be shown.

  In the illustrated example, the magnitude relationship between the reference voltage R (i-3) and the input voltage Vin (k) is determined at time t (i-3). Specifically, a comparison between the black circle and the x mark at time t (i-3) is performed. Since the determination result in this case is Vin (k)> R (i-3), the change in the magnitude relationship has not yet occurred. At the subsequent time t (i-2), the magnitude relationship between the reference voltage R (i-2) and the input voltage Vin (k) is determined. However, Vin (k)> R (i-2). No change in the magnitude relationship has yet occurred. Further, at time t (i−1), the magnitude relationship between the reference voltage R (i−1) and the input voltage Vin (k) is determined, but Vin (k)> R (i−1). Therefore, the change in the magnitude relationship has not yet occurred at this point. However, at time t (i), the magnitude relationship between the reference voltage R (i) and the input voltage Vin (k) is determined. At this time, Vin (k) <R (i) is reversed. Therefore, the magnitude relationship changes at this point.

  Let us consider how the comparison / determination circuit CPk shown in FIG. 12 performs in such a process. First, consider the operation at the time t (i-3). In this case, the difference circuit 10 outputs a difference voltage corresponding to “R (i−3) −Vin (k)”, and thus the difference voltage has a negative value. In the example shown in the figure, the sign determination circuit 12 determines that a change in the magnitude relationship has occurred when the applied difference voltage becomes a positive value, so at this point in time, no change determination is made. Similarly, at the determination timings at time t (i-2) and time t (i-1), since the difference voltage takes a negative value, change determination is not yet made. However, since the difference circuit 10 outputs the difference voltage e corresponding to “R (i) −Vin (k)” at the determination timing of the next time t (i), the difference voltage e becomes a positive value. A change determination is made.

  In this way, when the change determination is made at the determination timing at time t (i), the control circuit 13 can perform bit output according to this timing. That is, regarding the magnitude of the input voltage Vin (k), a determination result of R (i−1) ≦ Vin (k) <R (i) is obtained. For example, as shown in FIG. If it is determined that predetermined bit output is performed according to the magnitude of Vin (k), the comparison / determination circuit CPk corresponds to the determination result of R (i−1) ≦ Vin (k) <R (i). The specific bit output can be performed (first function of the comparison determination circuit CPk).

  On the other hand, the comparison determination circuit CPk needs to perform a process of outputting a residual voltage to be sent to the subsequent stage as a second function. It should be noted here that in the case of a conventional A / D converter, the residual voltage to be sent to the subsequent stage is the difference voltage e (absolute value e = R (i)) at the determination timing at time t (i). It is necessary to set the difference voltage d (absolute value d = Vin (k) −R (i−1)) at time t (i−1), which is the previous determination timing, instead of −Vin (k)). Is a point. In other words, the residual voltage output by the comparison / determination circuit CPk needs to be the difference between “the maximum of the reference voltages equal to or lower than Vin (k)” and “Vin (k)”. This can be easily understood by considering, for example, a process in which the residual voltage is sequentially sent to the subsequent stage and processed as shown in FIG.

  However, in the circuit configuration shown in FIG. 12, the difference voltage e corresponding to “R (i) −Vin (k)” has already been obtained from the difference circuit 10 at the determination timing at time t (i) when the change determination is made. Is output, and the difference voltage e is also temporarily stored in the memory circuit 11. For this reason, in the conventional A / D converter, the device for outputting the difference voltage d at the time t (i−1) that is the previous determination timing is required from the memory circuit 11.

  For example, when the signal indicating that the change determination is made from the sign determination circuit 12 to the control circuit 13 at the determination timing at time t (i), the control circuit 13 provides the reference voltage generation circuit 20. The reference voltage R (i−1) supplied at time t (i−1), which is the previous determination timing, may be supplied to the comparison determination circuit CPk instead of the original reference voltage. The waveform of the reference voltage R shown in FIG. 13 is obtained when such control is performed. That is, the original reference voltage R supplied from the reference voltage generation circuit 20 is a voltage R (i + 1) that is increased by one step from R (i) at time t (i + 1). Conversely, the circuit 13 supplies the voltage R (i−1) decreased by one step to the comparison / determination circuit CPk. Then, at the timing of time (i + 1), the memory circuit 11 holds a voltage value corresponding to the difference voltage d, and this can be output as Vout (k).

  The conventional A / D converter performs a process of sending the difference voltage d as a residual voltage to the subsequent stage by applying such a device. However, in order to apply such a device, it is necessary to provide the control circuit 13 with a function for performing the special processing as described above. In the sign determination circuit 12 as well, there is a situation in which the reverse rotation determination is made again at the time t (i + 1) after the magnitude reverse rotation determination is made at the time t (i). It is necessary to apply. For this reason, the actual circuit configuration must be complicated.

  The focus of the present invention is based on the idea that such inefficient processing can be omitted and the circuit configuration can be further simplified. The inventor of the present application obtains the folding angle and the difference voltage e at the time t (i) when the magnitude reversal determination is performed in the determination process shown in FIG. In addition, the inventors have come up with the idea that it would be possible to perform a process in which the difference voltage e is sent as a residual voltage to the subsequent stage.

  That is, conventionally, the residual voltage output for the comparison determination circuit CPk to send to the subsequent stage is the difference voltage d between “the maximum of the reference voltages equal to or lower than Vin (k)” and “Vin (k)”. In the present invention, the difference voltage e between “the minimum of the reference voltages exceeding Vin (k)” and “Vin (k)” is sent to the subsequent stage. It is used as the residual voltage output to the.

  However, if the difference voltage e is used instead of the difference voltage d, it is necessary to partially modify the processing operation. As is apparent from FIG. 13, the difference voltage d corresponds to “the length measured upward from the floor” when the voltage R (i−1) is considered as the floor, and corresponds to the floor. This is the residual to be added to the voltage R (i-1). On the other hand, the difference voltage e corresponds to “a length measured downward from the ceiling” when the voltage R (i) is considered as a ceiling, and is derived from the voltage R (i) corresponding to the ceiling. It should be a negative residual to be subtracted.

  Considering these points, the digital data output from the subsequent comparison judgment circuit should be handled as negative data with the sign reversed relative to the digital data output from the previous comparison judgment circuit. I understand. Conveniently, in the case of digital data composed of binary numbers, in order to reverse the sign, it is only necessary to perform a process of logically inverting each bit. In the end, if the difference voltage e is used instead of the difference voltage d, no trouble will occur if the logic inversion is performed on the bit output from the even-numbered comparison operation circuit.

  Eventually, the A / D converter to which the present invention is applied compares the magnitude relationship between the input voltage Vin (k) and a predetermined reference voltage R, outputs a bit B indicating the comparison result, and also inputs the input voltage Vin. A comparison operation circuit CPk that outputs a difference voltage between (k) and the reference voltage R, and an amplification circuit Ak that amplifies the difference voltage output from the comparison operation circuit CPk, and is output from the comparison operation circuit CPk in the previous stage. A plurality of stages are cascaded with the comparison operation circuit interposed in the amplification circuit so that the difference voltage is amplified by the amplification circuit Ak and then input to the subsequent comparison operation circuit CP (k + 1). When an analog signal is supplied to the first-stage comparison operation circuit CP1, it is an A / D converter that can obtain converted digital data as a bit output string from the comparison operation circuit at each stage. A feature of the present invention is that each comparison operation circuit has a function of outputting a difference voltage e related to the reference voltage R given when the magnitude relation between the input voltage Vin (k) and the reference voltage R changes. (In other words, it has a function of outputting a difference voltage e between “the minimum of the reference voltages R exceeding Vin (k)” and “Vin (k)”), even number A bit inversion means for performing logic inversion on the bit output from the comparison operation circuit at the stage is further provided.

  More specifically, the A / D converter according to the present invention generates a plurality of reference voltages R in order by gradually increasing the voltage, and supplies them to the comparison operation circuit at a predetermined timing. The generation circuit 20 is provided, and the comparison operation circuit CPk recognizes the timing at which the magnitude relationship between the input voltage Vin (k) and the reference voltage R changes, and outputs a specific bit associated with the change timing. It has a function.

  Several specific embodiments of the A / D converter according to the present invention based on such a basic technical idea will be described below.

<<< §5. First embodiment of A / D converter according to the present invention >>>
The basic configuration of the embodiment described here is almost the same as the basic configuration of the conventional A / D converter shown in FIG. That is, also in the embodiment according to the present invention, the comparison operation circuits CP1 to CP4 are comparison operation circuits each having the same configuration, and the magnitude relation between the input voltage Vin and the reference voltage R is compared, and the comparison result is obtained. Based on this, it has a function of outputting 1 bit and outputting a difference between both voltages as an output voltage Vout. Each of the amplifier circuits A1 to A3 is an amplifier circuit that amplifies the input voltage twice, and is interposed between the comparison operation circuits CP1 to CP4.

  However, in the embodiment according to the present invention, the processing operations of the comparison operation circuits CP1 to CP4 are slightly different. That is, in the case of the conventional A / D converter described in §1, the processing operation of the comparison operation circuit CPk was as shown in FIG. 2, but in the case of the first embodiment according to the present invention, The processing operation of the comparison operation circuit CPk is as shown in FIG. The right half of FIG. 14 shows the specific processing contents of the comparison operation circuit CPk executed based on the comparison result. As shown in the figure, in the example shown in FIG. 14, when Vin (k) <R1, the output bit B = 0 is output (first function), and the difference Vout (k) = R1−Vin (k) A voltage is output (second function). On the other hand, when Vin (k) ≧ R1, the output bit B = 1 is output (first function), and a differential voltage Vout (k) = R2−Vin (k) is output (second function). ). In any case, the difference voltage corresponds to the difference voltage e shown in FIG. 13, and this point is different from the conventional example shown in FIG.

  FIG. 15 is a diagram illustrating a specific processing operation of such a comparison operation circuit CPk. In the figure, R0 is the ground potential, R2 is the voltage value of the full range Vmax, R1 is an intermediate potential, and the bar graph indicates the magnitude of the input voltage Vin (k). As described above, the processing operation of the comparison operation circuit CPk is divided into two types based on the magnitude relationship between the input voltage Vin (k) and the reference voltage R1.

  FIG. 15A shows the processing operation when Vin (k) <R1. In this case, the output bit B = 0 is output (“0” in the frame indicates the value of the output bit B), and a differential voltage Vout (k) = R1−Vin (k) is output. As illustrated, a difference voltage corresponding to a residual obtained by subtracting the input voltage Vin (k) from the reference voltage R1 exceeding the input voltage Vout (k) is output as Vout (k).

  On the other hand, FIG. 15B shows the processing operation when Vin (k) ≧ R1. In this case, the output bit B = 1 is output (“1” in the frame indicates the value of the output bit B), and a differential voltage Vout (k) = R2−Vin (k) is output. As illustrated, a difference voltage corresponding to a residual obtained by subtracting the input voltage Vin (k) from the reference voltage R2 exceeding the input voltage Vout (k) is output as Vout (k).

  Next, a specific processing operation in which four sets of comparison operation circuits included in the A / D converter according to the first embodiment of the present invention are linked will be described with reference to FIG. CP1 to CP4 shown in FIG. 16 correspond to the comparison operation circuits CP1 to CP4 shown in FIG. 1, and specific processing operations in the respective comparison operation circuits are shown. Here, as in the conventional example described in §1, the following explanation will be made assuming specific voltage values (anonymous number) of ground potential R0 = 0, full range R2 = 100, and reference voltage R1 = 50. To.

  Now, it is assumed that a signal having a voltage corresponding to the voltage value “66” is given to the A / D converter as an analog signal to be converted. In this case, the input voltage supplied to the first-stage comparison operation circuit CP1 is Vin (1) = 66. Since the reference voltage R1 = 50, the comparison operation circuit CP1 executes the “processing operation in the case of Vin (k) ≧ R1” shown in FIG. 14, the output bit B1 = 1 is output, and Vout Based on the arithmetic expression (1) = R2−Vin (1), a differential voltage e of e = 100−66 = 34 is output as the output voltage Vout (1). The difference voltage e is amplified twice by the amplifier circuit A1, and is supplied as the input voltage Vin (2) to the second comparison operation circuit CP2. In the example shown in the figure, since e = 34, 2 · e = 68 is given to the second-stage comparison operation circuit CP2 (the one-dot chain line in FIG. Indicating that it will be sent).

  Thus, the input voltage applied to the second-stage comparison operation circuit CP2 is Vin (2) = 68. Since the reference voltage R1 = 50, the comparison operation circuit CP2 executes the “processing operation in the case of Vin (k) ≧ R1” shown in FIG. 14, the output bit B1 = 1 is output, and Vout Based on the equation (2) = R2−Vin (2), a differential voltage e of e = 100−68 = 32 is output as the output voltage Vout (2). The difference voltage e is amplified twice by the amplifier circuit A2, and is supplied as the input voltage Vin (3) to the third-stage comparison operation circuit CP3. In the illustrated example, since e = 32, 2 · e = 64 is given to the third-stage comparison operation circuit CP3.

  Subsequently, when the input voltage Vin (3) = 64 is applied to the third-stage comparison operation circuit CP3, the reference voltage R1 = 50. Therefore, in the comparison operation circuit CP3, “Vin (k ) ≧ R1 ”, the output bit B1 = 1 is output, and e = 100−64 = based on the arithmetic expression Vout (3) = R2−Vin (3). A difference voltage e of 36 is output as the output voltage Vout (3). The difference voltage e is amplified twice by the amplifier circuit A3, and is supplied as the input voltage Vin (4) to the fourth comparison operation circuit CP4. In the example shown in the figure, since e = 36, 2 · e = 72 is given to the fourth-stage comparison operation circuit CP4.

  Thus, when the input voltage Vin (4) = 72 is applied to the fourth-stage comparison calculation circuit CP4, the reference voltage R1 = 50. Therefore, the comparison calculation circuit CP4 displays “Vin (k)” shown in FIG. The processing operation when ≧ R1 ”is executed, the output bit B1 = 1 is output, and e = 100−72 = 28 based on the arithmetic expression Vout (4) = R2−Vin (4). The differential voltage e is output as the output voltage Vout (4). In the example shown here, the fourth-stage comparison operation circuit CP4 is the final stage. However, when the fifth-stage comparison operation circuit continues, this difference voltage e is amplified twice by the amplification circuit. And supplied to the fifth-stage comparison operation circuit.

  Thus, as a digital output from the A / D converter, a bit string “1111” in which output bits B1, B2, B3, and B4 are arranged in this order is obtained. If a process of performing logic inversion is performed on the bit outputs from the even-numbered comparison operation circuits CP2 and CP4, the bit string “1010” can be finally obtained. This is a digital value corresponding to the analog voltage value “66” when the full range R2 = 100, and matches the digital value obtained by the conventional A / D converter shown in FIG.

<<< §6. Second embodiment of A / D converter according to the present invention >>>
In §2, the configuration and operation of a conventional general A / D converter that outputs a comparison result in units of 2 bits from one comparison operation circuit has been described with reference to FIG. Here, an embodiment in which the present invention is applied to an A / D converter having the configuration shown in FIG. 5 will be described as a second embodiment.

  The basic configuration of the second embodiment described here is almost the same as the basic configuration of the conventional A / D converter shown in FIG. That is, also in the embodiment according to the present invention, the comparison operation circuits CP1 to CP4 are comparison operation circuits each having the same configuration, and the magnitude relation between the input voltage Vin and the reference voltage R is compared, and the comparison result is obtained. Based on this, it has a function of outputting 2 bits and outputting a difference between both voltages as an output voltage Vout. Each of the amplifier circuits A1 to A3 is an amplifier circuit that amplifies the input voltage four times, and is interposed between the comparison operation circuits CP1 to CP4.

  However, in the embodiment according to the present invention, the processing operations of the comparison operation circuits CP1 to CP4 are slightly different. That is, in the case of the conventional A / D converter described in §1, the processing operation of the comparison operation circuit CPk is as shown in FIG. 6, but in the case of the second embodiment according to the present invention, The processing operation of the comparison operation circuit CPk is as shown in FIG. In the conventional example shown in FIG. 6, four voltages R0, R1, R2, and R3 are used as the reference voltage R. In the embodiment shown in FIG. The voltages R1, R2, R3, and R4 are used. Here, the voltage R4 is a voltage corresponding to the full range Vmax. As already mentioned, the reference voltage R is given by a signal whose voltage increases stepwise with time. The step-like signal shown in the block of the comparison operation circuit CPk in FIG. 17 shows the waveform of such a reference signal. Therefore, the input voltage Vin (k) applied to the comparison operation circuit CPk is first compared with the reference voltage R1, subsequently compared with the reference voltage R2, then compared with the reference voltage R3, and finally with the reference voltage R4. Will be compared. However, if there is a change in the magnitude relationship in comparison with any of the reference voltages, the subsequent comparison operation becomes unnecessary.

  (1) to (4) shown in the lower half of FIG. 17 show the specific processing contents of the comparison operation circuit CPk executed based on each comparison result. As described above, first, comparison with the reference voltage R1 is performed as the first comparison processing. As a result, as shown in FIG. 17A, when Vin (k) <R1, the output bits BL = 0 and BR = 0 are output (first function), and Vout (k) = R1. A differential voltage of −Vin (k) is output (second function). In this case, the magnitude relationship has changed in comparison with the reference voltage R1 (the comparison with the reference voltage R0 is not performed, but the initial magnitude relationship is “input voltage> reference voltage”). , Change determination is performed). In this case, the comparison operation with the reference voltages R2, R3, and R4 is not necessary thereafter.

  On the other hand, when the comparison with the reference voltage R1 does not change the magnitude relationship (that is, when R1 ≦ Vin (k)), the comparison with the reference voltage R2 is performed as the second comparison process. . As a result, as shown in FIG. 17B, when R1 ≦ Vin (k) <R2, output bits BL = 0 and BR = 1 are output (first function), and Vout (k) = R2−Vin (k) is output (second function). In this case, the magnitude relationship changes in comparison with the reference voltage R2. Therefore, thereafter, the comparison operation with the reference voltages R3 and R4 is unnecessary.

  If no change in the magnitude relationship has occurred by comparison with the reference voltage R2 (that is, when R2 ≦ Vin (k)), comparison with the reference voltage R3 is performed as a third comparison process. As a result, as shown in FIG. 17 (3), when R2 ≦ Vin (k) <R3, output bits BL = 1 and BR = 0 are output (first function), and Vout (k) = R3-Vin (k) is output (second function). In this case, the comparison with the reference voltage R3 has caused a change in the magnitude relationship, so that the comparison operation with the reference voltage R4 is unnecessary.

  Finally, when no change in the magnitude relationship occurs even by comparison with the reference voltage R3, that is, when R3 ≦ Vin (k), the input voltage Vin (k) is equal to or higher than the voltage R3 and the full range Vmax (= R4) The voltage is within the following range. Therefore, a comparison with the reference voltage R4 is performed as a fourth comparison process. In the fourth comparison process, it is always determined that the magnitude relationship has changed. This is because the reference voltage R4 = full range Vmax, so that the input voltage Vin (k) ≦ R4 is always satisfied (when Vin (k) = R4, “input voltage> reference voltage” to “input voltage = reference”). To “Voltage”). Therefore, in this case, as shown in FIG. 17 (4), output bits BL = 1 and BR = 1 are output (first function), and a differential voltage Vout (k) = R4-Vin (k) is output. (Second function).

  Next, a specific processing operation in which four sets of comparison operation circuits included in the A / D converter according to the second embodiment are linked will be described with reference to FIG. CP1 to CP4 shown in FIG. 18 correspond to the comparison operation circuits CP1 to CP4 shown in FIG. 5, and specific processing operations in the respective comparison operation circuits are shown. In the figure, R0 is a ground potential, R4 is a voltage value of the full range Vmax, R1 to R3 are potentials at intermediate positions obtained by dividing R0 to R4 into four equal parts, and the bar graph indicates the magnitude of the input voltage Vin (k). It shows. Again, for the sake of convenience, the following description assumes a specific voltage value (anonymous number) of ground potential R0 = 0, full range R4 = 100, reference voltage R1 = 25, reference voltage R2 = 50, and reference voltage R3 = 75. To do.

  Now, it is assumed that a signal having a voltage corresponding to the voltage value “66” is given to the A / D converter as an analog signal to be converted. In this case, the input voltage supplied to the first-stage comparison operation circuit CP1 is Vin (1) = 66. For this reason, in the comparison with the reference voltages R1 and R2, the magnitude relationship of “input voltage> reference voltage” is maintained, but by the comparison with the reference voltage R3, the change in magnitude relationship of “input voltage <reference voltage” is maintained. Will occur. Therefore, in the comparison operation circuit CP1, the processing operation shown in FIG. 17 (3) is executed, B1 = 1 and B2 = 0 are output, and the difference voltage Vout (1) = R3−Vin (1) Is output. Specifically, a differential voltage e of e = 75−66 = 9 is output as the output voltage Vout (1). The difference voltage e is amplified four times by the amplifier circuit A1, and is supplied as the input voltage Vin (2) to the second comparison operation circuit CP2. In the example shown in the figure, since e = 9, 4 · e = 36 is given to the second-stage comparison operation circuit CP2 (the dashed-dotted line in FIG. Indicating that it will be sent).

  Thus, the input voltage applied to the second-stage comparison operation circuit CP2 is Vin (2) = 36. Therefore, in the comparison with the reference voltage R1, the magnitude relationship of “input voltage> reference voltage” is maintained, but the magnitude relationship of “input voltage <reference voltage” is changed by the comparison with the reference voltage R2. It will be. Therefore, in the comparison operation circuit CP2, the processing operation shown in FIG. 17 (2) is executed, B3 = 0 and B4 = 1 are output, and the difference voltage Vout (2) = R2−Vin (2). Is output. Specifically, a differential voltage e of e = 50−36 = 14 is output as the output voltage Vout (2). The difference voltage e is amplified four times by the amplifier circuit A2, and is supplied as the input voltage Vin (3) to the third-stage comparison operation circuit CP3. In the example shown in the figure, since e = 14, 4 · e = 56 is supplied to the third-stage comparison operation circuit CP3.

  Thus, the input voltage Vin (3) = 56 is applied to the third-stage comparison operation circuit CP3. For this reason, in the comparison with the reference voltages R1 and R2, the magnitude relationship of “input voltage> reference voltage” is maintained, but by the comparison with the reference voltage R3, the change in magnitude relationship of “input voltage <reference voltage” is maintained. Will occur. Therefore, in the comparison operation circuit CP3, the processing operation shown in FIG. 7 (3) is executed, B5 = 1 and B6 = 0 are output, and the difference voltage Vout (3) = R3−Vin (3). Is output. Specifically, a differential voltage e of e = 75−56 = 19 is output as the output voltage Vout (3). This difference voltage e is amplified four times by the amplifier circuit A3, and is supplied as the input voltage Vin (4) to the fourth comparison operation circuit CP4. In the illustrated example, since e = 19, 4 · e = 76 is supplied to the fourth-stage comparison operation circuit CP4.

  When an input voltage of Vin (4) = 76 is given to the final fourth comparison operation circuit CP4, the comparison of the reference voltages R1, R2, and R3 has a relationship of “input voltage> reference voltage”. However, the comparison with the reference voltage R4 causes a change in the magnitude relationship of “input voltage <reference voltage”. Therefore, in the comparison operation circuit CP4, the processing operation shown in FIG. 7 (4) is executed, B7 = 1 and B8 = 1 are output, and the difference voltage Vout (4) = R4−Vin (4). Is output. Specifically, a differential voltage e of e = 100−76 = 24 is output as the output voltage Vout (4). In the example shown here, the fourth-stage comparison operation circuit CP4 is the final stage. However, when the fifth-stage comparison operation circuit continues, this difference voltage e is amplified four times by the amplifier circuit. In this case, 4 · e = 96 is supplied to the fifth-stage comparison operation circuit.

  Thus, as a digital output from each of the comparison operation circuits CP1 to CP4, a bit string “10011011” in which the output bits B1 to B8 are arranged in this order is obtained. If the process of performing logic inversion is performed on the bit outputs from the comparison operation circuits CP2 and CP4, the bit string “10101000” can be finally obtained. This is a digital value corresponding to the analog voltage value “66” when the full range R4 = 100, and coincides with the digital value obtained by the conventional A / D converter shown in FIG.

<<< §7. Other Examples >>>
The embodiments described in §5 and §6 have a configuration in which four sets of comparison operation circuits CP1 to CP4 which are physically separate and independent are cascade-connected. Of course, the present invention is as shown in FIG. The present invention can also be applied to a cyclic A / D converter. FIG. 19 shows an embodiment in which the present invention is applied to such a cyclic A / D converter. The only difference between the cyclic A / D converter shown in FIG. 9 and the cyclic A / D converter shown in FIG. 19 is the processing operation of the comparison operation circuit CPk. That is, according to the algorithm shown in FIG. 6, the former outputs 2-bit data BL and BR based on the result of the comparison processing between the input voltage Vin (k) and each of the reference voltages R0, R1, R2, and R3, and the difference. While the voltage (corresponding to the differential voltage d shown in FIG. 4) is output as the output voltage Vout (k), the latter follows the algorithm shown in FIG. 17 and the input voltage Vin (k) and each reference voltage R1, R2, Based on the result of the comparison processing with R3 and R4, 2-bit data BL and BR are output, and a differential voltage (corresponding to the differential voltage e shown in FIG. 18) is output as the output voltage Vout (k).

  Also in the cyclic A / D converter shown in FIG. 19, the amplifier circuit Ak performs the amplification process four times, and the output voltage is given to the selector S in exactly the same way as the A / D converter of FIG. It is. In addition, when the selector S initially receives an analog signal to be converted, the selector S selects the analog signal, applies the analog signal to the comparison operation circuit CPk, and after the cyclic signal is supplied from the amplifier circuit Ak, The point that the signal is selected and given to the comparison operation circuit CPk is exactly the same as the A / D converter of FIG. However, the 2-bit outputs BL and BR output from the comparison operation circuit CPk may be left as they are in the case of the odd-numbered bit output, but in the case of the even-numbered bit output, it is necessary to perform logic inversion. It is necessary to provide bit inversion means for executing such processing.

  FIG. 20 is a block diagram showing an example in which the cyclic A / D converter shown in FIG. 19 is extended to an A / D converter that outputs a comparison result in units of 3 bits. The comparison operation circuit CPk has a function of outputting the comparison result as data B1, B2, B3 in units of 3 bits at every cycle. Therefore, eight voltages R1 to R8 are used as the reference voltage R. The step-like signal shown in the block of the comparison operation circuit CPk in FIG. 20 shows the waveform of such a reference signal. Here, when R0 is a ground potential and R8 is a voltage corresponding to the full range Vmax, R1 to R7 are intermediate potentials obtained by dividing the potential difference of R0 to R8 into eight equal parts. Further, the amplifier circuit Ak executes a process of amplifying the output voltage Vout (k) from the comparison operation circuit CPk by 8 times. Also in this case, the 3-bit outputs B1, B2, and B3 output from the comparison operation circuit CPk may be left as they are in the case of odd-numbered bit output, but in the case of even-numbered bit output, it is necessary to perform logic inversion. Therefore, it is necessary to separately provide bit inversion means for executing such processing.

FIG. 21 shows an example in which the cyclic A / D converter shown in FIGS. 19 and 20 is extended to an A / D converter that outputs a comparison result in units of n bits expressed using an arbitrary number n. FIG. The comparison operation circuit CPk has a function of outputting the comparison result as data B1, B2,. For this purpose, 2 ⁿ kinds of voltages R (1) to R (2 ⁿ ) are used as the reference voltage R. Here, when R (0) is a ground potential and R (2 ⁿ ) is a voltage corresponding to the full range Vmax, R (1) to R (2 ⁿ −1) are R (0) to R (2 ⁿ ) Are divided into 2 ⁿ equal parts (here, for convenience of reference, the i-th reference voltage is indicated by parenthesized reference R (i), but R (0), R (1 ), R (2),... Are the same as the reference voltages R0, R1, R2,. Note that the comparison operation circuit CPk is configured to operate normally when an input voltage Vin (k) of a full-range voltage range 0 to Vmax is applied, so that the voltage value of the analog signal to be converted is The maximum voltage Vmax needs to be set. On the other hand, the amplifier circuit Ak executes a process of amplifying the output voltage Vout (k) output as a difference voltage from the comparison operation circuit CPk by ²ⁿ times.

Also in the case of the A / D converter shown in FIG. 21, the n-bit outputs B1, B2,..., Bn output from the comparison operation circuit CPk may be left as they are in the case of odd-numbered bit output. In the case of even-numbered bit output, it is necessary to perform logic inversion, and therefore it is necessary to provide bit inversion means for performing such processing separately. Of course, it is necessary to provide a reference voltage generation circuit separately. The reference voltage generating circuit is obtained by ^{2 n} split the full range ⁽² n +1) voltage as R (0), R (1 ), R (2), ..., R a ^{(2 n)} Among them (where R (0) = 0, R (2 ⁿ ) = Vmax), ²ⁿ reference voltages R (1), R (2),..., R (2 ⁿ ) are determined in this order. A function is provided which is generated in a cycle and given to the comparison operation circuit CPk as a reference signal in which the voltage increases stepwise.

  Note that n is a parameter that determines the number of bits output from the comparison operation circuit CPk. Therefore, it is generally set to a natural number of 1 or more, but recently, 1.5 bits, 3.5 There has also been proposed a technique for handling output bits composed of bits and bits including decimal numbers such as 4.5 bits. The present invention is also applicable to such a technique, and in such a case, n is not limited to a natural number.

Upon receiving such a reference signal, the comparison operation circuit CPk performs a process of sequentially comparing the input voltage Vin (k) and the i-th reference voltage R (i) (i = 1, 2,..., ²ⁿ ). If the magnitude relationship between the input voltage and the reference voltage changes when the i-th reference voltage R (i) is given, the input voltage Vin (k) and the reference voltage R ( A difference voltage (absolute value) from i) is output as an output voltage Vout (k), and an n-bit bit string is output. Here, the n-bit bit string may correspond to the binary representation of the value (i−1).

  For example, as shown in FIG. 17, if the comparison operation circuit CPk outputs 2-bit data BL and BR, the magnitude relationship changes when compared with the first reference voltage R1 (FIG. 17 (1)). )), A bit string “00” corresponding to the binary representation of the value “1-1 = 0” is output, and the magnitude relationship changes when compared with the second reference voltage R2 (FIG. 17). In the case of (2), the bit string “01” corresponding to the binary representation of the value “2-1 = 1” is output, and the magnitude relationship changes when compared with the third reference voltage R3 ( In the case of FIG. 17 (3), the bit string “10” corresponding to the binary representation of the value “3-1 = 2” is output, and the magnitude relationship has changed when compared with the fourth reference voltage R4. In the case (in the case of FIG. 17 (4)), the bit string “4” corresponding to the binary representation of the value “4-1 = 3”. It may be output 1 ".

<<< §8. Specific configuration example of each part >>>
FIG. 22 is a block diagram showing a specific configuration example of the comparison operation circuit CPk included in the A / D converter according to the present invention, together with the reference voltage generation circuit 20 and the bit inversion means 30. In the case of the illustrated example, the comparison operation circuit CPk includes a difference circuit 10, a storage circuit 11, a sign determination circuit 12, and a control circuit 13. The reference voltage generation circuit 20 is a circuit for generating the reference voltage R described so far.

  The configuration of the comparison operation circuit CPk shown in FIG. 22 is substantially the same as that of the conventional device shown in FIG. That is, the difference circuit 10 is a circuit for obtaining a difference voltage between the input voltage Vin (k) and the reference voltage R, and the obtained difference voltage is given to the storage circuit 11 and the sign determination circuit 12. The memory circuit 11 temporarily holds this differential voltage. The sign determination circuit 12 determines the sign of the difference voltage (in other words, the magnitude relationship between the input voltage Vin (k) and the reference voltage R is determined).

  However, in the example shown in FIG. 22, the reference voltage R generated by the reference voltage generation circuit 20 is directly given to the difference circuit 10 without going through the control circuit 13. As described with reference to FIG. 13, in the case of the conventional apparatus, when the code change is determined at the timing t (i) in the code determination circuit 12, the reference is performed at the next timing t (i + 1). This is because the process of returning the voltage to R (i-1) needs to be performed, whereas in the case of the apparatus according to the present invention, such a process becomes unnecessary. However, in this example, the reference voltage R generated by the reference voltage generation circuit 20 is also supplied to the control circuit 13 in order to synchronize with the reference voltage.

  In this apparatus, the sign determination circuit 12 gives a signal indicating that to the storage circuit 11 and the control circuit 13 when the result of the code determination changes. When the memory circuit 11 receives a signal indicating that the determination result has changed, the memory circuit 11 outputs the difference voltage held at that time as the output voltage Vout (k). Specifically, in the example shown in FIG. 13, since the sign determination result changes at the time t (i), the memory circuit 11 stores the difference voltage e = R (i) held at this time. -Vin (k) is output as the output voltage Vout (k).

  On the other hand, the control circuit 13 that has received a signal indicating that the result of the sign determination has changed at the timing of time t (i) recognizes the value of i by referring to the reference voltage R supplied from the reference voltage generation circuit 20. can do. Therefore, bit strings B1, B2, B3,... Indicating data corresponding to the binary representation of the value (i-1) can be output.

  FIG. 22 shows only one-stage comparison operation circuit CPk, but actually, such comparison operation circuit CPk is cascade-connected via the amplifier circuit Ak. The bit inverting means 30 is provided only for the even-numbered comparison calculation circuit CPk among the comparison calculation circuits CPk connected in multiple stages. The bit string output from the odd number comparison operation circuit CPk may be output as it is without being logically inverted.

  That is, as a general theory, a comparison operation circuit of K sets (K is a natural number of 2 or more) and an amplification circuit of (K-1) sets are prepared, and the kth (k = 1 to K-1). The comparison operation circuit and the amplification circuit are alternately connected so that the difference voltage output from the comparison operation circuit is input to the (k + 1) th comparison operation circuit after being amplified by the kth amplification circuit. When the present invention is applied to an A / D converter, it is only necessary to provide a bit inversion means 30 for logically inverting the output bits from the even-numbered comparison operation circuit.

  FIG. 23 is a block diagram showing a basic configuration of an A / D converter that outputs a comparison result in units of 2 bits according to the present invention. The difference from the configuration of the conventional device shown in FIG. 5 is that each of the comparison operation circuits CP1 to CP4 constituting the device shown in FIG. 23 has a configuration as shown in FIG. R4 is given, and inverter circuits 31, 32, 33, and 34 are provided as the bit inversion means 30. The inverter circuits 31 and 32 are provided on the bit output line from the comparison operation circuit CP2 at the second stage, and perform the function of logically inverting the bits B3 and B4. The inverter circuits 33 and 34 are at the fourth stage. Are provided on the bit output line from the comparison operation circuit CP4, and function to logically invert the bits B7 and B8. Thus, as the bit inverting means 30, an inverter circuit provided on the bit output line from the even-numbered comparison operation circuit may be used.

  On the other hand, FIG. 24 is a block diagram showing a basic configuration when the present invention is applied to a cyclic A / D converter. The part of the comparison operation circuit CPk surrounded by the alternate long and short dash line in FIG. 24 has the same configuration as the comparison operation circuit CPk shown in FIG. However, the comparison operation circuit CPk shown in FIG. 22 is used in a multi-stage connection as in the example shown in FIG. 23, whereas the example shown in FIG. The component can serve as an A / D converter.

  The A / D converter shown in FIG. 24 includes a set of comparison operation circuits CPk and a set of amplification circuits Ak, and the difference voltage output as the output voltage Vout (k) from the comparison operation circuit CPk is obtained. After being amplified M times by the amplifier circuit Ak and then cycled so as to be input again to the same comparison operation circuit CPk, a cascade connection of a plurality of stages by one comparison operation circuit CPk itself is realized.

  The selector S provided in the previous stage of the comparison operation circuit CPk has a function of selectively outputting a signal given to the first input terminal and a signal given to the second input terminal. A signal line for supplying an analog signal (voltage V) to be converted is connected to the first input terminal of the selector S, and the amplified signal output from the amplifier circuit Ak is connected to the second input terminal. Is given to patrol. The input voltage Vin (k) is supplied to the comparison operation circuit CPk according to the signal selected by the selector S. As described above, the selector S selectively outputs the signal (analog signal to be converted) given to the first input terminal at the beginning when the analog signal to be converted is given, and cyclically outputs from the amplifier circuit Ak. After the received signal is given, the signal given to the second input terminal (the signal circulated from the amplifier circuit Ak) is selectively output.

  Further, as described above, the reference voltage generation circuit 20 generates a reference voltage that increases stepwise, and applies this to one input terminal of the difference circuit 10. The bit inverting means 30 performs logic inversion on the even-numbered bit output from the comparison operation circuit CPk. Such a bit inverting means 30 can be configured using, for example, an inverter circuit and a latch circuit.

<<< §9. Integration in solid-state imaging device >>>
FIG. 25 is a block diagram showing an application example in which the A / D converter according to the present invention is incorporated in a solid-state imaging device. A general solid-state imaging device includes an image sensor 100, a vertical shift register 110, a column current source 120, a CDS circuit 130, an output selection switch 140 for each column, a horizontal shift register 150, as illustrated. It has.

  In order to incorporate the A / D converter according to the present invention into such a general solid-state imaging device, a reference voltage generating circuit 160 is added, and, for example, a component (see FIG. 24) in the CDS circuit. The voltage generation circuit 20 may be incorporated for each column. The voltage V read for each column in the image sensor 100 is given as the voltage V shown on the left side of the drawing in the circuit of FIG. Further, the reference voltage generation circuit 20 in FIG. 24 plays the role of the reference voltage generation circuit 160 in the example shown in FIG. Thus, the digital output through the bit inversion means 30 in the circuit of FIG. 24 (the logical inversion of the even-numbered bit output) is converted into a digital output for each pixel through the output selection switch 140 shown in FIG. It will be taken out.

  FIG. 26 is a circuit diagram showing a specific circuit configuration example of the cyclic A / D converter (the selector S, the comparison operation circuit CPk, and the amplifier circuit Ak shown in FIG. 24) incorporated in the CDS circuit 130 shown in FIG. It is. In the embodiment shown here, the reference voltage generation circuit 160 shown in the lower part of the figure is provided outside the CDS circuit 130 (of course, it may be provided inside).

  The voltage V read from each pixel in the image sensor 100 is applied to the node P0, transmitted to the node P1 via the switch S1, and further transmitted to the node P2 via the buffer 131 (1x magnification). Is done. The node P2 and the node P3 are connected via the capacitive element C1. The negative input terminal of the OP amplifier 132 is connected to the node P3, and the first power supply voltage V1 is supplied to the positive input terminal. The output terminal of the OP amplifier 132 is connected to the node P4. Between the node P3 and the node P4, a capacitive element C2 and a switch S3 are connected in parallel with the OP amplifier 132.

  When the capacitance value of the capacitive element C1 is C1 and the capacitance value of the capacitive element C2 is C2, C1 = 4 · C2. This is because the amplification factor of the OP amplifier 132 is set to 4 times. Eventually, the circuit shown in FIG. 26 functions as the circuit shown in FIG.

  A node P5 is connected to the right side of the node P4 via the switch S4 and the capacitive element C3, and a node P6 is connected to the right side of the node P4 via the buffer 133 (magnification of 1). The node P5 is supplied with the second power supply voltage V2 via the switch S5. Nodes P1 and P6 are connected via a switch S2.

  Further, the reference voltage R generated by the reference voltage generation circuit 160 is applied to the node P1 through the capacitive element C4. Further, below the node P4, a node P7 is connected via an inverter 134, and further a latch circuit 135 is connected. The latch circuit 135 temporarily holds a 2-bit count value given from the outside in accordance with the change timing of the voltage (logic bit) that has passed through the inverter 134. The 2-bit data held in the latch circuit 135 is output to the outside as A / D conversion data via the switch S6.

  FIG. 27 is a timing chart for explaining the operation of the circuit shown in FIG. Here, t1 to t14 displayed in the left end column indicate predetermined operation timings executed in this order. The first half t1 to t7 are timings for performing CDS processing (sampling processing of the voltage read from the pixel) and the first A / D conversion processing, and the second half t8 to t14 are the second and subsequent times. This is the timing for performing the / D conversion process. On the other hand, S1 to S5 and R displayed in the upper column correspond to the switches S1 to S5 and the reference voltage R in the circuit of FIG. In each column of the timing chart, an ON / OFF switching state of each switch (“ON” is shown in bold type for easy understanding) and a reference voltage value (R0 to R4) are shown. Yes. Note that the switch S6 is simply a switch for outputting the digital data held in the latch circuit 135 to the outside, and therefore its switching state is not shown in the chart of FIG.

  First, in the first half operation, at the timing t1, the switch S1 is turned ON, and the voltage Vreset at the time of reset is supplied to the node P1 as the readout voltage V from the pixel. At this time, if the switch S3 is turned on and the nodes P3 and P4 are short-circuited, the negative feedback function of the OP amplifier 132 makes the voltage at the node P3 equal to the first power supply voltage V1. At this time, the switches S4 and S5 are ON, the switch S2 is OFF, and the reference voltage generation circuit 160 outputs the reference voltage R0.

  At subsequent timing t2, the voltage Vsignal of the pixel signal is applied to the node P1 as the readout voltage V from the pixel while the switch S1 is kept ON. At this time, when the switch S3 is turned OFF, the voltage of the node P4 becomes V1 + (Vreset−Vsignal) × 4 (as described above, C1 = 4 · C2, and the amplification factor of the OP amplifier 132 is quadrupled). Is set).

  At the next timing t3, the switch S1 is turned OFF, and the circuit in FIG. 26 is disconnected from the pixel. Then, starting from this timing t3, the reference voltage generation circuit 160 increases the reference voltage R stepwise. That is, the reference voltage R changes as R0, R1, R2, R3, and R4 at each timing t3, t4, t5, t6, and t7. On the other hand, the 2-bit count value given to the latch circuit 135 is changed to 00, 01, 10, and 11 at timings t4, t5, t6, and t7, respectively.

  The subsequent operation differs depending on the value of the voltage Vsignal of the read pixel signal, but here, as an example, the operation when R2 ≦ Vreset−Vsignal <R3 is shown. Now, paying attention to the magnitude relationship between the voltage of the node P4 and the power supply voltage V1, when R2 ≦ Vreset−Vsignal <R3, the magnitude relationship is reversed at the timing t6 so that the voltage of the node P4 <V1. . Therefore, since the digital value of the node P7 that has passed through the inverter 134 is also inverted, the switches S4 and S5 are switched OFF using this inversion. In the column of timing t6 in the chart of FIG. 27, a state in which such switching has been performed is shown. At the same time, the latch circuit 135 holds the 2-bit count value (“10” in this example) given at that time, and outputs it to the outside via the switch S6 at a predetermined timing. At this time, the voltage of the node P4 is V1 + ((Vreset−Vsignal) −R3) × 4, and the voltage of the node P5 is the second power supply voltage V2.

  At the subsequent timing t7, the reference voltage R changes to R4, but the state of each switch does not change. As described above, the chart in FIG. 27 shows the operation when R2 ≦ Vreset−Vsignal <R3 as an example, and thus the switches S4 and S5 are switched at the timing t6. Such switching is performed at any one of timings t4 to t7 according to the magnitude of Vsignal.

  The operation in the first half of the timing chart of FIG. 27 (reading of the voltage Vsignal and the first A / D conversion operation) has been described above. Subsequently, the operation in the second half (the second and subsequent A / D conversion operations). ).

  First, at timing t8, the switches S2, S3, S4 are turned on. Since the nodes P3 and P4 are short-circuited, the voltage of the node P3 becomes equal to the first power supply voltage V1 by the negative feedback function of the OP amplifier 132. Further, since the nodes P6 and P1 are short-circuited, the voltage at the node P5 = the voltage at the node P6 = the voltage at the node P1 = V2 − (((Vreset−Vsignal) −R3) × 4). At this time, the output of the reference voltage generation circuit 160 returns to the reference voltage R0.

  At subsequent timing t9, the switch S3 is turned off and the switch S5 is turned on. As a result, the voltage at the node P5 becomes the second power supply voltage V2, so the voltage at the node P1 also becomes V2. Therefore, the voltage of the node P4 is V1 + ((R3- (Vreset−Vsignal) × 4) × 4.

  Hereinafter, the operation at timings t10 to t14 (second A / D conversion operation) is the same as the above-described operation at timings t3 to t7 (first A / D conversion operation). In FIG. 27, as an example, an operation in the case of R2 ≦ (R3− (Vreset−Vsignal) × 4) <R3 is shown, and the switches S4 and S5 are switched OFF at the timing t13. . As a result, the 2-bit count value “10” is held in the latch circuit 135 and is output to the outside via the switch S6 at a predetermined timing.

  Thus, when the second A / D conversion operation is completed, the operation at timings t8 to t14 is performed again, and the third A / D conversion operation is executed. Similarly, by repeating the operations at timings t8 to t14, the fourth, fifth,..., A / D conversion operations can be executed, and 2-bit digital values can be output. Of course, bit inversion processing is performed by the bit inversion means 30 on the 2-bit digital value output in the even-numbered A / D conversion operation.

It is a block diagram which shows the basic composition of the A / D converter of the format which outputs the comparison result by the conventional general 1 bit unit. It is a figure which shows the general processing operation | movement of the comparison arithmetic circuit contained in the A / D converter shown in FIG. FIG. 3 is a diagram illustrating a specific processing operation of the comparison operation circuit illustrated in FIG. 2. FIG. 2 is a diagram illustrating a specific processing operation in which four sets of comparison operation circuits included in the A / D converter illustrated in FIG. 1 are linked. It is a block diagram which shows the basic composition of the A / D converter of the format which outputs the comparison result by the conventional general 2-bit unit. FIG. 6 is a diagram showing a general processing operation of a comparison operation circuit included in the A / D converter shown in FIG. 5. FIG. 6 is a diagram illustrating a specific processing operation of a comparison operation circuit included in the A / D converter illustrated in FIG. 5. FIG. 6 is a diagram illustrating a specific processing operation in which four sets of comparison operation circuits included in the A / D converter illustrated in FIG. 5 are linked. It is a block diagram which shows the basic composition of the cyclic | annular A / D converter of the format which outputs the comparison result by the conventional general 2-bit unit. It is a block diagram which shows the basic composition of the cyclic | annular A / D converter of the format which outputs a comparison result in the conventional general 3 bit unit. It is a block diagram which shows the basic composition of the cyclic | annular A / D converter of the format which outputs the comparison result by the conventional general n bit unit. It is a block diagram which shows the specific structural example of the comparison arithmetic circuit contained in the conventional general A / D converter. It is a time chart which compares the operation principle of the conventional general A / D converter, and the operation principle of the A / D converter which concerns on this invention. It is a figure which shows the general processing operation | movement of the comparison arithmetic circuit contained in the A / D converter of the format which outputs a comparison result per 1 bit unit based on this invention. FIG. 15 is a diagram illustrating a specific processing operation of the comparison operation circuit illustrated in FIG. 14. It is a figure which illustrates the concrete processing operation | movement which cooperated 4 sets of comparison arithmetic circuits contained in the A / D converter of the format which outputs a comparison result per bit which concerns on this invention. It is a figure which shows the general processing operation | movement of the comparison arithmetic circuit contained in the A / D converter of the format which outputs a comparison result per 2 bits based on this invention. It is a figure which illustrates the concrete processing operation | movement which cooperated 4 sets of comparison arithmetic circuits contained in the A / D converter of the format which outputs a comparison result per 2 bits based on this invention. It is a block diagram which shows the basic composition of the cyclic | annular A / D converter of the format which outputs a comparison result per 2 bits based on this invention. It is a block diagram which shows the basic composition of the cyclic | annular A / D converter of the format which outputs a comparison result per 3 bits based on this invention. It is a block diagram which shows the basic composition of the cyclic | annular A / D converter of the format which outputs a comparison result per n bit based on this invention. It is a block diagram which shows the specific structural example of the comparison arithmetic circuit contained in the A / D converter which concerns on this invention. It is a block diagram which shows the basic composition of the A / D converter of the format which outputs a comparison result per 2 bits based on this invention. It is a block diagram which shows the basic composition of the cyclic | annular A / D converter which concerns on this invention. It is a block diagram which shows the usage example which incorporated the A / D converter which concerns on this invention in the solid-state imaging device. It is a circuit diagram which shows the specific circuit structural example of the cyclic | annular A / D converter which concerns on this invention. 27 is a timing chart for explaining the operation of the circuit shown in FIG. 26.

Explanation of symbols

10: difference circuit 11: storage circuit 12: sign determination circuit 13: control circuit 20: reference voltage generation circuit 30: bit inversion means 31-34: inverter circuit 100: image sensor 110: vertical shift register 120: column current source 130: CDS circuit 131 including A / D converter: buffer 132: OP amplifier 133: buffer 134: inverter 135: latch circuit 140: switch 150: horizontal shift register 160: reference voltage generation circuits A, A1 to A3, Ak: amplification Circuits B, B1 to B8: Output bit BL: Left output bit BR: Right output bit C1 to C4: Capacitance elements CP1 to CP4, CPk: Comparison operation circuit d: Difference voltage e: Difference voltages P0 to P7: Nodes R, R0 -R8, R (i): Reference voltage S: Selectors S1-S6: Switches t, t (i): Times t1-t15: Imming V: Analog signal voltages V1 and V2 to be converted: power supply voltages Vin, Vin (1) to Vin (4), Vin (k): input voltages Vout, Vout (1) to Vout (4), Vout ( k): Output voltage

Claims (7)

A comparison operation circuit that compares the magnitude relationship between the input voltage and a predetermined reference voltage, outputs a bit indicating a comparison result, and outputs a difference voltage between the input voltage and the reference voltage;
An amplifier circuit for amplifying the differential voltage output by the comparison operation circuit;
With
The comparison operation circuit has a plurality of stages in a state where the amplification circuit is interposed so that the differential voltage output from the comparison operation circuit of the previous stage is amplified by the amplification circuit and then input to the comparison operation circuit of the subsequent stage. Cascaded,
When an analog signal to be converted is supplied to the first-stage comparison operation circuit, an A / D converter that obtains converted digital data as a bit output string from each comparison operation circuit,
The comparison operation circuit outputs a difference voltage related to the reference voltage that was given when the magnitude relationship between the input voltage and the reference voltage changed,
An A / D converter, further comprising bit inversion means for performing logic inversion on a bit output from the even-numbered comparison operation circuit. The A / D converter according to claim 1,
By gradually increasing the voltage, a plurality of reference voltages are generated in order, and a reference voltage generation circuit that gives this to the comparison operation circuit at a predetermined timing is provided.
An A / D converter, wherein the comparison operation circuit recognizes a timing at which the magnitude relationship between the input voltage and the reference voltage has changed, and outputs a specific bit associated with the change timing. The A / D converter according to claim 2,
A comparison operation circuit obtains a difference voltage between an input voltage and a reference voltage, a storage circuit that temporarily holds the difference voltage, a sign determination circuit that determines a sign of the difference voltage, and the sign determination circuit And a control circuit that outputs a specific bit based on the timing at which the determination result of the signal changes, and the storage circuit outputs a difference voltage held when the determination result of the sign determination circuit changes An A / D converter characterized by the above. The A / D converter according to claim 2 or 3,
The comparison operation circuit is configured to be provided with an input voltage from 0 to Vmax in the full range of voltage width,
A reference voltage generation circuit divides the full range by 2 ⁿ to obtain (2 ⁿ +1) different voltages R (0), R (1), R (2),..., R (2 ⁿ ). Among them (where R (0) = 0, R (2 ⁿ ) = Vmax), ²ⁿ reference voltages R (1), R (2),..., R (2 ⁿ ) are generated in this order. Let
When the comparison operation circuit changes in magnitude when comparing the input voltage with the i-th reference voltage R (i) (i = 1, 2,..., 2 ⁿ ), the input voltage and the Outputs a difference voltage from the i-th reference voltage R (i), and outputs an n-bit bit string corresponding to a binary representation of the value (i−1),
An A / D converter, wherein the amplifier circuit amplifies the difference voltage by ²ⁿ times. The A / D converter in any one of Claims 1-4 WHEREIN:
K difference (K is a natural number of 2 or more) comparison operation circuits and (K-1) amplification circuit, and the difference output from the kth (k = 1 to K-1) comparison operation circuit The comparison operation circuit and the amplification circuit are alternately connected so that the voltage is amplified by the kth amplification circuit and then input to the (k + 1) th comparison operation circuit.
An A / D converter, wherein the bit inversion means is constituted by an inverter circuit provided on a bit output line from the even-numbered comparison operation circuit. The A / D converter in any one of Claims 1-4 WHEREIN:
A set of comparison operation circuits and a set of amplification circuits, so that the differential voltage output from the comparison operation circuit is amplified by the amplification circuit and then input to the comparison operation circuit again. By doing so, a cascade connection of a plurality of stages by the comparison operation circuit itself is realized,
An A / D converter, wherein the bit inversion means performs logic inversion on the even-numbered bit output from the comparison operation circuit. The A / D converter according to claim 6, wherein
A selector that selectively outputs a signal applied to the first input terminal and a signal applied to the second input terminal; and an analog signal to be converted is input to the first input terminal of the selector. The signal line to be supplied is connected, the output terminal of the selector is connected to the input terminal for the input voltage of the comparison arithmetic circuit, and the output terminal for the differential voltage of the comparison arithmetic circuit is connected to the input terminal of the amplifier circuit. The output terminal of the amplifier circuit is connected to the second input terminal of the selector, and the selector selects the signal supplied to the first input terminal at the beginning when the analog signal to be converted is supplied. The A / D converter is characterized by selectively outputting the signal given to the second input terminal after the signal outputted from the amplifying circuit is given and the signal given to the second input terminal is selectively outputted.

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