JP2009176987A - Semiconductor apparatus and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To standardize a lead frame for a semiconductor apparatus having a single package wherein a plurality of semiconductor chips are mounted. <P>SOLUTION: The semiconductor apparatus includes: a microcomputer chip 2 (first semiconductor chip) having a plurality of pads 2c (first terminals); a memory chip 3 (second semiconductor chip) having a plurality of pads 3c (second terminals) arranged beside the microcomputer chip 2; a die pad 5c (first chip mounting portion) smaller than the dimension of the microcomputer chip 2; a suspension lead 5d; a bar die pad 5e (second chip mounting portion) extending in the direction wherein the memory chip 3 is arranged from the suspension lead 5d; a plurality of wires 6a (first wires) that connect the pad 2c and pad 3c; and a sealing body 4. In the mounting surface of the microcomputer chip 2 and memory chip 3, the region wherein the pad 2c and the pad 3c are overlapped in the thickness direction are required to be arranged so as to avoid the die pad 5c and the bar die pad 5e respectively. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly, to a technique effective when applied to a semiconductor device in which a plurality of semiconductor chips are mounted on a lead frame and sealed together by a sealing body.

  For example, in Japanese Patent Application Laid-Open No. 2005-303222 (Patent Document 1), a microcomputer chip is mounted on a tab (first chip mounting portion) formed in a frame shape, and is arranged beside the first chip mounting portion. A lead frame type semiconductor device in which a memory chip is mounted on a rectangular tab (second chip mounting portion) is described.

Further, for example, in Japanese Unexamined Patent Application Publication No. 2007-311930 (Patent Document 2), in a lead frame type semiconductor device in which one semiconductor chip is mounted in a single package, the outer dimensions of the die pad are the same as the outer dimensions of the semiconductor chip. A technique for manufacturing semiconductor chips having different external dimensions with a common lead frame by making the size smaller than the above is described.
JP-A-2005-303222 JP 2007-31930 A

  As an example of a semiconductor device such as a SIP (System In Package) in which a plurality of semiconductor chips are mounted in a single package, a semiconductor chip having an arithmetic processing function (hereinafter also referred to as a microcomputer chip) and a semiconductor chip having a memory circuit ( Hereinafter, there is a lead frame type semiconductor device including a memory chip).

  In a lead frame type semiconductor device, in order to improve the reflow crack resistance of the package, a die pad on which the microcomputer chip is mounted is provided in order to increase the contact area between the mounting surface of the microcomputer chip having a relatively large outer dimension and the sealing body. A frame-shaped die pad (chip mounting portion) is used (for example, Patent Document 1).

  However, if the die pad has a frame shape, there arises a problem that a lead frame having a different die pad outer dimension must be prepared for each outer dimension of the microcomputer chip. In this case, a jig for wire bonding is required for each type of lead frame.

  The inventor of the present invention is a technology capable of standardizing a lead frame in a semiconductor device such as SIP in which a plurality of semiconductor chips are mounted in a single package, that is, using a common lead frame regardless of the external dimensions of the semiconductor chip. We examined possible technologies.

  The present inventor firstly replaced a frame-shaped die pad described in, for example, Patent Document 1 with a die pad having an outer dimension smaller than that of a semiconductor chip (microcomputer chip) described in, for example, Patent Document 2. Was examined.

  However, when the technique described in Patent Document 1 and the technique described in Patent Document 2 are simply combined, wire bonding that electrically connects terminals formed on the main surfaces of the plurality of semiconductor chips using wires. It has been found that there are the following problems in the process (hereinafter referred to as W / B).

  In the W / B process, a lead frame on which a plurality of semiconductor chips are mounted is placed on a W / B stage, and terminals formed on the main surfaces of the plurality of semiconductor chips or between each terminal and the lead frame are arranged. The inner lead is electrically connected through a wire.

  For example, in a SIP having a microcomputer chip and a memory chip, when the microcomputer chip is mounted on a die pad having an outer dimension smaller than the outer dimension of the microcomputer chip chip, the outer peripheral edge of the microcomputer chip is mounted in a state protruding beyond the die pad. The For this reason, the terminal of the microcomputer chip formed along the outer periphery of the microcomputer chip is disposed at a position protruding from the die pad.

  When W / B is performed on a terminal placed at a position protruding from the die pad, the bonding position may be shifted because the microcomputer chip serving as a base becomes unstable. Further, when an excessive wire is cut, if an excessive external force is applied to the inside of the microcomputer chip through the terminals, the elements inside the microcomputer chip may be destroyed.

  If the W / B stage is processed so that the area protruding from the die pad of the microcomputer chip is directly supported by the W / B stage, the stability of the microcomputer chip that is the foundation during W / B can be improved. However, since the entire mounting surface of the memory chip is bonded to the die pad for the memory chip, the region where the terminals of the memory chip are arranged is supported by the die pad.

  Thus, when the terminals of one semiconductor chip (microcomputer chip) are supported by the W / B stage and the terminals of the other semiconductor chip (memory chip) are supported by the die pad, they are connected by W / B. There are two reference surfaces (surfaces supporting the lower side of the pad) at the time of / B. For this reason, a bonding failure may occur or an element inside the microcomputer chip may be destroyed.

  The present invention has been made in view of the above problems, and an object thereof is to provide a technique capable of standardizing a lead frame in a semiconductor device in which a plurality of semiconductor chips are mounted in a single package. is there.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, a semiconductor device according to an embodiment of the present invention is a semiconductor device having a plurality of semiconductor chips, the first main surface on which a first semiconductor element and a plurality of first terminals are formed, and the first A first semiconductor chip having a first back surface opposite to the main surface; a second main surface on which a second semiconductor element and a plurality of second terminals are formed; and a second back surface opposite to the first main surface A second semiconductor chip arranged side by side with the first semiconductor chip, and an outer dimension smaller than an outer dimension of the first back surface of the first semiconductor chip, A first chip mounting portion that is bonded to the first back surface of the first semiconductor chip, and is arranged to extend radially outward from the first chip mounting portion to support the first chip mounting portion. A plurality of suspension leads and the suspension leads A second chip mounting portion that is integrally formed with the first chip mounting portion via a pin and is joined to the second back surface of the second semiconductor chip, and a periphery of the first and second semiconductor chips. A plurality of leads disposed on the first electrode, a plurality of conductive first wires that electrically connect the first terminal and the second terminal, respectively, and the first terminal and the leads electrically A plurality of conductive second wires to be connected, a plurality of conductive third wires to electrically connect the second terminal and the lead, respectively, the first and second semiconductor chips, A sealing body for resin-sealing the plurality of first, second, and third wires, and the plurality of the first and second back surfaces of the first and second semiconductor chips. Overlapping the first terminal and the plurality of second terminals in the thickness direction Band is to arranged so as to avoid the first and second chip mounting portion.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  That is, the lead frame can be standardized in a semiconductor device in which a plurality of semiconductor chips are mounted in a single package.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges. Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted as much as possible. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
<Structure of semiconductor device>
FIG. 1 is a plan view of an essential part showing an example of the internal structure of the semiconductor device according to the first embodiment. FIGS. 2, 3, and 4 are AA, BB, and C- It is principal part sectional drawing along C line. FIG. 5 is an enlarged plan view of a main part around the semiconductor chip of the semiconductor device shown in FIG.

  The semiconductor device according to the first embodiment shown in FIGS. 1 to 5 is a semiconductor package in which a plurality of semiconductor chips are embedded in a resin-made sealing body 4. Here, the semiconductor device protrudes from the sealing body 4. A QFP (Quad Flat Package) 1 in which a plurality of outer leads 5b as external terminals are formed in a gull wing shape will be described as an example.

  In FIG. 1, for the sake of clarity, the number of terminals (pads) and the number of leads of each semiconductor chip are reduced. For example, a multi-pin type having 200 or more leads (pins) is shown. You may apply to QFP.

  The QFP (semiconductor device) 1 has a microcomputer chip (first semiconductor chip) 2 in which a semiconductor element and a plurality of pads (first terminals) 2c are formed on a main surface (first main surface) 2a. The QFP 1 includes a semiconductor chip and a plurality of pads (second terminals) 3c formed on a main surface (second main surface) 3a, and a memory chip (second semiconductor) arranged next to the microcomputer chip 2. Chip) 3. Here, an arithmetic processing function is formed in the semiconductor element (first semiconductor element) of the microcomputer chip 2. A memory circuit is formed in the semiconductor element (second semiconductor element) of the memory chip 3.

  The microcomputer chip 2, which is the first semiconductor chip, is a semiconductor chip having an arithmetic processing function. For example, functions such as a microprocessor and a chip set are integrated on one chip.

  On the other hand, the memory chip 3 as the second semiconductor chip is a semiconductor chip having a memory circuit, and is, for example, a DRAM (Dynamic Random Access Memory). The memory chip 3 has a rectangular outer shape as shown in FIG. 1, for example, and is arranged so as to have a longitudinal direction along one side of the microcomputer chip 2.

  The memory chip 3 operates under the control of the microcomputer chip 2. Therefore, as shown in FIG. 1, the microcomputer chip 2 has the number of terminals (the number of pads) in the microcomputer chip 2 and the memory chip 3. There are many.

  Further, a part of the pad 2c of the microcomputer chip 2 and a part of the pad 3c of the memory chip 3 are electrically connected via a wire (first wire) 6a. Signal transmission takes place. For this reason, more pads 2c are arranged on the side of the microcomputer chip 2 facing the memory chip 3 than on the other side.

  Around the microcomputer chip 2 and the memory chip 3, there are a plurality of inner leads 5 a that are a plurality of leads, and a plurality of outer leads 5 b that are connected to the inner leads 5 a and project from the side surface 4 a of the sealing body 4. And are arranged. A part of the pad 2c of the microcomputer chip 2 and a part of the pad 3c of the memory chip 3 are electrically connected to the inner lead 5a via a wire (second wire) 6b and a wire (third wire) 6c, respectively. Has been. A plurality of outer leads 5b protruding from the side surface 4a of the sealing body 4 serve as external connection terminals of the QFP 1.

  The microcomputer chip 2, the memory chip 3, and the wires 6a, 6b, and 6c are resin-sealed in the QFP 1 by a sealing body 4. That is, the QFP 1 is a SIP type semiconductor device in which a plurality of semiconductor chips 2 and 3 are mounted in a single package.

  The microcomputer chip 2 is mounted on a die pad (first chip mounting portion) 5c having an outer dimension smaller than the outer dimension of the back surface (second back surface) 2b, which is the mounting surface of the microcomputer chip 2. The die pad 5c has, for example, a substantially circular outer shape as shown in FIG. 1, and a plurality (four in FIG. 1) are arranged so as to extend radially in the outer peripheral direction of the QFP 1 (direction away from the die pad 5c). It is supported by the suspension lead 5d. More specifically, the plurality of suspension leads 5d are integrally formed so that each end portion (one end portion) of the plurality of suspension leads 5d is connected to the die pad 5c. In addition, an end portion (other end portion) opposite to the end portion is located on the outer edge portion side of the sealing body 4.

  The die pad 5 c has an outer dimension smaller than the outer dimension of the back surface 2 b of the microcomputer chip 2. For this reason, the outer periphery of the microcomputer chip 2 protrudes from the outer shape of the die pad 5c. For this reason, the area facing the die pad 5c on the back surface 2b of the microcomputer chip 2 is bonded to the die pad 5c via an adhesive such as Ag paste, for example. It is in close contact with the resin.

  By making the outer dimensions of the die pad 5c smaller than the outer dimensions of the back surface 2b of the microcomputer chip 2, the area where the back surface 2b of the microcomputer chip 2 and the resin of the sealing body 4 are in close contact with each other can be increased. Generation of reflow cracks can be prevented.

  In the first embodiment, as a means for increasing the contact area between the back surface 2b of the microcomputer chip 2 and the resin of the sealing body 4, the external dimensions of the back surface 2b of the microcomputer chip 2 instead of the frame-shaped die pad. A die pad 5c smaller than that is employed. Therefore, for example, even when the microcomputer chip 2 having an outer dimension smaller than that of the microcomputer chip 2 shown in FIGS. 1 and 5 is mounted, it can be mounted without changing the outer dimension of the die pad 5c. That is, since the microcomputer chip 2 having different external dimensions can be manufactured with a common lead frame, the lead frame can be standardized.

  In the first embodiment, since the outer dimensions of the die pad 5c are made smaller than the outer dimensions of the back surface 2b of the microcomputer chip 2, the pads 2c arranged on the outer peripheral side of the main surface 2a of the microcomputer chip 2 are the die pads 5c. It is arranged at the position that protrudes. Therefore, as shown in FIG. 5, the area | region which overlaps with the pad 2c of the microcomputer chip 2 in the thickness direction among the back surfaces 2b of the microcomputer chip 2 can be arrange | positioned avoiding the die pad 5c.

  In the first embodiment, the method of mounting the microcomputer chip 2 on the die pad 5c is not limited to the bonding with Ag paste, and the microcomputer chip 2 is attached to the die pad via a DAF (Die Attach Film) having an adhesive layer. You may mount on 5c. In this case, since the DAF having the adhesive layer is disposed on the back surface 2b of the microcomputer chip 2, the adhesive strength is improved when the resin is in contact with the DAF as compared with the case where the resin is in contact with the back surface 2b of the microcomputer chip 2. can do. Thereby, generation | occurrence | production of the reflow crack in QFP1 can further be prevented.

  On the other hand, the memory chip 3 is mounted on a bar die pad (second chip mounting portion) 5e disposed beside the die pad 5c. The bar die pad 5e is, for example, two elongated bar-shaped plates as shown in FIGS. 1 and 5, and is arranged so that the direction from the suspension lead 5d toward the memory chip 3 is the longitudinal direction. The bar die pad 5e is formed integrally with the die pad 5c via the suspension lead 5d. The bar die pad 5e has one end connected to the suspension lead 5d, and the other end connected to a bar support member 5f disposed outside the bar die pad 5e. Here, in the first embodiment, two bar die pads 5e are formed, and these two bar die pads 5e are respectively connected to two hanging leads 5d adjacent to each other among the four hanging leads 5d. It is connected.

  The bar support member 5f is formed integrally with the bar die pad 5e and the suspension lead 5d, and is formed so as to connect the suspension leads 5d to which the bar die pad 5e is connected among the plurality of suspension leads 5d.

  By providing the bar support member 5f and connecting it to one end of the bar die pad 5e, the support strength necessary for mounting the memory chip 3 can be sufficiently provided even if the bar die pad 5e has an elongated outer shape. That is, by providing the bar support member 5f, the bar die pad 5e can have an elongated outer shape.

  Further, by forming the bar die pad 5e into an elongated shape, as shown in FIG. 5, an area overlapping with the pad 3c of the memory chip 3 in the thickness direction in the back surface (second back surface) 3b that is the mounting surface of the memory chip 3 Can be arranged avoiding the bar die pad 5e. As a result, the QFP 1 according to the first embodiment can prevent the bonding position shift and the destruction of the elements inside the microcomputer chip 2 in the W / B process. Details of the QFP 1 will be described later. This will be described in detail when explaining the method.

  As a means for mounting the memory chip 3 on the bar die pad 5e, a method of adhering using an adhesive such as Ag paste or a method of adhering using DAF is used, similar to the means for mounting the microcomputer chip 2. Can do.

<Method for Manufacturing Semiconductor Device>
Next, a method for manufacturing QFP 1 shown in FIGS. 1 to 5 will be described. The QFP 1 of the first embodiment is obtained as follows. 6 is an enlarged plan view showing an enlarged portion corresponding to one semiconductor device of the lead frame used for manufacturing the semiconductor device of the first embodiment, and FIG. 7 is taken along the line DD shown in FIG. It is a principal part enlarged plan view.

  (A) First, the lead frame 5 shown in FIG. 6 is prepared. In the lead frame 5 prepared in this step, a unit lead frame (hereinafter simply referred to as a lead frame) corresponding to one semiconductor device shown in FIG. 6 is planarized by a support frame (not shown) of the lead frame 5. A plurality of them connected to each other can be used. In addition, the inner lead 5a, outer lead 5b (see FIG. 1), die pad 5c, suspension lead 5d, bar die pad 5e, and bar support member 5f formed on the lead frame 5 are integrally formed via a lead frame support frame or the like. Are connected to each other.

  For example, the lead frame 5 shown in FIG. 6 is obtained as follows. First, an iron-based (for example, 42 alloy) or copper-based (for example, copper or a copper plate with a Ni plating layer formed thereon) is prepared, and a predetermined pattern is formed by etching or pressing. Thus, the inner lead 5a, the outer lead 5b (see FIG. 1), the die pad 5c, the suspension lead 5d, the bar die pad 5e, the bar support member 5f, and the like are formed.

  Next, as an offset process, the positions of the die pad 5c, the bar die pad 5e, and the bar support member 5f on the plane are offset from the plane position of the inner lead 5a (downset in the first embodiment). In this offset process, for example, a punch and a die are used to bend a predetermined portion of the suspension lead 5d (for example, a bent portion indicated by a thin line in the middle of the suspension lead 5d in FIG. 6).

  The bent portion of the suspension lead 5d is disposed outside the portion where the bar support member 5f is connected. This is because the microcomputer chip 2 (see FIG. 5) and the memory chip 3 (see FIG. 5) are mounted on a flat surface in a die bonding process described later.

  When the offset process is completed, as shown in FIG. 7, the lead frame 5 in a state where the positions of the die pad 5c, the bar die pad 5e and the bar supporting member 5f on the plane are offset from the plane position of the inner lead 5a is obtained.

  (B) Next, a plurality of semiconductor chips shown in FIG. 8, that is, the microcomputer chip 2 and the memory chip 3 are prepared and mounted (bonded) to the die pad 5c and the bar die pad 5e, respectively (die bonding step).

  8 is an enlarged plan view of a main part showing a state in which the microcomputer chip and the memory chip are mounted on the lead frame shown in FIG. 6, and FIG. 9 is a cross-sectional view taken along the line EE shown in FIG.

  A plurality of pads 2c and 3c are formed on the main surfaces 2a and 3a of the microcomputer chip 2 and the memory chip 3, respectively. In this die bonding process, when the back surface 2b, 3b (see FIG. 9) side (mounting surface side) of the region where these pads 2c, 3c are formed is mounted on the lead frame 5, the die pad 5c, bar die pad 5e. The bar support member 5f and the suspension lead 5d are disposed so as to be exposed from the opening. That is, in the back surface 2 and the back surface 3b, the regions overlapping the pads 2c and 3c in the thickness direction are arranged avoiding the die pad 5c and the bar die pad 5e. This is to prevent bonding position shifts and destruction of elements inside the microcomputer chip 2 in the W / B process described later.

  As the die bonding method, a generally known bonding method can be used. For example, after a paste adhesive is applied in advance to a predetermined portion of the die pad 5c and the bar die pad 5e (or in addition to this, the bar support member 5f), the microcomputer chip 2 and the memory chip 3 are pressed and bonded to predetermined positions. Can be fixed. Further, as described above, a film having an adhesive layer such as DAF is attached in advance to the back surfaces 2b and 3b of the microcomputer chip 2 and the memory chip 3, and in this state, the microcomputer chip 2 and the memory chip 3 are pressed to a predetermined position. It may be bonded and fixed. Alternatively, a conductive adhesive (for example, Ag paste) in which conductive particles such as Ag are mixed in the adhesive paste may be used.

  (C) Next, as the W / B process, the microcomputer chip 2, the memory chip 3, and the inner leads 5a which are a plurality of leads are electrically connected.

  10 is an enlarged cross-sectional view of a main part showing a state where the lead frame shown in FIG. 9 is placed on the W / B stage, and FIG. 11 is a diagram between the microcomputer chip and the memory chip mounted on the lead frame shown in FIG. It is a principal part expanded sectional view which shows the state electrically connected through the wire. 12 is an enlarged cross-sectional view of a main part showing a state where the microcomputer chip and the inner lead mounted on the lead frame shown in FIG. 10 are electrically connected, and FIG. 13 is mounted on the lead frame shown in FIG. It is a principal part expanded sectional view which shows the state which electrically connected between the memory chip and the inner lead. FIG. 14 is an enlarged plan view of a main part showing a state after the microcomputer chip, the memory chip, and the inner lead mounted on the lead frame shown in FIG. 10 are electrically connected via wires. FIG. 15 shows a state after the microcomputer chip and the memory chip, which are modifications of the first embodiment, are mounted on a lead frame and the chip and the inner lead are electrically connected via a wire. It is a principal part enlarged plan view shown. FIG. 21 is a main part showing a state after electrically connecting the microcomputer chip, the memory chip, and the inner lead mounted on the lead frame as a comparative example of the first embodiment via wires. FIG. 22 is an enlarged plan view, and FIG. 22 is an enlarged sectional view of the main part of the W / B stage and lead frame shown in FIG.

  In this step, first, as shown in FIG. 10, the lead frame 5 on which the microcomputer chip 2 and the memory chip 3 are mounted is placed on the W / B stage 7. The surface of the W / B stage 7 corresponds to the shape of the opening between the die pad 5c, the bar die pad 5e, the bar support member 5f and the suspension lead 5d of the lead frame 5, and a plurality of first support surfaces 7a and second supports. It has a surface 7b.

  Therefore, areas of the back surfaces 2b and 3b of the microcomputer chip 2 and the memory chip 3 that overlap the pads 2c and 3c in the thickness direction are directly supported by the first support surface 7a of the W / B stage 7. It becomes. On the other hand, of the back surfaces 2b and 3b of the microcomputer chip 2 and the memory chip 3, the region bonded to the die pad 5c, the bar die pad 5e, or the bar support member 5f is disposed on the second support surface 7b. It is supported by the W / B stage 7 via the die pad 5e or the bar support member 5f.

  Next, as shown in FIGS. 11 to 14, the microcomputer chip 2, the memory chip 3, and the plurality of inner leads 5 a are electrically connected via wires 6 a, 6 b and 6 c.

  In the W / B process, for example, the tips of the wires 6a, 6b, and 6c are joined to a place (first pad 2c or pad 3c in the first embodiment) where heat, pressure, ultrasonic waves, or the like is used. . Thereafter, the wires 6a, 6b, and 6c are supplied and guided to the place where the second bond is made (inner lead 5a or pad 3c in the first embodiment) while forming a predetermined loop shape. Thereafter, the second wires are bonded to each other using heat, pressure, ultrasonic waves, etc., and the excess wires 6a, 6b, 6c are cut. When cutting the excess wires 6a, 6b, and 6c, the jig for holding the wires 6a, 6b, and 6c is rubbed and cut at the place where the second bond is made.

  Here, a plate-like die pad 5r that covers the entire back surface 3b of the memory chip 3 is used as a die pad for mounting the memory chip 3 as in the lead frame 5p shown in FIGS. 21 and 22 as a comparative example of the first embodiment. The case will be described.

  When the lead frame 5p shown in FIGS. 21 and 22 is used, the pad 2c of the microcomputer chip 2 is directly supported on the first support surface 7a of the W / B stage 7 as shown in FIG. On the other hand, the pad 3c of the memory chip 3 is supported on the second support surface 7b of the W / B stage 7 via the die pad 5r. In other words, the reference surface (surface supporting the lower side of the pad) when performing W / B is the reference surface when bonding to the pad 2c is the first support surface 7a and the reference surface when bonding to the pad 3c. Becomes the second support surface 7b and has different heights.

  By the way, when the W / B stage 7 is processed to form the first support surface 7a and the second support surface 7b, an error may occur with respect to the design height due to processing accuracy. That is, when W / B is performed between the pads 2c and 3c shown in FIGS. 21 and 22, there is an error in the heights of the first support surface 7a and the second support surface 7b that are the reference surfaces of the height of the pads 2c and 3c. Occurs. Also, the thickness of the lead frame 5p is likely to vary during the process of manufacturing the lead frame 5p. Therefore, if the thickness of the lead frame 5p (particularly the die pads 5c and 5r) placed on the W / B stage 7 is different, the first support surface 7a and the second support surface formed on the W / B stage 7 will be described. Even if the height of 7b can be formed accurately, an error occurs in the height of each pad 2c, 3c.

  When W / B is performed in a state where this error is large, the lead frame 5p itself is rattled (for example, one of the die pad 5c and the die pad 5r is lifted from the second support surface 7b of the W / B stage 7). Therefore, the bonding position may be displaced. Further, due to this error, an excessive external force may be applied to the pad 2c or the pad 3c during bonding. In particular, in order to cut the wire 6a, a jig for gripping the wire 6a is rubbed at a portion where the second bond is made (the pad 3c in FIGS. 21 and 22). When an excessive external force is applied to the pad 3c due to an error in the height of the second support surface 7b, which is the reference surface, when the wire 6a is cut, the external force is transmitted to the semiconductor element inside the memory chip 3, and the semiconductor element May be destroyed. Conversely, if the force applied to the pad 3c due to the height error of the second support surface 7b, which is the reference surface, is too weak, it may cause W / B defects.

  Therefore, in the first embodiment, as shown in FIG. 14, the memory chip 3 is mounted on a bar die pad 5e, which is an elongated bar-shaped plate, and the pad 3c and the pad 2c are arranged avoiding the die pad 5c and the bar die pad 5e. It was.

  As a result, both pads 2c and 3c can be supported on the first support surface 7a of the W / B stage 7 when W / B connects the pads 2c and 3c shown in FIG. . Therefore, the pad 2c and the pad 3c are W / B while being supported by the same reference surface (first support surface 7a). That is, the reference plane at the time of W / B can be made one. If the reference plane at the time of W / B is made one, it is possible to prevent or greatly suppress the occurrence of errors due to the processing accuracy when processing the W / B stage 7 described above. For this reason, it is possible to prevent the bonding position from being shifted due to this error. In addition, as shown in FIG. 11, an example in which the pad 3c of the memory chip 3 is a place where the second bond is made will be described. By using one reference plane at the time of W / B, the pad 3c can be connected to the pad 3c. The external force applied to the pad 3c when the wire 6a is joined or when the wire 6a is cut can be stored within an appropriate range. That is, breakage of the semiconductor element in the memory chip 3 and W / B failure can be prevented.

  In the first embodiment, the configuration in which the first bond is formed on the pad 2c and the second bond is formed on the pad 3c as shown in FIG. 11 has been described. Conversely, the first bond is formed on the pad 3c and the second bond is formed on the pad 2c. It is good also as composition which carries out a bond. In this case, breakage of the semiconductor element formed in the microcomputer chip 2 and W / B failure can be prevented.

  In the first embodiment, as shown in FIG. 14, the long side outside the memory chip 3 (the side far from the microcomputer chip 2) is bonded to the bar support member 5f. Therefore, by disposing the pad 3c only on the inner side (long side on the side close to the microcomputer chip 2), a region of the back surface 3b of the memory chip 3 that overlaps with the pad 3c in the thickness direction is formed as a die pad 5c, a bar die pad. 5e is exposed from the opening between the bar support member 5f and the suspension lead 5d. Thereby, the pad 3 c can be directly supported on the first support surface 7 a of the W / B stage 7.

  However, the arrangement of the memory chip 3 and the pad 3c is not limited to the structure shown in FIG. For example, when a microcomputer chip 2d having a smaller outer dimension than that of the microcomputer chip 2 shown in FIG. 14 is mounted like the microcomputer chip 2d shown in FIG. 15 which is a modification of the first embodiment, the memory chip 3d Is also arranged to be closer to the microcomputer chip 2d side. By bringing the memory chip 3d closer to the microcomputer chip 2d side and setting the distance between the two chips to a predetermined interval, the wire loop of the wire 6a is stabilized, so that contact between the wires 6a, 6b, and 6c is prevented. Because you can. In this case, as shown in FIG. 15, the memory chip 3d is mounted only on the bar die pad 5e. For this reason, the pad 3c in the memory chip 3d may be disposed also on the long side of the outside of the memory chip 3d (the side far from the microcomputer chip 2d).

  Incidentally, the wires 6b and 6c shown in FIG. 14 are joined to the inner leads 5a as second bonds, respectively. The height of the lead support surface (third support surface) 7c (see FIGS. 11 to 13) for supporting the inner lead 5a of the W / B stage 7 is the same as that of the first support surface 7a as shown in FIGS. Located higher than the height. That is, when W / B is performed on the inner lead 5a, the members supported by the two reference surfaces are connected by W / B.

  However, in the first embodiment, the first bond is the pad 2c or the pad 3c, and the inner lead 5a side is the second bond. The inner lead 5a is a metal plate and does not have a semiconductor element formed therein. Therefore, the allowable range of external force that can be applied during W / B is wider than that of the pad 3c of the memory chip 3. That is, by setting the inner lead 5a to the second bond side, it is possible to bond with a stronger force or to cut the wires 6b and 6c than the above-described bonding with the wire 6a, thereby preventing W / B defects. be able to.

  (D) Next, the microcomputer chip 2 and the memory chip 3 mounted on the lead frame 5 are resin-sealed with a seal 4. FIG. 16 is a plan view showing the entire structure of the lead frame after the microcomputer chip and the memory chip shown in FIG. 14 are sealed with a sealing body.

  In this step, for example, the lead frame 5 is sandwiched between molds (upper mold and lower mold) in which a cavity is formed for each unit lead frame, and a sealing resin is injected into the cavity and cured. When the mold is removed after the sealing resin is cured, the sealing body 4 is formed for each unit lead frame corresponding to one semiconductor device shown in FIG. 16, and the outer lead 5b is led out from the side surface of the sealing body. It will be in the state.

  (E) Next, the QFP 1 shown in FIGS. 1 to 5 is obtained by cutting and molding the outer lead 5b.

  As described above, in the first embodiment, the lead frame 5 can be standardized by making the outer dimensions of the die pad 5c on which the microcomputer chip 2 is mounted smaller than the outer dimensions of the back surface 2b of the microcomputer chip 2.

  If the outer dimension of the die pad 5c is made smaller than the outer dimension of the back surface 2b of the microcomputer chip 2, the pad 2c of the microcomputer chip 2 is disposed at a portion protruding from the die pad 5c. However, in the first embodiment, since the memory chip 3 arranged beside the microcomputer chip 2 is mounted on the elongated bar die pad 5e whose longitudinal direction is the direction from the suspension lead 5d toward the memory chip 3, the memory chip 3 The pad 3c can be arranged avoiding a region overlapping the bar die pad 5e in the thickness direction. As a result, the W / B stage can have a single reference surface when W / B is performed between the pads 2c and 3c via the wire 6a. When the reference plane of the W / B stage is made one, problems such as occurrence of bonding failure or destruction of the semiconductor element can be prevented. That is, the problem in standardizing the lead frame 5 can be solved.

(Embodiment 2)
FIG. 17 is an enlarged plan view of a main part showing the internal structure of the QFP 10 which is the semiconductor device of the second embodiment, and FIG. 18 shows a W / B process in the manufacturing process of the QFP 10 shown in FIG. It is a principal part expanded sectional view which shows the cross section along the FF line. The QFP 10 of the second embodiment has the same structure as the QFP 1 described in the first embodiment except for the shape of the mounting portion of the memory chip 3. Therefore, the illustration of the entire structure of the QFP 10 and the overlapping description are omitted.

  The difference between the QFP 10 of the second embodiment and the QFP 1 described in the first embodiment is the shape of the mounting portion of the memory chip 3. The lead frame 5g used for manufacturing the QFP 10 does not have the bar die pad 5e and the bar support member 5f described in the first embodiment. Instead of this, the lead frame 5g has a protruding portion 5h on the side facing the memory chip 3 of the two suspension leads 5d of the QFP 10, and this protruding portion 5h is the mounting portion (second portion of the memory chip 3). Functions as a chip mounting part).

  The shape of the protruding portion 5h is a triangle or a sector shape corresponding to the extending direction of the suspension lead 5d formed integrally, but the shape is not limited to this. Other shapes may be used as long as the support strength necessary for supporting the memory chip 3 is obtained and the shape does not interfere when placed on the W / B stage 7. In FIG. 17, the protrusion 5h is connected to the suspension lead 5d with a width wider than the short side of the memory chip 3, so that the memory chip 3 can be supported without providing the bar support member 5f as shown in FIG. However, in order to further increase the support strength, for example, a bar support member 5f as shown in FIG. 5 may be connected to the end of the protrusion 5h outside (the side far from the microcomputer chip 2).

  Further, the protruding portion 5h is disposed on both short sides of the memory chip 3, and the outer edges of both short sides of the memory chip 3 are bonded to the protruding portion 5h. By supporting the memory chip 3 with the protruding portions 5h arranged on both short sides in this way, the back surface 3b on both long sides of the memory chip 3 is W / B except for both ends during W / B. The first support surface 7a of the stage 7 can be directly supported. Therefore, if the pads 3c are arranged on the main surface 3a of the memory chip 3 at the center of both long sides (other than both ends bonded to the protruding portions 5h), the pads 3c are arranged so as to avoid the protruding portions 5h. Therefore, one reference plane can be obtained at the time of W / B in which the pads 2c and 3c are connected via the wire 6a. That is, W / B is performed while the pad 2c and the pad 3c are supported by the same reference surface (first support surface 7a). Accordingly, it is possible to prevent problems such as occurrence of bonding failure or destruction of the semiconductor element.

  Further, according to the second embodiment, if the pads 3c are arranged in the center of both long sides, the pads 3c are arranged avoiding the protruding portions 5h, so the first embodiment described above. The positional relationship between the pad 3c and the protruding portion 5h can be easily adjusted as compared with the QFP 1 described in the above. That is, the QFP 10 can facilitate the alignment of the memory chip 3 in the die bonding process as compared with the QFP 1, so that the manufacturing efficiency can be improved in addition to the effects described in the first embodiment.

  Further, in the QFP 10, since the arrangement of the pads 3c is concentrated and arranged at the center of both long sides of the memory chip 3, the arrangement space of the pads 3c can be effectively utilized. Therefore, it is possible to increase the arrangement pitch of the pads 3c as compared with the QFP 1 described in the first embodiment, or to increase the number of terminals (the number of pads 3c) at the same arrangement pitch.

  By the way, as shown in FIG. 5 described in the first embodiment, a part of the side of the microcomputer chip 2 on the memory chip 3 side is bonded to the bar die pad 5e which is the second chip mounting portion. For this reason, in order to have one reference plane at the time of W / B in which the pads 2c and 3c are connected via the wire 6a, it is necessary to arrange the pad 2c so as to avoid the bar die pad 5e as well as the pad 3c. is there. This also applies to the second embodiment, and as shown in FIG. 17, a part of the side of the microcomputer chip 2 on the memory chip 3 side is bonded to the protruding portion 5h which is the second chip mounting portion. That is, in order to have one reference plane at the time of W / B, it is necessary to consider the positional relationship between the bar die pad 5e shown in FIG. 5 or the protrusion 5h shown in FIG. 17 and the pad 2c.

  Here, in the second embodiment, since the protruding portions 5h are arranged only on both short sides of the memory chip 3, the pads 2c arranged on the side closer to the memory chip 3 of the microcomputer chip 2 are also centered. If it arrange | positions collectively on a part (except the both ends bonded to the protrusion part 5h), the pad 2c will be arrange | positioned avoiding the protrusion part 5h.

  Therefore, the QFP 10 can easily align the microcomputer chip 2 in the die bonding process as compared with the QFP 1, and can improve the manufacturing efficiency. Further, since the arrangement space of the pads 2c can be used effectively, the arrangement pitch of the pads 2c is widened compared to the QFP 1 described in the first embodiment, or the number of terminals (the number of pads 2c is the same arrangement pitch). ) Can be increased.

(Embodiment 3)
FIG. 19 is an enlarged plan view of the main part showing the internal structure of the QFP 11 which is the semiconductor device of the third embodiment, and FIG. 20 shows the W / B process in the manufacturing process of the QFP 11 shown in FIG. It is a principal part expanded sectional view which shows the cross section along GG line.

  19 and 20, the difference between the QFP 11 of the third embodiment and the QFP 1 described in the first embodiment is the shape of the chip mounting portion. The lead frame 5i used for manufacturing the QFP 11 has a die pad 5k having a larger outer dimension than the back surface 2b of the microcomputer chip 2 as a first chip mounting portion on which the microcomputer chip 2 is mounted. Further, the lead frame 5i has a die pad 5m having a larger outer dimension than the back surface 3b of the memory chip 3 and covering the entire surface of the back surface 3b as a second chip mounting portion on which the memory chip 3 is mounted.

  In the third embodiment, the microcomputer chip 2 and the memory chip 3 are mounted on the die pads 5k and 5m larger than the respective outer dimensions, so that the W / B is connected during the W / B connection between the pads 2c and 3c. It can be directly supported on the second support surface 7 b of the stage 7. That is, the reference surface at the time of W / B can be only the second support surface 7b. Accordingly, it is possible to prevent problems such as occurrence of bonding failure or destruction of the semiconductor element.

  Here, the area of the back surface 2 b of the microcomputer chip 2 is larger than the area of the back surface 3 b of the memory chip 3. Therefore, when the die pad 5k is formed so as to cover the entire back surface 2b of the microcomputer chip 2, when the completed QFP 11 is mounted on another substrate, the die pad 5k and the sealing body 4 (see FIG. 1) are bonded to each other. There is a risk of reflow cracks.

  Therefore, the die pad 5k according to the third embodiment forms a plurality (eight locations in FIG. 19) of openings 5n at positions facing the back surface 2b of the microcomputer chip 2. By forming a plurality of openings 5n, the area where the back surface 2b of the microcomputer chip 2 and the resin of the sealing body 4 are in close contact with each other can be widened, so that the occurrence of reflow cracks in the QFP 11 can be suppressed.

  Note that the opening 5n illustrated in FIG. 19 is an example, and is not limited thereto as long as reflow cracks can be suppressed. For example, a large number (for example, 20 or more) of elongated slit-shaped openings 5n can be formed.

  In the third embodiment, since a plurality of openings 5n are formed in the die pad 5k, depending on the size of the plane area of the microcomputer chip 2 (when smaller than the microcomputer chip 2 shown in FIG. 19), the pads 2c and the openings 5n May overlap in the thickness direction. However, since the opening 5n is divided into a plurality of parts in the third embodiment, the area per opening 5n is equal to the opening (die pad 5c, bar die pad 5e, bar) described in the first embodiment. Smaller than the opening between the support member 5f and the suspension lead 5d). Therefore, W / B can be performed on the pad 2c without forming the first support surface 7a of the W / B stage 7 as shown in FIG. 11 in the opening 5n. That is, even when the plane area of the microcomputer chip 2 is small, W / B can be performed using the second support surface 7b as a reference surface as shown in FIG. 20, so that the lead frame can be standardized.

  By the way, in order to prevent the occurrence of reflow cracks, the QFPs 1 and 10 described in the first and second embodiments increase the area where the back surface 2b of the microcomputer chip 2 and the resin of the sealing body 4 are in close contact with each other. This is more preferable.

  However, the QFP 11 of the third embodiment can obtain the following effects by making the outer dimensions of the die pad 5k larger than the outer dimensions of the microcomputer chip 2. That is, as shown in FIG. 19, the GND (reference potential) or power supply potential pad 2c of the microcomputer chip 2 and the die pad 5k are electrically connected via the wire 6d (fourth wire). Thus, GND or a power supply potential can be supplied from the die pad 5k. In this case, since it is necessary to electrically connect the die pad 5k to GND or an external connection terminal that supplies a power supply potential, for example, the end of the suspension lead 5d is branched and the GND or power It may be exposed as a potential outer lead (not shown).

  As another method for supplying GND or a power supply potential from the die pad 5k, the back surface 2b of the microcomputer chip 2 and the die pad 5k are bonded to the die pad 5k through a conductive adhesive such as Ag paste. And may be electrically connected. In this case, the number of terminals (the number of pads 2c) on the main surface 2a of the microcomputer chip 2 can be reduced.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the first embodiment, the example in which the bar die pad 5e is connected to the suspension lead 5d has been described. However, the bar die pad 5e may be connected to the die pad 5c.

  The present invention is particularly applicable to a semiconductor device such as a SIP in which a plurality of semiconductor chips are mounted on a lead frame and sealed together by a sealing body.

It is a principal part top view which shows an example of the internal structure of the semiconductor device which is one embodiment of this invention. It is principal part sectional drawing along the AA shown in FIG. It is principal part sectional drawing along the BB line shown in FIG. It is principal part sectional drawing along CC line shown in FIG. FIG. 2 is an enlarged plan view of a main part around a semiconductor chip of the semiconductor device shown in FIG. 1. FIG. 3 is an enlarged plan view showing an enlarged portion corresponding to one semiconductor device of a lead frame used for manufacturing a semiconductor device according to an embodiment of the present invention. It is a principal part enlarged plan view along the DD line | wire shown in FIG. FIG. 7 is an enlarged plan view of a main part showing a state in which a microcomputer chip and a memory chip are mounted on the lead frame shown in FIG. 6. It is sectional drawing along the EE line shown in FIG. FIG. 10 is an essential part enlarged cross-sectional view showing a state in which the lead frame shown in FIG. 9 is placed on the W / B stage. FIG. 11 is an essential part enlarged cross-sectional view showing a state in which a microcomputer chip and a memory chip mounted on the lead frame shown in FIG. 10 are electrically connected via wires. FIG. 11 is an enlarged cross-sectional view of a main part showing a state in which a microcomputer chip and an inner lead mounted on the lead frame shown in FIG. 10 are electrically connected. FIG. 11 is an essential part enlarged cross-sectional view showing a state in which a memory chip and an inner lead mounted on the lead frame shown in FIG. 10 are electrically connected. It is a principal part enlarged plan view which shows the state after electrically connecting between the microcomputer chip mounted in the lead frame shown in FIG. 10, a memory chip, and an inner lead via a wire. The main part which shows the state after mounting the microcomputer chip and memory chip which are the modifications of one embodiment of this invention in a lead frame, and electrically connecting between these chips and inner leads via a wire It is an enlarged plan view. FIG. 15 is a plan view showing the entire structure of the lead frame after the microcomputer chip and the memory chip shown in FIG. 14 are resin-sealed with a sealing body. It is a principal part enlarged plan view which shows an example of the internal structure of the semiconductor device which is other embodiment of this invention. FIG. 18 is an essential part enlarged cross-sectional view showing a cross section taken along line FF shown in FIG. 17 in the W / B process during the manufacturing process of the semiconductor device shown in FIG. 17; It is a principal part enlarged plan view which shows an example of the internal structure of the semiconductor device which is other embodiment of this invention. FIG. 20 is an essential part enlarged cross-sectional view showing a cross section along line GG shown in FIG. 19 in the W / B process during the manufacturing process of the semiconductor device shown in FIG. 19; The principal part enlarged plan view which shows the state after electrically connecting between the microcomputer chip mounted in the lead frame which is a comparative example of one embodiment of this invention, a memory chip, and an inner lead via a wire It is. FIG. 22 is an enlarged cross-sectional view of a main part of the W / B stage and lead frame shown in FIG. 21.

Explanation of symbols

1, 10, 11 QFP (semiconductor device)
2, 2d microcomputer chip (first semiconductor chip)
2a Main surface (first main surface)
2b Back side (first back side)
2c Pad (first terminal)
3, 3d memory chip (second semiconductor chip)
3a Main surface (second main surface)
3b Back side (second back side)
3c pad (second terminal)
4 Sealing body 4a Side surface 5, 5g, 5p Lead frame 5a Inner lead 5b Outer lead 5c, 5k Die pad (first chip mounting portion)
5d Hanging lead 5e Bar die pad (second chip mounting part)
5f Bar support member 5h Protruding part (second chip mounting part)
5m die pad (second chip mounting part)
5n opening 5r die pad 6a wire (first wire)
6b wire (second wire)
6c wire (third wire)
6d wire (fourth wire)
7 Wire Bonding (W / B) Stage 7a First Support Surface 7b Second Support Surface 7c Lead Support Surface

Claims (6)

A semiconductor device having a plurality of semiconductor chips,
A first semiconductor chip having a first main surface on which a first semiconductor element and a plurality of first terminals are formed, and a first back surface opposite to the first main surface;
A second main surface on which a second semiconductor element and a plurality of second terminals are formed, and a second back surface opposite to the first main surface, are arranged side by side with the first semiconductor chip. A second semiconductor chip,
A first chip mounting portion having an outer dimension smaller than an outer dimension of the first back surface of the first semiconductor chip and bonded to the first back surface of the first semiconductor chip;
A plurality of suspension leads arranged to extend radially outward from the first chip mounting portion and supporting the first chip mounting portion;
A second chip mounting portion that is integrally formed with the first chip mounting portion via the suspension lead and is joined to the second back surface of the second semiconductor chip;
A plurality of leads disposed around the first and second semiconductor chips;
A plurality of conductive first wires electrically connecting the first terminal and the second terminal, respectively;
A plurality of conductive second wires that electrically connect the first terminal and the lead;
A plurality of conductive third wires that electrically connect the second terminal and the lead;
The first and second semiconductor chips, and a sealing body for resin-sealing the plurality of first, second, and third wires;
Of the first and second back surfaces of the first and second semiconductor chips, regions overlapping with the plurality of first terminals and the plurality of second terminals in the thickness direction are the first and second surfaces, respectively. A semiconductor device characterized by being disposed avoiding a chip mounting portion. The semiconductor device according to claim 1,
The second chip mounting portion is a plurality of bar die pads whose longitudinal direction is a direction from the plurality of suspension leads toward the second semiconductor chip,
Each of the plurality of bar die pads has one end connected to the suspension lead, and the other end connected to a bar support member disposed outside the bar die pad.
The bar support member is formed integrally with the first chip mounting portion, the second chip mounting portion, and the suspension leads, and the suspension leads to which the plurality of bar die pads are connected among the plurality of suspension leads. A semiconductor device formed to connect each other. The semiconductor device according to claim 2,
The second semiconductor chip has a long side arranged along one side of the first semiconductor chip, and the second semiconductor chip has a long side far from the first semiconductor chip of the second semiconductor chip. An outer edge is bonded to the bar support member, and the second terminal is formed only on the long side of the second semiconductor chip close to the first semiconductor chip. apparatus. The semiconductor device according to claim 1,
The second semiconductor chip has a long side arranged along one side of the first semiconductor chip, and an outer edge of both short sides of the second semiconductor chip is the second chip mounting portion. A semiconductor device which is bonded to the semiconductor device. A semiconductor device having a plurality of semiconductor chips,
A first semiconductor chip having a first main surface on which a first semiconductor element and a plurality of first terminals are formed, and a first back surface opposite to the first main surface;
A second main surface on which a second semiconductor element and a plurality of second terminals are formed, and a second back surface opposite to the first main surface, are arranged side by side with the first semiconductor chip. A second semiconductor chip,
The first semiconductor chip has an outer dimension larger than the outer dimension of the first back surface, and has a plurality of openings at positions facing the first back surface of the first semiconductor chip, A first chip mounting portion to be bonded to the first back surface of the semiconductor chip;
A plurality of suspension leads arranged to extend outward from the first chip mounting portion and supporting the first chip mounting portion;
A second chip mounting portion formed integrally with the first chip mounting portion via the suspension lead, and joined to cover the second back surface of the second semiconductor chip and the entire surface thereof;
A plurality of leads disposed around the first and second semiconductor chips;
A plurality of conductive first wires electrically connecting the first terminal and the second terminal, respectively;
A plurality of conductive second wires that electrically connect the first terminal and the lead;
A plurality of conductive third wires that electrically connect the second terminal and the lead;
A semiconductor device comprising: the first and second semiconductor chips; and a sealing body that seals the plurality of first, second, and third wires with resin. The first back surface of a first semiconductor chip having a first main surface on which a first semiconductor element and a plurality of first terminals are formed, and a first back surface opposite to the first main surface, Bonding to a first chip mounting portion having an outer dimension smaller than the outer dimension of the first back surface of the semiconductor chip;
The second back surface of a second semiconductor chip having a second main surface on which a second semiconductor element and a plurality of second terminals are formed, and a second back surface opposite to the first main surface, Bonding to a second chip mounting portion formed integrally with the chip mounting portion and disposed beside the first chip mounting portion;
Electrically connecting the plurality of first terminals and the plurality of second terminals via a plurality of first wires, respectively;
A step of resin-sealing the first and second semiconductor chips and the plurality of first, second and third wires;
Of the first and second back surfaces of the first and second semiconductor chips, regions overlapping with the plurality of first terminals and the plurality of second terminals in the thickness direction are the first and second surfaces, respectively. Placed away from the chip mounting part,
In the step of electrically connecting the plurality of first terminals and the plurality of second terminals, the plurality of first terminals and the plurality of second terminals are supported on the same reference plane, respectively. A method for manufacturing a semiconductor device, comprising wire bonding.

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