JP2009170832A - Arithmetic method of layout pattern, photomask, method of manufacturing semiconductor device, semiconductor device, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that, when a contact layer positioned in another layer overlaps a narrow line&space pattern, that becomes a semi-transmissive pattern, disposed to remain a part of exposure light, for example, it is judged as disconnection electrically, so that, the contact region should be excluded as a rule violation, originally, namely, it is difficult to verify the contact region using a design rule checker. <P>SOLUTION: A region including a narrow line&space pattern is defined as a second region and the pattern and a normal pattern adjacent to the second region are handled as one aggregate pattern. When a mask including the second pattern is used, the intensity of light transmitted through second black and white regions is averaged and the light can be handled as a normal pattern for obtaining halftone light intensity. Therefore, processing can be performed using a rule checker such as DRC, LVS, ERC and the like, bugging is suppressed and the layout pattern can be obtained more accurately. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a layout pattern calculation method, a photomask, a semiconductor device manufacturing method, a semiconductor device, and an electronic apparatus.

  In the case of forming a thin film transistor (hereinafter referred to as TFT), a method is used in which a layer having a plurality of resist layer thicknesses is formed in a single photolithography process by adjusting the exposure amount. Specifically, the amount of light applied to the resist is adjusted to maintain the applied layer thickness and leave the resist, remove all resist, and reduce the layer thickness to leave the resist. It is a method of forming separately. In order to leave the resist in this way, it is necessary to adjust the exposure amount for each region.

  In this case, when the exposure is performed using a mask having a pattern and the lower limit of dimension capable of forming the pattern is treated as the spatial resolution, a photomask having an equivalent translucency is combined by combining patterns narrower than the spatial resolution. The method used is used. More specifically, a photomask having a line & space pattern narrower than the spatial resolution is used. Hereinafter, publication numbers of Patent Documents 1 to 3 using this technique are shown below. Some configurations of the photomask itself are also known, and publication numbers of Patent Document 4 are shown below.

JP 2007-53343 A JP-A-11-307780 JP 2002-134756 A JP 2007-13055 A

  Usually, as data handled by CAD, a pattern with less than spatial resolution is recognized as a defective pattern, so it is difficult to perform a design rule check of CAD data. In addition, when a pattern with less than spatial resolution is recognized as a non-defective pattern, a pattern that actually violates the rule may be overlooked.

  Even when a rule check is used with a pattern with less than spatial resolution as a non-defective product, the following problem occurs. Originally, when a contact region located in another layer overlaps a narrow line & space pattern that becomes a semi-transmissive pattern arranged to leave a part of the exposure light, for example, it is electrically judged as a disconnection, Eliminated as a rule violation. That is, it is difficult to verify using the design rule checker. Therefore, there arises a problem that the designer can only select a typical pattern and visually check the pattern.

  In this case, the design rule check is not performed for the area outside the visual determination, and the rule layout may be violated. When a layout that violates the rule is made, a failure occurs in the electrical characteristics, but a long period is required to search for a failure in the pattern layout from the failure in the electrical characteristics. In particular, there is a problem that an extremely long analysis period is required when a defect occurs in a part that is used less frequently and causes a fatal defect, such as an electrostatic countermeasure circuit.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

  Application Example 1 A layout pattern calculation method according to this application example, in which exposure is performed using a photomask having a pattern according to the layout pattern, and a dimension limit value that can form the pattern is treated as spatial resolution. A first pattern that includes a first black region, and includes at least part of the first black region including a region having a distance from the white region that is 1/2 or more of the spatial resolution in an arbitrary region; A shortest distance from the first pattern is a second pattern including a second black region having a value less than the spatial resolution, and is an arbitrary region within the second pattern and is ½ of the spatial resolution. The second pattern in which the white region exists at a distance smaller than the second black region, and the second black region exists at a distance smaller than ½ of the spatial resolution from an arbitrary point of the white region. There is disposed, and wherein the handling region comprising an OR between the first pattern and the second pattern as one of the pattern data.

  According to this, the layout pattern is designed to take a value less than the spatial resolution in the second pattern. Therefore, when a mask including the second pattern is used, the light intensity transmitted through the second black area and the white area is averaged, and a halftone light intensity can be obtained. That is, the second pattern functions as a normal pattern. By taking the OR of the second pattern and the first pattern, when handling the layout pattern, the area that takes a value less than the spatial resolution located in the second pattern, the area that is electrically disconnected, The separated area can be recognized as a normal layout pattern. Then, it becomes possible to extract a pattern that is really wrong.

  Application Example 2 A layout pattern calculation method according to the above application example, wherein the second pattern is a line & space pattern.

  According to the application example described above, the above-described halftone light intensity can be obtained with a small amount of data.

  Application Example 3 A layout pattern calculation method according to the application example described above, in which the OR of the first pattern and the second pattern is recognized as one pattern data, and other than in the second pattern A step of comparing and verifying the layout pattern and the design rule (DRC step: Design Rule Check step).

  According to the application example described above, it is possible to extract the disconnection pattern and the out-of-rule dimension in distinction from the disconnection pattern and the out-of-rule dimension which are located in the second pattern and perform a normal function.

  [Application Example 4] A layout pattern calculation method according to the above application example, in addition to the DRC process, a process of verifying whether the layout pattern matches a designed circuit diagram (LVS process: Layout Versus Schematic process) ) And a step of verifying whether the layout pattern operates electrically (ERC step: Electrical Rule Check step).

  According to the application example described above, it is possible to evaluate the contact deviation and the electrical characteristics by regarding the disconnection pattern and the non-rule dimension area located in the second pattern as a continuous pattern.

  Application Example 5 A layout pattern calculation method according to the above application example, wherein a ratio of the second black area to the white area is 10% or more and 90% or less.

  According to the application example described above, it is possible to provide a layout pattern from which a mask capable of controlling the amount of exposure light can be obtained.

  Application Example 6 A layout pattern calculation method according to the application example described above, wherein the layout pattern has a layout pattern obtained by negative / positive inversion of the layout pattern.

  According to the application example described above, both positive resists and negative resists can be dealt with, and the options for resists are widened.

  Application Example 7 When the photomask according to this application example is exposed using a photomask having a pattern according to the layout pattern and a dimensional limit value that can form the pattern is handled as a spatial resolution, the first black region is used. A first pattern including an area in which at least a part of the first black area has a distance from a white area that is 1/2 or more of the spatial resolution in an arbitrary area; and The shortest distance is a second pattern including a second black region having a value less than the spatial resolution, and is an arbitrary region within the second pattern at a distance smaller than ½ of the spatial resolution. The second pattern and the first pattern in which a white area exists and the second black area exists at a distance smaller than ½ of the spatial resolution from an arbitrary point of the white area And before A process of handling an area including an OR with the second pattern as one pattern data, recognizing it as one pattern data, and performing comparison verification between the layout pattern and the design rule other than in the second pattern (DRC process) : Design Rule Check step) includes the layout pattern confirmed.

  According to this, it is possible to mechanically verify the layout pattern, and it is possible to provide a photomask in which the occurrence of a defective pattern is surely suppressed.

  Application Example 8 In the photomask according to the application example, in addition to the DRC process, a process of verifying whether the layout pattern matches a designed circuit diagram (LVS process: Layout Versche Schematic process); The layout pattern includes at least one of steps of verifying whether the layout pattern is electrically operated (ERC step: Electrical Rule Check step).

  According to the application example described above, it is possible to evaluate the contact deviation and the electrical characteristics by regarding the disconnection pattern and the non-rule dimension area located in the second pattern as a continuous pattern.

  Application Example 9 The photomask according to the application example described above is characterized in that it has a layout pattern obtained by negative / positive inversion of the layout pattern.

  According to the application example described above, both positive resists and negative resists can be dealt with, and the options for resists are widened.

  [Application Example 10] The method of manufacturing a semiconductor device according to this application example is the first method in the case where exposure is performed using a photomask having a pattern according to the layout pattern, and the dimension limit value that can form the pattern is treated as spatial resolution. A first pattern including a black region, including at least a part of the first black region including a region having a distance from the white region of ½ or more of the spatial resolution in an arbitrary region; The shortest distance from the pattern is the second pattern including the second black area having a value less than the spatial resolution, and is smaller than ½ of the spatial resolution in an arbitrary area inside the second pattern. The second pattern in which the white region exists at a distance and the second black region exists at a distance smaller than ½ of the spatial resolution from an arbitrary point of the white region; and First par The region including the OR of the pattern and the second pattern is handled as one pattern data, is recognized as one pattern data, and the layout pattern and the design rule other than in the second pattern are compared and verified. A photolithographic process is performed using a photomask including the layout pattern confirmed in the process (DRC process: Design Rule Check process).

  According to this, it is possible to mechanically verify the layout pattern. As a result, a photomask in which mixing of defective patterns is reliably suppressed can be obtained. By performing a photolithography process using this photomask, it is possible to provide a method for manufacturing a semiconductor device in which the occurrence of defective patterns is suppressed.

  [Application Example 11] A method of manufacturing a semiconductor device according to the application example described above, wherein in addition to the DRC process, a process of verifying whether the layout pattern matches a designed circuit diagram (LVS process: Layout Versus Schematic process) ) And a step of verifying whether the layout pattern is electrically operated (ERC step: Electrical Rule Check step).

  According to the application example described above, it is possible to evaluate the contact deviation and the electrical characteristics by regarding the disconnection pattern and the non-rule dimension area located in the second pattern as a continuous pattern.

  Application Example 12 A method for manufacturing a conductor device according to the application example described above, wherein a photomask having a layout pattern obtained by negative / positive inversion of the layout pattern is used.

  According to the application example described above, both positive resists and negative resists can be dealt with, and the options for resists are widened.

  Application Example 13 In the semiconductor device according to this application example, when a photomask having a pattern according to the layout pattern is used for exposure and a dimension limit value that can form the pattern is handled as spatial resolution, the first black region is used. A first pattern including an area in which at least a part of the first black area has a distance from a white area that is 1/2 or more of the spatial resolution in an arbitrary area; and The shortest distance is a second pattern including a second black region having a value less than the spatial resolution, and is an arbitrary region within the second pattern at a distance smaller than ½ of the spatial resolution. The second pattern and the first pattern in which a white area exists and the second black area exists at a distance smaller than ½ of the spatial resolution from an arbitrary point of the white area Said A region including an OR including two patterns is handled as one pattern data, recognized as one pattern data, and compared and verified between the layout pattern and a design rule other than in the second pattern (DRC step: It is manufactured by performing a photolithography process using a photomask including the layout pattern confirmed by the Design Rule Check process.

  According to this, it is possible to mechanically verify the layout pattern. As a result, a photomask in which mixing of defective patterns is reliably suppressed can be obtained. By performing a photolithography process using this photomask and manufacturing the semiconductor device, it is possible to provide a semiconductor device in which the inclusion of defective patterns is suppressed.

  Application Example 14 In the conductor device according to the application example described above, in addition to the DRC process, a process of verifying whether the layout pattern matches a designed circuit diagram (LVS process: Layout Versche Schematic process); The layout pattern is manufactured using the photomask having the layout pattern including at least one of a process for verifying whether the layout pattern is electrically operated (ERC process: Electrical Rule Check process). And

  According to the application example described above, it is possible to evaluate the contact deviation and the electrical characteristics by regarding the disconnection pattern and the non-rule dimension area located in the second pattern as a continuous pattern.

  Application Example 15 A semiconductor device according to the application example described above, wherein the semiconductor device is manufactured using a photomask having a layout pattern obtained by negative / positive inversion of the layout pattern.

  According to the application example described above, both positive resists and negative resists can be dealt with, and the options for resists are widened.

  Application Example 16 An electronic apparatus according to this application example includes a semiconductor device manufactured using a photomask obtained by transferring a layout pattern obtained by using the layout pattern calculation method described above. Features.

  According to this, it is possible to form a semiconductor device having a layout pattern calculated by separating a normal pattern and a defective pattern, and provide an electronic apparatus in which defects caused by a layout pattern defect are suppressed. It becomes possible.

First Embodiment: Layout Pattern Calculation Method
Hereinafter, a layout pattern calculation method according to the present embodiment will be described with reference to the drawings. FIG. 1 is a flowchart showing a layout pattern calculation method according to this embodiment. FIG. 2 is a plan view of a layout pattern used for explaining the flowchart of FIG. FIG. 3 is a schematic diagram of a computer system that embodies processing according to the flowchart shown in FIG.

  First, the computer system shown in FIG. 3 will be described. The computer system 301 includes a ROM memory 302 for storing a startup program, a RAM 303 and a hard disk 304 having a function of storing a program for verifying a layout pattern, a keyboard 305, a mouse 306, a RAM 303, and the like serving as a human interface. A CPU 307 for processing information stored in the hard disk 304 in cooperation with each other and a display 308 for displaying the information are included. Hereinafter, the calculation method of the layout pattern 201 (see FIG. 2) will be described along the flow of the flowchart of FIG. 1 using FIGS. 2 and 3 as auxiliary drawings for explanation.

  First, the computer system 301 is activated. Specifically, turn on the power. In this process, the CPU 307 and other members are caused to perform a predetermined activation process according to the activation program stored in the ROM memory 302 shown in FIG.

  Then, the processing of the flowchart of FIG. 1 is started by “START”. This instruction is transmitted, for example, by moving the mouse 306 shown in FIG. 3 and clicking the “START” area displayed on the display 308.

  As the next step, information such as a pattern to be processed, a design rule, a wiring pattern, and electrical characteristic data is displayed on the display 308, and is selected / input using the keyboard 305 and the mouse 306.

  As the next step, the second pattern (pattern arranged to leave a part of the exposure light) is searched. Specifically, in this search, a white region exists at a distance smaller than 1/2 of the spatial resolution in an arbitrary region inside the black pattern located inside the pattern, and the spatial resolution is determined from an arbitrary point in the white region. A pattern in which the second black area exists at a distance smaller than 1/2 is searched. More specifically, the areas of the patterns 202a and 202b shown in FIG. 2 are shown. Here, as an example, a line and space pattern that can be processed with a small amount of data is used. This calculation is executed by transmitting the layout pattern stored in the hard disk 304 shown in FIG. 3 to the RAM 303 that can be processed at a higher speed via the CPU 307 and causing the RAM 303 and the CPU 307 to cooperate.

As the next step, the light transmittance of the pattern 202a and the pattern 202b shown in FIG. 2 is calculated. Specifically, the ratio between the black area and the white area included in the pattern is calculated. When forming a semi-transmissive area, if the ratio between the black area and the white area is too different, exposure by light amount control in the semi-transmissive area becomes difficult. Therefore, it is preferable to perform a correction / confirmation work when the ratio deviates from 10% to 90%.
When the correction / confirmation work has been performed, there is still a problem with the ratio between the black area and the white area, and if it is difficult to continue, the process ends. In addition, when this restriction is intentionally removed, the processing may be continued. This operation is performed by cooperating the RAM 303 and the CPU 307 shown in FIG.

  As the next step, a pattern that does not belong to the second pattern and includes an isolated pattern with a spatial resolution or less is searched. This calculation is performed by cooperating the RAM 303 and the CPU 307 shown in FIG. Then, the calculation result is displayed on the display 308. Here, correction / confirmation work is performed. If it is determined to be defective, the process is temporarily terminated and the layout pattern is corrected again.

  As the next step, the first pattern is searched. The first pattern includes, in at least a part of the interior of the black area, an area whose distance from the white area is 1/2 or more of the spatial resolution in an arbitrary area. A part of the pattern is arranged at a distance having a value less than the spatial resolution. This pattern shows, for example, the area of the pattern 203 in FIG. This calculation is also performed by cooperating the RAM 303 and the CPU 307 shown in FIG.

  As the next step, the OR of the first pattern and the second pattern is taken and recognized as one pattern 204. In this step, the patterns 202a, 202b, and 203 in FIG. 2 are recognized as one continuous pattern. This calculation is also performed by cooperating the RAM 303 and the CPU 307 shown in FIG. Here, the form of taking the OR of three patterns has been described, but this also corresponds to the case of processing including the case of becoming the OR of two patterns or the case of becoming the OR of four or more regions. be able to.

  As the next step, DRC (Design Rule Check) is performed on the layout pattern shown in FIG. Specifically, it is checked whether or not the design rule is satisfied for layers other than the layers shown in FIG. This calculation is performed by transmitting the information of other layers stored in the hard disk 304 shown in FIG. 3 and the design rule check program to the RAM 303 and cooperating with the CPU 307. When an area that does not satisfy the design rule is searched for by this calculation, the fact is output on the display 308. Here, correction / confirmation work is performed. If it is determined to be defective, the process is temporarily terminated and the layout pattern is corrected again.

  As the next step, if the design rule check is completed normally, an LVS (Layout Versuous Schematic) check is performed, and the elements created in the logic / circuit design stage and the connections between the elements are correct for the electrical design. Verify that they are consistent. In this case, since the first pattern and the second pattern are recognized as one pattern 204, information on the overlapping method such as a contact region located on the second pattern having the disconnection pattern is normal as a semi-transmissive pattern. It can be calculated by determining that it is connected to. This calculation is also performed using the hard disk 304, RAM 303, and CPU 307 shown in FIG. This calculation is also displayed on the display 308 when the electrical connection status is not in a desired state. Here, correction / confirmation work is performed. If it is determined to be defective, the process is temporarily terminated and the layout pattern is corrected again.

  As the next step, ERC (Electrical Rule Check) check is performed to check whether signal processing and delay time satisfy predetermined characteristics. This calculation is also performed using the hard disk 304, RAM 303, and CPU 307 shown in FIG. This calculation is also displayed on the display 308 if the electrical characteristics are not in the desired state. Here, correction / confirmation work is performed. If it is determined to be defective, the process is temporarily terminated and the layout pattern is corrected again.

  As the next step, the pattern 204 shown in FIG. 2 is returned to the original discrete pattern. In this case, when the pattern 204 is corrected, it is desirable to perform the processing in consideration of the influence. This processing is also performed using the hard disk 304, RAM 303, and CPU 307 shown in FIG.

  After these processes are completed, an “END” signal is displayed on the display 308 and the process is terminated.

  By performing such processing, it is possible to recognize a semi-transparent pattern having an apparent disconnection pattern as a normal pattern and perform desired processing.

(Modification to layout pattern calculation method)
In the first embodiment described above, the line and space pattern is used to form the semi-transmissive region, but instead, a line and space pattern orthogonal to the line and space pattern may be used. Moreover, not only a line & space pattern but a checkered pattern, a lattice pattern, a discrete pattern, etc. may be used, and if it is a figure which satisfy | fills the above-mentioned rule, there will be no restriction | limiting in particular.

  Alternatively, the second pattern may be designated as a special pattern area separately from the automatic search, and the subsequent processing may be performed. In this case, it is possible to reduce the possibility of causing an error by conforming to an unexpected pattern.

  Further, the layout pattern 201 used here is processed so as to be adapted to the case where a positive resist in which a black pattern remains is used. However, in the case where a negative resist is used, the black and white pattern is inverted to form a semi-transmissive region. This can be dealt with by using a pattern. In addition, the black and white pattern may be appropriately reversed for other layers in association with the relationship with the process conditions.

  The LVS check and ERC check can be omitted depending on the layout conditions.

(Second Embodiment: Photomask)
Hereinafter, the present embodiment will be described with reference to the drawings. FIG. 4A shows a plan view of a photomask 401 having a semi-transmissive region and an enlarged view of the balloon. 4B is a cross-sectional view taken along line AA ′ in FIG. 4A, and an enlarged view is shown in a balloon. The photomask 401 includes a reticle 407 including a quartz substrate 402 and a light shielding layer 403 using chromium, an outer frame 404, and a pellicle 405. The outer frame 404 and the pellicle 405 are for protecting the quartz substrate 402 and the light shielding layer 403 from contamination. More specifically, when performing exposure while focusing on the light shielding layer 403, the pellicle 405 is present in a region separated from the focal position by the height of the outer frame 404. Therefore, even if a foreign object is attached to the pellicle 405 in the exposure process, the image exists in a region out of focus. Therefore, the foreign object does not form an image when exposure is performed, and as a result, the influence of the foreign object on the transfer pattern. Can be avoided. Here, the pellicle 405 is formed by using an organic thin film such as nitrocellulose that has been subjected to an antireflection coating with respect to the exposure wavelength. A semi-transmissive region 406 is disposed in the blowing portion (enlarged portion) in FIGS.

  Next, a manufacturing process for forming the reticle 407 constituting the photomask 401 will be described. 5A to 5C are process cross-sectional views for forming the reticle 407. FIG. Here, for the sake of convenience of explaining the fine pattern, the illustration is limited to a narrow region where the pattern can be explained.

  First, after washing and drying the quartz substrate 402, a light shielding layer precursor 403a using chromium is formed.

  Next, an EB (Electron Beam) exposure resist 408 is applied using a spin coat method or the like, dried, and solidified. As a material constituting the resist for EB exposure 408, for example, by using a negative type chemically amplified resist solution, the properties of the resist for EB exposure 408 can be controlled with a small amount of EB exposure. Therefore, it is possible to perform EB exposure processing with high throughput.

  Next, EB exposure is performed. Here, as in the first embodiment, DRC check, LVS check, ERC check, and the like are performed on the data used for EB exposure including the area corresponding to the semi-transmissive area 406. For this reason, the exposure process can be performed without causing data omission. FIG. 5A shows the result of the steps up to here. In the drawing, an unexposed area is indicated by a white pattern 408a, and an exposed area is indicated by a black pattern 408b. In the EB exposure, a fine line & space pattern for forming the semi-transmissive region 406 is arranged, and the line & space pattern size when using i-line (mercury lamp emission line: wavelength 365 nm) is 0. It is formed with a pattern size of about 5 μm & 1.0 μm.

  Next, the EB exposure resist 408 is developed, and the EB exposure resist 408 is removed leaving a desired pattern including the semi-transmissive region 406. FIG. 5B shows the result of the steps up to here.

  Next, the light shielding layer precursor 403a is etched using the EB exposure resist 408 as a mask to form the light shielding layer 403, and then the EB exposure resist 408 is peeled off. FIG. 5C shows the result of the steps up to here.

  Since this photomask 401 has undergone a DRC check, an LVS check, an ERC check, etc., including the translucent region 406, the occurrence of defects due to omission of confirmation can be suppressed. Therefore, it is possible to provide a photomask 401 that can form an optical image on a semiconductor wafer with higher accuracy.

Third Embodiment: Semiconductor Device and Semiconductor Device Manufacturing Method
Hereinafter, the present embodiment will be described with reference to the drawings. FIG. 6A shows a circuit for connecting an N-type TFT 601N as a semiconductor device having an LDD (Lightly Doped Drain) structure and a P-type TFT 601P not having an LDD structure and also as a semiconductor device to perform an inverter operation. FIG. 5B is a plan view showing an example, FIG. 5B is a cross-sectional view taken along the line AA ′ of the N-type TFT 601N, and FIG. 5C is a cross-sectional view taken along the line BB ′ of the P-type TFT 601P. In this cross-sectional view, the contact connected to the TFT, the interlayer insulating layer, and the like are omitted.

  As shown in FIG. 6B, the N-type TFT 601N disposed on the substrate 602 via the buffer layer 615 includes a source / drain region 603N and a channel region 604N in order to suppress characteristic deterioration due to hot carriers. An LDD region 605 is disposed therebetween to disperse the electric field strength applied to the source / drain region 603N. A gate insulating layer 607 is disposed on the semiconductor layer 606 (source / drain region 603N, channel region 604N, LDD region 605). A gate electrode 608N is disposed at a position facing the channel region 604N with the gate insulating layer 607 interposed therebetween, and controls conduction / cutoff of the N-type TFT 601N.

  In the P-type TFT 601P disposed on the substrate 602 via the buffer layer 615, characteristic deterioration due to hot carriers does not occur. As shown in FIG. 6C, the LDD region 605 disposed in the N-type TFT 601N to omit hot carrier generation is omitted. Similar to the N-type TFT 601N, the P-type TFT 601P includes a source / drain region 603P and a channel region 604P. A gate insulating layer 607 is disposed on the semiconductor layer 606 (source / drain region 603P, channel region 604P). A gate electrode 608P is disposed at a position facing the channel region 604P with the gate insulating layer 607 interposed therebetween, and controls conduction / cutoff of the P-type TFT 601P.

  As shown in FIG. 6A, the gate electrode 608N of the N-type TFT 601N and the gate electrode 608P of the P-type TFT 601P are connected and receive an input signal through the contact 616. One end of the source / drain region 603N and one end of the source / drain region 603P are electrically connected by a metal wiring 610 through a contact 609DN and a contact 609DP. Then, an electrical signal is transmitted to the next stage circuit via the contact 611.

  The other end of the source / drain region 603N is electrically connected to the metal wiring 614N through the contact 612N. And it connects with a power supply via the contact 613N. Similarly, the other end of the source / drain region 603P is electrically connected to the metal wiring 614P through the contact 612P. Then, it is grounded through the contact 613P.

  Next, a method for manufacturing the N-type TFT 601N and the P-type TFT 601P will be described. FIGS. 7A to 7D and FIGS. 8A to 8C are process cross-sectional views for explaining a method for manufacturing the N-type TFT 601N and the P-type TFT 601P.

First, the substrate 602 using light-transmitting glass or the like as a material is washed. Then, after forming a buffer layer 615 using a material such as SiO ₂ , an amorphous silicon layer is formed, and a semiconductor layer 606 made of polysilicon is formed by performing processing such as laser annealing.

  Next, after applying and drying a photoresist layer 703, exposure is performed using a photomask 704. FIG. 7A is a process cross-sectional view in a state where the exposure process is performed. As a light source, i-line of a mercury lamp is used. On the photomask 704, a line & space pattern narrower than the spatial resolution, more specifically, a pattern of about 0.5 μm & 1.0 μm is arranged. This area functions as a semi-transmissive area 705. The semi-transmissive region 705 is disposed in a region corresponding to the source / drain region 603N of the N-type TFT 601N shown in FIG.

  The photomask 704 is subjected to DRC check, LVS check, ERC check and the like including the semi-transmissive region 705. For this reason, the occurrence of missing data confirmation is suppressed. By using this photomask 704, the frequency of occurrence of errors can be reduced, and the photoresist layer 703 can be exposed more reliably.

  Next, after the exposure process is completed, development is performed. A process cross-sectional view after development is shown in FIG. The photoresist layer 703 is left in the region corresponding to the N-type TFT 601N and the P-type TFT 601P shown in FIG. In the region corresponding to the source / drain region 603N of the N-type TFT 601N, which is the region corresponding to the transflective region 705 of the photomask 704, the layer thickness of the photoresist layer 703 is thin. Specifically, the LDD region 605, the source / drain region 603P of the P-type TFT 601P, and the channel region 604P have a layer thickness of 1 μm between the channel region 604N of the N-type TFT 601N shown in FIG. . On the other hand, the thickness of the source / drain region 603N of the N-type TFT 601N is controlled to about 200 nm.

Next, phosphorus ions are implanted. As the acceleration energy, a value of about 50 keV is used, and a dose amount of about 1 × 10 ¹⁵ cm ⁻² is used. With this acceleration energy, phosphorus does not reach the region with a layer thickness of 1 μm, and passes through the region with a layer thickness of 200 nm to form the source / drain region 603N of the N-type TFT 601N. FIG. 7C shows a process cross-sectional view during the ion implantation process.

  Next, the semiconductor layer 606 is etched using the photoresist layer 703 as a mask. By performing dry etching using a chlorine-based gas, the etching selectivity between the photoresist layer 703 and the semiconductor layer 606 (polysilicon) can be increased. Therefore, when the layer thickness is 200 nm, the semiconductor layer 606 can be etched. FIG. 7D shows a process cross-sectional view after this process is completed.

Next, the photoresist layer 703 is removed by ashing, and a gate insulating layer 607 is formed. The gate insulating layer 607 has a thickness of about 100 nm. For example, TEOS (tetraethoxysilane: Si (OC ₃ H ₅ ) ₄ ) is used as a gas, and can be formed at a processing temperature of about 350 ° C. .

  Next, in order to form the gate electrodes 608N and 608P, an electrode layer having a three-layer structure of TiN / Al / Ti is formed by sputtering. It is preferable to use a value of about 100 nm / 400 nm / 50 nm for each layer thickness. After the electrode layer is formed, gate electrodes 608N and 608P are formed by using a photolithography / etching process.

Next, phosphorus ions are implanted using the gate electrodes 608N and 608P as a mask. The LDD region 605 is formed in the N-type TFT 601N by using the acceleration energy of 50 keV and the dose of about 1 × 10 ¹³ cm ⁻² . The structure after this step is shown in FIG.

Next, a photoresist layer 706 is formed on the N-type TFT 601N, and boron ion implantation is performed. The acceleration energy is 30 keV and the dose is about 1 × 10 ¹⁵ cm ⁻² . In this step, a larger amount of boron is ion-implanted into the source / drain region 603P of the P-type TFT 601P than phosphorus implanted to form the LDD region 605 in the N-type TFT 601N. Therefore, the source / drain region 603P of the P-type TFT 601P exhibits a P-type conductivity type having a high concentration. FIG. 8B shows a process cross-sectional view during the ion implantation process.

  Thereafter, the first interlayer insulating layer 707 and the metal wiring layer 709 can be formed using a known manufacturing method, and the N-type TFT 601N and the P-type TFT 601P shown in FIG. 8C can be formed. By using the manufacturing method described above, an error occurs by using a photomask 704 that has been subjected to a mask pattern error check through a DRC check, an LVS check, an ERC check, or the like in the semi-transmissive region 705 (see FIG. 7A). It is possible to provide a manufacturing method of the N-type TFT 601N and the P-type TFT 601P to be suppressed.

(Fourth embodiment: example of mounting on an electronic device)
Next, an electronic device having the above structure will be described. In the present embodiment, for the sake of description of an electronic apparatus that drives and displays liquid crystal using an N-type TFT 601N (see FIG. 6), a cross-sectional structure of a typical liquid crystal panel is described, and then a specific example is given. A typical electronic device will be exemplified.

  FIG. 9 is a cross-sectional view of a liquid crystal panel including a liquid crystal layer. The TFT array substrate 100 is mainly composed of a translucent substrate 602 made of a translucent material such as glass, a pixel electrode 9 formed on the surface of the liquid crystal layer 102, an N-type TFT 601N, and an alignment layer 110. ing. The counter substrate 104 is mainly composed of a counter substrate body 104A made of a translucent material such as glass, a common electrode 108 formed on the surface of the liquid crystal layer 102, and an alignment layer 110.

  Specifically, in the TFT array substrate 100, a buffer layer 615 made of a silicon oxide layer or the like is formed immediately above the substrate 602. Further, a pixel electrode 9 made of a transparent conductive material such as indium tin oxide (ITO) is provided on the surface of the substrate 602 on the liquid crystal layer 102 side, and the potential of each pixel electrode 9 is positioned adjacent to each pixel electrode 9. An N-type TFT 601N is provided to control the above.

  A semiconductor layer 606 made of polycrystalline silicon is formed in a predetermined pattern on the buffer layer 615, and a gate insulating layer 607 made of a silicon oxide layer or the like is formed on the semiconductor layer 606. This gate insulating layer On the gate 607, a gate electrode 608N is formed. In the semiconductor layer 606, a region facing the gate electrode 608N with the gate insulating layer 607 interposed therebetween is a channel region 604N in which a channel is formed by an electric field from the gate electrode 608N.

  In the semiconductor layer 606, a source / drain region 603N is formed so as to sandwich a region where the channel region 604N and the LDD region 605 are combined. An N-type TFT 601N is configured by the gate electrode 608N, the gate insulating layer 607, the source / drain region 603N of the semiconductor layer 606, the LDD region 605, the channel region 604N, and the like.

  In this embodiment, the N-type TFT 601N has an LDD structure, and the source / drain region 603N includes a source / drain region 603N, which is a high concentration region having a relatively high impurity concentration, respectively. An LDD region 605 which is a relatively low concentration region is formed.

  A first interlayer insulating layer 707 made of a silicon oxide layer or the like is formed on the substrate 602 on which the gate electrode 608N is formed, and the data line 6a and the source line 6b are formed on the first interlayer insulating layer 707. Is formed. The data line 6a is electrically connected to one end of the source / drain region 603N (source side) of the semiconductor layer 606 through a contact hole 92 formed in the first interlayer insulating layer 707. The source line 6b The source / drain region 603N (drain side) is electrically connected through the contact hole 94 in which the first interlayer insulating layer 707 is formed.

  A second interlayer insulating layer 5 made of acrylic resin or the like is formed on the first interlayer insulating layer 707 on which the data line 6a and the source line 6b are formed. The pixel electrode 9 is electrically connected to the source line 6 b through a contact hole 96 formed in the second interlayer insulating layer 5.

  Further, the capacitor line 3b is disposed opposite to the extended portion 1f of the semiconductor layer 606 from the source / drain region 603N via an insulating layer integrally formed with the gate insulating layer 607, and these extended portions 1f. A storage capacitor 98 is formed by the capacitor line 3b.

  An alignment layer 110 for controlling the alignment of liquid crystal molecules in the liquid crystal layer 102 is formed on the outermost surface of the TFT array substrate 100 on the liquid crystal layer 102 side.

  On the other hand, in the counter substrate 104, light incident on the liquid crystal device on the surface of the counter substrate main body 104A on the liquid crystal layer 102 side is prevented from entering at least the channel region 604N and the LDD region 605 of the semiconductor layer 606. A light shielding layer 106 is formed. A common electrode 108 made of ITO or the like is formed on almost the entire surface of the counter substrate body 104A on which the light shielding layer 106 is formed, and the liquid crystal molecules in the liquid crystal layer 102 are formed on the liquid crystal layer 102 side. An alignment layer 110 is formed for controlling the alignment.

  FIGS. 10A to 10C are schematic diagrams for explaining an example of mounting an electronic device including the N-type TFT 601N and the P-type TFT 601P shown in FIG. FIG. 10A shows a configuration of a mobile personal computer including an N-type TFT 601N and a P-type TFT 601P. The personal computer 2000 includes an N-type TFT 601N, a P-type TFT 601P, and a main body 2010. The main body 2010 is provided with a power switch 2001 and a keyboard 2002. FIG. 10B shows a configuration of a mobile phone provided with an N-type TFT 601N and a P-type TFT 601P. The cellular phone 3000 includes a plurality of operation buttons 3001 and scroll buttons 3002. 10C shows a configuration of a personal digital assistant (PDA: Personal Digital Assistants) to which the N-type TFT 601N and the P-type TFT 601P are applied. The mobile information terminal 4000 includes a plurality of operation buttons 4001 and a power switch 4002. When the button 4001 is operated, various information such as an address book and a schedule book are processed by the N-type TFT 601N and the P-type TFT 601P.

  Note that electronic devices on which the N-type TFT 601N and the P-type TFT 601P are mounted include those shown in FIG. 10, a digital still camera, a liquid crystal television, a viewfinder type, a monitor direct view type video tape recorder, a car navigation device, a pager, The present invention can be applied to electronic notebooks, calculators, word processors, workstations, videophones, POS terminals, devices equipped with touch panels, and the like.

The flowchart which shows the calculation method of a layout pattern. The top view of the layout pattern used in order to demonstrate a flowchart. The schematic diagram of the computer system which embodies the processing according to a flow chart. (A) is a top view of the photomask which has a translucent area | region, (b) is the sectional view on the A-A 'line of (a). FIG. 10 is a process cross-sectional view for forming a reticle. (A) is a plan view of an inverter using an N-type TFT and a P-type TFT, (b) is a cross-sectional view taken along line AA ′ of (a) of the N-type TFT, and (c) is a diagram of (a) of the P-type TFT. BB 'sectional drawing. (A)-(d) is process sectional drawing for demonstrating the manufacturing method of N type TFT and P type TFT. (A)-(c) is process sectional drawing for demonstrating the manufacturing method of N type TFT and P type TFT. Sectional drawing of a liquid crystal panel. Schematic for demonstrating the example of mounting of the electronic device containing N type TFT and P type TFT.

Explanation of symbols

  1f: Extension portion, 3b: Capacitance line, 5: Second interlayer insulating layer, 6a: Data line, 6b ... Source line, 9 ... Pixel electrode, 92 ... Contact hole, 94 ... Contact hole, 96 ... Contact hole, 98 ... Storage capacitor 102 ... Liquid crystal layer 104 ... Counter substrate 104A ... Counter substrate body 106 ... Light shielding layer 108 ... Common electrode 110 ... Orientation layer 201 ... Layout pattern 202a ... Pattern 202b ... Pattern 203 ... Pattern, 204 ... Pattern, 301 ... Computer system, 302 ... ROM memory, 303 ... RAM, 304 ... Hard disk, 305 ... Keyboard, 306 ... Mouse, 307 ... CPU, 308 ... Display, 401 ... Photomask, 402 ... Quartz substrate, 403 ... Light-shielding layer, 403a ... Light-shielding layer precursor, 404 ... Outer frame, 405 ... 406 ... translucent region, 407 ... reticle, 408 ... EB exposure resist, 408a ... white pattern, 408b ... black pattern, 601N ... N-type TFT, 601P ... P-type TFT, 602 ... substrate, 603N ... source Drain region, 603P ... source / drain region, 604N ... channel region, 604P ... channel region, 605 ... LDD region, 606 ... semiconductor layer, 607 ... gate insulating layer, 608N ... gate electrode, 608P ... gate electrode, 609DN ... contact, 609DP ... contact, 610 ... metal wiring, 611 ... contact, 612N ... contact, 612P ... contact, 613N ... contact, 613P ... contact, 614N ... metal wiring, 614P ... metal wiring, 615 ... buffer layer, 616 ... contact, 703 ... Photo cash register Layer, 704... Photomask, 705... Translucent region, 706... Photoresist layer, 707... First interlayer insulating layer, 709... Metal wiring layer, 2000 ... personal computer, 2001 ... power switch, 2002 ... keyboard, 2010. Main unit, 3000 ... mobile phone, 3001 ... operation button, 3002 ... scroll button, 4000 ... information portable terminal, 4001 ... operation button, 4002 ... power switch.

Claims (16)

A layout pattern calculation method, wherein exposure is performed using a photomask having a pattern according to the layout pattern, and a dimension limit value capable of forming the pattern is treated as a spatial resolution.
A first pattern that includes a first black region, and includes at least part of the first black region including a region having a distance from the white region that is 1/2 or more of the spatial resolution in an arbitrary region;
A shortest distance from the first pattern is a second pattern including a second black region having a value less than the spatial resolution, and is an arbitrary region within the second pattern and is ½ of the spatial resolution. The second pattern in which the white area exists at a distance smaller than the second area, and the second black area exists at a distance smaller than ½ of the spatial resolution from an arbitrary point of the white area. Is placed,
A method of calculating a layout pattern, wherein an area including an OR of the first pattern and the second pattern is handled as one pattern data.   The layout pattern calculation method according to claim 1, wherein the second pattern is a line & space pattern. A layout pattern calculation method according to claim 1 or 2,
Recognizing an OR of the first pattern and the second pattern as one pattern data;
A step (DRC step: Design Rule Check step) of comparing and verifying the layout pattern and the design rule other than in the second pattern;
A method of calculating a layout pattern, comprising: The layout pattern calculation method according to any one of claims 1 to 3, wherein in addition to the DRC step,
A step of verifying whether the layout pattern matches the designed circuit diagram (LVS step: Layout Versus Schematic step);
A layout pattern calculation method comprising: at least one of a step of verifying whether the layout pattern is electrically operated (ERC step: Electrical Rule Check step).   5. The layout pattern calculation method according to claim 1, wherein a ratio of the second black area to the white area is 10% or more and 90% or less. Pattern calculation method.   6. The layout pattern calculation method according to claim 1, wherein the layout pattern has a layout pattern obtained by negative / positive inversion of the layout pattern. When exposure is performed using a photomask having a pattern according to the layout pattern, and a dimension limit value that can form the pattern is treated as a spatial resolution,
A first pattern that includes a first black region, and includes at least part of the first black region including a region having a distance from the white region that is 1/2 or more of the spatial resolution in an arbitrary region;
A shortest distance from the first pattern is a second pattern including a second black region having a value less than the spatial resolution, and is an arbitrary region within the second pattern and is ½ of the spatial resolution. The second pattern in which the white area exists at a distance smaller than the second area, and the second black area exists at a distance smaller than ½ of the spatial resolution from an arbitrary point of the white area. When,
A region including an OR of the first pattern and the second pattern is handled as one pattern data, and is recognized as one pattern data,
A photomask comprising the layout pattern confirmed in a step of performing a comparison verification between the layout pattern and a design rule other than in the second pattern (DRC step: Design Rule Check step). The photomask according to claim 7, wherein in addition to the DRC step,
A step of verifying whether the layout pattern matches the designed circuit diagram (LVS step: Layout Versus Schematic step);
A photomask comprising: a step of verifying whether the layout pattern is electrically operated (ERC step: Electrical Rule Check step).   9. The photomask according to claim 7, wherein the photomask has a layout pattern obtained by negative / positive inversion of the layout pattern. When exposure is performed using a photomask having a pattern according to the layout pattern, and a dimension limit value that can form the pattern is treated as a spatial resolution,
A first pattern that includes a first black region, and includes at least part of the first black region including a region having a distance from the white region that is 1/2 or more of the spatial resolution in an arbitrary region;
A shortest distance from the first pattern is a second pattern including a second black region having a value less than the spatial resolution, and is an arbitrary region within the second pattern and is ½ of the spatial resolution. The second pattern in which the white area exists at a distance smaller than the second area, and the second black area exists at a distance smaller than ½ of the spatial resolution from an arbitrary point of the white area. When,
A region including an OR of the first pattern and the second pattern is handled as one pattern data, and is recognized as one pattern data,
Performing a photolithographic process using a photomask including the layout pattern confirmed in a process (DRC process: Design Rule Check) for comparing and verifying the layout pattern and the design rule other than in the second pattern A method of manufacturing a semiconductor device. It is a manufacturing method of the semiconductor device according to claim 10, Comprising: In addition to the DRC process,
A step of verifying whether the layout pattern matches the designed circuit diagram (LVS step: Layout Versus Schematic step);
Performing a photolithographic process using a photomask including the layout pattern including at least one of processes of verifying whether the layout pattern is electrically operated (ERC process: Electrical Rule Check process). A method of manufacturing a semiconductor device.   12. The method of manufacturing a semiconductor device according to claim 10, wherein a photomask having a layout pattern obtained by negative / positive inversion of the layout pattern is used. When exposure is performed using a photomask having a pattern according to the layout pattern, and a dimension limit value that can form the pattern is treated as a spatial resolution,
A first pattern that includes a first black region, and includes at least part of the first black region including a region having a distance from the white region that is 1/2 or more of the spatial resolution in an arbitrary region;
A shortest distance from the first pattern is a second pattern including a second black region having a value less than the spatial resolution, and is an arbitrary region within the second pattern and is ½ of the spatial resolution. The second pattern in which the white area exists at a distance smaller than the second area, and the second black area exists at a distance smaller than ½ of the spatial resolution from an arbitrary point of the white area. A region including an OR of the first pattern and the second pattern is treated as one pattern data, and recognized as one pattern data,
A photolithographic process is performed using a photomask including the layout pattern confirmed in the process of comparing and verifying the layout pattern and the design rule other than in the second pattern (DRC process: Design Rule Check process). A semiconductor device manufactured by: 14. The semiconductor device according to claim 13, wherein in addition to the DRC process,
A step of verifying whether the layout pattern matches the designed circuit diagram (LVS step: Layout Versus Schematic step);
The layout pattern is manufactured using the photomask having the layout pattern including at least one of a process for verifying whether the layout pattern is electrically operated (ERC process: Electrical Rule Check process). A semiconductor device.   15. The semiconductor device according to claim 13, wherein the semiconductor device is manufactured using a photomask having a layout pattern obtained by negative / positive inversion of the layout pattern.   An electronic device comprising: a semiconductor device manufactured using a photomask obtained by transferring a layout pattern obtained by using the layout pattern calculation method according to claim 1. machine.

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