KR20170076180A - Array Substrate For Touch Display Device And Method Of Fabricating The Same - Google Patents

Abstract

The present invention provides a semiconductor device comprising a substrate, a thin film transistor disposed on the substrate, a planarization layer disposed on the thin film transistor and having an opening corresponding to a drain electrode of the thin film transistor, A first protection layer disposed on the common electrode and including a first contact hole exposing the common electrode, and a second protection layer disposed on the first protection layer, A pixel electrode arranged on the first passivation layer and connected to the drain electrode; and a pixel wiring arranged so as to cover the common wiring on the common wiring, A common electrode is formed directly above the planarization layer and a common electrode and a planarization layer are simultaneously formed using a transflective mask, The manufacturing cost and the manufacturing time are reduced.

Description

[0001] The present invention relates to an array substrate for a touch display device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a touch display device, and more particularly to an array substrate for an in-cell type touch display device in which a touch electrode and wiring are integrated with a display panel and a method of manufacturing the same.

In view of the information age, the display field has also been rapidly developed. As a flat panel display device (FPD) having the advantages of thinning, light weight, and low power consumption in response to the information age, ), A plasma display panel device (PDP), an organic light emitting diode (OLED) display device, and a field emission display device (FED) cathode ray tube (CRT).

Recently, a touch display device (or a touch screen) having a touch panel mounted on a display panel has been spotlighted.

The touch display device is used as an output means for displaying an image and is used as an input means for inputting a user's command by touching a specific portion of the displayed image. The touch panel is operated in accordance with a position information detection method, Method, an infrared method, and an ultrasonic method.

That is, when the user touches the touch panel while viewing the image displayed on the display panel, the touch panel can detect the position information of the corresponding part and compare the detected position information with the position information of the image to recognize the user's command.

In recent years, in order to make a portable terminal such as a smart phone, a tablet PC, and the like slimmer, electrodes and wiring constituting the touch panel are connected to the substrate of the display panel (In-cell type) touch display device in which the touch panel is formed and integrated with the touch panel.

Such an insensitive-type touch display device will be described with reference to the drawings.

1 is a cross-sectional view of a conventional array substrate for an in-cell type touch display device.

1, the conventional array substrate for an in-cell type touch display device includes a substrate 20, a thin film transistor T, a common wiring 44, a common electrode 48, and a pixel electrode 52 do.

Specifically, a light shielding layer 22 is formed on each pixel region on the substrate 20, and a buffer layer 24 is formed on the entire surface of the substrate 20 above the light shielding layer 22.

An active layer 26 is formed on the buffer layer 24 corresponding to the light shielding layer 22 and a gate insulating layer 28 is formed on the entire surface of the substrate 20 above the active layer 26.

A gate electrode 30 is formed on the gate insulating layer 28 corresponding to the active layer 26 and an interlayer insulating layer 32 is formed on the entire surface of the substrate 20 above the gate electrode 30, The layer 32 and the gate insulating layer 28 have contact holes that expose both ends of the active layer 26.

A source electrode 34 and a drain electrode 36 are formed on the upper part of the interlayer insulating layer 32 corresponding to the active layer 26. The source electrode 34 and the drain electrode 36 are formed on the interlayer insulating layer 32, Is connected to both ends of the active layer 26 through contact holes in the gate insulating layer 28 and the gate insulating layer 28.

The active layer 26, the gate electrode 30, the source electrode 34 and the drain electrode 36 constitute a thin film transistor (TFT) T, and the light shielding layer 22 is a thin film transistor And blocks the light that is incident on the active layer 26 of the pixel T.

A first passivation layer 38 is formed on the entire surface of the substrate 20 above the source electrode 34 and the drain electrode 36. A planarization layer 40 is formed on the entire surface of the substrate 20 above the first passivation layer 38, The planarization layer 40 has an opening exposing the first passivation layer 38 on the drain electrode 36. [

A second protective layer 42 is formed on the entire surface of the substrate 20 above the planarization layer 40 and a common wiring 44 is formed on the second protective layer 42.

A third passivation layer 46 is formed on the entire surface of the substrate 20 above the common wiring 44. The third passivation layer 46 has a contact hole exposing the common wiring 44. [

A common electrode 48 is formed in each pixel region on the third passivation layer 46 and the common electrode 48 is connected to the common wiring 44 through the contact hole of the third passivation layer 46.

A fourth protective layer 50 is formed on the entire surface of the substrate 20 above the common electrode 48. The fourth protective layer 50, the third protective layer 46, the second protective layer 42, The protective layer 38 has a contact hole exposing the drain electrode 36 in the opening of the planarization layer 40.

A pixel electrode 52 is formed in each pixel region on the fourth passivation layer 50. The pixel electrode 52 includes a fourth passivation layer 50, a third passivation layer 46, a second passivation layer 42 And the contact hole of the first passivation layer 38, as shown in Fig.

Here, the common electrode 48 may be patterned for each touch block including a specific number of pixel regions, and the common electrode 48 of each touch block may be independently connected to the driver through the common line 44.

The pixel electrodes 52 may have a plurality of bar shapes spaced apart from each other.

A conventional in-cell type touch display device including such an array substrate can operate by dividing one frame into a display period and a touch period. During the display period, a common voltage is applied to the common electrode 48, A data voltage is applied to display an image by rearranging the liquid crystal layer by an electric field generated between the common electrode 48 and the pixel electrode 52. During the touch period, a touch voltage is applied to the common electrode 48, The position of the touch input can be sensed by analyzing the change of capacitance of the common electrode 48 according to the voltage.

In the conventional array substrate for an in-cell type touch display device, the common wiring 44 and the common electrode 48 of the same touch block are connected to each other. However, the common wiring 44 and the common electrode 48 of the different touch blocks, It is necessary to form the common wiring 44 and the common electrode 48 by patterning them in different layers independently of each other.

In order to prevent the common wiring 44 and the common electrode 48 of the different touch blocks from being affected by coupling or the like, a third protective layer 46 The contact hole should be formed by patterning the third passivation layer 46 to connect the common wiring 44 and the common electrode 48 of the same touch block formed of different layers.

The thickness of the dielectric layer between the common electrode 48 and the pixel electrode 52 forming the storage capacitor must be minimized so that only one insulating layer is formed in a cross sectional area The common electrode 48 and the pixel electrode 52 should be formed.

Such a limitation has a problem in that the number of exposure masks used in the fabrication of the conventional array substrate for an in-cell type touch display device increases.

For example, in a conventional array substrate for an in-cell type touch display device, a first mask for the light-shielding layer 22, a second mask for the active layer 26, a third mask for the gate electrode 30, an interlayer insulating layer 32 A fourth mask for the contact hole of the gate insulating layer 28, a fifth mask for the source electrode 34 and the drain electrode 36, a sixth mask for the opening of the planarization layer 40, 7 mask, the eighth mask for the contact hole of the third protective layer 46, the ninth mask for the common electrode 48, the fourth protective layer 50, the third protective layer 46, the second protective layer 42, The tenth mask for the contact hole of the first protective layer 38, and the eleventh mask for the pixel electrode 52, so that the manufacturing steps are increased and the manufacturing cost and the manufacturing time There is an increasing problem.

SUMMARY OF THE INVENTION The present invention has been made in order to solve such a problem, and it is an object of the present invention to provide a method of manufacturing a semiconductor device, in which a common electrode is formed directly above a planarization layer, and a common electrode and a planarization layer are formed simultaneously using a transflective mask, And an object of the present invention is to provide an array substrate for a touch display device and a manufacturing method thereof.

The present invention provides a touch display device in which common wirings and pixel electrodes are continuously formed and pixel wirings are formed immediately above common wirings, the number of exposure masks is reduced, manufacturing cost and manufacturing time are reduced, It is an object of the present invention to provide an array substrate and a method of manufacturing the same.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a substrate; a thin film transistor disposed on the substrate; a planarization layer disposed on the thin film transistor and having an opening corresponding to a drain electrode of the thin film transistor; A first protective layer disposed over the planarization layer and including a first contact hole disposed on the common electrode and exposing the common electrode; and a second protection layer disposed on the first protection layer, A common electrode connected to the common electrode through a contact hole; a pixel electrode disposed on the first protective layer and connected to the drain electrode; and a pixel wiring arranged to cover the common wiring on the common wiring The present invention also provides an array substrate for a touch display device.

The first passivation layer may further include a second contact hole exposing the drain electrode, and the pixel electrode may be connected to the drain electrode through the second contact hole.

The array substrate for a touch display device may further include a connection pattern in contact with the drain electrode through the second contact hole and in contact with the pixel electrode.

The common wiring and the connection pattern may be formed of the same layer and the same material.

The array substrate for a touch display device may further include a light shielding layer disposed on the substrate corresponding to the thin film transistor, a buffer layer disposed between the light shielding layer and the thin film transistor, and a buffer layer disposed between the thin film transistor and the planarization layer. And a second protective layer disposed thereon.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor comprising the steps of: forming a thin film transistor on a substrate; forming a planarization layer on the thin film transistor including an opening corresponding to a drain electrode of the thin film transistor; Forming a first passivation layer including a first contact hole exposing the common electrode on the common electrode, forming a second passivation layer on the common electrode through the first contact hole, Forming a common wiring to be connected to the pixel electrode; forming a pixel wiring connected to the drain electrode on the first protection layer; and forming a pixel wiring covering the common wiring over the common wiring, A method of manufacturing an array substrate is provided.

The step of forming the planarization layer and the common electrode may include forming the planarization layer and the common electrode material layer on the top of the thin film transistor, Wherein the common electrode material layer is exposed in a region corresponding to the drain electrode and has a first thickness in a region corresponding to the common electrode and in a region corresponding to the planarization layer exposed to the outside of the common electrode, Forming a common electrode pattern and the openings by etching the common electrode material layer and the planarization layer using the first photoresist pattern as an etch mask; A step of ashing the first photoresist pattern to correspond to the planarization layer exposed to the outside of the common electrode, Forming a second photoresist pattern exposing the common electrode pattern in a region corresponding to the common electrode and forming a second photoresist pattern having a third thickness in a region corresponding to the common electrode, And forming the common electrode by etching.

The first passivation layer may further include a second contact hole exposing the drain electrode, and the pixel electrode may be connected to the drain electrode through the second contact hole.

The step of forming the common interconnection may include forming a connection pattern that contacts the drain electrode through the second contact hole.

The manufacturing method of the array substrate for a touch display device may further include forming a light shielding layer on the substrate corresponding to the thin film transistor, forming a buffer layer between the light shielding layer and the thin film transistor, And forming a second passivation layer between the transistor and the planarization layer.

According to the present invention, by forming the common electrode directly above the planarization layer and simultaneously forming the common electrode and the planarization layer using the semi-transparent mask, the number of exposure masks is reduced, and manufacturing cost and manufacturing time are reduced.

Further, the present invention has the effect of reducing the number of exposure masks, reducing the manufacturing cost and the manufacturing time, and preventing the corrosion of the common wiring by continuously forming the common wiring and the pixel electrode and forming the pixel wiring directly above the common wiring .

1 is a cross-sectional view of a conventional array substrate for an in-cell type touch display device.
2 is a plan view of a self-capacitance-type in-cell type touch display device according to an embodiment of the present invention;
3 is a cross-sectional view of an array substrate for a self-capacitance type in-cell type touch display device according to an embodiment of the present invention.
4A to 4I are sectional views for explaining a manufacturing method of an array substrate for a self-capacitance type in-cell type touch display device according to an embodiment of the present invention.

Hereinafter, an array substrate for an in-cell type touch display device and a method of manufacturing the same will be described with reference to the accompanying drawings.

FIG. 2 is a plan view of a self-capacitance type in-cell type touch display device according to an embodiment of the present invention. FIG. 3 is a cross-sectional view of a self- Sectional view of the array substrate.

2, the self-capacitance type in-cell type touch display apparatus according to the embodiment of the present invention includes a touch display panel 110 and a driving unit 180.

The touch display panel 110 includes a plurality of common electrodes 142 disposed on each touch block on the substrate 120 and a plurality of common electrodes 142 connecting the common electrodes 142 and the driving units 180 And the common wiring 146. The common electrodes 142 of each touch block may have a rectangular shape.

Although not shown, the touch display panel 110 may be a liquid crystal panel including two substrates spaced apart from each other and a liquid crystal layer between two substrates, and the plurality of common electrodes 142 may be formed of two substrates The touch display panel 110 may perform a display operation using a common voltage or perform a touch operation using a touch voltage.

The driving unit 180 applies a common voltage to a plurality of common electrodes 142 of the touch display panel 110 during a display period of one frame and generates a common voltage between the common electrode 142 and the pixel electrode The liquid crystal molecules of the liquid crystal layer are rearranged into an electric field to display an image or a touch voltage is applied to a plurality of common electrodes 142 of the touch display panel 110 during a touch period of one frame, The position of the touch input is sensed by analyzing the change of the capacitance of the common electrode 142. [

The driving unit 180 may further supply a gate voltage and a data voltage to the touch display panel 110 for a display operation.

3, an array substrate for an in-cell type touch display device of the self-capacitance type according to the embodiment of the present invention includes a substrate 120, a thin film transistor T, a common electrode 142, 146 and a pixel electrode 150. The substrate 120 may be one of two substrates constituting a liquid crystal panel.

Specifically, a light shielding layer 122 is formed on each pixel region on the substrate 120, and a buffer layer 124 is formed on the entire surface of the substrate 120 above the light shielding layer 122.

The light shielding layer 122 is for blocking light incident on the active layer 126 of the thin film transistor T and may include at least one of an opaque metal material, an opaque organic material, and an opaque semiconductor material, for example. have.

An active layer 126 is formed on the buffer layer 124 corresponding to the light shielding layer 122 and a gate insulating layer 128 is formed on the entire surface of the substrate 120 over the active layer 126.

The active layer 126 may be formed of silicon such as amorphous silicon, polycrystalline silicon, indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), zinc indium And an oxide semiconductor material such as zinc indium oxide (ZIO).

A gate electrode 130 is formed on the gate insulating layer 128 corresponding to the active layer 126 and an interlayer insulating layer 132 is formed on the entire surface of the substrate 120 over the gate electrode 130. In the interlayer insulating layer 132, The layer 132 and the gate insulating layer 128 have contact holes that expose both ends of the active layer 126.

A source electrode 134 and a drain electrode 136 are formed on the interlayer insulating layer 132 corresponding to the active layer 126. The source electrode 134 and the drain electrode 136 are formed on the interlayer insulating layer 132, Is connected to both ends of the active layer 126 through the contact holes of the gate insulating layer 132 and the gate insulating layer 128.

Here, the active layer 126, the gate electrode 130, the source electrode 134, and the drain electrode 136 constitute a thin film transistor (TFT) T.

A first passivation layer 138 is formed on the entire surface of the substrate 120 on the source electrode 134 and the drain electrode 136 and a planarization layer 140 is formed on the entire surface of the substrate 120 over the first passivation layer 138. [ The planarization layer 140 has an opening exposing the first passivation layer 138 on the drain electrode 136.

The first passivation layer 138 may be formed of an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiN x), and the planarization layer 140 may be formed of an organic insulating material such as photo acryl have.

The first passivation layer 138 is used to improve the contact characteristics between the planarization layer 140 of the organic insulating material and the source electrode 134 and the drain electrode 136 of the metal material. In the embodiment, the first protective layer 138 may be omitted.

A common electrode 142 is formed on the planarization layer 140 and a second protection layer 144 is formed on the entire surface of the substrate 120 above the common electrode 142. The second protection layer 144 is formed on the common electrode 142, And the second passivation layer 144 and the first passivation layer 138 have contact holes exposing the drain electrodes 136. [

The common electrode 142 is made of a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) ) it may be formed of an inorganic insulating material such as silicon oxide (SiO ₂₎ or silicon nitride (SiNx).

A common wiring 146 and a connection pattern 148 are formed on the second passivation layer 144 corresponding to the common electrode 142 and the drain electrode 136, 144 and the connection pattern 148 is connected to the drain electrode 136 through the contact holes of the second passivation layer 144 and the first passivation layer 138 .

The common wiring 146 and the connection pattern 148 may be formed of a single layer or multiple layers of a metal conductive material such as aluminum (Al), molybdenum (Mo), titanium (Ti), neodymium (Nd)

The connection pattern 148 may be omitted and the pixel electrode 150 may be connected to the drain electrode 136. The connection pattern 148 may be formed on the drain electrode 136, Or may be directly contacted.

A pixel electrode 150 is formed on the second protective layer 144 corresponding to the connection pattern 148 and the common electrode 142 and a pixel wiring 152 is formed on the common wiring 146.

The pixel electrode 150 and the pixel wiring 152 may be made of a transparent conductive material such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO) .

The pixel wiring 152 is formed so as to completely cover the common wiring 146 to protect the common wiring 146 and to prevent corrosion of the common wiring 146. The common wiring 146 may be formed in multiple layers The thickness of the lowermost layer of the multilayer is formed to be smaller than the thickness of the pixel electrode 150 and the pixel wiring 152 so that the pixel electrode 150 and the pixel wiring 152 are not cut off by the step of the common wiring 146 .

For example, when the pixel electrode 150 and the pixel wiring 152 are formed of ITO (about 50 nm), the common wiring 146 is formed of Mo (about 20 nm) / Al (about 300 nm) / Mo ). ≪ / RTI >

Here, the common electrode 142 may be patterned for each touch block including a specific number of pixel regions, and the common electrode 142 of each touch block is connected to the driving portion (FIG. 2 180 < / RTI >

The pixel electrode 150 may have a plurality of bar shapes spaced apart from each other and a horizontal electric field may be generated between the common electrode 142 and the pixel electrode 150 by a common voltage and a data voltage.

As described above, in the array substrate for the in-cell type touch display device of the self-capacitance type according to the embodiment of the present invention, the common electrode 142 and the planarization layer 140 are formed simultaneously with one transflective mask, The contact hole for connecting the drain electrode 150 and the drain electrode 136 and the contact hole for connecting the common electrode 146 and the common electrode 142 are simultaneously formed with one exposure mask, It is possible to reduce the number of masks, which will be described with reference to the drawings.

4A to 4I are cross-sectional views for explaining a manufacturing method of an array substrate for a self-capacitance type in-cell type touch display device according to an embodiment of the present invention.

As shown in FIG. 4A, a light-shielding layer (not shown) is formed on the substrate 120 using at least one of an opaque metal material, an opaque organic material, and an opaque semiconductor material, A light shielding layer 122 is formed on the substrate 120 through a photolithographic process using a first mask including development and etching of the light-shielding layer.

4B, a buffer layer 124 is formed of an insulating material on the entire surface of the substrate 120 above the light-shielding layer 122, and then an active layer is formed on the buffer layer 124 using one of silicon and oxide semiconductor materials. A material layer (not shown) is formed, and a photoresist layer is formed on the buffer layer 124 corresponding to the light-shielding layer 122 through a photolithography process using a second mask including exposure and development and etching of the active material layer An active layer 126 is formed.

A gate insulating layer 128 is formed of an insulating material on the entire surface of the substrate 120 on the active layer 126 and then a gate insulating layer 128 is formed on the gate insulating layer 128 using a metal material, A gate insulating layer 128 corresponding to the active layer 126 is formed through a photolithography process using a third mask including forming a layer (not shown) and exposing and developing the photoresist layer and etching the gate material layer The gate electrode 130 is formed.

4D, an interlayer insulating layer 132 is formed of an insulating material on the entire surface of the substrate 120 over the gate electrode 130, and exposure and development of the photoresist layer and development of the interlayer insulating layer 132 and gate A contact hole exposing both ends of the active layer 126 is formed in the interlayer insulating layer 132 and the gate insulating layer 128 through a photolithography process using a fourth mask including etching of the insulating layer 128.

As shown in FIG. 4E, a metal material layer (not shown) is formed on the interlayer insulating layer 132 using a metal material, and a fifth layer including a photoresist layer, A source electrode 134 and a drain electrode 136 spaced apart from each other are formed on the interlayer insulating layer 132 corresponding to the active layer 126 through a photolithography process using a mask.

At this time, the source electrode 134 and the drain electrode 136 are connected to both ends of the active layer 126 through the contact holes of the interlayer insulating layer 132 and the gate insulating layer 128, respectively.

A first protective layer 138 is formed on the entire surface of the substrate 120 over the source electrode 134 and the drain electrode 136 using an inorganic insulating material and then an organic insulating material is used A planarization layer 140 is formed on the entire surface of the substrate 120 on the first protective layer 138 and a common electrode material layer (not shown) is formed on the planarization layer 140 using a transparent conductive material do.

A drain electrode 136 (not shown) is formed in the planarization layer 140 through a photolithography process using a sixth mask including exposure, development, ashing of the photoresist layer, ashing and planarization layer 140 and etching of the common electrode material layer. And a common electrode 142 is formed on the planarization layer 140. The common electrode 142 is formed on the upper surface of the planarization layer 140,

Specifically, a planarization layer 140 and a common electrode material layer are sequentially formed, a photoresist layer (not shown) is formed on the common electrode material layer, and a sixth mask is disposed on the photoresist layer.

At this time, the sixth mask has a semi-transmissive area (A) for passing ultraviolet rays, a shielding area (C) for shielding ultraviolet rays, and a semi-transmissive area (B) The transmissive region A corresponds to the opening of the planarization layer 140 (that is, corresponds to the drain electrode 136), and the blocking region C corresponds to the common electrode 142 And the semi-transmissive region B corresponds to the planarization layer 140 exposed to the outside of the common electrode 142. In this case,

Then, a photoresist layer is exposed by irradiating ultraviolet rays through a transflective mask, and the exposed photoresist layer is developed to form a first photoresist pattern. The photoresist layer corresponding to the transmissive area A of the transflective mask The photoresist layer corresponding to the blocking region C of the transflective mask remains intact and the photoresist layer corresponding to the transflective region B of the transflective mask is partially removed and partly remained .

Accordingly, the first photoresist pattern exposes the common electrode material layer in the region corresponding to the drain electrode 136, has a first thickness in the region corresponding to the common electrode 142, and exposes to the outside of the common electrode 142 And a second thickness less than the first thickness in a region corresponding to the planarization layer (140).

Thereafter, the common electrode material layer is etched using the first photoresist pattern as an etching mask to form a common electrode pattern (not shown) exposing the planarization layer 140 corresponding to the drain electrode 136 The planarization layer 140 is continuously etched to form openings in the planarization layer 140 to expose the first passivation layer 138 over the drain electrode 136. [

For example, the common electrode material layer of the transparent conductive material may be etched by wet etching, and the planarization layer 140 of the organic insulating material may be etched by dry etching.

Thereafter, the first photoresist pattern is ashed to form the second photoresist pattern. The first photoresist pattern having the first thickness corresponding to the blocking region C of the semi-transmissive mask is partially removed and partially remains , The first photoresist pattern having the second thickness corresponding to the transflective region (B) of the semi-transparent mask is completely removed.

The second photoresist pattern exposes the common electrode pattern of the region corresponding to the planarization layer 140 exposed to the outside of the common electrode 142 and the first protective layer 138 above the drain electrode 136, Which is a value obtained by subtracting the second thickness from the first thickness in the region corresponding to the electrode 142.

Thereafter, the common electrode 142 is formed by etching the common electrode pattern using the second photoresist pattern as an etching mask.

For example, the common electrode pattern of the transparent conductive material can be etched by wet etching.

As described above, after the planarization layer 140 and the common electrode material layer are continuously formed on the first protective layer 138, the opening of the planarization layer 140 and the common electrode layer (142) can be formed at the same time, and as a result, the number of exposure masks can be reduced.

The second protective layer 144 is formed on the entire surface of the substrate 120 above the common electrode 142 by using an inorganic insulating material and then exposed and developed in the photoresist layer, The common electrode 142 is formed on the second passivation layer 144 through the photolithography process using the seventh mask including the etching of the first passivation layer 144 and the etching of the second passivation layer 144 and the first passivation layer 138 And a contact hole exposing the drain electrode 136 to the second passivation layer 144 and the first passivation layer 138 is formed.

As shown in FIG. 4H, a common wiring material layer (not shown) is formed on the second passivation layer 144 using a metal material, and exposure and development of the photoresist layer and etching of the common wiring material layer A common wiring 146 and a connection pattern 148 are formed on the second passivation layer 144 corresponding to the common electrode 142 and the drain electrode 136 through a photolithography process using an eighth mask.

The common wiring 146 and the connection pattern 148 are formed of the same layer and the same material and the common wiring 146 is connected to the common electrode 142 through the contact hole of the second protection layer 144, The connection pattern 148 is connected to the drain electrode 136 through the contact holes of the second passivation layer 144 and the first passivation layer 138.

A pixel electrode material layer (not shown) is formed on the common wiring 146 and the connection pattern 148 and the second passivation layer 144 using a transparent conductive material, And the second passivation layer 144 is formed on the connection pattern 148 and the common electrode 142 through a photolithography process using a ninth mask including the exposure and development of the pixel electrode material layer, And a pixel wiring 152 is formed on the common wiring 146. [

The pixel electrode 150 is connected to the drain electrode 136 through the connection pattern 148 and the pixel wiring 152 is formed so as to completely cover the common wiring 146 to protect the common wiring 146, Thereby preventing the wiring 146 from being corroded.

As described above, the pixel electrode 150 directly contacts the connection pattern 148 connected to the drain electrode 136, so that the second passivation layer 144 for connection between the pixel electrode 150 and the drain electrode 136 And the contact hole of the first passivation layer 138 and the contact hole of the second passivation layer 144 for the connection of the common wiring 146 and the common electrode 142 can be formed simultaneously with the seventh mask, As a result, the number of exposure masks can be further reduced.

As described above, in the array substrate for the in-cell type touch display device of the self-capacitance type according to the embodiment of the present invention, the common electrode 142 and the planarization layer 140 are formed simultaneously with one transflective mask, A contact hole for connecting the common electrode line 150 and the drain electrode 136 and a contact hole for connecting the common line 146 and the common electrode 142 are simultaneously formed with one exposure mask, Can be reduced from 11 to 9 in total, resulting in a reduction in manufacturing cost and manufacturing time.

The pixel wiring 152 covers the common wiring 146 completely, thereby preventing the common wiring 146 from being corroded. As a result, reliability and stability can be improved.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It can be understood that

110: touch display panel 120: substrate
T: thin film transistor 140: planarization layer
142: common electrode 146: common wiring
150: pixel electrode

Claims (10)

Claims [1]
A thin film transistor disposed on the substrate;
A planarization layer disposed on the thin film transistor and having an opening corresponding to a drain electrode of the thin film transistor;
A common electrode disposed on the planarization layer;
A first protective layer disposed on the common electrode and including a first contact hole exposing the common electrode;
A common line disposed on the first passivation layer and connected to the common electrode through the first contact hole;
A pixel electrode disposed on the first passivation layer and connected to the drain electrode;
And a common wiring, the pixel wiring
And an array substrate for a touch display device.
The method according to claim 1,
Wherein the first protective layer further includes a second contact hole exposing the drain electrode,
And the pixel electrode is connected to the drain electrode through the second contact hole.
3. The method of claim 2,
And a connection pattern in contact with the drain electrode through the second contact hole and in contact with the pixel electrode.
The method of claim 3,
Wherein the common wiring and the connection pattern are made of the same layer and the same material.
The method according to claim 1,
A light shielding layer disposed on the substrate corresponding to the thin film transistor;
A buffer layer disposed between the light-shielding layer and the thin film transistor;
A second protective layer disposed between the thin film transistor and the planarization layer,
Further comprising: an array substrate for a touch display device;
Forming a thin film transistor on the substrate;
Forming a planarization layer on the thin film transistor, the planarization layer including an opening corresponding to a drain electrode of the thin film transistor, and a common electrode disposed on the planarization layer;
Forming a first protective layer on the common electrode, the first protective layer including a first contact hole exposing the common electrode;
Forming a common wiring on the first passivation layer through the first contact hole and connected to the common electrode;
A pixel electrode connected to the drain electrode on the first passivation layer, and a pixel wiring covering the common wiring on the common wiring
And forming a pattern on the substrate.
The method according to claim 6,
Wherein the step of forming the planarization layer and the common electrode comprises:
Sequentially forming the planarization layer and the common electrode material layer on the thin film transistor;
Wherein the common electrode material layer is exposed on the common electrode material layer in a region corresponding to the drain electrode using a transflective mask and has a first thickness in a region corresponding to the common electrode, Forming a first photoresist pattern having a second thickness smaller than the first thickness in a region corresponding to the exposed planarization layer;
Etching the common electrode material layer and the planarization layer using the first photoresist pattern as an etch mask to form a common electrode pattern and the openings;
The first photoresist pattern is ashed to expose the common electrode pattern in a region corresponding to the planarization layer exposed to the outside of the common electrode, and a second photoresist having a third thickness in a region corresponding to the common electrode, Forming a pattern;
Etching the common electrode pattern using the second photoresist pattern as an etching mask to form the common electrode
And forming a pattern on the substrate.
The method according to claim 6,
Wherein the first protective layer further includes a second contact hole exposing the drain electrode,
And the pixel electrode is connected to the drain electrode through the second contact hole.
9. The method of claim 8,
Wherein forming the common wiring includes:
And forming a connection pattern in contact with the drain electrode through the second contact hole.
The method according to claim 6,
Forming a light shielding layer on the substrate corresponding to the thin film transistor;
Forming a buffer layer between the light-shielding layer and the thin film transistor;
Forming a second passivation layer between the thin film transistor and the planarization layer
The method comprising the steps of:

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