JP2009164374A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain a semiconductor device using a MESFET which obtains desired carrier mobility and drain current, is operated to produce a high output and reduces a gate leakage current. <P>SOLUTION: The semiconductor device 20 according to one embodiment of the invention comprises a semiconductor substrate 2 of a first conductivity type, a drain region 3 and a source region 3 of a second conductivity type formed on the semiconductor substrate 2, a channel region 4 which is formed on the semiconductor substrate 2 between the drain region 3 and the source regions 3 and which is made of two or more semiconductor layers of the first conductivity type, and a gate electrode 5 which is formed on the channel region 4 to form a Schottky contact with the channel region 4. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a MESFET.

  As a transistor used in a semiconductor device, a metal-semiconductor field effect transistor (MESFET) is widely known. FIG. 4 is a diagram showing a configuration of a semiconductor device 50 including a conventional MESFET. The semiconductor device 50 is formed on the insulating substrate 1 and the insulating substrate 1, the buffer layer 2 made of a semiconductor layer containing p-type impurities, and the source / drain region 3 made of an n-type semiconductor layer formed on the buffer layer 2. A channel region 4 formed on the buffer layer 2 and between the source region and the drain region and formed of an n-type semiconductor layer; and a gate electrode 5 formed of metal on the channel region 4. The MESFET in the semiconductor device 50 includes a buffer layer 2, a source / drain region 3, a channel region 4, and a gate electrode 5.

  In this MESFET, the width of a channel, which is a carrier path, is controlled by a depletion layer formed immediately below the Schottky junction interface, and the current flowing between the drain and the source is controlled by the voltage applied to the gate. Such MESFET is disclosed in Non-Patent Document 1 below.

Hirotaka Motoyama, “VLSI LSI Encyclopedia”, Science Forum Co., Ltd., March 31, 1988, 1st edition, 1st edition, P.414, “Schottky (barrier) gate field effect transistor”

  A conventional MESFET has a configuration using a single semiconductor layer as a channel region, and controls a depletion layer formed in the channel region by a gate voltage and controls a drain current during MESFET operation. However, since the semiconductor single layer film is used for the channel region, even if the gate voltage is adjusted to eliminate the depletion layer width, the carrier path cross-sectional area becomes constant. Therefore, the drain current is also saturated, and a further increase in the drain current cannot be expected. As described above, the conventional MESFET has a problem that a desired carrier mobility and drain current cannot be obtained because the channel region is composed of a single layer.

  In addition, since there is no barrier layer between the channel layer and the gate electrode, there is a problem in that the gate leakage current increases, thereby deteriorating the movement of electrons in the channel and the transistor operation is not improved.

  Therefore, the present invention has been made to solve such a problem, and can obtain a desired carrier mobility and drain current, can operate at a high output, and can reduce gate leakage current. An object of the present invention is to obtain a semiconductor device including a MESFET that can be used.

  A semiconductor device according to an embodiment of the present invention includes a first conductive type semiconductor substrate, a drain region and a source region formed on the semiconductor substrate, each including a second conductive type semiconductor layer, and the drain on the semiconductor substrate. A channel region formed between two or more semiconductor layers of the second conductivity type formed between the region and the source region; and a gate electrode formed on the channel region and in Schottky contact with the channel region.

  According to the semiconductor device in one embodiment of the present invention, the channel region includes two or more semiconductor layers. Therefore, by controlling the gate voltage, it is possible to select an appropriate channel layer such as mobility and band gap on the semiconductor properties, so that desired carrier mobility and drain current can be obtained, and high output operation is achieved. can do.

  In addition, by forming a barrier layer in the uppermost layer of the channel region, the gate leakage current can be reduced and the movement of electrons in the channel can be improved.

<Embodiment 1>
FIG. 1 is a diagram showing a configuration of a semiconductor device 20 including a MESFET according to the first embodiment of the present invention. The semiconductor device 20 according to the present embodiment is formed on the insulating substrate 1 and the insulating substrate 1, and is formed on the buffer layer 2 and the buffer layer 2 made of, for example, a Si semiconductor containing p-type (first conductivity type) impurities. For example, a source / drain region 3 made of an n-type (second conductivity type) Si semiconductor layer and a channel formed on the buffer layer 2 between the source / drain regions 3 and made of two or more n-type semiconductor layers. The gate electrode 5 formed on the region 4 and the channel region 4 and making Schottky contact with the channel region 4 is provided. In the present embodiment, the channel region 4 is formed of three layers of the Si layer 6 / SiGe layer 7 / InAs layer 8 from the lower layer. The MESFET in the semiconductor device 20 includes a buffer layer 2 (semiconductor substrate), a source / drain region 3, a channel region 4 (Si layer 6 / SiGe layer 7 / InAs layer 8), and a gate electrode 5.

Here, the mobility of the Si metal in the Si layer 6 is 1350 cm ² / V · S. The mobility of SiGe metal in the SiGe layer 7 is about 1350 to 3600 cm ² / V · S. The mobility of InAs metal in the InAs layer 6 is about 33000 cm ² / V · S. That is, the channel region 4 has a configuration in which mobility is increased from the lower layer.

  Next, the operation of the semiconductor device 20 (MESFET) will be described. As described above, the semiconductor device 20 (MESFET) has the channel region 4 between the source / drain regions 3 formed of the diffusion layers. The channel region 4 is formed of the same conductivity type as the source / drain region 3. A metal forming a Schottky junction is in direct contact with the channel region 4, and this metal becomes the gate electrode 5.

  Since the channel region 4 is formed with the same conductivity type as the source / drain region 3, when a potential difference is applied between the source and drain, a region that is not depleted in the channel region 4 becomes a conductive region and a current flows. That is, by applying a forward gate voltage to the Schottky junction, the width of the depletion layer of the channel region 4 decreases from the lowermost layer side. As a result, this conductive region increases and the channel current increases. As described above, the semiconductor device 20 realizes the transistor operation by controlling the channel current with the gate voltage.

  Further, the channel region 4 in this embodiment is formed by three layers of Si layer 6 / SiGe layer 7 / InAs layer 8, and the region not depleted from the lowest layer is controlled by controlling the gate voltage. Thus, a layer to be a conductive region can be selected. That is, when a small drain current is desired to flow, the gate voltage is adjusted so that only the Si layer 6 becomes a conductive region. When it is desired to increase the drain current, the gate voltage is adjusted so that the three layers of the Si layer 6 / SiGe layer 7 / InAs layer 8 become conductive regions.

  As described above, the channel region 4 of the semiconductor device 20 in this embodiment includes two or more semiconductor layers and has a structure in which mobility is increased from the lower layer, so that a depletion layer is formed with a voltage applied to the gate. By controlling and controlling the channel layer which is a path of carriers, desired carrier mobility and drain current can be obtained. In addition, since the InAs layer 8 having high mobility is provided in the uppermost layer of the channel layer, the carrier mobility increases as the channel layer through which carriers pass becomes the uppermost layer, and a high drain current can be obtained.

  Further, since the Si layer 6 having a low mobility is provided in the lowermost carrier layer, when the ON current is applied, the depletion layer width decreases, and the overshoot of the drain current at the moment when the drain current starts flowing can be reduced.

<Embodiment 2>
FIG. 2 is a diagram showing a configuration of the semiconductor device 30 including the MESFET according to the second embodiment of the present invention. The channel region 4 of the semiconductor device 30 (MESFET) in the present embodiment is formed of three layers of the Si layer 6 / SiGe layer 7 / GaAs layer 9 from the lower layer. The gate electrode 5 is made of Pt metal. Since other configurations are the same as those of the first embodiment, description thereof is omitted.

Here, the mobility and band gap of the Si metal in the Si layer 6 are 1350 cm ² / V · S, 1.11 eV. The mobility and band gap of SiGe metal in the SiGe layer 7 are about 1350 to 3600 cm ² / V · S, 0.66 to 1.11 eV. The mobility and band gap of GaAs metal in the GaAs layer 9 are 8500 cm ² / V · S, 1.42 eV. That is, the channel region 4 has a structure in which mobility is increased from the lower layer and a GaAs layer 9 having a large band gap is formed in the uppermost layer. Since the operation of the semiconductor device 30 is the same as that of the semiconductor device 20 in the first embodiment, the description thereof is omitted.

  As described above, since the semiconductor device 30 according to the present embodiment includes the GaAs barrier layer having a large band gap on the surface of the channel layer, the leakage current of the gate is reduced and the movement of electrons in the channel can be improved. . Further, since the gate electrode 5 is made of Pt metal having a high Schottky barrier barrier, the potential barrier can be increased to 0.85 eV, and the gate leakage current can be further reduced.

  In addition, the channel region of the semiconductor device 30 in the present embodiment includes two or more semiconductor layers and is formed so as to have high mobility from the lower layer, and the Si layer 6 having low mobility is formed in the lowermost carrier layer. Therefore, the same effects as those of the semiconductor device 20 in the first embodiment can be obtained.

<Embodiment 3>
FIG. 3 is a diagram showing a configuration of the semiconductor device 40 including the MESFET according to the third embodiment of the present invention. The channel region 4 of the semiconductor device 40 (MESFET) in the present embodiment is formed of three layers of the Si layer 6 / SiGe layer 7 / GaN layer 10 from the lower layer. The gate electrode 5 is made of Pt metal. Since other configurations are the same as those of the first embodiment, description thereof is omitted.

Here, the mobility and band gap of the Si metal in the Si layer 6 are 1350 cm ² / V · S, 1.11 eV. The mobility and band gap of SiGe metal in the SiGe layer 7 are about 1350 to 3600 cm ² / V · S, 0.66 to 1.11 eV. The mobility and band gap of GaN metal in the GaN layer 10 are 600 cm ² / V · S, 3.44 eV. That is, the channel region 4 has a configuration in which the GaN layer 10 having a large band gap is formed in the uppermost layer. Since the operation of the semiconductor device 40 is the same as that of the semiconductor device 20 in the first embodiment, the description thereof is omitted.

  As described above, the semiconductor device 40 according to the present embodiment includes a GaN barrier layer having a band gap larger than that of GaAs on the surface of the channel layer, thereby further reducing gate leakage current and improving movement of electrons in the channel. Can be made. Further, since the gate electrode 5 is made of Pt metal having a high Schottky barrier barrier, the potential barrier can be increased to 0.85 eV, and the gate leakage current can be further reduced.

  In addition, since the channel region of the semiconductor device 40 in the present embodiment includes two or more semiconductor layers and the Si layer 6 having low mobility in the lowermost carrier layer, the semiconductor device 20 in the first embodiment. Has the same effect as.

It is the figure which showed the structure of the semiconductor device provided with MESFET in Embodiment 1 of this invention. It is the figure which showed the structure of the semiconductor device provided with MESFET in Embodiment 2 of this invention. It is the figure which showed the structure of the semiconductor device provided with MESFET in Embodiment 3 of this invention. It is the figure which showed the structure of the semiconductor device provided with MESFET in a prior art.

Explanation of symbols

  1 Insulating substrate, 2 buffer layer, 3 source / drain region, 4 channel region, 5 gate electrode, 6 Si layer, 7 SiGe layer, 8 InAs layer, 9 GaAs layer, 10 GaN layer, 20, 30, 40, 50 semiconductor apparatus.

Claims (7)

A first conductivity type semiconductor substrate;
A drain region and a source region formed on the semiconductor substrate and made of a semiconductor layer of a second conductivity type;
A channel region formed on the semiconductor substrate and between the drain region and the source region, the channel region including two or more semiconductor layers of a second conductivity type;
A semiconductor device comprising: a gate electrode formed on the channel region and in Schottky contact with the channel region.   The semiconductor device according to claim 1, wherein in the channel region, a semiconductor layer having a carrier mobility smaller than that of another layer is disposed in a lowermost layer.   3. The semiconductor device according to claim 1, wherein a semiconductor layer having a band gap larger than that of the other layers is arranged in the uppermost layer in the channel region.   The semiconductor device according to claim 1, wherein the channel region is formed of three layers of a Si layer / SiGe layer / InAs layer from a lower layer.   2. The semiconductor device according to claim 1, wherein the channel region is formed of three layers of a Si layer / SiGe layer / GaAs layer from the lower layer.   The semiconductor device according to claim 1, wherein the channel region is formed of three layers of a Si layer / SiGe layer / GaN layer from a lower layer.   The semiconductor device according to claim 1, wherein the gate electrode is made of Pt.

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