JP2009158962A - Semiconductor package and method of manufacturing the same - Google Patents

Semiconductor package and method of manufacturing the same Download PDF

Info

Publication number
JP2009158962A
JP2009158962A JP2009014738A JP2009014738A JP2009158962A JP 2009158962 A JP2009158962 A JP 2009158962A JP 2009014738 A JP2009014738 A JP 2009014738A JP 2009014738 A JP2009014738 A JP 2009014738A JP 2009158962 A JP2009158962 A JP 2009158962A
Authority
JP
Japan
Prior art keywords
insulating film
substrate
pad
functional element
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2009014738A
Other languages
Japanese (ja)
Other versions
JP4908528B2 (en
Inventor
Michikazu Tomita
道和 冨田
Tatsuo Suemasu
龍夫 末益
Sayaka Hirafune
さやか 平船
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujikura Ltd
Original Assignee
Fujikura Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujikura Ltd filed Critical Fujikura Ltd
Priority to JP2009014738A priority Critical patent/JP4908528B2/en
Publication of JP2009158962A publication Critical patent/JP2009158962A/en
Application granted granted Critical
Publication of JP4908528B2 publication Critical patent/JP4908528B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor package excellent in airtightness, moisture resistance and chemical resistance. <P>SOLUTION: The semiconductor package includes: a first substrate at least including a semiconductor base, a functional element provided on one of surfaces of the semiconductor base, a pad electrically connected with the functional element via a first wire, and a through electrode filled with a first conductor via an insulation film A in a fine pore electrically connected with the pad and extending from one of the surfaces of the semiconductor base to the other; and a second substrate bonded with one of the surfaces of the first substrate through the use of a sealant provided around the functional element. The insulation film A is formed to couple with an insulation film B provided on the other surface of the semiconductor base, an insulation film C provided on the external side face of the semiconductor base, and an insulation film D provided on the external side face of the sealant. The exterior of the insulation film is, more preferably, covered doubly with a conductor. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、機能素子を有し表裏を繋ぐ貫通電極を有する半導体パッケージの封止構造及びその製造方法に関するものである。   The present invention relates to a sealing structure of a semiconductor package having a functional element and a through electrode connecting the front and back and a manufacturing method thereof.

従来、半導体受光センサー等の機能素子の実装には、セラミック、樹脂などで形成された封止容器内部に収納、封止する方法が広く用いられてきた。図5にその一例を示す(例えば、特許文献1参照。)。
図に示す半導体パッケージ40は、半導体基板41、貫通電極45b、封止材47及びキャップ基板46から構成されている。半導体基板41の上には集光効率を向上させるためのマイクロレンズ44bを備えた受光素子44aが形成されていて、配線44c及び貫通電極45bを通して半導体パッケージ40の外部に通じている。
ガラス板などの光透過性保護部材46は、受光センサー44a及びマイクロレンズ44bには触れないように間隙を保って、封止材47を介して半導体基板41の上に接着固定されている。また封止材47は、受光センサー44aの周囲を切れ目なく囲い、かつ、受光センサー44aを覆わず、そして保護部材46が受光センサー44a及びマイクロレンズ44bに接しないように、塗布後硬化させている。この封止材47は前述のように光透過性保護部材46を固定して、受光センサー44aやマイクロレンズ44bを機械的に保護すると共に、受光センサー44aやマイク4レンズ44bを周囲の雰囲気から遮断する機能も持つ。
Conventionally, for mounting a functional element such as a semiconductor light receiving sensor, a method of storing and sealing inside a sealing container formed of ceramic, resin or the like has been widely used. An example is shown in FIG. 5 (see, for example, Patent Document 1).
A semiconductor package 40 shown in the drawing is composed of a semiconductor substrate 41, a through electrode 45 b, a sealing material 47 and a cap substrate 46. On the semiconductor substrate 41, a light receiving element 44a having a microlens 44b for improving the light collection efficiency is formed and communicates with the outside of the semiconductor package 40 through the wiring 44c and the through electrode 45b.
The light-transmitting protective member 46 such as a glass plate is bonded and fixed on the semiconductor substrate 41 via a sealing material 47 while keeping a gap so as not to touch the light receiving sensor 44a and the micro lens 44b. Further, the sealing material 47 surrounds the light receiving sensor 44a seamlessly, does not cover the light receiving sensor 44a, and is cured after application so that the protective member 46 does not contact the light receiving sensor 44a and the microlens 44b. . As described above, the sealing material 47 fixes the light-transmitting protective member 46 to mechanically protect the light receiving sensor 44a and the micro lens 44b, and also shields the light receiving sensor 44a and the microphone 4 lens 44b from the surrounding atmosphere. It also has a function to do.

特開2001−351997号公報JP 2001-351997 A

このような半導体パッケージは、以下のような手順で製造される。すなわち、
先ず半導体基板41に、受光センサー44a、図示省略の受光センサー44a用の駆動回路や出力の処理回路、配線回路44cなどを通常の半導体形成手段により形成する。
次に、半導体基板41の配線回路部に非貫通の深孔を異方性エッチングなどにより穿ち、深孔内面に図示省略の絶縁層と、配線回路部44cに接続する導電層からなる貫通電極45bを堆積する。
次いで、個々の受光センサー44aの周囲を切れ目なく囲み、かつ、これを覆わないように封止材47をスクリーン印刷法、ディスペンス法などの手段により半導体基板の片方の面に塗布する。
次に、半導体基板とほぼ同じ平面寸法を有する光透過性保護部材46を圧着し、封止材47に熱や紫外線などを作用させて封止材47を硬化させる。
次いで、半導体基板41の裏面側から先に形成した貫通電極45bが露出するまでエッチングを行う。
最後に、所定の寸法にダイシングして多数の半導体パッケージ40を取得する。
Such a semiconductor package is manufactured by the following procedure. That is,
First, on the semiconductor substrate 41, a light receiving sensor 44a, a driving circuit for the light receiving sensor 44a (not shown), an output processing circuit, a wiring circuit 44c, and the like are formed by normal semiconductor forming means.
Next, a non-penetrating deep hole is formed in the wiring circuit portion of the semiconductor substrate 41 by anisotropic etching or the like, and a through electrode 45b comprising an insulating layer (not shown) on the inner surface of the deep hole and a conductive layer connected to the wiring circuit portion 44c. To deposit.
Next, the sealing material 47 is applied to one surface of the semiconductor substrate by means of a screen printing method, a dispensing method, or the like so as to surround the individual light receiving sensors 44a without being cut off and to cover them.
Next, a light-transmitting protective member 46 having substantially the same planar dimensions as the semiconductor substrate is pressure-bonded, and the sealing material 47 is cured by applying heat or ultraviolet light to the sealing material 47.
Next, etching is performed until the through electrode 45b formed earlier from the back side of the semiconductor substrate 41 is exposed.
Finally, a large number of semiconductor packages 40 are obtained by dicing to a predetermined size.

このようにして得られた半導体パッケージの周囲の側面には、半導体基板41と光透過性保護部材46を接合する封止材47が露出している。封止材47としては一般に合成樹脂が用いられるため、材質によっては気密性、耐湿性、あるいは耐薬品性等が必ずしも充分とは言えない。そのため、半導体素子の安定した動作と長寿命が得られないという問題がある。
本発明は、素子の安定した動作と長寿命を確保するために、高性能の気密性や耐湿性、あるいは耐薬品性を具備した半導体パッケージ構造を得ることを一つの目的とする。
本発明のもう一つの目的は、このような気密性や耐湿性、あるいは耐薬品性を具備した半導体パッケージ構造を、大幅な工程増加を来すことなく得るための製造方法を提供することにある。
A sealing material 47 that joins the semiconductor substrate 41 and the light-transmissive protective member 46 is exposed on the side surface around the semiconductor package thus obtained. Since a synthetic resin is generally used as the sealing material 47, airtightness, moisture resistance, chemical resistance, and the like are not necessarily sufficient depending on the material. Therefore, there is a problem that stable operation and long life of the semiconductor element cannot be obtained.
An object of the present invention is to obtain a semiconductor package structure having high-performance airtightness, moisture resistance, or chemical resistance in order to ensure stable operation and long life of the device.
Another object of the present invention is to provide a manufacturing method for obtaining a semiconductor package structure having such hermeticity, moisture resistance, or chemical resistance without significantly increasing the number of steps. .

上記課題を解決するため、本発明の半導体パッケージの一つは、半導体基材と、該半導体基材の一方の面側に配置された機能素子及び該機能素子に第1の配線を介して電気的に接続されたパッドと、該パッドと電気的に接続され前記半導体基材の一方の面から他方の面に至る微細孔内に絶縁膜Aを介して第1の導電体を形成してなる貫通電極とを少なくとも備えてなる第1の基板、及び前記機能素子の周囲に配置された封止材を用いて、前記第1の基板の一方の面と接合されてなる第2の基板からなる半導体パッケージであって、前記絶縁膜Aは、前記半導体基材の他方の面に配置される絶縁膜B、前記半導体基材の外側面に配置される絶縁膜C及び前記封止材の外側面に配置される絶縁膜Dとを具備した半導体パッケージとした。
このような構造の半導体パッケージとすれば、パッケージ側面に封止材が露出することがなく、遮蔽効果の高い絶縁物で覆われているので気密性、耐湿性、あるいは耐薬品性等が向上したものとなる。
In order to solve the above-described problems, one of the semiconductor packages of the present invention includes a semiconductor substrate, a functional element disposed on one surface side of the semiconductor substrate, and an electrical connection to the functional element via a first wiring. And a first conductor is formed through an insulating film A in a fine hole electrically connected to the pad and extending from one surface of the semiconductor substrate to the other surface. A first substrate having at least a through electrode, and a second substrate bonded to one surface of the first substrate using a sealing material disposed around the functional element. In the semiconductor package, the insulating film A includes an insulating film B disposed on the other surface of the semiconductor substrate, an insulating film C disposed on the outer surface of the semiconductor substrate, and an outer surface of the sealing material. A semiconductor package having an insulating film D disposed on the substrate.
With the semiconductor package having such a structure, the sealing material is not exposed on the side surface of the package and is covered with an insulating material having a high shielding effect, so that airtightness, moisture resistance, chemical resistance, etc. are improved. It will be a thing.

さらに、本発明の半導体パッケージは、前記絶縁膜A、前記半導体基材の他方の面に配置される絶縁膜B、前記半導体基材の外側面に配置される絶縁膜C及び前記封止材の外側面に配置される絶縁膜Dを一体化したものとすることができる。
また、前記パッケージ外側面の絶縁膜の表面を、さらに導電体で被覆したものとすることができる。
各絶縁膜を一体化することにより、絶縁性能が高まる利点がある。また、導電体で被覆することにより、気密性、耐湿性、あるいは耐薬品性等が一層向上したものとなる。
Furthermore, the semiconductor package of the present invention includes the insulating film A, the insulating film B disposed on the other surface of the semiconductor substrate, the insulating film C disposed on the outer surface of the semiconductor substrate, and the sealing material. The insulating film D disposed on the outer surface can be integrated.
The surface of the insulating film on the outer surface of the package may be further covered with a conductor.
By integrating each insulating film, there is an advantage that the insulating performance is enhanced. Further, by coating with a conductor, airtightness, moisture resistance, chemical resistance and the like are further improved.

本発明の半導体パッケージの製造方法の一つは、半導体基材の一面に機能素子、第1の配線及びパッドを設けてなる第1の基板に対して、第2の基板を機能素子が内側になるようにして封止材を用いて接合する工程と、前記半導体基材の他方の面に所定のパターンを有するマスクを形成する工程と、前記半導体基材を前記マスクを介してエッチングして前記パッドに対応する位置に該パッドに達する孔を形成するとともに、前記機能素子、第1の配線及びパッドを取り囲むように前記封止材に達する溝を形成する工程と、該溝の底部にある封止材をエッチング除去して第2の基板を露出させる工程と、前記孔及び溝の内面に絶縁膜を形成する工程と、該孔の底部に形成された絶縁膜をエッチング除去する工程と、該孔内に第1の導電体を充填して貫通電極を形成する工程と、前記第2の基板まで達する貫通孔の内壁に沿って切断する工程とを含む製造方法とした。
このような製造方法とすれば、貫通電極形成工程を利用して絶縁物層も形成できるので工程数の増加は少なく、その上優れた気密性、耐湿性、あるいは耐薬品性を有する半導体パッケージを得ることができる。
One of the methods for manufacturing a semiconductor package according to the present invention is such that a functional element, a first wiring and a pad are provided on one surface of a semiconductor substrate, and a second substrate is placed inside the second substrate. Bonding using a sealing material, forming a mask having a predetermined pattern on the other surface of the semiconductor substrate, etching the semiconductor substrate through the mask, and Forming a hole reaching the pad at a position corresponding to the pad, forming a groove reaching the sealing material so as to surround the functional element, the first wiring, and the pad; and a seal at a bottom of the groove Etching the stopper to expose the second substrate; forming an insulating film on the inner surface of the hole and groove; etching removing the insulating film formed on the bottom of the hole; Fill the hole with the first conductor Forming a through electrode Te, was manufacturing method comprising a step of cutting along the inner wall of the through-hole reaching the second substrate.
With such a manufacturing method, an insulating layer can also be formed using the through electrode forming process, so that the number of processes is not increased, and a semiconductor package having excellent airtightness, moisture resistance, or chemical resistance is obtained. Obtainable.

本発明のもう一つの半導体パッケージの製造方法は、半導体基材の一面に機能素子、第1の配線及びパッドを設けてなる第1の基板に対して、第2の基板を機能素子が内側になるようにして封止材を用いて接合する工程と、前記半導体基材の他方の面に所定のパターンを有するマスクを形成する工程と、前記半導体基材を前記マスクを介してエッチングして前記パッドに対応する位置に該パッドに達する孔を形成するとともに、前記機能素子、第1の配線及びパッドを取り囲むように前記封止材に達する溝を形成する工程と、該溝の底部にある封止材をエッチング除去して第2の基板を露出させる工程と、前記孔及び溝の内面に絶縁膜を形成する工程と、該孔の底部に形成された絶縁膜をエッチング除去する工程と、該孔内に第1の導電体を充填して貫通電極を形成すると同時に、前記溝内にも第1の導電体を充填する工程と、前記第2の基板まで達する溝内に形成された第1の導電体を切断する工程とを含む製造方法とした。
この方法によっても貫通電極形成工程を利用して絶縁物層及び導電体層が同時に形成できるので工程数の増加は少なく、その上一層優れた気密性、耐湿性、あるいは耐薬品性を有する半導体パッケージを得ることができる。
According to another method of manufacturing a semiconductor package of the present invention, a functional element, a first wiring, and a pad are provided on one surface of a semiconductor substrate. Bonding using a sealing material, forming a mask having a predetermined pattern on the other surface of the semiconductor substrate, etching the semiconductor substrate through the mask, and Forming a hole reaching the pad at a position corresponding to the pad, forming a groove reaching the sealing material so as to surround the functional element, the first wiring, and the pad; and a seal at a bottom of the groove Etching the stopper to expose the second substrate; forming an insulating film on the inner surface of the hole and groove; etching removing the insulating film formed on the bottom of the hole; The first conductor in the hole Forming a through electrode by filling and filling the groove with a first conductor, and cutting the first conductor formed in the groove reaching the second substrate; It was set as the manufacturing method containing.
Also by this method, the insulating layer and the conductor layer can be formed at the same time by using the through electrode forming process, so that the number of processes is not increased, and the semiconductor package has further excellent airtightness, moisture resistance, or chemical resistance. Can be obtained.

本発明の半導体パッケージによれば、半導体パッケージの側面が強固な絶縁膜や導電体によって覆われているので、半導体パッケージを形成する封止材の種類によらず優れた気密性や耐湿性、あるいは耐薬品性を具備した半導体パッケージが得られ、パッケージ素子の安定した動作と長寿命が確保される。
また、本発明の半導体パッケージの製造方法によれば、貫通電極形成工程を利用して絶縁物層や導電体も形成できるので工程数の増加は少なく、その上優れた特性の半導体パッケージを得ることができる点でまことに有用である。
According to the semiconductor package of the present invention, since the side surface of the semiconductor package is covered with a strong insulating film or conductor, excellent airtightness and moisture resistance regardless of the type of sealing material forming the semiconductor package, or A semiconductor package having chemical resistance is obtained, and stable operation and a long life of the package element are ensured.
In addition, according to the method for manufacturing a semiconductor package of the present invention, since an insulating layer and a conductor can be formed using a through electrode forming process, the number of processes is not increased and a semiconductor package with excellent characteristics can be obtained. It is really useful in that it can.

本発明の第1の実施形態の半導体パッケージの断面図である。It is sectional drawing of the semiconductor package of the 1st Embodiment of this invention. 本発明の第2の実施形態の半導体パッケージの断面図である。It is sectional drawing of the semiconductor package of the 2nd Embodiment of this invention. 本発明の半導体パッケージの製造方法を説明する断面工程図である。It is sectional process drawing explaining the manufacturing method of the semiconductor package of this invention. 図3に続く断面工程図である。FIG. 4 is a sectional process diagram subsequent to FIG. 3; 従来の半導体パッケージの断面図である。It is sectional drawing of the conventional semiconductor package.

(第1の実施形態)
図1に、本発明の第1の実施形態に係わる半導体パッケージの断面構造を示す。本発明の第1の実施形態に係わる半導体パッケージ1は、機能素子12が形成された第1の基板10とキャップ基板をなす第2の基板20とが封止材30を用いて接合されて構成されている。
第1の基板10は、一方の表面に機能素子12と、これに接続する第1の配線13及びパッド14が形成され、他方の表面と該パッド14を電気的に接続する貫通電極15を備えた半導体基板11からなっている。貫通電極15は半導体基板11の表裏両面を貫通する微細孔16の内面に、絶縁膜A17aを介して第1の導電体18を充填して構成されている。
(First embodiment)
FIG. 1 shows a cross-sectional structure of a semiconductor package according to the first embodiment of the present invention. The semiconductor package 1 according to the first embodiment of the present invention has a configuration in which a first substrate 10 on which a functional element 12 is formed and a second substrate 20 forming a cap substrate are bonded using a sealing material 30. Has been.
The first substrate 10 includes a functional element 12 on one surface, a first wiring 13 and a pad 14 connected thereto, and a through electrode 15 that electrically connects the other surface to the pad 14. It consists of a semiconductor substrate 11. The through electrode 15 is configured by filling the inner surface of the fine hole 16 penetrating both the front and back surfaces of the semiconductor substrate 11 with the first conductor 18 through the insulating film A17a.

本実施形態では、絶縁膜A17aが半導体基板11の他の面に形成された絶縁膜B17b、半導体基板11の側面に形成された絶縁膜C17c、及び半導体パッケージ1の封止材30の側面に形成された絶縁膜D17dと連結して一体に形成されている例を示している。
絶縁膜17は一体に形成されている必要はなく、例えば前記絶縁膜A17a、絶縁膜C17c及び絶縁膜D17dは、プラズマCVDを使用して窒化膜で形成し、絶縁膜B17bは熱酸化法を使用した酸化膜で形成することができる。
あるいはまた、絶縁膜17全体をプラズマCVDを使用して窒化膜や酸化膜で一体形成した後、RIEなどによる微細孔底面の絶縁膜除去工程においてオーバーエッチングするなどの方法により前記絶縁膜A17a、絶縁膜C17c及び絶縁膜D17dを残して絶縁膜B17bの部分を除去し、ポリアミド樹脂やポリイミド樹脂等の合成樹脂などを使用してあらためて絶縁膜B17bを形成することもできる。
すなわち、本発明の半導体パッケージにおいては、図1に示す絶縁膜A17a、絶縁膜B17b、絶縁膜C17c及び絶縁膜D17dを具備していれば良いことになる。
本発明の半導体パッケージ1の外周は、第2の基板20の表面と貫通電極15の端面を除いた側面と底面が絶縁膜17で被覆されてるので、気密性や耐湿性、あるいは耐薬品性に優れた半導体パッケージとなり、封止材30も絶縁膜17dで被覆されてるので、接合部界面から大気中の湿分が侵入することもなく、機能素子が完全に保護されるので動作が安定し、また寿命も格段に長くなる。
In this embodiment, the insulating film A17a is formed on the other surface of the semiconductor substrate 11, the insulating film B17b formed on the side surface of the semiconductor substrate 11, and the side surface of the sealing material 30 of the semiconductor package 1. In this example, the insulating film D17d is formed integrally with the insulating film D17d.
The insulating film 17 does not need to be integrally formed. For example, the insulating film A17a, the insulating film C17c, and the insulating film D17d are formed of a nitride film using plasma CVD, and the insulating film B17b is formed of a thermal oxidation method. The oxide film can be formed.
Alternatively, the insulating film A17a, the insulating film 17a, and the insulating film 17 are formed by a method such as forming the whole insulating film 17 integrally with a nitride film or an oxide film using plasma CVD and then over-etching in an insulating film removing process on the bottom surface of the fine hole by RIE or the like. The insulating film B17b can be formed again by using the synthetic resin such as polyamide resin or polyimide resin by removing the insulating film B17b while leaving the film C17c and the insulating film D17d.
That is, the semiconductor package of the present invention only needs to include the insulating film A17a, the insulating film B17b, the insulating film C17c, and the insulating film D17d shown in FIG.
Since the outer periphery of the semiconductor package 1 of the present invention is covered with the insulating film 17 on the side surface and bottom surface of the second substrate 20 except for the surface of the second substrate 20 and the end surface of the through electrode 15, the airtightness, moisture resistance, or chemical resistance is improved. Since it becomes an excellent semiconductor package and the sealing material 30 is also covered with the insulating film 17d, moisture in the atmosphere does not enter from the interface of the joint, and the functional element is completely protected, so the operation is stable, In addition, the service life is significantly increased.

(第2の実施形態)
図2に、本発明の第2の実施形態に係わる半導体パッケージ2の断面構造を示す。本発明の第2の実施形態に係わる半導体パッケージ2は、内部の構造は第1の実施形態に係わる半導体パッケージ1と同様である。すなわち、機能素子12が形成された第1の基板10とキャップ基板をなす第2の基板20とが封止材30を用いて接合して構成されていて、第1の基板10は、一方の表面に機能素子12と、これに接続する第1の配線13及びパッド14が形成され、他方の表面と該パッド14を電気的に接続する貫通電極15を備えた半導体基板11からなっている。貫通電極15は半導体基板11の表裏両面を貫通する微細孔16の内面に、絶縁膜A17aを介して第1の導電体18を充填して構成されている。この絶縁膜A17aは、半導体基板11の他の面に形成された絶縁膜B17b、半導体基板11の側面に形成された絶縁膜C17c、及び半導体パッケージ1の封止材30の側面に形成された絶縁膜D17dと連結して一体に形成されている。
第2の実施形態に係わる半導体パッケージ2では、前記半導体基板11の側面に形成された絶縁膜C17c及び封止材30の側面に形成された絶縁膜D17dの表面を、さらに第2の導電体19で被覆してある。
半導体パッケージの側面が絶縁膜に加えて導電体で二重に被覆してあるので、シール機能はさらに強固となり、機能素子が完全に保護されて動作が安定し、また寿命も一層長くなる。
(Second Embodiment)
FIG. 2 shows a cross-sectional structure of a semiconductor package 2 according to the second embodiment of the present invention. The semiconductor package 2 according to the second embodiment of the present invention has the same internal structure as the semiconductor package 1 according to the first embodiment. That is, the first substrate 10 on which the functional element 12 is formed and the second substrate 20 that forms the cap substrate are joined using the sealing material 30, and the first substrate 10 A functional element 12, a first wiring 13 and a pad 14 connected to the functional element 12 are formed on the surface, and the semiconductor substrate 11 includes a penetrating electrode 15 that electrically connects the other surface to the pad 14. The through electrode 15 is configured by filling the inner surface of the fine hole 16 penetrating both the front and back surfaces of the semiconductor substrate 11 with the first conductor 18 through the insulating film A17a. The insulating film A17a includes an insulating film B17b formed on the other surface of the semiconductor substrate 11, an insulating film C17c formed on the side surface of the semiconductor substrate 11, and an insulating film formed on the side surface of the sealing material 30 of the semiconductor package 1. It is formed integrally with the film D17d.
In the semiconductor package 2 according to the second embodiment, the surface of the insulating film C17c formed on the side surface of the semiconductor substrate 11 and the surface of the insulating film D17d formed on the side surface of the sealing material 30 are further provided on the second conductor 19. It is covered with.
Since the side surface of the semiconductor package is doubly covered with the conductor in addition to the insulating film, the sealing function is further strengthened, the functional element is completely protected, the operation is stabilized, and the life is further increased.

次に、これらの半導体パッケージの製造方法の一例について図面を用いて説明する。
図3及び図4は、本発明の半導体パッケージの製造方法を示す断面工程図である。
まず、シリコン等の半導体基板11の表面に、例えば光デバイス等の所望の機能素子12や接続に必要な第1の配線13及びパッド14を通常の半導体製造プロセスを利用して形成し、第1の基板10を形成する。
第1の配線13及びパッド14としては、例えばアルミニウム(Al)や銅(Cu)、アルミニウム−シリコン(Al−Si)合金、アルミニウム−シリコン−銅(Al−Si−Cu)合金等の導電性に優れる材料が好適に用いられるが、これらの材料は酸化されやすい性質を有している。
Next, an example of a method for manufacturing these semiconductor packages will be described with reference to the drawings.
3 and 4 are cross-sectional process diagrams illustrating a method for manufacturing a semiconductor package of the present invention.
First, a desired functional element 12 such as an optical device and a first wiring 13 and a pad 14 necessary for connection are formed on the surface of a semiconductor substrate 11 such as silicon using a normal semiconductor manufacturing process. The substrate 10 is formed.
As the first wiring 13 and the pad 14, for example, aluminum (Al), copper (Cu), an aluminum-silicon (Al-Si) alloy, an aluminum-silicon-copper (Al-Si-Cu) alloy or the like can be used. Although excellent materials are preferably used, these materials are easily oxidized.

次いで、図3(a)に示すように、機能素子12を搭載した前記第1の基板10とキャップ材となる第2の基板20とを、封止材30を使用して接合する。この際、機能素子12を内側にして、かつ機能素子12に接触しないようにして第2の基板20をかぶせて接合する。第2の基板20もシリコン等の半導体基板が利用できる。封止材30としては、例えば感光性もしくは非感光性の液状樹脂(UV硬化型樹脂、可視光硬化型樹脂、赤外光硬化型樹脂、熱硬化型樹脂等)やドライフィルムが挙げられる。樹脂の種類としては、エポキシ樹脂、シリコン樹脂、アクリル樹脂、ポリイミド樹脂等が利用でき、半導体パッケージの使用環境に応じて適宜選択すればよい。
封止材30層を形成するには、例えば液状樹脂を使用して印刷法により所定位置に塗布したり、ドライフィルムを貼り付けてこれをフォトリソグラフィー技術により所定位置のみ残してパターニングする方法等が利用できる。
Next, as shown in FIG. 3A, the first substrate 10 on which the functional element 12 is mounted and the second substrate 20 serving as a cap material are bonded using a sealing material 30. At this time, the second substrate 20 is covered and bonded so that the functional element 12 is on the inner side and is not in contact with the functional element 12. The second substrate 20 can also be a semiconductor substrate such as silicon. Examples of the sealing material 30 include photosensitive or non-photosensitive liquid resins (UV curable resins, visible light curable resins, infrared light curable resins, thermosetting resins, etc.) and dry films. As the type of resin, epoxy resin, silicon resin, acrylic resin, polyimide resin, or the like can be used, and may be appropriately selected according to the use environment of the semiconductor package.
In order to form the sealing material 30 layer, for example, a liquid resin is applied to a predetermined position by a printing method, or a dry film is attached and patterned by leaving a predetermined position by a photolithography technique. Available.

次に、図3(b)に示すように、半導体基板11の他方の表面にマスク5を形成する。
マスク5としては例えばUV硬化型樹脂やポリイミド系感光性樹脂等を使用し、フォトリソグラフィーにより所定位置に開口部5a,5bを設ける。ここで開口部5aは配線構造を形成するための微細孔16を搾孔するためのものであり、パッド14に対応する位置に例えば円形の小孔として形成する。一方、開口部5bは機能素子12を保護するためのものであり、機能素子12を中心にして第1の配線13とパッド14を取り囲むようにして形成する。
Next, as shown in FIG. 3B, a mask 5 is formed on the other surface of the semiconductor substrate 11.
As the mask 5, for example, a UV curable resin, a polyimide-based photosensitive resin, or the like is used, and openings 5 a and 5 b are provided at predetermined positions by photolithography. Here, the opening 5a is for squeezing the fine hole 16 for forming the wiring structure, and is formed as a circular small hole at a position corresponding to the pad 14, for example. On the other hand, the opening 5b is for protecting the functional element 12, and is formed so as to surround the first wiring 13 and the pad 14 with the functional element 12 as the center.

次に、図3(c)に示すように、マスク5を利用して例えば反応性イオンエッチング(Deep Reactiv Ion Etching:DRIE)法等を使用して、開口部5a,5b位置の半導体基板11をエッチングし、微細孔16と溝7を形成する。DRIE法を用いることにより、精度の高い孔加工が可能となる。DRIE法とは、エッチングガスに六フッ化硫黄(SF6 )を用い、高密度プラズマによるエッチングと、側壁へのパッシベーション成膜を交互に行うことにより(Bosch プロセス)、シリコン基板を深堀エッチングするものである。図示は省略するが、平面的には溝7は機能素子12を取り囲むように溝状に形成される。その後、必要ならばマスク5を剥離除去する。
微細孔16は円形に限定されず、パッド14との接触面積が確保できるような大きさであれば如何なる大きさでもよく、その形状は楕円形、四角形、三角形、矩形など如何なる形状でもよい。
さらに、微細孔16を形成する方法も、DRIE法に限定されず、水酸化カリウム(KOH)水溶液などによるウェットエッチング法を用いても構わない。
Next, as shown in FIG. 3C, the semiconductor substrate 11 at the positions of the openings 5a and 5b is formed by using, for example, a reactive ion etching (DRIE) method using a mask 5. Etching is performed to form fine holes 16 and grooves 7. By using the DRIE method, it is possible to perform drilling with high accuracy. The DRIE method uses sulfur hexafluoride (SF6) as an etching gas, and alternately etches with high-density plasma and forms a passivation film on the sidewall (Bosch process) to deep-etch the silicon substrate. is there. Although not shown, the groove 7 is formed in a groove shape so as to surround the functional element 12 in plan view. Thereafter, the mask 5 is peeled off if necessary.
The micro holes 16 are not limited to a circle, and may have any size as long as the contact area with the pad 14 can be secured, and the shape may be any shape such as an ellipse, a rectangle, a triangle, and a rectangle.
Further, the method for forming the micro holes 16 is not limited to the DRIE method, and a wet etching method using a potassium hydroxide (KOH) aqueous solution or the like may be used.

次に、図3(d)に示すように、ドライエッチング等の手段を用いて溝7の底部7aにある封止材30を除去する。
ここで、あらかじめ封止材30にスクライブラインを設けておけば、この工程を省略することもできる。
Next, as shown in FIG. 3D, the sealing material 30 at the bottom 7a of the groove 7 is removed using means such as dry etching.
Here, if a scribe line is provided in the sealing material 30 in advance, this step can be omitted.

次に、図4(e)に示すように、図3(d)の状態で基板全面に絶縁膜17を形成する。絶縁膜17としては、酸化珪素(SiO2 )、窒化珪素(Si3N4)、リンシリケートガラス(PSG)、ボロンリンシリケートガラス(BPSG)等が利用でき、半導体パッケージの使用環境に応じて適宜選択すればよい。SiO2 、Si3N4はCVDを利用すれば任意の厚さに成膜できる。SiO2 からなる絶縁膜を成膜するには、例えば、シランやテトラエトキシシラン(TEOS)を原料とするプラズマCVD法により形成することができる。
この方法によれば、図1及び図2に示す絶縁膜A17a、絶縁膜B17b、絶縁膜C17c及び絶縁膜D17dを一体に形成することができる。
Next, as shown in FIG. 4E, an insulating film 17 is formed on the entire surface of the substrate in the state shown in FIG. As the insulating film 17, silicon oxide (SiO 2), silicon nitride (Si 3 N 4), phosphorus silicate glass (PSG), boron phosphorus silicate glass (BPSG), or the like can be used, and may be appropriately selected according to the use environment of the semiconductor package. . SiO2 and Si3N4 can be formed into arbitrary thicknesses by using CVD. In order to form the insulating film made of SiO2, for example, it can be formed by plasma CVD using silane or tetraethoxysilane (TEOS) as a raw material.
According to this method, the insulating film A17a, the insulating film B17b, the insulating film C17c, and the insulating film D17d shown in FIGS. 1 and 2 can be integrally formed.

次に、図4(f)に示すように、ドライエッチングを利用して微細孔16及び溝7の底部にある絶縁膜17を除去し、パッド14及び第2の基板20の表面14a,20aを露出させる。ただし、溝7の底部の絶縁膜17は、必ずしもエチング除去する必要はない。
また、SiO2 をエッチングする場合には、四フッ化炭素(CF4 )を用いたReactive Ion Etching(RIE) 法を用いることができる。
Next, as shown in FIG. 4F, the fine hole 16 and the insulating film 17 at the bottom of the groove 7 are removed using dry etching, and the pads 14 and the surfaces 14a and 20a of the second substrate 20 are formed. Expose. However, the insulating film 17 at the bottom of the trench 7 does not necessarily need to be etched away.
In addition, when etching SiO2, a reactive ion etching (RIE) method using carbon tetrafluoride (CF4) can be used.

次に、図4(g)に示すように、溶融金属吸引法等を用いて微細孔16内に第1の導電体18を形成する。この際、図4(g)のように微細孔16内にのみ導電体18を形成しても良いが、図4(g’)に示すように、微細孔16と同時に溝7内にも第2の導電体19を形成する方法を採用することもできる。
導電体としては、電気の良導体であれば特に制限は無く、例えば電気抵抗が低い銅、アルミニウム、ニッケル、クロム、銀、錫等の他に、Au−Sn、Sn−Pb等の合金、あるいはSn基、Pb基、Au基、In基、A)基などのはんだ合金等の金属が利用できる。金属を使用すれば第2の導電体として使用する場合にも、使用環境に合った金属を使用すれば、遮蔽効果の優れたものとなる。
Next, as shown in FIG. 4G, a first conductor 18 is formed in the microhole 16 using a molten metal suction method or the like. At this time, the conductor 18 may be formed only in the fine hole 16 as shown in FIG. 4G, but as shown in FIG. A method of forming the second conductor 19 can also be employed.
The conductor is not particularly limited as long as it is a good electrical conductor. For example, in addition to copper, aluminum, nickel, chromium, silver, tin, etc. having a low electrical resistance, alloys such as Au—Sn, Sn—Pb, or Sn A metal such as a solder alloy such as a group, Pb group, Au group, In group, or A) group can be used. If a metal is used as the second conductor, if a metal suitable for the usage environment is used, the shielding effect is excellent.

そして、図4(g)に示す溝7の内壁に沿った線L1,L2で切断すれば、図1に示す第1の実施形態の半導体パッケージ1が得られる。
半導体パッケージ1の外周は、第2の基板20の表面と貫通電極15の端面を除いた側面と底面が絶縁膜17で被覆されてるので、気密性や耐湿性、あるいは耐薬品性に優れた半導体パッケージとなり、封止材30も絶縁膜17dで被覆されてるので、接合部界面から大気中の湿分が侵入することもなく、機能素子が完全に保護されるので動作が安定し、また寿命も格段に長くなる
And if it cut | disconnects by the lines L1 and L2 along the inner wall of the groove | channel 7 shown in FIG.4 (g), the semiconductor package 1 of 1st Embodiment shown in FIG. 1 will be obtained.
Since the outer periphery of the semiconductor package 1 is covered with the insulating film 17 on the side surface and the bottom surface of the second substrate 20 except for the end surface of the through electrode 15, a semiconductor having excellent airtightness, moisture resistance, or chemical resistance. Since it becomes a package and the sealing material 30 is also covered with the insulating film 17d, moisture in the atmosphere does not enter from the interface of the joint, and the functional element is completely protected, so that the operation is stable and the life is also long. Markedly longer

ここで、図4(g’)に示すように、微細孔16内と同時に溝7内にも第2の導電体19を形成して、溝7内の第2の導電体19の中央に沿った線L3で切断すれば、図2に示す第2の実施形態の半導体パッケージ2が得られる。第2の導電体としては、先の第1の導電体18と同じ金属を使用すれば、一つの工程で同時に形成できるので都合がよい。
半導体パッケージ2は、半導体基板11の側面に形成された絶縁膜C17c及び封止材30の側面に形成された絶縁膜D17dの表面が、さらに第2の導電体19で被覆してある。
半導体パッケージの側面が絶縁膜に加えて金属の導電体で二重に被覆してあるので、シール機能はさらに強固となり、機能素子が完全に保護されて動作が安定し、また寿命も一層長くなる。
Here, as shown in FIG. 4G ′, the second conductor 19 is formed in the groove 7 at the same time as the minute hole 16, and along the center of the second conductor 19 in the groove 7. By cutting along the line L3, the semiconductor package 2 of the second embodiment shown in FIG. 2 is obtained. If the same metal as that of the first conductor 18 is used as the second conductor, it is convenient because it can be formed simultaneously in one process.
In the semiconductor package 2, the surface of the insulating film C 17 c formed on the side surface of the semiconductor substrate 11 and the surface of the insulating film D 17 d formed on the side surface of the sealing material 30 are further covered with the second conductor 19.
Since the side surface of the semiconductor package is double-coated with a metal conductor in addition to the insulating film, the sealing function is further strengthened, the functional element is completely protected, the operation is stabilized, and the lifetime is further increased. .

本発明は、半導体パッケージの高性能化と長寿命が確保される点でまことに有用である。   The present invention is very useful in that high performance and long life of a semiconductor package are secured.

1,2,40 半導体パッケージ、7 溝、10 第1の基板、11 半導体基板、12 機能素子、13 第1の配線、14 パッド、15 貫通電極、16 微細孔、17 絶縁膜、18 第1の導電体、19 第2の導電体、20 第2の基板、30 封止材。   1, 2, 40 Semiconductor package, 7 grooves, 10 1st substrate, 11 Semiconductor substrate, 12 Functional element, 13 1st wiring, 14 Pad, 15 Through electrode, 16 Micro hole, 17 Insulating film, 18 1st Conductor, 19 2nd conductor, 20 2nd board | substrate, 30 sealing material.

Claims (5)

半導体基材と、該半導体基材の一方の面側に配置された機能素子及び該機能素子に第1の配線を介して電気的に接続されたパッドと、該パッドと電気的に接続され前記半導体基材の一方の面から他方の面に至る微細孔内に絶縁膜Aを介して第1の導電体を形成してなる貫通電極とを少なくとも備えてなる第1の基板、及び前記機能素子の周囲に配置された封止材を用いて前記第1の基板の一方の面と接合されてなる第2の基板からなる半導体パッケージであって、前記絶縁膜Aは、前記半導体基材の他方の面に配置される絶縁膜B、前記半導体基材の外側面に配置される絶縁膜C及び前記封止材の外側面に配置される絶縁膜Dとを具備してなることを特徴とする半導体パッケージ。   A semiconductor substrate, a functional element disposed on one side of the semiconductor substrate, a pad electrically connected to the functional element via a first wiring, and the pad electrically connected to the pad A first substrate comprising at least a through electrode formed by forming a first conductor through an insulating film A in a fine hole extending from one surface of the semiconductor substrate to the other surface, and the functional element A semiconductor package comprising a second substrate joined to one surface of the first substrate using a sealing material disposed around the substrate, wherein the insulating film A is the other of the semiconductor substrates. An insulating film B disposed on the surface of the semiconductor substrate, an insulating film C disposed on the outer surface of the semiconductor substrate, and an insulating film D disposed on the outer surface of the sealing material. Semiconductor package. 前記絶縁膜Aは、前記半導体基材の他方の面に配置される絶縁膜B、前記半導体基材の外側面に配置される絶縁膜C及び前記封止材の外側面に配置される絶縁膜Dと一体化されていることを特徴とする請求項1に記載の半導体パッケージ。   The insulating film A includes an insulating film B disposed on the other surface of the semiconductor substrate, an insulating film C disposed on the outer surface of the semiconductor substrate, and an insulating film disposed on the outer surface of the sealing material. The semiconductor package according to claim 1, wherein the semiconductor package is integrated with D. 前記絶縁膜C及び前記絶縁膜Dは、さらに第1の導電体と同じ部材からなる第2の導電体で被覆されていることを特徴とする請求項1または請求項2に記載の半導体パッケージ。   The semiconductor package according to claim 1 or 2, wherein the insulating film C and the insulating film D are further covered with a second conductor made of the same member as the first conductor. 半導体基材の一面に機能素子、第1の配線及びパッドを設けてなる第1の基板に対して、第2の基板を機能素子が内側になるようにして封止材を用いて接合する工程と、前記半導体基材の他方の面に所定のパターンを有するマスクを形成する工程と、前記半導体基材を前記マスクを介してエッチングして前記パッドに対応する位置に該パッドに達する孔を形成するとともに、前記機能素子、第1の配線及びパッドを取り囲むように前記封止材に達する溝を形成する工程と、該溝の底部にある封止材をエッチング除去して第2の基板を露出させる工程と、前記孔及び溝の内面に絶縁膜を形成する工程と、該孔の底部に形成された絶縁膜をエッチング除去する工程と、該孔内に第1の導電体を充填して貫通電極を形成する工程と、前記第2の基板まで達する貫通孔の内壁に沿って切断する工程
とを含むことを特徴とする半導体パッケージの製造方法。
A step of bonding a second substrate to a first substrate provided with a functional element, a first wiring, and a pad on one surface of a semiconductor substrate using a sealing material so that the functional element is on the inside. And forming a mask having a predetermined pattern on the other surface of the semiconductor substrate, and etching the semiconductor substrate through the mask to form a hole reaching the pad at a position corresponding to the pad And a step of forming a groove reaching the sealing material so as to surround the functional element, the first wiring, and the pad, and the second substrate is exposed by etching away the sealing material at the bottom of the groove A step of forming an insulating film on the inner surfaces of the hole and the groove, a step of etching away the insulating film formed on the bottom of the hole, and filling the hole with the first conductor to penetrate Forming the electrode and the second substrate; The method of manufacturing a semiconductor package which comprises a step of in reaching along the inner wall of the through-hole cutting.
半導体基材の一面に機能素子、第1の配線及びパッドを設けてなる第1の基板に対して、第2の基板を機能素子が内側になるようにして封止材を用いて接合する工程と、前記半導体基材の他方の面に所定のパターンを有するマスクを形成する工程と、前記半導体基材を前記マスクを介してエッチングして前記パッドに対応する位置に該パッドに達する孔を形成するとともに、前記機能素子、第1の配線及びパッドを取り囲むように前記封止材に達する溝を形成する工程と、該溝の底部にある封止材をエッチング除去して第2の基板を露出させる工程と、前記孔及び溝の内面に絶縁膜を形成する工程と、該孔の底部に形成された絶縁膜をエッチング除去する工程と、該孔内に第1の導電体を充填して貫通電極を形成すると同時に、前記溝内にも第1の導電体を充填する工程と、前記第2の基板まで達する溝内に形成された第1の導電体を切断する工程とを含むことを特徴とする半導体パッケージの製造方法。   A step of bonding a second substrate to a first substrate provided with a functional element, a first wiring, and a pad on one surface of a semiconductor substrate using a sealing material so that the functional element is on the inside. And forming a mask having a predetermined pattern on the other surface of the semiconductor substrate, and etching the semiconductor substrate through the mask to form a hole reaching the pad at a position corresponding to the pad And a step of forming a groove reaching the sealing material so as to surround the functional element, the first wiring, and the pad, and the second substrate is exposed by etching away the sealing material at the bottom of the groove A step of forming an insulating film on the inner surfaces of the hole and the groove, a step of etching away the insulating film formed on the bottom of the hole, and filling the hole with the first conductor to penetrate At the same time as forming the electrode, in the groove Process and the method of manufacturing a semiconductor package which comprises a step of cutting the first conductor formed on the second groove which reaches to the substrate to fill the first conductor.
JP2009014738A 2009-01-26 2009-01-26 Semiconductor package Expired - Fee Related JP4908528B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009014738A JP4908528B2 (en) 2009-01-26 2009-01-26 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009014738A JP4908528B2 (en) 2009-01-26 2009-01-26 Semiconductor package

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2004194663A Division JP4271625B2 (en) 2004-06-30 2004-06-30 Semiconductor package and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2009158962A true JP2009158962A (en) 2009-07-16
JP4908528B2 JP4908528B2 (en) 2012-04-04

Family

ID=40962569

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009014738A Expired - Fee Related JP4908528B2 (en) 2009-01-26 2009-01-26 Semiconductor package

Country Status (1)

Country Link
JP (1) JP4908528B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8497557B2 (en) 2009-04-06 2013-07-30 Denso Corporation Semiconductor device
KR20210118450A (en) 2019-03-06 2021-09-30 미쓰비시덴키 가부시키가이샤 Semiconductor device and method for manufacturing the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0487354A (en) * 1990-07-30 1992-03-19 Hitachi Ltd Semiconductor device
JPH06224318A (en) * 1993-01-26 1994-08-12 Kyocera Corp Semiconductor device
JP2003116066A (en) * 2001-10-04 2003-04-18 Sony Corp Solid-state image sensing device and manufacturing method therefor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0487354A (en) * 1990-07-30 1992-03-19 Hitachi Ltd Semiconductor device
JPH06224318A (en) * 1993-01-26 1994-08-12 Kyocera Corp Semiconductor device
JP2003116066A (en) * 2001-10-04 2003-04-18 Sony Corp Solid-state image sensing device and manufacturing method therefor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8497557B2 (en) 2009-04-06 2013-07-30 Denso Corporation Semiconductor device
KR20210118450A (en) 2019-03-06 2021-09-30 미쓰비시덴키 가부시키가이샤 Semiconductor device and method for manufacturing the same
DE112019006965T5 (en) 2019-03-06 2021-11-11 Mitsubishi Electric Corporation Semiconductor device and method of manufacturing the same
DE112019006965B4 (en) 2019-03-06 2023-04-27 Mitsubishi Electric Corporation Semiconductor device and method of manufacturing the same

Also Published As

Publication number Publication date
JP4908528B2 (en) 2012-04-04

Similar Documents

Publication Publication Date Title
JP4271625B2 (en) Semiconductor package and manufacturing method thereof
JP5344336B2 (en) Semiconductor device
US9181084B2 (en) Electronic device package and fabrication method thereof
JP4722702B2 (en) Semiconductor package and manufacturing method thereof
TWI573253B (en) Sensor package with exposed sensor array and method of making same
TWI387065B (en) Electronic device packages and methods of formation
KR101420934B1 (en) Wire bond interposer package for cmos image sensor and method of making same
JP5450295B2 (en) Imaging apparatus and manufacturing method of imaging apparatus
EP1167281A2 (en) Chip scale surface-mountable packaging method for electronic and MEMS devices
JP2005109221A (en) Wafer-level package and its manufacturing method
US20080296714A1 (en) Wafer level package of image sensor and method for manufacturing the same
JP2008066679A (en) Solid-state imaging apparatus, and manufacturing method thereof
CN107369695B (en) Chip package and method for manufacturing the same
TWI525805B (en) Low profile image sensor
JP2010232400A (en) Semiconductor substrate, method of manufacturing semiconductor substrate, and semiconductor package
JP2009016623A (en) Semiconductor package
JP4908528B2 (en) Semiconductor package
JP2014241446A (en) Sensor package and manufacturing method thereof
JP2011159882A (en) Semiconductor device, and method of manufacturing the same
JP2009043893A (en) Semiconductor package and manufacturing method thereof
JP2007288024A (en) Sensor chip, and manufacturing method thereof
CN217405421U (en) Packaging structure
CN211555854U (en) Packaging structure and semiconductor device
CN107946335B (en) CMOS image sensing packaging structure and manufacturing method thereof
KR102409479B1 (en) Wafer level hermetic package manufacturing method

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110705

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110905

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20111011

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111212

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120104

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120112

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150120

Year of fee payment: 3

R151 Written notification of patent or utility model registration

Ref document number: 4908528

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150120

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees