JP2009152859A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which can improve a mirror accuracy of a current mirror circuit without complicating a circuit. <P>SOLUTION: A semiconductor integrated circuit has a reference current generation circuit 1 generating a reference current which flows through a current mirror circuit, a mirror source first transistor M1 which flows the reference current between a drain and a source, a mirror destination second transistor M2 composing the current mirror circuit with the M1, a differential amplifier 2 which uses the M2 as a current source, and a mirror deviation adjusting circuit 3 which matches a drain voltage of the M1 with the drain voltage of the M2. The mirror deviation adjusting circuit 3 composed of a fifth transistor M5 is connected to a drain side of the M1, and a gate voltage of the M5 is matched with the average of both gate voltages of a third transistor M3 and a fourth transistor M4 connected to the drain side of the M2. Thus, the deviation of the drain voltages between the M1 and the M2 is eliminated. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit having a current mirror circuit.

  A semiconductor integrated circuit is configured by combining a number of MOS transistors. A current mirror circuit can be configured by arranging MOS transistors in pairs. Since the current mirror circuit can flow a current proportional to the reference current, it can be used as a current source such as a differential amplifier.

  When configuring a current mirror circuit using MOS transistors, the gates of a pair of MOS transistors are connected to each other, and a reference current is passed between the drain and source of one of the MOS transistors (hereinafter, mirror source transistor). As a result, a current of an amount obtained by multiplying the reference current by the mirror ratio flows between the drain and source of the other MOS transistor (hereinafter referred to as mirror destination transistor). The mirror ratio is the ratio of the gate width of a pair of MOS transistors.

  If the current mirror circuit is designed without any contrivance, the drain voltage of the mirror source transistor and the drain voltage of the mirror destination transistor are different. Even if both drain voltages are different, if the output resistance of the mirror destination transistor is sufficiently high, the current is accurately copied from the mirror source transistor to the mirror destination transistor, so that no problem occurs.

  However, a transistor used in the advanced process cannot obtain a sufficiently high output resistance. If the output resistance of the mirror destination transistor is not high enough, if the drain voltage of the mirror source transistor and the drain voltage of the mirror destination transistor are different, the current flowing through the mirror destination transistor is shifted due to the low output resistance. Arise. More specifically, when the drain voltage of the mirror destination transistor is high, the current of the mirror destination transistor increases. Conversely, when the drain voltage is low, the current decreases. When such a shift occurs, the DC operating point of a circuit (for example, a differential amplifier) connected to the drain of the mirror destination transistor shifts, and the transconductance changes to change the gain of the differential amplifier. When the next stage circuit is also connected to the output of the differential amplifier, the DC operating point of this next stage circuit is also shifted, and the same problem can occur in this next stage circuit.

As the miniaturization of the MOS transistor progresses, the output resistance of the MOS transistor becomes smaller, and the above-described problem becomes remarkable.
JP-A-6-104762

  The present invention provides a semiconductor integrated circuit capable of improving the mirror accuracy of a current mirror circuit without complicating the circuit.

  According to one embodiment of the present invention, a first transistor through which a reference current flows, a second transistor that forms a current mirror circuit together with the first transistor, and the second transistor as a current source are used to obtain a difference. A differential amplifier having third and fourth transistors for generating a differential output signal corresponding to a dynamic input signal; a drain voltage or a collector voltage of the first transistor; and a drain voltage or a collector voltage of the second transistor And a mirror deviation adjusting circuit connected to the drain or collector of the first transistor so that the two are equal to each other. A semiconductor integrated circuit is provided.

  According to the present invention, the mirror accuracy of the current mirror circuit can be improved without complicating the circuit.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a circuit diagram of a semiconductor integrated circuit according to the first embodiment of the present invention. The semiconductor integrated circuit of FIG. 1 includes a reference current generation circuit 1 that generates a reference current that flows in a current mirror circuit, a mirror-source first transistor M1 that flows a reference current between a drain and a source, and a first transistor M1. The second transistor M2 at the mirror destination constituting the current mirror circuit, the differential amplifier 2 using the second transistor M2 as a current source, the drain voltage of the first transistor M1, and the drain voltage of the second transistor M2 And a mirror deviation adjusting circuit 3 for matching the two.

The differential amplifier 2 includes third and fourth transistors M3 and M4 whose sources are commonly connected to the drain of the second transistor M2. Differential input signals IN ⁺ and IN ⁻ are applied to the gate of the third transistor M3 and the gate of the fourth transistor M4, and a differential output is output from the drain of the third transistor M3 and the drain of the fourth transistor M4. Signals OUT ⁺ and OUT ⁻ are output. The differential input signals IN ⁺ and IN ⁻ may be AC signals or DC signals.

  The mirror deviation adjustment circuit 3 includes a fifth transistor M5 and a reference voltage generation circuit 4 that sets a gate voltage of the fifth transistor M5. The drain of the fifth transistor M5 is connected to the gate of the first transistor M1, and the source of the fifth transistor M5 is connected to the drain of the first transistor M1.

The reference voltage generation circuit 4 applies an average voltage (common mode voltage) of the gate voltage of the third transistor M3 and the gate voltage of the fourth transistor M4 to the gate of the fifth transistor M5. The reference voltage generation circuit 4 may perform a process of averaging the gate voltages (differential input signals IN ⁺ and IN ⁻ ) of the third and fourth transistors M3 and M4, but the differential input signal IN ⁺ , IN ⁻ is an AC signal, the reference voltage generation circuit 4 may generate the common mode voltage described above. This common mode voltage generates not only the gate of the fifth transistor M5 but also the differential input signals IN ⁺ and IN ⁻ which are applied to both gates of the third and fourth transistors M3 and M4. It is also applied to a circuit (not shown). This circuit (not shown) generates an AC signal that fluctuates up and down with the common mode voltage as a reference, and these AC signals become differential input signals IN ⁺ and IN ⁻ .

  The semiconductor integrated circuit of FIG. 1 shows an example in which all of the first to fifth transistors M1 to M5 are configured by N-type MOS transistors, but may be configured by P-type MOS transistors as will be described later. . Moreover, you may comprise with a bipolar transistor (NPN transistor or PNP transistor).

  By applying the average value of the gate voltages of the third and fourth transistors M3 and M4 to the gate of the fifth transistor M5, the drain voltage of the first transistor M1 constituting the current mirror circuit and the second voltage The drain voltage of the transistor M2 can be made equal. When the drain voltage of the first transistor M1 and the drain voltage of the second transistor M2 are equal, the current flowing between the drain and source of the first transistor M1, and the current flowing between the drain and source of the second transistor M2 Is equal to the ratio (mirror ratio) of the gate width of the first transistor M1 and the gate width of the second transistor M2. That is, with the circuit configuration as shown in FIG. 1, a current that matches the mirror ratio can be passed to the drain of the second transistor.

The drain-source current of the first transistor M1 is equal to the drain-source current of the fifth transistor M5, and the drain-source current of the second transistor M2 is the drain-source current of the third transistor M3. And the drain-source current of the fourth transistor M4, the gate widths of the first to fifth transistors M5 are W (M1), W (M2), W (M3), and W (M4), respectively. , W (M5), the following equation (1) holds.
W (M1): W (M2) = W (M5): {W (M3) + W (M4)} = 1: n
... (1)

  Therefore, the output current of the second transistor M2 that is the mirror destination transistor is a mirror ratio (M (M2) / W (M1)) to the reference current that flows between the drain and source of the first transistor M1 that is the mirror source transistor. The current value is multiplied by.

  Thus, in this embodiment, in order to make the drain voltage of the mirror source transistor (first transistor M1) coincide with the drain voltage of the mirror destination transistor (second transistor M2), the drain side of the first transistor M1 Is connected to the mirror shift adjustment circuit 3 comprising the fifth transistor M5, and the gate voltage of the fifth transistor M5 is connected to the drain side of the second transistor M2 of the third and fourth transistors M3 and M4. Since it matches the average value of both gate voltages, there is no deviation between the drain voltage of the first transistor M1 and the drain voltage of the second transistor M2. Therefore, the output current of the second transistor M2, which is the mirror destination transistor, becomes a value obtained by multiplying the reference current flowing through the first transistor M1, which is the mirror source transistor, by the mirror ratio of the current mirror circuit, thereby improving the mirror accuracy. I can plan.

  According to this embodiment, even when the miniaturization of the transistor advances and the output resistance of the second transistor M2 that is the mirror destination transistor becomes small, the drain voltage of the mirror source transistor matches the drain voltage of the mirror destination transistor. Therefore, the deviation between the design value and the actual measurement value of the semiconductor integrated circuit can be reduced, and the electrical characteristics of the entire semiconductor integrated circuit can be improved.

  Further, since the mirror deviation adjusting circuit 3 of the present embodiment can be configured by only the fifth transistor M5, the mirror accuracy of the current mirror circuit can be improved without complicating the circuit configuration, and the semiconductor can be further integrated. Is possible.

(Second Embodiment)
In the second embodiment described below, the gate voltages of the transistors in the mirror deviation adjustment circuit 3 are made to coincide with the gate voltages of the third and fourth transistors M3 and M4 constituting the differential amplifier 2. .

  FIG. 2 is a circuit diagram of a semiconductor integrated circuit according to the second embodiment of the present invention. In FIG. 2, the same reference numerals are given to components common to FIG. 1, and the differences will be mainly described below.

  In the semiconductor integrated circuit of FIG. 2, the configuration of the mirror deviation adjusting circuit 3 is different from that of FIG. The mirror deviation adjusting circuit 3 in FIG. 2 includes a sixth transistor M6 connected in parallel to the fifth transistor M5. The sixth transistor M6 is also an N-type MOS transistor.

  In the fifth and sixth transistors M5 and M6, the drains are connected to each other, and the sources are also connected to each other. The gate of the fifth transistor M5 is connected to the gate of the third transistor M3, and the gate of the sixth transistor M6 is connected to the gate of the fourth transistor M4.

In the circuit of FIG. 1, when differential input signals IN ⁺ and IN ⁻ having large amplitude are applied to the gates of the third and fourth transistors M3 and M4, the current mirror circuit is caused by the nonlinearity of the MOS transistor. Thus, the drain voltage of the first transistor M1 and the drain voltage of the second transistor M2 are shifted, and the accuracy of the mirror ratio cannot be improved.

  Therefore, in the circuit of FIG. 2, the sixth transistor M6 is provided in the mirror displacement adjustment circuit 3, and the same voltage as the gates of the third and fourth transistors M3 and M4 is applied to the fifth and sixth transistors M5, M5, This is supplied to each gate of M6.

In the circuit of FIG. 2, the differential input signals IN ⁺ and IN ⁻ applied to the gates of the third and fourth transistors M3 and M4 are also applied to the gates of the fifth and sixth transistors M5 and M6. Therefore, regardless of the amplitudes of the differential input signals IN ⁺ and IN ⁻ , the drain voltage of the first transistor M1 can always match the drain voltage of the second transistor M2.

The mirror ratio in the circuit of FIG. 2 is expressed by the following equation (2).
W (M1): W (M2) = {W (M5) + W (M6)}: {W (M3) + W (M4)} = 1: n (2)

  Therefore, the drain-source current of the second transistor M2 that is the mirror destination transistor is equal to the reference current that flows between the drain and source of the first transistor M1 that is the mirror source transistor with a mirror ratio (n = W (M2) / The current value is multiplied by W (M1)).

As described above, in the second embodiment, since the differential input signals IN ⁺ and IN ⁻ applied to the differential amplifier 2 connected to the mirror destination transistor are also applied to the mirror displacement adjustment circuit 3, the differential input is performed. Even when the amplitudes of the signals IN ⁺ and IN ⁻ are large, the drain voltages of the first and second transistors M1 and M2 constituting the current mirror circuit can be matched to improve the mirror accuracy.

(Third embodiment)
In the third embodiment described below, a mixer input circuit is connected to a current mirror circuit, and a signal obtained by synthesizing an AC signal having another frequency with a differential input signal IN ⁺ , IN ⁻ is a differential output signal. Output as OUT ⁺ and OUT ⁻ .

  FIG. 3 is a circuit diagram of a semiconductor integrated circuit according to the third embodiment of the present invention. In FIG. 3, the same reference numerals are given to components common to FIG. 2, and different points will be mainly described below.

  The circuit of FIG. 3 has a configuration in which a mixer input circuit 5 is connected to the circuit of FIG. The mixer input circuit 5 is connected between the gate of the first transistor M1 and the gate of the second transistor M2 constituting the current mirror circuit.

  The mixer input circuit 5 of FIG. 3 includes a resistor R1 and a capacitor C1, and the resistor R1 is connected between the gate of the first transistor M1 and the gate of the second transistor M2. One end of the capacitor C1 is connected between the resistor R1 and the gate of the second transistor M2, and an AC signal is applied to the other end of the capacitor C1. The resistor R1 functions to block the AC signal IN from flowing to the transistor M1 side. The capacitor C1 is a coupling capacitor that allows the AC signal IN to pass but blocks the bias voltage.

By connecting the mixer input circuit 5 between the gate of the first transistor M1 and the gate of the second transistor M2, the transistors M2, M3 and M4 function as a mixer circuit. Specifically, the transistors M3 and M4 output differential output signals OUT ⁺ and OUT ⁻ having a frequency obtained by synthesizing the frequencies of the differential input signals IN ⁺ and IN ^{− and} the frequency of the AC signal IN.

In the first and second embodiments described above, the differential input signals IN ⁺ and IN ⁻ applied to the gates of the third and fourth transistors M3 and M4 may be either DC or AC, but the third embodiment The differential input signals IN ⁺ and IN ⁻ are limited to alternating current. The differential input signals IN ⁺ and IN ⁻ applied to the differential amplifier 2 and the AC signal IN applied to the mixer input circuit 5 are unrelated signals, and the frequency of both may be different or the same. There is also a possibility.

The operation of the semiconductor integrated circuit of FIG. 3 will be described below. The AC signal IN applied to the mixer input circuit 5 is applied to the gate of the second transistor M2 without passing through the resistor R1 after passing through the capacitor C1. Therefore, a current corresponding to the AC signal IN flows through the drain of the second transistor M2. This current is distributed to the third and fourth transistors M3 and M4 in accordance with the magnitude relationship between the differential input signals IN ⁺ and IN ⁻ . Since the AC signal IN and the differential input signals IN ⁺ and IN ⁻ have different frequencies, the differential output signals OUT ⁺ and OUT ⁻ flowing through the drains of the third and fourth transistors M3 and M4 are the AC signal IN. And the frequency of the differential input signals IN ⁺ and IN ⁻ .

Since the semiconductor integrated circuit of FIG. 3 also has the mirror displacement adjustment circuit 3, the drain voltage of the first transistor M1 and the drain voltage of the second transistor M2 constituting the current mirror circuit can be matched, and the mirror ratio can be increased. The corresponding current flows through the second transistor M2 which is a mirror destination transistor, and the currents of the differential output signals OUT ⁺ and OUT ⁻ also have values corresponding to the mirror ratio.

As described above, in the third embodiment, even when the mixer input circuit 5 is connected to the current mirror circuit, the differential output signals OUT ⁺ and OUT ⁻ having a current value corresponding to the mirror ratio can be generated.

(Fourth embodiment)
In the fourth embodiment, the configuration of the mixer input circuit 5 is simplified as compared with the third embodiment.

  FIG. 4 is a circuit diagram of a semiconductor integrated circuit according to the fourth embodiment of the present invention. In FIG. 4, the same components as those in FIG. 3 are denoted by the same reference numerals, and different points will be mainly described below.

  The semiconductor integrated circuit of FIG. 4 includes a mixer input circuit 5a having a configuration different from that of FIG. 4 includes only the capacitor C1, one end of the capacitor C1 is connected to the drain of the second transistor M2, which is a mirror destination transistor, and the AC signal IN is applied to the other end of the capacitor C1. The

When an alternating signal IN is applied to the mixer input circuit 5a, the drain current of the second transistors M2, a current corresponding to the AC signal IN is superimposed, accordingly, the differential output signal OUT ^+, OUT ^- current Also changes. Differential output signal ^OUT +, OUT ^- while the OUT ⁺ is the AC signal IN and the differential input signal ^IN +, IN ^- current corresponding to the difference between ^- the other IN of. Differential output signal ^OUT +, OUT ^-, the AC signal IN and the differential input signal ^IN +, IN ^{- -} other OUT of one current corresponding to the sum of the IN ⁺ of.

  Unlike the mixer input circuit 5 of FIG. 3, the mixer input circuit 5a of FIG. 4 does not amplify the AC signal IN applied to the mixer input circuit 5a by the second transistor M2, so that the amplitude of the AC signal IN is sufficiently high. Applicable in some cases. On the other hand, when the amplitude of the AC signal IN is small, the mixer input circuit 5a of FIG. 3 that amplifies the AC signal IN by the second transistor M2 is more desirable.

  Also in the semiconductor integrated circuit of FIG. 4, since the drain voltages of the first and second transistors M1 and M2 constituting the current mirror circuit coincide with each other as in the semiconductor integrated circuit of FIGS. The matching current can be supplied to the second transistor M2 which is the mirror destination transistor, and the mirror accuracy can be improved.

  As described above, in the fourth embodiment, the circuit configuration of the mixer input circuit 5a can be simplified and the configuration of the entire semiconductor integrated circuit can be simplified as compared with the third embodiment.

(Other embodiments)
In the third to fourth embodiments described above, the mixer input circuit 5a is added to the circuit of the second embodiment shown in FIG. 2, but the mixer input circuit 5a is added to the circuit of the first embodiment shown in FIG. May be added.

  In the first to fourth embodiments described above, the example in which the semiconductor integrated circuit is configured using the N-type MOS transistor has been described. However, the semiconductor integrated circuit may be configured using the P-type MOS transistor.

  FIG. 5 is a circuit diagram showing an example in which a semiconductor integrated circuit having the same configuration as that of the first embodiment is configured using a P-type MOS transistor. As can be seen from FIG. 5, the direction of current flow is opposite to that in FIG. 1, but the connection relationship between the MOS transistors is the same as in FIG. The source of the fifth transistor M5a constituting the mirror deviation adjusting circuit 3 is connected to the drain of the first transistor M1a which is a mirror source transistor, and the drain of the fifth transistor M5a is connected to the gate of the first transistor M1a. Is done.

  Various circuits can be configured by using the semiconductor integrated circuit described in the first to fourth embodiments. FIG. 6 is a circuit diagram of an operational amplifier configured using the semiconductor integrated circuit described in the first embodiment. 6 corresponds to the circuit of FIG. The output of the differential amplifier 2 is output after being amplified by the transistor M6. A current source 6 is connected to the transistor M6.

In FIG. 1, the differential input signals IN ⁺ and IN ⁻ are applied to the third and fourth transistors M3 and M4 constituting the differential amplifier 2, but in FIG. 6, the third and fourth transistors M3 and M4 are applied. The signals applied to the gates are not the differential input signals IN ⁺ and IN ⁻ . The input signal IN is applied to the third transistor M3, and the gate of the fourth transistor M4 is set to the reference voltage Vb.

  The operational amplifier of FIG. 6 includes a resistor R3 interposed between the gate of the third transistor M3 and the terminal of the input signal IN, and a resistor R4 interposed between the third transistor M3 and the terminal of the output signal OUT. And have. These R3 and R4 are resistance elements that determine the gain of the operational amplifier, and the output signal OUT is amplified to R4 / R3 times the input signal IN.

  In addition, the differential amplifier circuit can be configured using the semiconductor integrated circuits described in the first to fourth embodiments.

  For example, FIG. 7 is a circuit diagram of a fully differential amplification type inverting amplifier configured using the semiconductor integrated circuit described in the first embodiment. In FIG. 7, the same reference numerals are given to components common to FIG. 6, and the differences will be mainly described below.

In the circuit of FIG. 7, the differential input signals IN ⁺ and IN ⁻ are input, and the differential output signals OUT ⁺ and OUT ⁻ are output. One input signal IN ^- is input to the gate of the transistor M3 via a resistor R3. A resistor R4 is interposed between the gate and the terminal of one output signal OUT ⁺ . The other input signal IN ⁺ is input to the gate of the transistor M4 via the resistor R5. Resistor R6 is inserted between the terminal ^- the gate and the other of the output signal OUT.

In the circuit of FIG. 7, the input signal IN ⁼ IN + -IN ^- and then, the output signal ^OUT = ^OUT + -OUT ^- and, if the gain to A, represented by OUT = A × IN.

Here, the gain A is represented by a value obtained by dividing the resistor R4 or R6 corresponding to the differential output signals OUT ⁺ and OUT ⁻ by the resistor R3 or R5 corresponding to the differential input signals IN ⁺ and IN ⁻ . Since the circuit of FIG. 7 is a differential amplifier, R3 = R5, R4 = R6, and A = R4 / R3 = R6 / R5.

  The circuits shown in FIGS. 6 and 7 are merely examples, and various modifications can be applied.

1 is a circuit diagram of a semiconductor integrated circuit according to a first embodiment of the present invention. The circuit diagram of the semiconductor integrated circuit which concerns on the 2nd Embodiment of this invention. The circuit diagram of the semiconductor integrated circuit which concerns on the 3rd Embodiment of this invention. The circuit diagram of the semiconductor integrated circuit which concerns on the 4th Embodiment of this invention. FIG. 3 is a circuit diagram showing an example in which a semiconductor integrated circuit having a configuration similar to that of the first embodiment is configured using a P-type MOS transistor. FIG. 3 is a circuit diagram of an inverting amplifier configured using the semiconductor integrated circuit described in the first embodiment. 1 is a circuit diagram of a fully differential amplification type inverting amplifier configured using the semiconductor integrated circuit described in the first embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Reference current generation circuit 2 Differential amplifier 3 Mirror shift adjustment circuit 4 Reference voltage generation circuit 5, 5a Mixer input circuit M1 1st transistor M2 2nd transistor M3 3rd transistor M4 4th transistor M5 5th transistor

Claims (5)

A first transistor through which a reference current flows;
A second transistor constituting a current mirror circuit together with the first transistor;
A differential amplifier having third and fourth transistors for generating a differential output signal according to a differential input signal using the second transistor as a current source;
A mirror displacement adjustment circuit connected to the drain or collector of the first transistor so that the drain voltage or collector voltage of the first transistor is equal to the drain voltage or collector voltage of the second transistor; A semiconductor integrated circuit comprising: The mirror displacement adjustment circuit includes a fifth transistor,
A DC average voltage of the gate voltage or base voltage of the third transistor and the gate voltage or base voltage of the fourth transistor is applied to the gate or base of the fifth transistor,
The source or emitter of the fifth transistor is connected to the drain or collector of the first transistor, and the drain or collector of the fifth transistor is connected to the gate or base of the first transistor. The semiconductor integrated circuit according to claim 1. The mirror deviation adjusting circuit includes fifth and sixth transistors in which sources or emitters are connected to each other and drains or collectors are connected to each other,
The gate or base of the third transistor is connected to one gate or base of the fifth and sixth transistors, and the gate or base of the fourth transistor is connected to the other gate or base,
The source or emitter of the fifth and sixth transistors is connected to the drain or collector of the first transistor, and the drain or collector of the fifth and sixth transistors is connected to the gate or base of the first transistor. The semiconductor integrated circuit according to claim 1, wherein: A mixer input circuit connected between the gates or bases of the first and second transistors;
The mixer input circuit is
An impedance element connected between the gates or bases of the first and second transistors;
A capacitor element having one end connected to a connection node between the impedance element and the gate or base of the second transistor, and the other end receiving an AC signal unrelated to the differential input signal; The semiconductor integrated circuit according to claim 1, wherein: A mixer input circuit connected between the gates or bases of the first and second transistors;
The mixer input circuit is
4. A capacitor element having one end connected to the drain or collector of the second transistor and the other end receiving an AC signal unrelated to the differential input signal. The semiconductor integrated circuit in any one.

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