JP2009147686A - Data output circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem that the output timing of effective output data is not constant for every test in a test employing automatic test equipment (ATE) for a data output circuit in an LSI (large scale integrated circuit) comprising a PLL (phase locked loop) circuit or the like. <P>SOLUTION: The data output circuit 20 has a clock producing circuit 21 and a reset control circuit 22, wherein an output control circuit 23 is connected to the output side of the circuit 21. The circuit 21 is constituted of a PLL circuit 21a which activates and outputs a clock signal LK when the phase of a reference clock signal RCK coincides with the phase of an internal clock signal PCK oscillated in the circuit and then outputs the signal PCK and a frequency division circuit 21b which divides the signal PCK and outputs the clock signal CK. The circuit 22 controls the signal LK by a lock enable signal LKEB and changes a timing for releasing the reset condition of the circuit 21b. The circuit 23 inputs the signal CK and outputs the output data TXD of effective data with a predetermined timing when the data output condition is enabled. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention is mounted on a semiconductor integrated circuit such as an integrated circuit (hereinafter referred to as “IC”) or a large scale integrated circuit (hereinafter referred to as “LSI”), and is a data output circuit having a clock generation circuit or the like, such as an IC. When performing a data output test on a semiconductor integrated circuit or the like using an automatic test equipment (hereinafter referred to as “ATE”) such as a tester, the test may be facilitated and highly accurate. The present invention relates to a possible data output circuit.

  Conventionally, as a technique for facilitating the test and the like, for example, there are those described in the following documents.

JP-A-9-185900 JP-A-10-26654

  Patent Document 1 describes a technique of a dynamic random access memory (DRAM) that performs a test without increasing the number of external terminals and shortens the test time. Patent Document 2 describes a semiconductor device technology that can realize a test without newly adding a dedicated terminal and further reduce the test time. Examples of data output circuits related to these include the following.

FIG. 9 is a schematic configuration diagram showing a conventional data output circuit.
The data output circuit 10 is provided in an LSI, for example, and has a phase locked loop circuit (hereinafter referred to as “PLL circuit”) 11. A frequency divider 12 and a selector 13 are provided on the output side. The output control circuit 14 is connected via

  Here, the data output circuit 10 receives the reference clock signal RCK of the PLL circuit 11, the test mode signal TMD, and the test clock signal TCK used in the test mode. The reference clock signal RCK is input to the reference clock input terminal ref of the PLL circuit 11. The internal clock signal PCK output from the output terminal pllo of the PLL circuit 11 is input to the clock input terminal dclk of the frequency divider circuit 12. Further, the lock signal LK is output from the output terminal lock of the PLL circuit 11 and is input to the asynchronous reset terminal rn that is the low active input terminal in the frequency divider circuit 12. A frequency-divided clock signal DCK is output from the output terminal div of the frequency divider circuit 12.

  The lock signal LK is logic “0” until the PLL circuit 11 is locked, and becomes logic “1” when the PLL circuit 11 is locked. The time from when the reference clock signal RCK is input to the PLL circuit 11 to when the internal clock signal PCK and the lock signal LK are output differs depending on the specifications of each PLL circuit 11, and the manufacturing process such as LSI, voltage, The circuit may change each time the circuit is tested due to various factors such as not only the temperature but also the state after power-on of the LSI or the like.

  When the lock signal input to the asynchronous reset terminal rn of the frequency divider circuit 12 is “0”, the frequency-divided clock signal DCK of the frequency divider circuit 12 is reset to “0”. When the lock signal LK is “1”, the frequency dividing circuit 12 can divide the internal clock signal PCK and outputs a divided clock signal DCK obtained by dividing the internal clock signal PCK by 1 / M (for example, 4). To do.

  In the selector 13, the test clock signal TCK input to the data output circuit 10 and the frequency-divided clock signal DCK that is the output of the frequency-dividing circuit 12 depend on the value of the test mode signal TMD input to the data output circuit 10. This is selected and output as a clock signal CK for the output control circuit 14. The test clock signal TCK is selected when the test mode signal TMD is “1”, and the divided clock signal DCK is selected when the test clock signal TMD is “0”.

  The clock signal CK is input to the clock input terminal clk of the output control circuit 14, and output data TXD is output from the output terminal out of the output control circuit 14.

FIG. 10 is a timing chart showing the operation of the data output circuit 10 of FIG.
At time T0, the data output circuit 10 is initialized by an initialization signal given from ATE or the like. Hereinafter, the operation (I) when the test clock signal TCK is not used and the operation (II) when the test clock signal TCK is used will be described.

(I) Operation when the test clock signal TCK is not used First, the test mode signal TMD is always “0”. The PLL circuit 11 is oscillated by being supplied with a reference clock signal RCK having a frequency corresponding to this specification. When a certain time elapses, the internal clock signal PCK of the PLL circuit 11 starts to oscillate, and the lock signal LK becomes “1”. As shown in assertion timing examples (1) and (2) at which the lock signal LK becomes “1” (that is, active), the oscillation timing and locking timing of the internal clock signal PCK differ each time the LSI is tested. Sometimes.

(I) (a) Example of assertion timing of lock signal LK (1)
At time T1, the internal clock signal PCK of the PLL circuit 11 starts to oscillate. At time T2, the lock signal LK becomes “1”. After time T2, since the asynchronous reset terminal rn of the frequency divider circuit 12 is “1” by the lock signal LK, the frequency divider circuit 12 can divide the internal clock signal PCK. At time T4, the divided clock signal DCK starts to oscillate. Since the test mode signal TMD is “0”, the selector 13 selects the divided clock signal DCK as the clock signal CK. The output control circuit 14 starts to operate after the clock signal CK is input. When the data output condition is enabled (satisfied) in the output control circuit 14, the output data TXD that has become valid data starts to be output from the output terminal out at time T6.

(I) (b) Example of assertion timing of lock signal LK (2)
At time T2, the internal clock signal PCK of the PLL circuit 11 starts to oscillate, and at time T3, the lock signal LK becomes “1”. After time T3, since the asynchronous reset terminal rn of the frequency dividing circuit 12 is “1” by the lock signal LK, the frequency dividing circuit 12 can divide the internal clock signal PCK. At time T5, the divided clock signal DCK starts to oscillate. The selector 13 selects the divided clock signal DCK as the clock signal CK because the test mode signal TMD is “0”. The output control circuit 14 starts to operate after the clock signal CK is input. When the data output condition is enabled in the output control circuit 14, the output control circuit 14 starts to output the output data TXD that has become valid data at time T7.

  As described in the above two assertion timing examples (1) and (2), when the test clock signal TCK is not used, the oscillation of the internal clock signal PCK of the PLL circuit 11 and the change in the timing of the lock cause The output timing of the output data TXD of the data output circuit 10 may be different every time a test is performed.

  In the LSI data output test, using an ATE such as an IC tester, it is confirmed that the LSI is operating according to the specifications of the LSI, including functional tests, whether the LSI is operating normally, and whether the characteristics are satisfactory. To do. When various data output tests of the data output circuit 10 are performed, the test pattern is defined in advance with expected output values of “0” and “1” for each test cycle. Therefore, if the output timing of the output data TXD of the data output circuit 10 is shifted, even if the circuit function is operating normally, the test result is caused by “phase shift” or “cycle shift” from the expected value of the output timing. May fail. Therefore, when performing a data output test in such a system, perform the same test multiple times, and pass the test result if it matches the expected value one or more times in any number of times (pass) Is used.

(II) Operation When Using Test Clock Signal TCK At time T0 in FIG. 10, the data output circuit 10 is initialized by an initialization signal given from ATE or the like. When the test clock signal TCK is used, the test mode signal TMD is always “1”. When the test clock signal TCK starts to be input at an arbitrary timing, the selector 13 selects the test clock signal TCK as the clock signal CK because the test mode signal TMD is “1”. The output control circuit 14 starts to operate after the clock signal CK is input. When the data output condition is enabled in the output control circuit 14, the output data TXD of valid data starts to be output from the output terminal out at time T4.

  As the circuit configuration of the data output circuit 10, in FIG. 9, the selector 13 selects either the divided clock signal DCK or the test clock signal TCK of the divider circuit 12, but the internal clock signal PCK or the test clock is selected. A circuit configuration for selecting one of the signals TCK is also conceivable. When the test mode signal TMD is “0”, the internal clock signal PCK is directly input to the clock input terminal clk of the output control circuit 14.

  When the test clock signal TCK is used, the frequency-divided clock signal DCK is not selected, so that the selector 13 and the output control circuit 14 are independent of the oscillation of the internal clock signal PCK output from the PLL circuit 11 and the change in the locking timing. By the operation of the logic circuit, the output timing of the output data TXD that is valid data output from the data output circuit 10 can be made constant.

  However, the conventional data output circuit 10 has the following problems (A) and (B).

(A) When the test clock signal TCK is not used As shown in the assertion timing examples (1) and (2) of the lock signal LK in FIG. 10, the output which is valid data output from the output control circuit 14 from the time T0 The timing at which the data TXD starts to output is different from the predetermined timing due to various factors such as the specifications of each PLL circuit 11, the manufacturing process of the LSI, etc., the voltage, temperature, and the state after turning on the power of the LSI, etc. There is. As a countermeasure, a method is used in which the same test is performed a plurality of times, and the test result is passed if it matches the expected value one or more times, and the test time becomes longer. .

  In addition, the output timing shift of the output data TXD can also occur due to a design error factor such as a SETUP / HOLD timing error of the logic circuit such as the selector 13 or the output control circuit 14, and therefore the expected value As for the test method using the test result as the pass, the reliability as the test result was not satisfactory.

(B) When using test clock signal TCK As shown in the case of using test clock signal TCK in FIG. 10, output control circuit 14 receives test clock signal TCK as clock signal CK from time T0. The operation is started, and the output of the valid data output data TXD is started at time T4 which is a fixed timing. However, in such a test method, two input pins (terminals) for the test clock signal TCK and the test mode signal TMD are necessary, and the number of LSI pins increases. In addition, since the PLL circuit 11 and the frequency dividing circuit 12 are not tested, it is necessary to add a test pattern for the PLL circuit 11 and the frequency dividing circuit 12 and perform a test separately, thereby increasing the test time.

  The test clock signal TCK is input from outside the LSI by an ATE such as an IC tester. The ATE has a structure that can test various circuits, unlike a normal system board that is a board optimized for actual use. In general, a load consisting of a capacitance and a resistance due to a signal line connecting the ATE and the circuit is added to the data input / output terminal to the circuit, so that it cannot be operated at high speed like a system board due to the specifications of the ATE. There is a case. If the high-speed clock signal cannot be input due to such restrictions on the ATE side, the data output circuit 10 operating with the high-speed clock signal at the actual operating frequency cannot be tested. In this case, a delay failure of the LSI (for example, a failure when the delay appears to increase when the resistance increases as the wiring resistance becomes thin during LSI manufacturing) cannot be tested. Property) was not satisfactory. That is, if the LSI can be tested at the normal operating frequency, the delay fault can be tested. However, when the LSI is operated with the test clock signal TCK having a low frequency, even if there is a delay fault, if the delay falls within one cycle of the test clock signal TCK, the LSI seems to operate normally. Cannot be detected because cannot be detected.

  In order to solve such a conventional problem, the present invention controls the timing for releasing a reset state in a clock generation circuit such as a PLL circuit, thereby reducing test time and increasing the reliability of test results. A data output circuit is provided.

  The data output circuit of the present invention generates a clock signal, and when the frequency of the clock signal reaches a predetermined value, a clock generation circuit that releases the reset state and outputs the clock signal, and the predetermined control signal by the first control signal The reset control circuit changes the timing for releasing the reset state by controlling the value of the clock signal, and is activated when the clock signal of the clock generation circuit whose timing for releasing is changed by the reset control circuit is input, And an output control circuit that outputs valid data at a predetermined timing when the output condition is satisfied.

  According to the data output circuit of the present invention, since the circuit configuration does not use the test mode signal and the reset state is released after the operation of the clock generation circuit is stabilized, the following (a) to (c) There is an effect like this.

  (A) The output of a clock signal starts at the same timing every time a test is performed, and the output control circuit activated by the input of the clock signal outputs the output data as valid data at the same other timing. For this reason, it is not necessary to perform the same test multiple times, so that the test time can be shortened.

  (B) The test time can be shortened by the amount that it is not necessary to add a test for the clock generation circuit.

  (C) Since the test can be performed at the actual operating frequency without using the test clock signal, the reliability as the test result (for example, the completeness of the test including the delay fault test) can be improved.

  The data output circuit generates a clock signal in the clock generation circuit, and when the frequency of the clock signal reaches a predetermined value, the reset state is canceled and the clock signal is output, and the reset control circuit outputs the first clock signal. The timing for releasing the reset state is changed by controlling the predetermined value by a control signal. Furthermore, the output control circuit is activated when the clock signal of the clock generation circuit whose timing to be released is changed by the reset control circuit is input, and when the data output condition is satisfied, valid data is transmitted at a predetermined timing. Is output.

  For example, the clock generation circuit compares the phase of the internal clock signal oscillated internally with the phase of the reference clock signal input from the outside, and activates and outputs the lock signal when the two phases coincide with each other. A lock loop circuit that outputs the internal clock signal having a frequency, and a frequency dividing circuit that is activated when the reset state is released and divides the frequency of the internal clock signal to output the clock signal. Yes. The reset control circuit includes control means for outputting a reset signal for controlling a signal representing the predetermined value by the first control signal and changing a timing for releasing the reset state.

(Configuration of Example 1)
FIG. 1 is a schematic configuration diagram of a data output circuit showing a first embodiment of the present invention.
The data output circuit 20 is, for example, a circuit provided in an LSI, and includes a clock generation circuit 21 and a reset control circuit 22, and an output control circuit 23 is connected to the output side of the clock generation circuit 21. ing.

  The clock generation circuit 21 generates a clock signal CK. When the frequency of the clock signal CK reaches a predetermined value, the clock generation circuit 21 releases the reset state and outputs the clock signal CK. For example, the PLL is a lock loop circuit. The circuit 21a and a frequency dividing circuit 21b connected to the output side are configured.

  The reset control circuit 22 is a circuit that changes the timing for releasing the reset state by controlling the predetermined value by a first control signal (for example, lock enable signal) LKEB, and is configured by a control means. This control means controls a signal representing the predetermined value by a lock enable signal LKEB to output a reset signal CLRN that changes the timing for releasing the reset state (for example, a 2-input type AND circuit, hereinafter The AND circuit is referred to as an “AND circuit”) 22a.

  The output control circuit 23 is activated (operated) when the clock signal CK of the clock generation circuit 21 whose timing to be released has been changed by the reset control circuit 22 is input, and when the data output condition is satisfied (enabled). This is a circuit that outputs output data TXD that is valid data at a predetermined timing.

  Here, the PLL circuit 21a constituting the clock generation circuit 21 compares the phase of the internal clock signal PCK oscillated inside with the phase of the reference clock signal (for example, the reference clock signal) RCK, and compares the two phases. Is a circuit that activates (for example, sets to “1”) and outputs the lock signal LK when the two coincide with each other and outputs the internal clock signal PCK having a constant frequency. Therefore, the reference clock signal RCK is input to the reference clock input terminal ref of the PLL circuit 21a. The frequency of the reference clock signal RCK is a frequency corresponding to the specification of the PLL circuit 21a. The PLL circuit 21a sets the lock signal LK to "1" when the phase of the internal clock signal PCK oscillated internally and the phase of the external reference clock signal RCK coincide with each other and outputs it from the first output terminal lock. An internal clock signal PCK having a constant frequency obtained by multiplying the frequency of the signal RCK by 2 is output from the second output terminal pllo. The internal clock signal PCK is input to the clock input terminal dclk of the frequency dividing circuit 21b.

  The lock signal LK and the lock enable signal LKEB output from the output terminal lock of the PLL circuit 21a are input to the AND circuit 22a. The lock enable signal LKEB is a signal generated by a test pattern that becomes “1” after the maximum lock time is exceeded in the ATE test pattern in consideration of the maximum lock time according to the specification of the PLL circuit 21a. . The AND circuit 22a takes a logical product of the lock signal LK and the lock enable signal LKEB and outputs a reset signal CLRN corresponding to the logical result. The reset signal CLRN is input to the reset terminal rn in the low active operation asynchronously in the frequency dividing circuit 21b.

  The frequency dividing circuit 21b is composed of, for example, a flip-flop circuit or a shift register. When the reset signal CLRN input to the reset terminal rn is “0”, the clock signal CK that is the output of the frequency dividing circuit 21b is And is reset to “0”. When the reset signal CLRN is “1”, the frequency dividing circuit 21b can perform frequency division, and the frequency of the internal clock signal PCK output from the PLL circuit 21a is 1 / M frequency division (where M is an integer of 2 or more). ) Is output from the output terminal div. The value of M is set to an arbitrary value (for example, 4) according to the circuit specifications when used in an actual LSI.

  The clock signal CK output from the frequency dividing circuit 21 a is input to the clock input terminal clk of the output control circuit 23. The output control circuit 23 starts operating when the clock signal CK is input, and outputs the output data TXD, which is valid data, from the output terminal out at a predetermined timing when the data output condition is enabled. Regardless of the output format, the output data TXD may be serial data or parallel data, or data on a bidirectional bus or unidirectional.

FIG. 2 is a schematic configuration diagram showing an example of the output control circuit 23 in FIG.
The output control circuit 23 includes a control circuit 23a that controls the entire circuit. Further, a transmission packet generation circuit 23b, a serial conversion circuit 23c, and an output buffer 23d controlled by the control circuit 23a are connected in cascade.

  Here, the clock signal CK is input to the control circuit 23a, the transmission packet generation circuit 23b, and the serial conversion circuit 23c via the clock input terminal clk. The control circuit 23a, the transmission packet generation circuit 23b, and the serial conversion circuit 23c are circuits that operate in synchronization with the rising edge of the clock signal CK. The control circuit 23a is a circuit that generates and outputs a packet generation enable signal genenb, a load signal load, and an output enable signal txenb. The packet generation enable signal genenb is input to the transmission packet generation circuit 23b, the load signal load is input to the serial conversion circuit 23c, and the output enable signal txenb is input to the output buffer 23d. The transmission packet generation circuit 23b is a circuit that generates and outputs parallel transmission packet data PAR, which is controlled by the packet generation enable signal genenb.

  The parallel transmission packet data PAR is input to the serial conversion circuit 23c. The timing for reading (loading) data is controlled by the load signal load. When the load signal load is asserted, the serial conversion circuit 23c temporarily stores (latches) the loaded parallel transmission packet data PAR in an internal register and serializes the data. It is a circuit that converts and outputs transmission packet data SER. The serial transmission packet data SER is input to the output buffer 23d. The output buffer 23d is a circuit that is controlled by the output enable signal txenb and outputs the serial transmission packet data SER from the output terminal out as the output data TXD when the output enable signal txenb is asserted.

(Operation of Example 1)
FIG. 3 is a timing chart showing the operation of the data output circuit 20 of FIG.
At time T0 in FIG. 3, the data output circuit 20 is initialized by an initialization signal provided from ATE or the like. The reference clock signal RCK supplied from the ATE oscillates at a frequency corresponding to the specification of the PLL circuit 21a. The output data TXD is invalid data because the data output condition in the output control circuit 23 is not satisfied (because it is disabled). At time T1, the internal clock signal PCK output from the PLL circuit 21a starts oscillating. When the phase of the internal clock signal PCK matches the phase of the reference clock signal RCK at time T2, the lock signal LK becomes “1”. At this time, since the lock enable signal LKEB supplied from the ATE is “0”, the reset signal CLRN output from the AND circuit 22a is “0”, and the frequency dividing circuit 21b is reset.

  When the lock enable signal LKEB becomes “1” at the time T3 after the maximum lock time according to the specification of the PLL circuit 21a has elapsed, the reset signal CLRN output from the AND circuit 22a becomes “1”, thereby dividing the frequency. The reset terminal rn of the circuit 21b becomes “1”. Then, the frequency dividing circuit 21b is released from the reset state, can divide the internal clock signal PCK, and starts a 1/4 frequency dividing operation. At time T4 of the fourth rising edge of the internal clock signal PCK from time T3, the clock signal CK starts oscillating.

  In the output control circuit 23 of FIG. 2, when the clock signal CK is input, the control circuit 23a, the transmission packet generation circuit 23b, and the serial conversion circuit 23c start operation. The control circuit 23a generates and outputs a packet generation enable signal genenb, a load signal load, and an output enable signal txenb. The transmission packet generation circuit 23b is controlled by the packet generation enable signal genenb, generates parallel transmission packet data PAR, and outputs the parallel transmission packet data PAR to the serial conversion circuit 23c. The serial conversion circuit 23c is controlled by a load signal load, latches the loaded parallel transmission packet data PAR into an internal register, converts the serial transmission packet data SER into serial transmission packet data SER, and outputs the serial transmission packet data SER to the output buffer 23d. The output of the output buffer 23d is controlled by the output enable signal txenb.

  When the data output condition is enabled and the output enable signal txenb is asserted, at time T5 in FIG. 3, the output buffer 23d outputs the serial transmission packet data SER, which is valid data, from the output terminal out as the output data TXD. Start. The output data TXD output after time T5 is checked for dynamic characteristics or the like by an output pattern or the like at ATE to determine whether the data output circuit 20 is good or bad. Note that the output data TXD from time T0 to immediately before time T5 is invalid data.

  Even if the assertion time of the lock signal LK output from the PLL circuit 21a in FIG. 1 may change from test to test, the lock enable signal LKEB supplied from the ATE has passed the maximum lock time according to the specifications of the PLL circuit 21a. After that, it is set to “1”. Thereby, the frequency dividing circuit 21b starts the frequency dividing operation at the same timing for each test. As a result, the clock signal CK is input to the output control circuit 23 at the same timing for each test, and the output data TXD is output from the output control circuit 23 at the same timing.

(Effect of Example 1)
According to the first embodiment, since the lock enable signal LKEB is set to “1” after the maximum lock time according to the specification of the PLL circuit 21a has elapsed, the assertion time of the lock signal LK output from the PLL circuit 21a changes for each test. Even in this case, the following effects (a) to (c) are obtained.

  (A) The frequency dividing operation of the frequency dividing circuit 21b is started at the same timing for each test, and the clock signal CK is input to the output control circuit 23 at the same timing for each test. Therefore, the output data TXD that is valid data can be output from the data output circuit 20 at the same timing.

  (B) It is not necessary to repeat the same test a plurality of times, determine and output a test result, and it is not necessary to add a test for the PLL circuit 21a and the frequency dividing circuit 21b. Thereby, the test time can be shortened.

  (C) The test clock signal TCK as in the prior art is not required, and the test can be performed at the actual operating frequency based on the reference clock signal RCK. Thereby, the reliability (for example, the completeness of a test including a delay fault test etc.) as a test result can be improved.

(Configuration of Example 2)
FIG. 4 is a schematic configuration diagram of a data output circuit showing the second embodiment of the present invention. Elements common to the elements in FIG. 1 showing the first embodiment are denoted by the same reference numerals.

  In the data output circuit 20A of the second embodiment, a reset control circuit 22A having a different configuration from that of the reset control circuit 22 of the first embodiment is provided. The reset control circuit 22A counts the number of pulses of the reference clock signal RCK and, when the count value becomes a constant value, count means (for example, a counter) 22b that outputs the count value CNT, and the counter 22b Comparing means (for example, a comparator) 22c that compares the output count value CNT with the fixed set value LCNT (= N) and outputs the comparison result CMP, and controls the lock signal LK by the comparison result CMP. And a control means (for example, a two-input AND circuit similar to that of the first embodiment) 22a for outputting the reset signal CLRN. Other configurations are the same as those of the first embodiment.

  Here, the reference clock signal RCK supplied from the ATE is input to the input terminal cclk of the counter 22b. The frequency of the reference clock signal RCK is a frequency corresponding to the specification of the PLL circuit 21a as in the first embodiment. The counter 22b is initialized by a reset signal (not shown) given from ATE or the like. After initialization, the counter 22b counts up the number of pulses by +1 in synchronization with the rising edge of the pulse of the reference clock signal RCK, and a certain value (for example, When counting up to the set value LCNT), the count-up operation is stopped and the same count value CNT (= N) is continuously output. The count value CNT and the set value LCNT are respectively input to the comparator 22c.

  The lock time until the lock signal LK output from the PLL circuit 21a becomes "1" varies depending on the manufacturing process, voltage, temperature, and other conditions, but the maximum time in the specification can be determined, so the {PLL circuit The integer value (N) equal to or greater than the result of the maximum lock time of 21a} / {period of the reference clock signal RCK} (rounded up after the decimal point) is set as the set value LCNT.

  The comparator 22c is a circuit that compares the count value CNT with the set value LCNT, and outputs “0” when the comparison result CMP does not match, and outputs “1” when they match. The comparison result CMP is input to the AND circuit 22a instead of the lock enable signal LKEB of the first embodiment. The AND circuit 22a is a circuit that sets the reset signal CLRN to "1" when both the lock signal LK and the comparison result CMP are "1".

(Operation of Example 2)
FIG. 5 is a timing chart showing the operation of the data output circuit 20A of FIG.
At time T0, the data output circuit 20A is initialized by an initialization signal such as ATE. The reference clock signal RCK oscillates at a frequency corresponding to the specification of the PLL circuit 21a. The count value CNT of the counter 22b is initialized to "0" by the initialization signal. Since the count value CNT is “0” and is not equal to the set value LCNT (= N), the comparison result CMP of the comparator 22c is “0”. At time T1, the counter 32a counts up by 1, 2, 3,... +1 in synchronization with the rising edge of the pulse after the rising edge of the first pulse of the reference clock signal RCK. At time T2, the internal clock signal PCK output from the PLL circuit 21a starts oscillating.

  When the phase of the internal clock signal PCK matches the phase of the reference clock signal RCK at time T3, the lock signal CK becomes “1”. At this time, since the set value LCNT (= N) and the count value CNT (= N−4) are not equal, the comparison result CMP is “0”, and the reset signal CLRN output from the AND circuit 22a is “0”. Become.

  When the counter 22b counts up to the count value CNT (= N) at time T4 after the maximum lock time according to the specification of the PLL circuit 21a has elapsed, the count value CNT (= N) and the set value LCNT (= N) are obtained. Therefore, the comparison result CMP is “1”. Therefore, the reset signal CLRN output from the AND circuit 22a is “1”. After time T4, the counter 22b stops the count-up operation and continues to output the count value CNT (= N), so the comparator 22c continues to output “1” as the comparison result CMP. By the reset signal CLRN output from the AND circuit 22a, the frequency dividing circuit 21b has the reset terminal rn set to “1” to cancel the reset state, and the internal clock signal PCK can be frequency-divided. To start.

  At time T5, the frequency dividing circuit 21b starts oscillating the clock signal CK. The output control circuit 23 starts to operate when the clock signal CK is input. When the data output condition is enabled in the output control circuit 23, the output of the output data TXD, which is valid data, is started at time T6. The operation after time T5 is the same as the operation after time T4 in the first embodiment. Note that the output data TXD from time T0 to immediately before time T6 is invalid data.

  Even when the assertion time of the lock signal LK output from the PLL circuit 21a changes for each test, the count value CNT (= N) of the counter 22b and the set value after the maximum lock time according to the specification of the PLL circuit 21a has passed. LCNT (= N) matches. As a result, the comparison result CMP of the comparator 22c becomes “1”, and the reset signal CLRN output from the AND circuit 22a becomes “1”. Therefore, as in the first embodiment, the frequency divider circuit has the same timing for each test. The frequency dividing operation 21b starts. As a result, the clock signal CK is input to the output control circuit 23 at the same timing for each test, and the output data TXD is output from the output control circuit 23 at the same timing.

(Effect of Example 2)
According to the second embodiment, after the maximum lock time according to the specification of the PLL circuit 21a has elapsed, the count value CNT of the counter 22b reaches the set value LCNT (= N), thereby releasing the reset state of the frequency divider circuit 21b. Since the timing becomes the same and the output data TXD is output from the output control circuit 23 at the same timing for each test, the following effects (a) and (b) are obtained.

(A) There are effects similar to those of the first embodiment.
(B) Since there is no need for an input pin for inputting the conventional test clock signal TCK and the lock enable signal LKEB of the first embodiment, the number of LSI pins can be reduced.

(Configuration of Example 3)
FIG. 6 is a schematic configuration diagram of a data output circuit showing the third embodiment of the present invention. Elements common to those in FIG. 4 showing the second embodiment are denoted by common reference numerals.

  The data output circuit 20B of the third embodiment is a modification of the second embodiment, and instead of the reset control circuit 22A of the second embodiment, a reset control circuit 22B having a different configuration is provided. . The reset control circuit 22B counts the number of pulses of the reference clock signal RCK. When the reset signal CLRN is input, the reset control circuit 22B outputs predetermined bit data CNT [n] (where n is a natural number) as a count result. First control means (for example, a counter) 22d and a second control signal (for example, enable signal) ENB control the validity / invalidity of predetermined bit data CNT [n] and output a control result CNTE (for example, And a second control means (e.g., a second logic circuit similar to that of the second embodiment) that controls the lock signal LK based on the control result CNTE and outputs the reset signal CLRN. And a 2-input AND circuit 22a which is a logic circuit of the above. Other configurations are the same as those of the second embodiment.

Here, the reference clock signal RCK is input to the clock terminal cclk of the counter 22d having the set terminal s for asynchronous and high active operation. The frequency of the reference clock signal RCK is a frequency corresponding to the specification of the PLL circuit 21a, as in the second embodiment. The counter 22d counts up the number of pulses by +1 in synchronization with the rising edge of the pulse of the reference clock signal RCK, and the bit data CNT [n] of the nth bit counted from the 0th least significant bit of the count value CNT. Is output from the output terminal co, and when the reset signal CLRN “1” is input to the bit terminal s, all the bits of the count value CNT are set to “all 1 (111... 111b)”. n is selected to be an integer value of a multiple of 2 (2 ⁿ ) equal to or greater than the result of {maximum lock time of PLL circuit 21a} ÷ {period of reference clock signal RCK} (rounded up after the decimal point). Therefore, the bit data CNT [n] becomes “1” after a sufficient time has elapsed from the timing when the lock signal LK of the PLL circuit 21a becomes “1”.

  Bit data CNT [n] and an enable signal ENB for controlling validity / invalidity of the bit data CNT [n] are input to the AND circuit 22e. The AND circuit 22e is a circuit that takes a logical product of the bit data CNT [n] and the enable signal ENB and outputs a control result CNTE corresponding to the logical product. The control result CNTE is input to the AND circuit 22a instead of the lock comparison result CMP of the second embodiment. The reset signal CLRN, which is the output of the AND circuit 22a, is input to the set terminal s of the counter 22d and the reset terminal rn of the frequency dividing circuit 21b.

(Operation of Example 3)
FIG. 7 is a timing chart showing the operation of the data output circuit 20B of FIG.
First, when the enable signal ENB is “0”, both the control result CNTE output from the AND circuit 22e and the reset signal CLRN output from the AND circuit 22a remain “0”. For this reason, the frequency dividing circuit 21b remains reset, and the output control circuit 23 does not operate.

Next, the case where the enable signal ENB is “1” will be described.
At time T0, the data output circuit 20B is initialized by an initialization signal such as ATE. The reference clock signal RCK oscillates at a frequency corresponding to the specification of the PLL circuit 21a. The bit data CNT [n] output from the counter 22d is “0”. As a result, the control result CNTE output from the AND circuit 22e is “0”. Further, the reset signal CLRN output from the AND circuit 22a is “0” according to the control result CNTE of “0”. Immediately before time T4, the count value CNT of the counter 22d is counted up to 2 ⁿ -1. The reset signal CLRN “0” is input to the set terminal s of the counter 22d. Thereafter, the same operation as in the second embodiment is performed until time T4.

At time T4, the count value CNT of the counter 22d is counted up to 2 ⁿ at the rising edge of the pulse of the reference clock signal RCK. At this time, the bit data CNT [n] of the nth bit in the count value CNT of the counter 22d is “1”. As a result, the control result CNTE output from the AND circuit 22e becomes “1”. Since the lock signal LK is already “1” at time T3, the reset signal CLRN output from the AND circuit 22a at time T4 is “1”. Until the time T4, “0” was set to the asynchronous set terminal s of the counter 22d. However, the reset signal CLRN becomes “1” at the time T4, so the count value CNT of the counter 22d becomes ^2n. Immediately after, it is set to “all 1”.

  Thereafter, the reset signal CLRN is “1” and the count value CNT of the counter 22d remains set to “all 1”, so that the bit data CNT [n] of the nth bit continues to be “1”. To do. The clock signal CK starts oscillating from time T5, and thereafter operates similarly to the second embodiment.

Even when the assertion time of the lock signal LK of the PLL circuit 21a changes for each test, after the maximum lock time according to the specification of the PLL circuit 21a has passed, the count value CNT of the counter 22d becomes ²ⁿ , and the reset signal CLRN becomes “1”. Thereby, the frequency dividing operation of the frequency dividing circuit 221b starts at the same timing for each test. As a result, the clock signal CK is input to the output control circuit 23 at the same timing for each test, and the output data TXD is output from the output control circuit 23 at the same timing.

(Effect of Example 3)
According to the third embodiment, after the maximum lock time according to the specification of the PLL circuit 21a has elapsed, the bit data CNT [n] of the counter 22b becomes ²ⁿ , and the timing for releasing the reset state of the frequency divider circuit 21b is set for each test. Since the output data TXD is output from the output control circuit 23 at the same timing, the following effects (a) and (b) are obtained.

(A) There are effects similar to those of the first embodiment.
(B) The comparator 22c according to the second embodiment is not required, and the count-up enable control (not shown) for the counter 22b according to the second embodiment is not required. Therefore, the data output circuit 20B is a smaller circuit than the second embodiment. Can be realized.

(Configuration of Example 4)
FIG. 8 is a schematic configuration diagram of a data output circuit showing the fourth embodiment of the present invention. Elements common to those in FIG. 1 showing the first embodiment are denoted by common reference numerals.

  In the data output circuit 20C of the fourth embodiment, a reset control circuit 22C having a different configuration from that of the reset control circuit 22 of the first embodiment is provided. The reset control circuit 22C includes a two-input type AND circuit 22a that is the same control means as in the first embodiment, and a selection means (for example, a selector) 22f. The selector 22f is controlled by the test mode signal TMD. When the test mode signal TMD is activated and becomes “1”, for example, the selector 22f selects the reset signal CLRN output from the AND circuit 22a and applies it to the frequency divider circuit 21b. When the test mode signal TMD is deactivated and becomes, for example, “0”, the lock signal LK output from the PLL circuit 21a is selected and supplied to the frequency dividing circuit 21b. Other configurations are the same as those of the first embodiment.

(Operation of Example 4)
As the operation of the data output circuit 20C, the normal operation (1) when the test mode signal TMD is “0” and the operation (2) when the test mode signal TMD is “1” will be described below. explain.

(1) Normal Operation When the test mode signal TMD is “0”, the selector 22f selects the lock signal LK output from the PLL circuit 21a and applies it to the reset terminal rn of the frequency divider circuit 21b. In this data output circuit 20C, the operation until the lock signal LK becomes “1” and the frequency divider circuit 21 starts the 1/4 frequency division operation with respect to the internal clock signal PCK is the same as in FIG. 3 until time T2 in FIG. Thereafter, as in the first embodiment, the frequency dividing circuit 21b continues the frequency dividing operation and starts oscillation of the clock signal CK. The output control circuit 23 to which the clock signal CK is input starts outputting the output data TXD when the data output condition in the output control circuit 23 is enabled as in the first embodiment.

(2) Test operation
When the test mode signal TMD is “1”, the selector 22f selects the reset signal CLRN and applies it to the frequency divider circuit 21b. Thus, the operation is the same as in the first embodiment.

(Effect of Example 4)
According to the fourth embodiment, since the selector for selecting either the reset signal CLRN or the lock signal LK by the test mode signal TMD is provided, the following effects (a) and (b) are obtained.

(A) The data output circuit 20C can be used in the normal non-test mode without using the lock enable signal LKEB.
(B) If the test mode signal TMD is set to “1” and the reset signal CLRN is selected, the same operation and effect as in the first embodiment can be obtained.

(Modification)
The present invention is not limited to the above-described embodiments, and various usage forms and modifications are possible. For example, the following forms (a) to (g) are used as the usage form and the modified examples.

  (A) For explanation of the operation, the cycle of the reference clock signal RCK shown in the timing charts of FIGS. 3, 5 and 7, the frequency multiplication value for the internal clock signal PCK output from the PLL circuit 21a, and the frequency dividing circuit 21b The frequency dividing ratio, the oscillation start timing of the PLL circuit 21a, the assertion timing of the lock signal LK, and the time from the input of the clock signal CK to the output data TXD in the output control circuit 23 are changed to various values. it can.

  (B) Similarly to the fourth embodiment, in the second and third embodiments, the selector 22f can be additionally used. The selector 22f selects the lock signal LK when the test mode signal TMD is “0”, selects the reset signal CLRN when the test mode signal TMD is “1”, and outputs the reset signal CLRN to the frequency dividing circuit 21b. You may comprise the selection means of the other circuit which controls so that cancellation | release may become arbitrary timings.

  (C) In the second and third embodiments, it has been described that the reference clock signal RCK of the PLL circuit 21a is used as the clock signal of the counters 22b and 22d and incremented by +1. However, the counting means for counting an arbitrary time is used. Any other clock signal or the like may be used. The counters 22b and 22d may be either a count-up type or a count-down type, and the count-up value and the count-down value are not limited to +1, +2,.

  (D) In the third embodiment, the case where the count value CNT of the counter 22d is set to “all 1” when the reset signal CLRN input to the set terminal s of the counter 22d becomes “1” has been described. For example, only the nth bit may be set to “1” and the other bits may be cleared to “0”.

  (E) The circuits of the first to fourth embodiments may be changed to a circuit configuration that operates in synchronization with falling edges of pulses such as the reference clock signal RCK, the internal clock signal PCK, and the clock signal CK.

  (F) The PLL circuit 21a and the frequency dividing circuit 21b may be configured by other clock generation circuits capable of generating a predetermined clock signal such as a delay lock loop circuit and an oscillation circuit. Further, the reset control circuits 22, 22A, 22B, 22C and the output control circuit 23 may be configured by circuits other than those illustrated.

  (G) The data output circuits 20, 20A, 20B, and 20C may be configured by a semiconductor integrated circuit other than the LSI.

1 is a schematic configuration diagram of a data output circuit showing a first embodiment of the present invention. FIG. 2 is a schematic configuration diagram illustrating an example of an output control circuit in FIG. 1. 2 is a timing chart showing an operation of the data output circuit of FIG. 1. It is a schematic block diagram of the data output circuit which shows Example 2 of this invention. 5 is a timing chart showing the operation of the data output circuit of FIG. It is a schematic block diagram of the data output circuit which shows Example 3 of this invention. 7 is a timing chart showing an operation of the data output circuit of FIG. 6. It is a schematic block diagram of the data output circuit which shows Example 4 of this invention. It is a schematic block diagram which shows the conventional data output circuit. 10 is a timing chart showing the operation of the conventional data output circuit of FIG.

Explanation of symbols

20, 20A, 20B, 20C Data output circuit 21 Clock generation circuit 21a PLL circuit 21b Frequency dividing circuit 22, 22A, 22B, 22C Reset control circuit 23 Output control circuit 22a, 22e AND circuit 22b, 22d Counter 22c Comparator 22f Selector

Claims (9)

A clock generation circuit for generating a clock signal and releasing the reset state when the frequency of the clock signal reaches a predetermined value, and outputting the clock signal;
A reset control circuit for controlling the predetermined value by a first control signal to change a timing for releasing the reset state;
An output control circuit that activates when the clock signal of the clock generation circuit whose timing to release is changed by the reset control circuit is input and outputs valid data at a predetermined timing when a data output condition is satisfied;
A data output circuit comprising: The clock generation circuit includes:
The phase of the internal clock signal oscillated internally is compared with the phase of the reference clock signal input from the outside. When the two phases match, the lock signal is activated and output, and the internal clock signal having a constant frequency is output. A lock loop circuit to
A frequency dividing circuit that is activated when the reset state is released and divides the frequency of the internal clock signal to output the clock signal;
The data output circuit according to claim 1, further comprising:   The reset control circuit is configured by control means for outputting a reset signal for controlling a signal representing the predetermined value by the first control signal and changing a timing for releasing the reset state. The data output circuit according to claim 1. The reset control circuit includes:
Counting means for counting the number of pulses of the reference clock signal and outputting the count value when the count value becomes a constant value;
Comparing means for comparing the count value output from the counting means with a set value and outputting the comparison result;
Control means for outputting a reset signal for controlling a signal representing the predetermined value according to the comparison result and changing a timing for releasing the reset state;
The data output circuit according to claim 1, comprising: The reset control circuit includes:
Counting means for counting the number of pulses of the reference clock signal and outputting predetermined bit data as a count result when a reset signal for changing the timing for releasing the reset state is input;
First control means for controlling validity / invalidity of the predetermined bit data by a second control signal and outputting a control result;
Second control means for controlling the signal representing the predetermined value according to the control result and outputting the reset signal;
The data output circuit according to claim 1, comprising:   The control means is constituted by a logic circuit that takes the logic of the first control signal and the signal representing the predetermined value and outputs the reset signal corresponding to the logic result. The data output circuit according to claim 3.   5. The control means comprises a logic circuit that takes the logic of the comparison result and the signal representing the predetermined value and outputs the reset signal corresponding to the logic result. The data output circuit described. The first control means includes a first logic circuit that takes the logic of the second control signal and the predetermined bit data and outputs the control result corresponding to the logic result,
The second control means is constituted by a second logic circuit that takes the logic of the control result and a signal representing the predetermined value and outputs the reset signal corresponding to the logic result. 6. The data output circuit according to claim 5, wherein: The data output circuit according to claim 6, 7 or 8 further comprises:
Controlled by a test mode signal, when the test mode signal is activated, the reset signal is selected and the clock signal is supplied to the output control circuit, and when the test mode signal is deactivated, the predetermined value A data output circuit comprising selection means for selecting a signal representing the signal and supplying the clock signal to the output control circuit.

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