JP2009139914A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device capable of measuring illuminance of a wide dynamic range. <P>SOLUTION: A capacitor element charged beforehand is discharged according to the illuminance in the surrounding of a display element. A data is decreased to reflect the conditions that the level of the voltage between both electrodes of the capacitor element is gradually lowered by the discharge, and a trigger signal is outputted if the data becomes equal to or lower than a threshold value. A clock signal CLK whose cycle of changing levels gradually becomes long is generated. A count value outputted at each change of the clock signal's level is sampled when the trigger signal is outputted. A dynamic range in the sampled count value becomes wide; namely, the illuminance of the wide dynamic range can be measured. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to a display device capable of measuring illuminance with a wide dynamic range.

  In a device provided with a display device, it is desired to reduce power consumption. In a liquid crystal display device provided in such a device, a method of reducing power consumption by reducing the luminance of a backlight is studied in the nighttime when the illuminance around the display portion is low. Further, in a display device using organic EL (electro-luminescence), similarly, when the illuminance is low, it is considered that the power consumption can be reduced by reducing the luminance of the light emitting pixels. Specifically, a proposal has been made to provide an optical sensor circuit around a display unit in a display device and lower the luminance of a backlight or a pixel using the output.

In the liquid crystal display devices disclosed in Patent Document 1 and Patent Document 2, an optical sensor circuit is provided separately from the display panel. However, since this hinders downsizing and thinning of the device, it is disclosed in Patent Document 3. In the liquid crystal display device, the display panel includes an optical sensor circuit, thereby enabling a reduction in size and thickness. Moreover, in the liquid crystal display device disclosed in Patent Document 3, for example, the luminance of the backlight is controlled so that the illuminance can be accurately measured.
JP-A-4-174819 Japanese Patent Laid-Open No. 9-146073 JP 2007-114315 A

  By the way, in the measurement of illuminance in the above-described display device or the like, the following operation is performed. That is, the count value is updated every time the level of the predetermined clock signal is inverted, the trigger signal is output at a timing corresponding to the illuminance, and the count value is sampled when the trigger signal is output. The sampled count value is in accordance with the illuminance.

  Here, when the cycle of level inversion of the clock signal is short, the time length until the count value updated by the clock signal changes from the maximum value to the minimum value becomes short. Therefore, depending on the sampled count value, for example, the illuminance can be expressed only in the range from about 80 [lx] to about 1000 [lx]. That is, the dynamic range at the illuminance indicated by the count value is as low as about 10 times.

  Accordingly, the usage environment of the display device is limited to indoors where the illuminance is low, or limited to outdoors where the illuminance is high, and as a result, the convenience of the display device is impaired.

  The present invention has been made in view of the above, and an object thereof is to provide a display device capable of measuring illuminance with a wide dynamic range.

  In order to solve the above problems, a display device according to a first aspect of the present invention includes a display unit having a plurality of pixels, a capacitor element, and discharging the charged capacitor element in accordance with the illuminance around the display unit. The predetermined data is reduced to reflect a situation in which the level of the voltage between both electrodes of the photoelectric sensor circuit and the capacitor element gradually decreases due to discharge, and the data falls below a predetermined threshold value. An operation circuit that outputs a trigger signal when the clock signal is generated, a clock signal generation circuit that generates a clock signal whose level inversion cycle becomes gradually longer, a counter that updates and outputs a predetermined count value for each level inversion in the clock signal, A sampling latch circuit that samples the count value output at each level inversion when the trigger signal is output. And wherein the door.

  According to a second aspect of the present invention, there is provided a display device comprising: a display unit configured by a plurality of pixels; a capacitor element; and a photoelectric conversion element that discharges the charged capacitor element in accordance with illuminance around the display unit. The predetermined data is decreased so as to reflect a situation in which the voltage level between the two poles of the optical sensor circuit and the capacitor element gradually decreases due to discharge, and a trigger signal is generated when the data falls below a predetermined threshold. An arithmetic circuit for outputting, a clock signal generating circuit for generating a clock signal that repeats level inversion, a counter that updates and outputs a predetermined count value for each level inversion in the clock signal, and a count that is output for each level inversion A sampling latch circuit that samples a value when the trigger signal is output, and the sampled count value A map table in which a corresponding output value is associated with each of a plurality of ranges that can belong is searched from the map table for a range to which the sampled count value belongs, and is associated with the searched range And a value conversion circuit that outputs an output value, and the larger the output value in the map table, the smaller the range of count values associated with the output value.

  According to the first aspect of the present invention, by providing a clock signal generation circuit that generates a clock signal whose level inversion period becomes gradually longer, the dynamic range in the sampled count value becomes wider, that is, a wider dynamic range. Illuminance can be measured.

  According to the second aspect of the present invention, in the map table, the larger the output value is, the smaller the range of the count value associated with the output value is, so that the dynamic range in the output value is widened, that is, the wide dynamic range. Can be measured.

  Hereinafter, a display device (here, a liquid crystal display device) to which the present invention is applied will be described in detail with reference to the drawings.

[First Embodiment]
FIG. 1 shows an example of a liquid crystal display device according to the first embodiment. In the liquid crystal display device 1, a liquid crystal cell is formed by a pair of light-transmitting insulating substrates, and a liquid crystal material is sealed in a gap between them to form a liquid crystal layer. Specifically, a liquid crystal layer 4 is sealed between the array substrate 2 and the counter substrate 3.

  The array substrate 2 uses, for example, a light-transmissive insulating substrate made of glass or the like as a support substrate. On the light-transmissive insulating substrate, scanning lines arranged substantially parallel to each other at equal intervals, or substantially orthogonal to these scanning lines. Signal lines arranged in layers, an interlayer insulating film (transparent insulating film) that is interposed between the scanning lines and the signal lines to electrically insulate them, and a switching element disposed near the intersection of the scanning lines and the signal lines Thin film transistors (TFTs) are formed.

  In the array substrate 2, pixel electrodes electrically connected to the switching elements through through holes formed in the interlayer insulating film are arranged in a matrix. Note that, as described above, signal lines, scanning lines, switching elements such as thin film transistors, interlayer insulating films, and the like are disposed between the light-transmissive insulating substrate of the array substrate 2 and the pixel electrodes. These illustrations are omitted. Further, an alignment film is provided on almost the entire surface of the array substrate 2 on which the pixel electrodes are provided. This is also omitted here.

  On the other hand, the counter substrate 3 also has a light-transmitting insulating substrate made of glass or the like as a support substrate, and a color filter layer 5 corresponding to each pixel is formed on the surface on the liquid crystal layer 4 side. A transparent counter electrode 6 made of a transparent conductive material such as ITO (Indium Tin Oxide) is formed on the entire surface so as to cover the surface. The color filter layer is a resin layer colored in colors by pigments or dyes, and is configured by combining filter layers of R, G, B colors, for example. Although not shown, a so-called black matrix layer is formed at the pixel boundary portion of each color filter layer for the purpose of improving the contrast.

  In the liquid crystal display device 1 having the above configuration, polarizing plates 7 and 8 are provided outside the array substrate 2 and the counter substrate 3, respectively, and an image display is performed using the backlight 9 disposed on the back side as a light source. Done.

  FIG. 2 is a schematic plan view of the liquid crystal display device 1, and a black matrix BM is formed in a frame-shaped portion surrounding the display portion A composed of pixels so that light from the backlight 9 does not leak. It has become. An external LSI 10 is mounted on the array substrate 2 by chip-on-glass (COG) outside the region where the black matrix BM is formed.

  The basic configuration of the liquid crystal display device 1 has been described above. In the liquid crystal display device 1 of the present embodiment, the opening 11 is provided in the black matrix BM in the frame-shaped portion surrounding the display portion A, and here A photosensor circuit 12 for measuring ambient light illuminance is provided on the array substrate 2. Further, under the black matrix BM, an optical sensor circuit 13 for measuring a background current is installed on the array substrate 2 in a light-shielded state.

  FIG. 3 is a circuit diagram of the optical sensor circuits 12 and 13 formed on the array substrate 2. The photosensor circuits 12 and 13 are equal to each other, and include a photodiode 55 and a capacitor element 56. The photodiode 55 of the optical sensor circuit 12 is provided as a photoelectric conversion element that converts light around the display unit A into an electrical signal.

  In each photosensor circuit 12, 13, a predetermined voltage Vprc is precharged to the capacitor element 56 at a predetermined timing. In the photosensor circuit 12, a photocurrent according to the illuminance around the display unit A flows through the photodiode 55. In the optical sensor circuit 13, a so-called background current flows through the photodiode 55.

  FIG. 4 is a block diagram showing a part of the external LSI 10 together with the photosensor circuits 12 and 13 and the photosensor circuit 14 further provided. The optical sensor circuit 14 is for measuring backlight illuminance, for example, and receives only light from the backlight 9.

  The external LSI 10 includes a precharge circuit 111, an arithmetic circuit 112, a clock signal generation circuit 113, a counter 114, a sampling latch circuit 115, and a parallel / serial conversion circuit 116.

  First, the precharge circuit 111 applies a constant voltage Vprc to each of the photosensor circuits 12, 13, and 14. The precharge circuit 111 supplies the start signal SRT (for example, one pulse signal) to each of the photosensor circuits 12, 13, 14, the clock signal generation circuit 113, at a predetermined timing while the voltage Vprc is applied. This is applied to the counter 114 and the parallel-serial conversion circuit 116.

  Each photosensor circuit 12, 13, 14 precharges (precharges) capacitor element 56 with voltage Vprc. Specifically, for example, the wiring to which the voltage Vprc is applied and the positive electrode of the capacitor element 56 are connected by turning on an analog switch (not shown) formed of a thin film transistor or the like. As a result, the voltage between both electrodes of the capacitor element 56 becomes the voltage Vprc.

  When each of the photosensor circuits 12, 13, and 14 is supplied with the start signal SRT, for example, the analog switch is turned off to disconnect the capacitor element 56 from the wiring to which the voltage Vprc is applied. Since a photocurrent and a background current having a magnitude corresponding to the illuminance around the display unit A and the illuminance of light from the backlight 9 flow through the photodiode 55, the capacitor element 56 is discharged, and the voltage between the two electrodes Will go down. Each photosensor circuit 12, 13, 14 outputs the positive voltage of each capacitor element 56 as an electrical signal Photo 1, Photo 2, Photo 3.

  The arithmetic circuit 112 generates predetermined data and reduces the data to reflect a situation in which the level of the electric signal Photo1 output from the photosensor circuit 12 for measuring ambient light illuminance gradually decreases due to the discharge of the capacitor element 56. . At this time, the arithmetic circuit 112 obtains data based on the level of the electrical signal Photo2 output from the photosensor circuit 13 for measuring the background current and the level of the electrical signal Photo3 output from the photosensor circuit 14 for measuring the backlight illuminance. to correct. Note that the arithmetic circuit 112 reduces data so as to reflect a situation in which the level of the electric signal Photo1 gradually decreases even after correction.

  The arithmetic circuit 112 stores a threshold value in advance, and gives a trigger signal TRG (for example, one pulse signal) to the sampling latch circuit 115 when the corrected data becomes equal to or less than the threshold value.

  The clock signal generation circuit 113 supplies the clock signal CLK to the counter 114 and the parallel / serial conversion circuit 116.

  As shown in FIG. 5, the clock signal generation circuit 113 generates a clock signal CLK in which the level inversion period starting from, for example, the time t1 after the time t0 when the start signal SRT is given is gradually increased. CLK is supplied to the counter 114 and the parallel-serial conversion circuit 116.

  Returning to FIG. 4, the counter 114 here decrements the count value CNT, and resets the count value CNT when the start signal SRT is given. Here, the count value CNT is a 4-bit value. The count value CNT is reset to 16 which is the maximum value in the range of 1 to 16 which can be indicated by 4 bits, and is decremented by 1 until it reaches 1 which is the minimum value of the range.

  The counter 114 decrements the count value CNT every time the level of the clock signal CLK is inverted. The counter 114 supplies the sampling latch circuit 115 with a parallel signal every time the count value CNT is reset or decremented.

  The sampling latch circuit 115 samples the count value CNT supplied from the counter 114 when the trigger signal TRG is output, and supplies the sampled count value CNT to the parallel / serial conversion circuit 116 as a parallel signal. The parallel-serial conversion circuit 116 converts the given parallel signal into a serial signal and outputs it.

  As shown in FIG. 6, since the count value CNT sampled and output as a serial signal is a 4-bit value, the count value CNT is any value in the range of 1 to 16.

  Further, the count value CNT is in accordance with the illuminance.

  For example, as the illuminance is lower, the level of the electric signal Photo1 in FIG. Therefore, the lower the illuminance, the later the timing of supplying the trigger signal TRG. Therefore, the lower the illuminance, the smaller the count value CNT that is sampled and output as a serial signal.

  In the first embodiment, the count value CNT is 1 when the illuminance is, for example, about 90 [lx], which is relatively low. In this case, the count value CNT when the illuminance is, for example, about 90000 [lx] is 16. That is, the count value CNT can express a dynamic range of about 1000 times in illuminance.

  As shown in FIG. 5, as a comparative example, the clock signal generation circuit 113 generates a clock signal CLK ′ having a constant level inversion period, and supplies the clock signal CLK ′ to the counter 114 and the parallel-serial conversion circuit 116. think of.

  While the level inversion cycle in the clock signal CLK of the first embodiment becomes gradually longer, the level inversion cycle in the clock signal CLK ′ in the comparative example is constant, so that the count value CNT in the counter 114 in the comparative example is The time length from 16 to 1 may be shorter than the time length from 16 to 1 in the count value CNT in the first embodiment.

  Therefore, in the first embodiment, as described above, the count value CNT can express a dynamic range of about 1000 times in illuminance, whereas in the comparative example, for example, the dynamic range of about 10 times. There are cases where it can only be expressed.

  As shown in FIG. 6, for example, in the comparative example, the count value CNT when the illuminance is about 70 [lx] may be 1, and the count value CNT when the illuminance is about 1000 [lx] may be 16. is there.

  On the other hand, as described above, in the first embodiment, the count value CNT when the illuminance is about 90 [lx] is set to 1, and the count value CNT when the illuminance is about 90000 [lx] is set to 1. It can be set to 16.

  Further, according to the first embodiment, by using the clock signal CLK whose level inversion period becomes gradually longer, the linearity between the illuminance expressed in logarithm and the count value as shown in FIG. Can be improved.

  Therefore, according to the first embodiment, by providing the clock signal generation circuit 113 that generates the clock signal CLK whose level inversion period becomes gradually longer, the dynamic range in the sampled count value CNT becomes wider, That is, illuminance with a wide dynamic range can be measured. As a result, it is possible to measure the illuminance even in a completely dark room or in a clear outdoor environment.

  The present invention is not limited to the first embodiment, and various modifications can be made without departing from the gist of the present invention.

  For example, in the first embodiment, the arithmetic circuit 112 corrects the data, but the correction may not be performed. In this case, the photosensor circuit 13 for measuring the background current and the photosensor circuit 14 for measuring the backlight illuminance are unnecessary.

[Second Embodiment]
FIG. 7 shows an example of a liquid crystal display device according to the second embodiment. The liquid crystal display device 1A has a configuration similar to that of the liquid crystal display device 1 according to the first embodiment, and the same components are denoted by the same reference numerals, and redundant description is omitted. To do.

  As shown in FIG. 7, in the liquid crystal display device 1 </ b> A, a black matrix BM is formed in a frame-shaped portion surrounding the display unit A. An external LSI 10A is mounted outside the area where the black matrix BM is formed.

  Photosensor circuits 121, 122, and 123 are arranged in the black matrix BM region. Each of the optical sensor circuits 121, 122, and 123 has the configuration including the optical sensor circuit 12 and the arithmetic circuit 112 of the first embodiment, and outputs the respective trigger signals TRG1, TRG2, and TRG3 in the same manner as the trigger signal TRG. To do. Each trigger signal is given to the external LSI 10A. For example, one of the optical sensor circuits 121, 122, and 123 receives light from the backlight 9, and the remaining one receives light around the display unit A.

  FIG. 8 is a block diagram showing a part of the external LSI 10 </ b> A together with the optical sensor circuits 121, 122, and 123.

  The external LSI 10A includes a precharge circuit 111, a clock signal generation circuit 113A, counters 1141, 1142 and 1143, sampling latch circuits 1151, 1152 and 1153, and value conversion circuits 1171, 1172 and 1173. Each of the optical sensor circuits 121, 122, and 123 is configured to include the optical sensor circuit 12 and the arithmetic circuit 112 of the first embodiment.

  First, the precharge circuit 111 applies a constant voltage Vprc to the photosensor circuits 121, 122, and 123. The precharge circuit 111 sends the start signal SRT to the photosensor circuits 121, 122 and 123, the clock signal generation circuit 113A, and the counters 1141, 1142 and 1143 at a predetermined timing while the voltage Vprc is applied. give.

  Each photosensor circuit 121, 122, and 123 precharges capacitor element 56 with voltage Vprc. Thereby, the voltage between both electrodes of the internal capacitor element 56 becomes the voltage Vprc.

  Each photosensor circuit 121, 122, and 123 disconnects the capacitor element 56 from the wiring to which the voltage Vprc is applied when the start signal SRT is given. Since a photocurrent and a background current having a magnitude corresponding to the illuminance around the display unit A and the illuminance of light from the backlight 9 flow through the photodiode 55, the capacitor element 56 is discharged, and the voltage between the two electrodes Will go down. Each photosensor circuit 121, 122, and 123 applies the positive voltage of each capacitor element 56 to the internal arithmetic circuit 112 as an electrical signal Photo 11, Photo 12, and Photo 13.

  Each arithmetic circuit 112 generates predetermined data and reduces the data to reflect a situation in which the level of each electric signal gradually decreases due to the discharge of the capacitor element 56.

  Each arithmetic circuit 112 supplies each trigger signal TRG1, TRG2, and TRG3 (for example, one pulse signal) to each sampling latch circuit 1151, 1152, and 1153 when the data becomes less than the threshold value.

  The clock signal generation circuit 113A applies the clock signal CLK 'shown in FIG. 5, that is, the clock signal CLK' that repeats level inversion at a constant cycle, to the counters 1141, 1142, and 1143.

  Returning to FIG. 8, the counters 1141, 1142 and 1143 increase (increment) the count values CNT1, CNT2 and CNT3 here, and reset the count values when the start signal SRT is given. Here, the count value is a 16-bit value. The count value is reset to 0, which is the minimum value in the range from 0 to 65535, which can be indicated by 16 bits, and is incremented by 1 until it reaches 65535, which is the maximum value in the range.

  Each counter increments each count value every time the level of the clock signal CLK ′ is inverted. Each counter gives each sampling latch circuit 1151, 1152, and 1153 every time the count value is reset or incremented.

  Each sampling latch circuit samples the count value given from each counter when each trigger signal is output, and gives the sampled count values CNT1, CNT2, and CNT3 to each value conversion circuit 1171, 1172, and 1173 as a parallel signal.

  Each value conversion circuit converts the count values CNT1, CNT2, and CNT3 into output values OUT1, OUT2, and OUT3, and outputs them.

  As shown in FIG. 9, each value conversion circuit has a map table in which a corresponding output value is associated with each of a plurality of ranges to which a count value can belong.

  When the sampled count value is actually given, each value conversion circuit searches the range to which the count value belongs from the map table of FIG. 9, and outputs the output value associated with the searched range as the output value OUT1. , OUT2 and OUT3 are output as parallel signals.

  The map table is configured to output a larger output value as the sampled count value is smaller. In the map table, the larger the output value, the smaller the range of count values associated with the output value.

  Similar to the count value of the first embodiment shown in FIG. 6, since the output value to be output is a 4-bit value, the output value is any value in the range of 1 to 16. .

  The output value depends on the illuminance.

  For example, as the illuminance is lower, the level of the electrical signals Photo11, Photo12 and Photo13 in FIG. Therefore, the lower the illuminance, the later the timing of supplying each trigger signal. Since the count value is incremented, the sampled count value increases as the illuminance decreases.

  Further, since the map table is configured to output a larger output value as the count value is smaller, the output value is smaller as the illuminance is lower. That is, the output value depends on the illuminance.

  In the second embodiment, similarly to the count value of the first embodiment shown in FIG. 6, the output value can express a dynamic range of about 1000 times in illuminance.

  Here, as a comparative example, a case is considered where the size of each count value range is equal in the map table.

  For example, in order to make the linearity between the illuminance expressed in logarithm and the output value good in the range of the output values “10” to “16”, the output values “10” to “16” are set to the respective output values. For example, the size of the associated range is set to “100”, and the size of the range associated with each other output value is also set to “100”.

  Thus, in the second embodiment, the maximum value of the count value is “65535”, whereas in the comparative example, the maximum value of the count value is “1600” (= 100 × 16). In the example, the illuminance (low illuminance) in a situation where the count value is larger than “1600” may not be expressed.

  Therefore, in the comparative example, for example, only about 10 times the dynamic range may be expressed, whereas in the second embodiment, the output value in illuminance is, for example, as in the first embodiment. A dynamic range of about 1000 times can be expressed.

  Further, according to the second embodiment, in the map table, the range of the count value associated with the output value is reduced as the output value is increased, thereby widening the linearity between the illuminance and the count value. Can be improved over time.

  Therefore, according to the second embodiment, in the map table, the larger the output value, the smaller the range of the count value associated with the output value, so that the dynamic range in the output value becomes wider, that is, It can measure illuminance with a wide dynamic range. As a result, it is possible to measure the illuminance even in a completely dark room or in a clear outdoor environment. The present invention is not limited to the first and second embodiments, and various modifications can be made without departing from the gist of the present invention.

  For example, in the second embodiment, the clock signal CLK ′ having a constant level inversion period is used. However, as in the first embodiment, the clock signal CLK having a gradually increasing level inversion period is used. May be.

  In the second embodiment, the map table is set for each value conversion circuit, so that variations between output values caused by variations in the characteristics of the photoelectric conversion elements in each photosensor circuit are within an allowable range. You may make it fit in.

  Further, when the liquid crystal display device of the second embodiment is mass-produced, for example, the map table is set for each liquid crystal display device so that the performance difference regarding the illuminance expression between the liquid crystal display devices falls within an allowable range. May be.

  In the first and second embodiments, the display device is a liquid crystal display device. However, the display device may be an organic EL device, and in this case, the illuminance measurement is the same as the present embodiment. A similar configuration may be adopted.

  In the first and second embodiments, the photodiode 55 is used as the photoelectric conversion element that discharges the capacitor element charged in the optical sensor circuit in accordance with the illuminance around the display unit. May be a phototransistor or the like.

It is a schematic sectional drawing which shows typically an example of the liquid crystal display device which concerns on the 1st Embodiment of this invention. FIG. 2 is a schematic plan view of the liquid crystal display device shown in FIG. 1. FIG. 2 is a circuit diagram of an optical sensor circuit included in the liquid crystal display device shown in FIG. 1. FIG. 2 is a block diagram showing a part of an external LSI included in the liquid crystal display device shown in FIG. 1 together with each photosensor circuit. It is a figure which shows the waveform of the clock signal used with the liquid crystal display device shown in FIG. It is a figure which shows the relationship between the illumination intensity in the liquid crystal display device shown in FIG. 1, and the sampled count value. It is a schematic plan view which shows typically an example of the liquid crystal display device which concerns on the 2nd Embodiment of this invention. FIG. 8 is a block diagram showing a part of an external LSI included in the liquid crystal display device shown in FIG. 7 together with each photosensor circuit. It is a figure which shows the map table used with the liquid crystal display device shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,1A ... Liquid crystal display device 2 ... Array substrate 3 ... Opposite substrate 4 ... Liquid crystal layer 5 ... Color filter layer 6 ... Transparent counter electrode 7, 8 ... Polarizing plate 9 ... Backlight 10, 10A ... External LSI
12, 13, 14, 121, 122, 123 ... optical sensor circuit 55 ... photodiode 56 ... capacitor element 111 ... precharge circuit 112 ... arithmetic circuit 113, 113A ... clock signal generation circuit 114, 1141, 1142, 1143 ... counter 115 1151, 1152, 1153... Sampling latch circuit 116... Parallel serial conversion circuit 1171, 1172, 1173... Value conversion circuit A... Display unit BM. Photo1, Photo2, Photo3, Photo11, Photo12, Photo13 ... Electric signal SRT ... Start signal TRG, TRG1, TRG2, TRG3 ... Trigger signal

Claims (3)

A display unit composed of a plurality of pixels;
An optical sensor circuit including a capacitor element, a photoelectric conversion element that discharges the charged capacitor element in accordance with illuminance around the display unit;
An arithmetic circuit that reduces predetermined data to reflect a situation in which a voltage level between both electrodes of the capacitor element gradually decreases due to discharge, and outputs a trigger signal when the data falls below a predetermined threshold;
A clock signal generation circuit for generating a clock signal in which the period of level inversion gradually increases;
A counter that updates and outputs a predetermined count value for each level inversion in the clock signal;
And a sampling latch circuit that samples a count value output at each level inversion when the trigger signal is output. A display unit composed of a plurality of pixels;
An optical sensor circuit including a capacitor element, a photoelectric conversion element that discharges the charged capacitor element in accordance with illuminance around the display unit;
An arithmetic circuit that reduces predetermined data to reflect a situation in which a voltage level between both electrodes of the capacitor element gradually decreases due to discharge, and outputs a trigger signal when the data falls below a predetermined threshold;
A clock signal generation circuit for generating a clock signal that repeats level inversion;
A counter that updates and outputs a predetermined count value for each level inversion in the clock signal;
A sampling latch circuit that samples the count value output at each level inversion when the trigger signal is output;
A map table in which a corresponding output value is associated with each of a plurality of ranges to which the sampled count value can belong, and a range to which the sampled count value belongs is searched from the map table. A value conversion circuit that outputs an output value associated with the range,
The display device according to claim 1, wherein the larger the output value in the map table, the smaller the range of count values associated with the output value.   The display device according to claim 1, wherein the optical sensor circuit is provided in a frame-shaped part surrounding the display unit.

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