JP2009136122A - High-speed pulse power supply device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-speed pulse power supply device which quickly starts power supply during the start-up of the power supply and has small current ripples after current rising. <P>SOLUTION: One ends of primary coils of a plurality of transformers 8a, 8b, and 8c, each having a sufficient volt-time product that allows passing of pulse power, are respectively individually connected to one pole of a DC power supply via first semiconductor switches 4a, 4b, and 4c. The other ends of the primary coils of the transformers 8a, 8b, and 8c are collectively connected to the other pole of the DC power supply via a second conductor switch 7. Each first diode 6a, 6b, and 6c is connected between each connection point, which connects between the primary coil of each transformer 8a, 8b, and 8c and each first semiconductor switch 4a, 4b, and 4c, and the other pole of the DC power supply as a polarity in which a current in steady time does not flow. Secondary coils of the transformers 8a, 8b, and 8c are connected in series so as to supply a current, induced in the secondary coils by a current flowing in the primary coils, to a load via a third diode 9. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a high-speed pulse power supply device used for electroplating or the like.

  It is known that when a certain type of electroplating, electropolishing, or the like is performed, the finish is improved by applying a pulse current. The inventor of the present application has applied for a patent considering a high-speed pulse power supply device suitable for such applications, and is disclosed as Patent Document 1. The present invention includes a transformer having a voltage time product sufficient to pass pulsed power, a semiconductor switch connected between each terminal on the primary side of the transformer and both poles of a DC power source, a transformer primary side, Between the connection point of the semiconductor switch and the other pole of the DC power supply, a diode connected to a polarity that does not flow a steady-state current, and a DC power connected to the secondary side of the transformer and connected to the load when the semiconductor switch is conductive It is comprised from the diode which supplies.

  According to the present invention, since the switching of the load current is performed on the primary side of the transformer having a high voltage, there is an advantage that the semiconductor switch for performing the switching may have a small current capacity. In addition, since the current can be kept constant by the opening and closing operation of the semiconductor switch after the current rise, the DC power supply voltage can be increased, so that a pulse current with a good waveform with a fast current rise can be obtained. Since the voltage generated in the transformer can be used at the time of falling, there is an advantage that the falling can be accelerated without using a damping resistor.

However, a pulse current with a shorter energization time may be required for more advanced processing such as plating, in which case a shorter rise time corresponding to that is required, and a higher output at the time of energization rise. A voltage is required. On the other hand, in the power supply device shown in Patent Document 1, since the current is kept constant by the opening / closing operation of the semiconductor switch after the current rise, the DC power supply voltage is increased to speed up the current rise. Then, it is necessary to shorten the on-time of the semiconductor switch after the current rises. For this reason, there is a problem that even a high-speed semiconductor switch is difficult to respond, and even if the semiconductor switch can respond, the ripple of the output current increases.
JP 2002-30497 A

  The present invention solves the above-mentioned problems, and at the start of energization, a high-speed pulse power supply device that can make the start-up fast by a high output voltage and can suppress the output current ripple small by a low output voltage after the current rise It was made to provide.

  In order to solve the above problem, the high-speed pulse power supply device according to the invention of claim 1 is configured such that one end of each primary coil of a plurality of transformers having a voltage-time product sufficient to pass pulse power is individually first. The other end of the primary coil of the transformer is connected to the other pole of the DC power source through the second semiconductor switch, and the primary coil of each transformer The first diode is connected between the connection point of each first semiconductor switch and the other pole of the DC power supply as a polarity that does not allow current to flow during steady state, and the connection point between the primary coil of the transformer and the second semiconductor switch The second diode is connected between each of the DC power supply and one pole of the DC power supply so that the current does not flow in a steady state, and the secondary coil of each transformer is connected in series, and the secondary coil is applied by the voltage applied to the primary coil. Induced by It is characterized in applying a voltage to a load via the third diode.

  Here, the second semiconductor switch is continuously turned on during the energization period of the pulse, and at the start of energization, the plurality of first semiconductor switches are simultaneously turned on, and the current becomes constant after the load current rises. It is preferable to provide a control means for generating a drive signal for turning on and off the first semiconductor switch, and the control means generates a drive signal to be given to the first semiconductor switch by pulse width control. Is preferably sequentially supplied to each first semiconductor switch for each cycle of a carrier serving as a reference for pulse width control.

  According to another aspect of the present invention, there is provided a high-speed pulse power supply apparatus according to the invention of claim 4, wherein one end of each primary coil of a plurality of transformers having a sufficient voltage-time product to pass pulse power is individually provided. Connected to one pole of the DC power supply via the first semiconductor switch, the other end of the primary coil of the transformer is connected to the other pole of the DC power supply via the second semiconductor switch, and the primary of each transformer The first diode is connected between the connection point of the coil and each of the first semiconductor switches and the other pole of the DC power source as a polarity that does not allow current to flow during normal operation, and the primary coil of the transformer and the second semiconductor switch Connect the second diode between the connection point and one pole of the DC power supply so that the current does not flow during steady state, and connect the secondary coil of each transformer and the output of the separately provided switching power supply in series. And each transformer It is characterized in that the voltage applied to the primary coil of the applied load added together and output voltage of the voltage switching power induced in the secondary coil. Here, it is assumed that the output of the switching power supply is controlled by pulse width control, and the carrier serving as a reference for the pulse width control is set to the same cycle whose phase is different from that of the carrier serving as the reference for the pulse width control of the first semiconductor switch. It is preferable.

  According to the first aspect of the present invention, since the plurality of first semiconductor switches are simultaneously turned on at the start of energization of the pulse, a high total voltage of the secondary voltages of the plurality of transformers is applied to the load, and the current rises quickly. become. In addition, after the current rises, the first semiconductor switch is turned on and off so that the current becomes constant, but the period during which the first semiconductor switch is turned on at the same time is shortened and further turned on at the same time. Becomes one. As a result, the output voltage is lowered, so that the ON time of the first semiconductor switch is not extremely shortened, and the drive signal is supplied to each first semiconductor switch for each cycle of the carrier that is a reference for pulse width control. If given sequentially, the switching frequency of each first semiconductor switch is lowered, so that the switching loss of the first semiconductor switch can be kept low and the ripple of the output current can be reduced.

  According to the invention of claim 4, since the output of the switching power supply is connected in series, when the pulse energization is started, a high sum of the secondary voltage of the plurality of transformers and the output voltage of the switching power supply is applied to the load. The current rises quickly. In addition, after the current rises, the first semiconductor switch and the switching power supply are controlled so that the current becomes constant. In the case of a pulse with a long energization time, the current is supplied from the switching power supply to the load. Is advantageous in that the voltage-time product can be made small. Furthermore, when the output of the switching power supply is controlled by pulse width control, and the carrier used as the reference for the pulse width control has the same period that is different in phase from the carrier used as the reference for the pulse width control of the first semiconductor switch Has the advantage that the ripple of the output voltage and output current is reduced when the first semiconductor switch and the switching power supply operate simultaneously.

Next, the best mode for carrying out the present invention will be specifically described with reference to the drawings.
FIG. 1 is a connection diagram of a main circuit showing an embodiment of the invention of claim 1, wherein a DC power source for converting AC power supplied from an AC input terminal 3 by a rectifier 1 and a capacitor 2 into DC power is provided. is there. The positive poles of the DC power supply are connected to the positive poles of a plurality of semiconductor switches 4a, 4b, 4c, which are first semiconductor switches, and the cathode of a diode 5, which is a second diode, and the semiconductor switches 4a, 4b. The cathodes of diodes 6a, 6b, and 6c, which are first diodes each having an anode connected to the minus pole of the DC power source, are connected to the negative poles of 4c. The anode of the diode 5 is connected to the plus pole of the semiconductor switch 7 which is the second semiconductor switch having the minus pole connected to the minus pole of the DC power supply.

  Primary coils of transformers 8a, 8b, 8c are respectively connected between the negative poles of the semiconductor switches 4a, 4b, 4c and the positive pole of the semiconductor switch 7, and the secondary coils of the transformers 8a, 8b, 8c are respectively connected. Are connected in series and connected to the output terminal 10 via a diode 9 which is a third diode. In the diode 9, when any one of the semiconductor switches 4a, 4b, and 4c and the semiconductor switch 7 are turned on and a voltage is applied to the primary coil of the transformers 8a, 8b, and 8c, a current due to the voltage induced in the secondary coil is generated. Keep the current flowing. It is desirable to use high-speed elements for these semiconductor switches 4a, 4b, 4c and 7, diodes 5 and 6a, 6b and 6c and diode 9. Further, the transformers 8a, 8b, and 8c are assumed to have a voltage-time product sufficient to pass pulse power. The transformers 8a, 8b, and 8c can increase the voltage time product by cutting the iron core and inserting a gap in the cut surface.

  FIG. 2 is a block diagram showing an example of a control device for controlling the high-speed pulse power supply device having the configuration shown in FIG. 1, and an error amplifier for comparing a detection signal of an output current measured by a current sensor with a set reference signal. 11, a clock generation circuit 12 that generates a reference clock signal, a carrier signal generation circuit 13 that generates a triangular carrier signal based on the clock generated by the clock generation circuit 12, and an output of the error amplifier 11. An adder 14 that adds a reference voltage to the error signal, a carrier signal generated by the carrier signal generation circuit 13 and a comparison signal that is an output of the adder 14 are compared, and output while the comparison signal exceeds the value of the carrier signal. And a switch 16, 17, 18 for selecting a reference voltage.

  The clock signal generated by the clock generation circuit 12 is added to the pulse width detection circuit 19 and the drive signal generation circuit 20 in addition to the carrier signal generation circuit 13, and the output of the first comparator 15 is the pulse width detection circuit 19 and the drive. In addition to the signal generation circuit 20. The pulse width detection circuit 19 measures the pulse width generated by the first comparator 15 by measuring the time from the rising edge of the clock signal to the rising edge of the output of the first comparator 15, and the pulse width is the upper limit or When the lower limit is reached, a detection signal is generated, and the detection signal is added to the mode switching circuit 21.

  The mode switching circuit 21 switches the mode according to the detection signal generated by the pulse width detection circuit 19, and the switches 16, 17, 18 are opened / closed and the drive signal generation circuit 20 is set in accordance with the output of the mode switching circuit 21. The drive signal generation circuit 20 determines the drive signals A, B, and C of the semiconductor switches 4a, 4b, and 4c based on conditions set by the output of the mode switching circuit 21, the output of the first comparator 15, and the clock. Generate. Reference numeral 22 denotes a second comparator which compares the error signal with a reference voltage and outputs a detection signal when the error signal is equal to or lower than the reference voltage. The detection signal of the second comparator 22 is a mode switching circuit. In addition to 21. D is a drive signal of the semiconductor switch 7 output from the drive signal generation circuit 20.

  3 to 5 show waveforms of respective parts of the control device having the above-described configuration, P is a clock signal, Q is a carrier signal and a comparison signal, R is an output signal of the first comparator 15, A, B, C is a drive signal for driving the semiconductor switches 4a, 4b, 4c. In Q, the triangular wave indicates the carrier signal, and the horizontal straight line indicates the error signal. In both cases, the right half of the error signal is larger than the left half. FIG. 3 shows a case where the error signal is relatively small. The carrier signal has an amplitude of 3V, the error signal has a maximum amplitude of 9V, and the reference voltages selected by the switches 16, 17, and 18 are 0V, -3V, and-, respectively. 6V corresponds to a case where the error signal is 3V or less.

  In this state, the switches 17 and 18 are opened and the switch 16 is closed so that the reference voltage of 0 V is selected. The error signal is directly added to the first comparator 15 as the comparison signal, and the comparison signal indicates the value of the carrier signal. As long as the output exceeds R, the output is generated. The output of the first comparator 15 is applied to the drive signal generation circuit 20, and the drive signal generation circuit 20 sequentially converts the output of the first comparator 15 into the drive signal A for each cycle of the clock signal as shown in FIG. , B and C. Therefore, each of the drive signals A, B, and C has the same width as the output of the first comparator 15. When the error signal increases and the comparison signal increases, the pulse width of the output of the first comparator 15 increases, and when the comparison signal reaches 3V, the pulse width reaches the upper limit. The pulse width detection circuit 19 detects this and sends a detection signal to the mode switching circuit 21. The mode switching circuit 21 opens the switches 16 and 18 and closes the switch 17 and stores the state.

  When the switch 17 is closed, a reference voltage of −3 V is selected, and the adder 14 adds the reference voltage to the error signal and applies it to the first comparator 15 as a comparison signal. FIG. 4 shows this state. The comparison signal is a value obtained by subtracting 3V from the error signal. When the error signal is 3V to 6V, the comparison signal is 0V to 3V. The drive signal generation circuit 20 is conditionally set by a signal from the mode switching circuit 21, and sequentially raises the drive signals A, B, and C at the rise of the output of the first comparator 15, and each of the first one after one clock. The drive signals A, B and C are sequentially lowered at the fall of the output of the comparator 15, and this is repeated. As a result, the drive signals A, B, and C each have a width obtained by adding one clock cycle to the output of the first comparator 15.

  When the error signal is further increased, the pulse width of the output of the first comparator 15 is increased. When the error signal is 6V and the comparison signal is 3V, the pulse width reaches the upper limit. The pulse width detection circuit 19 detects this and sends a detection signal to the mode switching circuit 21. The mode switching circuit 21 opens the switches 16 and 17 and closes the switch 18 according to the signal and the stored current state, and stores the state. When the switch 18 is closed, a reference voltage of -6V is selected, the comparison signal is a value obtained by subtracting 6V from the error signal, and when the error signal is 6V to 9V, the comparison signal is 0V to 3V.

  FIG. 5 shows this state. The drive signal generation circuit 20 is conditionally set by a signal from the mode switching circuit 21 and sequentially raises the drive signals A, B, and C at the rise of the output of the first comparator 15. The drive signals A, B, and C are sequentially lowered at the fall of the output of the first comparator 15 after two clocks, and this is repeated. As a result, the drive signals A, B, and C each have a width obtained by adding two clock cycles to the output of the first comparator 15. When the error signal is further increased, the pulse width of the output of the first comparator 15 is increased. When the error signal is 9V and the comparison signal is 3V, the pulse width reaches the upper limit. The pulse width detection circuit 19 detects that the pulse width has reached the upper limit and sends a detection signal to the mode switching circuit 21. The mode switching circuit 21 changes the state of the switches 16, 17, 18 and the drive signal generation circuit 20. I will not let you.

  Next, when the error signal becomes small, the pulse width of the output of the first comparator 15 decreases, and when the error signal becomes 6V and the comparison signal becomes 0V, the pulse width reaches the lower limit. The pulse width detection circuit 19 detects this and sends a detection signal to the mode switching circuit 21. The mode switching circuit 21 opens the switches 16 and 18 and closes the switch 17 according to the signal and the stored current state, and stores the state. When the switch 17 is closed, the reference voltage of −3V is selected as described above, and the state shown in FIG. 4 is restored. The drive signal generation circuit 20 also returns to the conditions shown in FIG. 4, and the drive signals A, B, and C each have a width obtained by adding one clock cycle to the output of the first comparator 15.

  When the error signal further decreases, the pulse width of the output of the first comparator 15 decreases, and when the error signal becomes 3V and the comparison signal becomes 0V, the pulse width reaches the lower limit. The pulse width detection circuit 19 detects this and sends a detection signal to the mode switching circuit 21. The mode switching circuit 21 opens the switches 17 and 18 and closes the switch 16 according to the signal and the stored current state, and stores the state. When the switch 16 is closed, the reference voltage of 0V is selected as described above, and the state shown in FIG. 3 is restored. The drive signal generation circuit 20 also returns to the conditions shown in FIG. 3, and the output of the first comparator 15 is sequentially distributed to the drive signals A, B, and C for each cycle of the clock signal. The drive signals A, B, and C are respectively The width is the same as the output of the first comparator 15.

  As described above, in the control device configured as described above, the widths of the drive signals A, B, and C change according to the change in the magnitude of the error signal, and the same width as the output of the first comparator 15 or the second The width is obtained by adding one cycle or two cycles of the clock to the output of one comparator 15. Thus, when the drive signals A, B, and C shown in FIG. 4 have a width obtained by adding one cycle of the clock to the output of the first comparator 15, two of the drive signals A, B, and C are simultaneously driven. When the drive signal A, B, or C shown in FIG. 5 has a width obtained by adding two clock cycles to the output of the first comparator 15, three of the drive signals A, B, and C are present. At the same time, a period in which the drive signal exists is generated.

  Here, when the drive signal changes from the same width as the output of the first comparator 15 to a width obtained by adding two cycles of the clock to the output of the first comparator 15 or vice versa. It always changes through a state in which the output of the first comparator 15 is added with one clock period. Since the second comparator 22 sends a detection signal to the mode switching circuit 21 when the error signal is below the reference voltage, if the reference voltage is set to 3V, the mode switching circuit 21 will drive the drive signal when the error signal becomes 3V or below. The conditions of the drive signal generation circuit 20 are set so that A, B, and C have the same width as the output of the first comparator 15. As a result, when the error signal of 6V or more suddenly becomes 3V or less, the drive signals A, B, and C immediately have the same width as the output of the first comparator 15.

  The operation of the high-speed pulse power supply device configured as described above will be described below. FIG. 6 shows the waveform of the main part when one pulse is output. A, B, and C are drive signals for the semiconductor switches 4a, 4b, and 4c, respectively, and D is a drive signal for the semiconductor switch 7. , G is an output voltage, and H is an output current. AC power supplied from the AC input terminal 3 is converted into DC power by the rectifier 1 and stored in the capacitor 2. When the pulse energization starts, the semiconductor switches 4a, 4b, and 4c are first supplied with a drive signal having the same width as the output of the first comparator 15, but when the pulse energization starts, the output current is zero and the error signal is maximum. Therefore, the drive signal has a width obtained by rapidly adding one cycle of the clock to the output of the first comparator 15, and further having a width obtained by adding two cycles of the clock to the output of the first comparator 15. Become. The semiconductor switch 7 is continuously supplied with a drive signal during the energization period of the pulse.

  Each of the semiconductor switches 4a, 4b, 4c and the semiconductor switch 7 is turned on when a drive signal is given, and a DC voltage is applied to the primary coils of the transformers 8a, 8b, 8c. As a result, a voltage is induced on the secondary side of the transformers 8 a, 8 b, 8 c, and a current flows to the load through the diode 9. Current flows through the primary switches of the transformers 8a, 8b, and 8c through the semiconductor switches 4a, 4b, and 4c and the semiconductor switch 7 while the semiconductor switches 4a, 4b, and 4c are turned on. Is turned off, current flows through the semiconductor switch 7 and the diodes 6a, 6b, 6c.

  In a state where the drive signal has a width obtained by adding two cycles of the clock to the output of the first comparator 15, there is a period in which the drive signal is simultaneously applied to all of the semiconductor switches 4a, 4b, and 4c. In the meantime, a DC voltage is simultaneously applied to all the primary coils of the transformers 8a, 8b, 8c, and the sum of the voltages of all the secondary coils of the transformers 8a, 8b, 8c is applied to the load. As a result, a high voltage is applied to the load, and the current rises quickly. When the current flowing through the load rises and approaches the set current, and the error signal decreases, the drive signal has a width obtained by adding one cycle of the clock to the output of the first comparator 15.

  When the drive signal has a width obtained by adding one cycle of the clock to the output of the first comparator 15, there is a period in which the drive signal is simultaneously applied to two of the three semiconductor switches 4a, 4b, and 4c. In the meantime, a DC voltage is simultaneously applied to two of the three primary coils of the transformers 8a, 8b and 8c, and the sum of the voltages of the two secondary coils of the transformers 8a, 8b and 8c is applied to the load. Become. When the error signal is further reduced, the drive signal has the same width as the output of the first comparator 15. When the drive signal has the same width as the output of the first comparator 15, the drive signal is given to only one of the three semiconductor switches 4a, 4b and 4c, and the load of the transformers 8a, 8b and 8c is applied to the load. The voltage of one secondary coil is applied.

  In this way, when the error signal is large, a total of three secondary voltages of the transformers 8a, 8b, and 8c is added to the load when it is slightly large, two when it is slightly large, and one when it is small. Thus, after the current rises quickly, the voltage is lowered and the current is controlled to be constant. When the current suddenly rises and the error voltage decreases and changes rapidly from 6 V to 3 V, it is detected by the second comparator 22, and the drive signals A, B, and C are detected by the first comparator 15. Since the voltage applied to the load is equal to the voltage of one of the transformers 8a, 8b, and 8c, the current does not overshoot.

  In the control device having the above-described configuration, the drive signals given to the semiconductor switches 4a, 4b, and 4c are shifted up every clock cycle, so that the semiconductor switches 4a, 4b, and 4c are driven every clock cycle. It will be turned on sequentially. As a result, the switching frequency of each of the semiconductor switches 4a, 4b, and 4c becomes one third of the carrier frequency, and there is an advantage that the switching loss is reduced. Further, since any one of the semiconductor switches 4a, 4b, and 4c is turned on every clock cycle, there is an advantage that the ripple of the output voltage and the output current is reduced.

  During the energization period of the pulse, a voltage in one direction is applied to the primary coils of the transformers 8a, 8b, and 8c, and the iron core is saturated. The transformers 8a, 8b, and 8c pass the pulse power during this period. Therefore, saturation is not reached. Magnetic energy is stored in the transformers 8a, 8b, and 8c by the excitation current during this period. When the energization period of the pulse ends, the semiconductor switches 4a, 4b, 4c and the semiconductor switch 7 are all turned off. The current flowing through the primary coils of the transformers 8a, 8b, 8c flows into the capacitor 2 through the diodes 6a, 6b, 6c and the diode 5, and the magnetic energy stored in the transformers 8a, 8b, 8c is recovered, so that the iron core is recovered. Thus, the next pulse power can be passed. At this time, a voltage having a reverse polarity is generated in the primary coil of the transformers 8a, 8b, and 8c, and the reverse polarity voltage is generated in the secondary coils of the transformers 8a, 8b, and 8c. This reverse voltage is applied to the load and rapidly attenuates the load current.

  FIG. 7 is a connection diagram of a main circuit showing an embodiment of the invention of claim 4, wherein a DC power source for converting AC power supplied from an AC input terminal 33 by a rectifier 31 and a capacitor 32 into DC power is provided. is there. The positive pole of the DC power source is connected to the positive poles of the semiconductor switches 34a and 34b as the first semiconductor switch and the cathode of the diode 35 as the second diode, and is connected to the negative pole of the semiconductor switches 34a and 34b. Are connected to the cathodes of diodes 36a and 36b, which are first diodes each having an anode connected to the negative pole of the DC power supply. Further, the anode of the diode 35 is connected to the plus pole of the semiconductor switch 37 which is the second semiconductor switch having the minus pole connected to the minus pole of the DC power supply. The minus pole of the semiconductor switches 34a and 34b and the semiconductor switch 37 are connected. The primary coils of transformers 38a and 38b are connected between the positive poles.

  Further, the positive poles of the semiconductor switches 39a, 39b are connected to the positive pole of the DC power source, and the semiconductor switches 40a, 39a, 39b are connected to the negative pole of the DC power source, respectively. 40b is connected. The primary coil of the transformer 41 is connected between the connection point of the semiconductor switches 39a and 40a and the connection point of the semiconductor switches 39b and 40b. The secondary coil of the transformer 41 is provided with a center tap and both ends. Are connected to diodes 42a and 42b, respectively, to form a rectifier circuit. Further, the rectifier circuit and the secondary coils of the transformers 38 a and 38 b are connected in series and connected to the output terminal 43.

  When the secondary coils of the transformers 38a and 38b are connected in series, when any of the semiconductor switches 34a and 34b and the semiconductor switch 37 are turned on and a current flows through the primary coils of the transformers 38a and 38b, the primary coil The polarity induced in the secondary coil by the current flowing through the coil is set to the polarity that flows through the diodes 42a and 42b. Also in the second embodiment, the transformers 38a and 38b have voltage and time products sufficient to pass pulse power, and the semiconductor switches 34a, 34b and 37 and the semiconductor switches 39a, 39b, 40a, It is desirable to use high-speed elements for 40b, diodes 35 and 36a, 36b, and diodes 42a, 42b.

  In this configuration, the semiconductor switches 39a and 39b, the semiconductor switches 40a and 40b, the transformer 41, and the diodes 42a and 42b constitute a so-called switching power supply, and the semiconductor switch 4a having three circuits in the configuration shown in FIG. Although one of the circuits consisting of 4b and 4c and transformers 8a, 8b and 8c is replaced with a switching power supply, it goes without saying that a switching power supply may be added as it is. The diode 9 connected to the secondary coil of the transformers 8a, 8b, 8c connected in series with the configuration shown in FIG. 1 has the role of the diodes 42a, 42b connected to the secondary coil of the transformer 41. It fulfills and can be removed.

  FIG. 8 is a block diagram showing an example of the control device for the high-speed pulse power supply device shown in FIG. 7. The basic portions are the same as those shown in FIG. 2, and the same parts are denoted by the same reference numerals. is there. The difference is that a third comparator 44 is provided, and the carrier signal generation circuit 13 generates two carrier signals having a phase difference of 180 degrees, and one of the generated carrier signals is supplied to the first comparator 15 and the other is generated. Is added to the third comparator 44, and the configuration and operation of the drive signal generation circuit 20 are different. The drive signal generating circuit 20 is based on the conditions set by the output of the mode switching circuit 21, the output of the first comparator 15, the output of the third comparator 44, and the clock, and the semiconductor switches 34a, 34b. And 37, and drive signals A, B and D, and semiconductor switches 39a and 40b and 39b and 40a, and drive signals E and F are generated.

  9 to 11 show waveforms of respective parts of the control device having the above-described configuration, P is a clock signal, Q is a carrier signal and a comparison signal, R is an output signal of the first comparator 15, and S is a third signal. , A and B are driving signals for driving the semiconductor switches 34a and 34b, E is a driving signal for the semiconductor switches 39a and 40b, and F is a driving signal for the semiconductor switches 39b and 40a. In Q, the solid triangle wave indicates the carrier signal applied to the first comparator 15, the dotted triangle wave indicates the carrier signal applied to the third comparator 44, and the horizontal straight line indicates the error signal. The right half is larger than the left half.

  FIG. 9 shows a case where the error signal is relatively small. The carrier signal amplitude is 3 V, the error signal amplitude is 9 V at the maximum, and the reference voltages selected by the switches 16, 17, 18 are 0 V, −3 V, − 6V corresponds to a case where the error signal is 3V or less. In this state, the error signal is directly added to the first comparator 15 and the third comparator 44 as a comparison signal, and outputs such as R and S are generated while the comparison signal exceeds the value of the carrier signal. As shown in FIG. 9, the drive signal generation circuit 20 alternately outputs the output signal of the third comparator 44 to the drive signals E and F, and does not output them to the drive signals A and B. As a result, the drive signals of the semiconductor switches 39a, 39b, 40a, 40b have the same width as the output signal of the third comparator 44, and the drive signals of the semiconductor switches 34a, 34b become zero width.

  When the error signal increases to 3 V, the pulse width of the output of the first comparator 15 reaches the upper limit. The pulse width detection circuit 19 issues a detection signal, and the mode switching circuit 21 receiving the detection signal opens the switches 16 and 18 and closes the switch 17 to store the state. FIG. 10 shows this state, and the comparison signal has a value obtained by subtracting 3 V from the error signal. The drive signal generation circuit 20 alternately outputs a drive signal having the maximum width unrelated to the pulse width of the output of the third comparator 44 to the drive signals E and F, and alternately outputs the output signal of the first comparator 15. The drive signals A and B are distributed and output. As a result, the drive signals of the semiconductor switches 39a, 39b, 40a, and 40b have the maximum width, and the drive signals of the semiconductor switches 34a and 34b have the same width as the output signal of the first comparator 15.

  When the error signal becomes larger and the error signal becomes 6V and the comparison signal becomes 3V, the pulse width of the output of the first comparator 15 reaches the upper limit. The pulse width detection circuit 19 issues a detection signal, and the mode switching circuit 21 receiving the detection signal opens the switches 16 and 17 and closes the switch 18 to store the state. FIG. 11 shows this state, and the comparison signal is a value obtained by subtracting 6 V from the error signal. The drive signal generation circuit 20 alternately outputs a drive signal having a maximum width unrelated to the pulse width of the output of the third comparator 44 to the drive signals E and F, and is driven at the rising edge of the output of the first comparator 15. The signals A and B are alternately raised, and the drive signals A and B are lowered at the fall of the output of the first comparator 15 after one clock, and this is repeated. As a result, the drive signals of the semiconductor switches 39a, 39b, 40a, and 40b have the maximum width, and the drive signals of the semiconductor switches 34a and 34b have the width obtained by adding one cycle of the clock to the output of the first comparator 15.

  When the error signal is further increased, the pulse width of the output of the first comparator 15 is increased. When the error signal is 9V and the comparison signal is 3V, the pulse width reaches the upper limit. The error signal does not exceed 9V, and the pulse width detection circuit 19 detects that the pulse width has reached the upper limit and sends a detection signal to the mode switching circuit 21, but the mode switching circuit 21 switches the switches 16, 17, 18. And the state of the drive signal generation circuit 20 is not changed. When the error signal becomes smaller from here, the state shown in FIG. 10 is returned to the state shown in FIG. 9 in the same manner as the control device shown in FIG.

  As described above, the driving signals A and B have a width of zero, the same width as the pulse width of the output of the first comparator 15, and one cycle of the clock added to the output of the first comparator 15 depending on the magnitude of the error signal. The drive signals E and F have either the same width as the output pulse width of the third comparator 44, or the maximum width unrelated to the output pulse width of the third comparator 44. . When the drive signals A and B have a width obtained by adding one cycle of the clock to the output of the first comparator 15, a period in which the drive signals A and B are output at the same time occurs. Since the second comparator 22 sends a detection signal to the mode switching circuit 21 when the error signal suddenly decreases and falls from 6V to 3V, the mode switching circuit 21 has the drive signals A and B having zero width. In addition, the conditions of the drive signal generation circuit 20 are set so that the drive signals E and F have the same width as the pulse width of the output of the third comparator 44.

  The high-speed pulse power supply device configured as described above operates as described below. FIG. 12 shows a waveform of a main part when one pulse is output. A and B are driving signals for the semiconductor switches 34a and 34b, D is a driving signal for the semiconductor switch 37, and E is a semiconductor switch 39a. And 40b, F is a drive signal for the semiconductor switches 39b and 40a, G is an output voltage, and H is an output current. The AC power supplied from the AC input terminal 33 is converted into DC power by the rectifier 31 and stored in the capacitor 32. Needless to say, the semiconductor switches 39a and 40b and the semiconductor switches 39b and 40a must be insulated when a drive signal is applied.

  At the start of pulse energization, the semiconductor switches 39a, 39b, 40a, and 40b are first supplied with a drive signal having the same width as the output of the third comparator 44. However, when the pulse energization starts, the output current is zero and the error signal Therefore, the drive signal applied to the semiconductor switches 39a, 39b, 40a, and 40b rapidly becomes the maximum width. Further, the drive signal supplied to the semiconductor switches 34a and 34b rapidly becomes the same as the pulse width of the output of the first comparator 15 from zero width, and further, one cycle of the clock is added to the output of the first comparator 15. The added width. A drive signal is continuously supplied to the semiconductor switch 37 during the energization period of the pulse.

  When a drive signal is given, the semiconductor switches 39a and 40b and the semiconductor switches 39b and 40a are turned on alternately, and an alternating current flows through the primary coil of the transformer 41. The AC power induced in the secondary coil of the transformer 41 is rectified by the diodes 42a and 42b. Further, the semiconductor switches 34a and 34b and the semiconductor switch 37 are turned on, and a DC voltage is applied to the primary coils of the transformers 38a and 38b. As a result, a voltage is induced on the secondary side of the transformers 38a and 38b, and a current flows to the load through the diodes 42a and 42b. Current flows through the primary coils of the transformers 38a and 38b through the semiconductor switches 34a and 34b and the semiconductor switch 37 while the semiconductor switches 34a and 34b are on, and when the semiconductor switches 34a and 34b are turned off, A current flows through the diodes 36a and 36b.

  In a state where the drive signal applied to the semiconductor switches 34a and 34b has a width obtained by adding one clock cycle to the output of the first comparator 15, there is a period in which the drive signals are simultaneously applied to the semiconductor switches 34a and 34b. During this time, the semiconductor switches 34a and 34b are simultaneously turned on, and a DC voltage is simultaneously applied to the primary coils of the transformers 38a and 38b. The voltage and diode of the two secondary coils of the transformers 38a and 38b are applied to the load. The sum of the voltages rectified by 42a and 42b is added. As a result, a high voltage is applied to the load, and the current rises quickly. Thereafter, the semiconductor switches 39a, 39b, 40a, 40b and the semiconductor switches 34a, 34b are repeatedly turned on and off according to the drive signal, and the semiconductor switch 37 continues to be on.

  When the current flowing through the load rises and approaches the set current and the error signal becomes smaller, a drive signal having the same width as the output of the first comparator 15 is supplied to the semiconductor switches 34a and 34b. As a result, the sum of the voltage of one of the secondary coils of the transformers 38a and 38b and the voltage rectified by the diodes 42a and 42b is applied to the load. When the error signal is further reduced, the drive signal is not applied to the semiconductor switches 34a and 34b, and only the voltage rectified by the diodes 42a and 42b is applied to the load. When the error signal is further reduced, the width of the drive signal applied to the semiconductor switches 39a, 39b, 40a, and 40b is reduced, and the current flowing through the load is controlled to be constant.

  In this way, when the error signal is large, the voltage of two transformers 38a and 38b is added, and when it is slightly large, the voltage of one is added to the voltage rectified by the diodes 42a and 42b and added to the load, and the error signal is small. Sometimes only the voltage rectified by the diodes 42a, 42b is applied to the load. As a result, after the current rises quickly due to the high voltage, the voltage is controlled to be low and the current to be constant. When the current suddenly rises and the error voltage suddenly decreases to 3 V or less, the drive signals A and B are zero in width, and the drive signals E and F are the output pulse width of the third comparator 44. Since they have the same width, only the voltage rectified by the diodes 42a and 42b is applied to the load, and the current does not overshoot.

  If the drive signals supplied to the semiconductor switches 34a and 34b are alternately raised every clock cycle, the semiconductor switches 34a and 34b are alternately turned on every clock cycle. As a result, the ripples of the output voltage and output current are reduced, and the switching frequency of the semiconductor switches 34a and 34b is ½ of the carrier frequency, which has the advantage of reducing the switching loss. Further, if the carriers that generate the drive signals for the semiconductor switches 39a, 39b, 40a, and 40b and the carriers that generate the drive signals for the semiconductor switches 34a and 34b have the same period with different phases, the semiconductor switches 39a and 40b or the semiconductor The time when the switches 39b and 40a are turned on is different from the time when the semiconductor switches 34a and 34b are turned on, and the ripples of the output voltage and output current are further reduced.

  When the pulse energization period ends, the semiconductor switches 34a and 34b and the semiconductor switch 37 are all turned off. The current flowing in the primary coil of the transformers 38a and 38b flows into the capacitor 32 through the diodes 36a and 36b and the diode 35, the magnetic energy stored in the transformers 38a and 38b is recovered, and the magnetic flux in the iron core is reset. The reverse polarity voltage is generated in the primary coil of the transformers 38a and 38b, the voltage is induced in the secondary coil, and the reverse voltage is applied to the load to rapidly attenuate the load current. The configuration is the same as that shown in FIG. At this time, all the semiconductor switches 39a, 39b, 40a, and 40b are also turned off, and the operation as the switching power supply is stopped.

  As described above, according to each of the above-described embodiments, the sum of the secondary voltages of the plurality of transformers 8a, 8b, 8c, or the two of the plurality of transformers 38a, 38b at the start of pulse energization. Since the high voltage of the total voltage of the switching power supply composed of the next voltage and the semiconductor switches 39a, 39b, 40a, 40b, the transformer 41, and the diodes 42a, 42b is applied to the load, the current rises quickly. After the current rises, two or one of the secondary voltages of the transformers 8a, 8b and 8c, or one of the secondary voltages of the transformers 38a and 38b are added to the output voltage of the switching power supply. The output voltage of the switching power supply or the switching power supply is applied to the load, and the on-time of each semiconductor switch is not extremely shortened even when controlling to a constant current because the voltage is low. There is.

  In any of the above embodiments, the semiconductor switches 4a, 4b, 4c or the semiconductor switches 34a, 34b are controlled in pulse width, and as a result, when the width of the drive signal is wide, three or two semiconductor switches are provided. Although a period during which the power is turned on is generated at the same time, it is also possible to forcibly give a drive signal at the same time when energization is started. If the drive signals are forcibly given at the same time, the semiconductor switches 4a, 4b, 4c or the semiconductor switches 34a, 34b are continuously turned on at the same time, and the current rise can be made faster.

FIG. 3 is a connection diagram of a main circuit showing the configuration of the invention of claim 1. It is a block diagram which shows the structure of a control apparatus. It is a figure which shows the waveform of a drive signal. It is a figure which shows the waveform of a drive signal. It is a figure which shows the waveform of a drive signal. It is a wave form diagram of the principal part at the time of operation. FIG. 7 is a connection diagram of a main circuit showing the configuration of the invention of claim 4. It is a block diagram which shows the structure of a control apparatus. It is a figure which shows the waveform of a drive signal. It is a figure which shows the waveform of a drive signal. It is a figure which shows the waveform of a drive signal. It is a wave form diagram of the principal part at the time of operation.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Rectifier 2 Capacitor 3 AC input terminal 4a, 4b, 4c Semiconductor switch 5 Diode 6a, 6b, 6c Diode 7 Semiconductor switch 8a, 8b, 8c Transformer 9 Diode 10 Output terminal 11 Error amplifier 12 Clock generation circuit 13 Carrier signal generation circuit DESCRIPTION OF SYMBOLS 14 Adder 15 1st comparator 16, 17, 18 switch 19 Pulse width detection circuit 20 Drive signal generation circuit 21 Mode switching circuit 22 2nd comparator 31 Rectifier 32 Capacitor 33 AC input terminal 34a, 34b Semiconductor switch 35, 36a, 36b Diode 37 Semiconductor switch 38a, 38b Transformer 39a, 39b, 40a, 40b Semiconductor switch 41 Transformer 42a, 42b Diode 43 Output terminal 44 Third comparator

Claims (5)

  One end of a primary coil of a plurality of transformers having a voltage-time product sufficient to pass pulsed power is individually connected to one pole of a DC power source via a first semiconductor switch, and the primary coil of the transformer The other end is connected to the other pole of the DC power supply through a batch second semiconductor switch, and the first terminal is connected between the primary coil of each transformer, the connection point of each first semiconductor switch, and the other pole of the DC power supply. The diode is connected as a polarity that does not flow the steady-state current, and the second diode does not flow between the connection point of the primary coil of the transformer, the second semiconductor switch, and one pole of the DC power supply. It is connected as a polarity, the secondary coil of each transformer is connected in series, and a voltage induced in the secondary coil by a voltage applied to the primary coil is applied to a load via a third diode. Fast pulse Source apparatus.   During the energization period of the pulse, the second semiconductor switch is continuously turned on, and at the start of energization, the plurality of first semiconductor switches are simultaneously turned on, and after the load current rises, the current is kept constant. 2. The high-speed pulse power supply device according to claim 1, further comprising control means for generating a drive signal for turning on and off one semiconductor switch.   The control means generates a drive signal to be applied to the first semiconductor switch by pulse width control, and sequentially applies the drive signal to each first semiconductor switch for each cycle of a carrier serving as a reference for pulse width control. The high-speed pulse power supply device according to claim 1 or 2, wherein the high-speed pulse power supply device is used.   One end of a primary coil of a plurality of transformers having a voltage-time product sufficient to pass pulsed power is individually connected to one pole of a DC power source via a first semiconductor switch, and the primary coil of the transformer The other end is connected to the other pole of the DC power supply through a batch second semiconductor switch, and the first terminal is connected between the primary coil of each transformer, the connection point of each first semiconductor switch, and the other pole of the DC power supply. The diode is connected as a polarity that does not flow the steady-state current, and the second diode does not flow between the connection point of the primary coil of the transformer, the second semiconductor switch, and one pole of the DC power supply. Connect as the polarity, connect the secondary coil of each transformer and the output of the switching power supply separately provided in series, the voltage induced in the secondary coil by the voltage applied to the primary coil of each transformer and the switching power supply Fast pulse power supply and applying the combined load plus the power voltage.   It is assumed that the output of the switching power supply is controlled by pulse width control, and the carrier used as the reference for the pulse width control has the same period that is different in phase from the carrier used as the reference for the pulse width control of the first semiconductor switch. The high-speed pulse power supply device according to claim 4.

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