JP2009135458A5 - - Google Patents

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Publication number
JP2009135458A5
JP2009135458A5 JP2008273591A JP2008273591A JP2009135458A5 JP 2009135458 A5 JP2009135458 A5 JP 2009135458A5 JP 2008273591 A JP2008273591 A JP 2008273591A JP 2008273591 A JP2008273591 A JP 2008273591A JP 2009135458 A5 JP2009135458 A5 JP 2009135458A5
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JP
Japan
Prior art keywords
protruding electrode
electrode
insulating resin
covering
resin layer
Prior art date
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Granted
Application number
JP2008273591A
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Japanese (ja)
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JP4698722B2 (en
JP2009135458A (en
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Publication date
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Priority to JP2008273591A priority Critical patent/JP4698722B2/en
Priority claimed from JP2008273591A external-priority patent/JP4698722B2/en
Priority to US12/266,907 priority patent/US8129846B2/en
Priority to CN2008102463746A priority patent/CN101488487B/en
Publication of JP2009135458A publication Critical patent/JP2009135458A/en
Publication of JP2009135458A5 publication Critical patent/JP2009135458A5/ja
Application granted granted Critical
Publication of JP4698722B2 publication Critical patent/JP4698722B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Claims (14)

絶縁樹脂層と、
前記絶縁樹脂層の一方の表面に設けられた配線層と、
前記配線層の前記絶縁樹脂層側の表面に設けられた突起電極と、
前記突起電極の頂部面と、側面のうち前記配線層と接する領域を除いた前記頂部面と連続する領域とを被覆し、金属層よりなる被覆部と、
を備えることを特徴とする素子搭載用基板。
An insulating resin layer;
A wiring layer provided on one surface of the insulating resin layer;
Protruding electrodes provided on the surface of the insulating resin layer side of the wiring layer;
Covering the top surface of the protruding electrode and the region of the side surface that is continuous with the top surface excluding the region in contact with the wiring layer, a covering portion made of a metal layer,
An element mounting board comprising:
前記被覆部とは不連続であり、前記配線層の表面と前記突起電極の側面とが接する基端部を含む前記基端部からの一部を少なくとも被覆し、金属層よりなる他の被覆部を備えることを特徴とする請求項1に記載の素子搭載用基板。   Other covering portions which are discontinuous with the covering portion and cover at least a part from the base end portion including the base end portion where the surface of the wiring layer and the side surface of the protruding electrode are in contact with each other, and are made of a metal layer The device mounting substrate according to claim 1, comprising: 前記金属層は、前記突起電極の降伏応力の40%より大きく100%以下の降伏応力を有することを特徴とする請求項1または2に記載の素子搭載用基板。   The element mounting substrate according to claim 1, wherein the metal layer has a yield stress that is greater than 40% and less than or equal to 100% of the yield stress of the protruding electrode. 前記金属層は、前記突起電極の降伏応力の50%以上75%以下の降伏応力を有し、且つ前記被覆部は、前記突起電極の側面のうち前記突起電極の前記頂部面から前記配線層の前記突起電極が設けられた側の表面までの高さの1/2以下の領域を被覆していることを特徴とする請求項1または2に記載の素子搭載用基板。   The metal layer has a yield stress of not less than 50% and not more than 75% of the yield stress of the protruding electrode, and the covering portion extends from the top surface of the protruding electrode to the wiring layer on the side surface of the protruding electrode. 3. The element mounting substrate according to claim 1, wherein a region of ½ or less of the height to the surface on the side where the protruding electrode is provided is covered. 絶縁樹脂層と、
前記絶縁樹脂層の一方の表面に設けられた配線層と、
前記配線層の前記絶縁樹脂層側の表面に設けられた突起電極と、
を備え、
前記突起電極は、側面に前記配線層側が細くなるような段差を有することを特徴とする素子搭載用基板。
An insulating resin layer;
A wiring layer provided on one surface of the insulating resin layer;
Protruding electrodes provided on the surface of the insulating resin layer side of the wiring layer;
With
The element mounting board according to claim 1, wherein the protruding electrode has a step on the side surface such that the wiring layer side becomes narrower.
前記突起電極は、側面の前記段差よりも前記配線層側に、前記配線層側が太くなるような段差を有し、当該段差により太くなった領域が前記配線層まで延在していることを特徴とする請求項5に記載の素子搭載用基板。   The protruding electrode has a step which is thicker on the wiring layer side on the wiring layer side than the step on a side surface, and a region thickened by the step extends to the wiring layer. The element mounting substrate according to claim 5. 請求項1ないし6のいずれか1項に記載の素子搭載用基板と、
前記素子搭載用基板の前記突起電極に対向する素子電極が設けられた半導体素子と、
前記配線層と前記半導体素子との間に設けられた絶縁樹脂層と、
を備え、
前記突起電極が前記絶縁樹脂層を貫通し、前記突起電極と前記素子電極とが電気的に接続されていることを特徴とする半導体モジュール。
The device mounting board according to any one of claims 1 to 6,
A semiconductor element provided with an element electrode facing the protruding electrode of the element mounting substrate;
An insulating resin layer provided between the wiring layer and the semiconductor element;
With
The semiconductor module, wherein the protruding electrode penetrates the insulating resin layer, and the protruding electrode and the element electrode are electrically connected.
前記絶縁樹脂層は、加圧によって塑性流動を起こすことを特徴とする請求項7に記載の半導体モジュール。   The semiconductor module according to claim 7, wherein the insulating resin layer causes plastic flow by pressurization. 突起電極が設けられた金属板を準備する工程と、
前記突起電極の頂部面と、側面のうち前記金属板と接する領域を除いた前記頂部面と連続する領域とを金属を用いて被覆する被覆工程と、
前記突起電極が形成された前記金属板と、前記突起電極に対応する素子電極が設けられた半導体素子とを、絶縁樹脂層を介して圧着し、前記突起電極が前記絶縁樹脂層を貫通することにより、前記突起電極と前記素子電極とを電気的に接続させる圧着工程と、
前記金属板を選択的に除去して配線層を形成する工程と、
を含むことを特徴とする半導体モジュールの製造方法。
Preparing a metal plate provided with protruding electrodes;
A covering step of covering the top surface of the protruding electrode and a region continuous with the top surface excluding a region in contact with the metal plate among side surfaces using a metal;
The metal plate on which the protruding electrode is formed and a semiconductor element on which an element electrode corresponding to the protruding electrode is pressed through an insulating resin layer, and the protruding electrode penetrates the insulating resin layer. A crimping step for electrically connecting the protruding electrode and the element electrode;
Selectively removing the metal plate to form a wiring layer;
A method for manufacturing a semiconductor module, comprising:
突起電極が設けられた金属板を準備する工程と、
前記突起電極の頂部面と、側面のうち前記金属板と接する領域を除いた前記頂部面と連続する領域とを金属を用いて被覆する被覆工程と、
前記突起電極が形成された前記金属板に、前記突起電極を被覆する前記金属が露出するように絶縁樹脂層を積層する工程と、
前記突起電極に対応する素子電極が設けられた半導体素子を前記絶縁樹脂層が積層された金属板に圧着して、前記突起電極と前記素子電極とを電気的に接続する圧着工程と、
前記金属板を選択的に除去して配線層を形成する工程と、
を含むことを特徴とする半導体モジュールの製造方法。
Preparing a metal plate provided with protruding electrodes;
A covering step of covering the top surface of the protruding electrode and a region continuous with the top surface excluding a region in contact with the metal plate among side surfaces using a metal;
Laminating an insulating resin layer on the metal plate on which the protruding electrode is formed so that the metal covering the protruding electrode is exposed;
Crimping a semiconductor element provided with an element electrode corresponding to the protruding electrode to a metal plate on which the insulating resin layer is laminated, and electrically connecting the protruding electrode and the element electrode;
Selectively removing the metal plate to form a wiring layer;
A method for manufacturing a semiconductor module, comprising:
突起電極が設けられた金属板を準備する工程と、Preparing a metal plate provided with protruding electrodes;
前記突起電極の頂部面と、側面のうち前記金属板と接する領域を除いた前記頂部面と連続する領域とを金属を用いて被覆する被覆工程と、A covering step of covering the top surface of the protruding electrode and a region continuous with the top surface excluding a region in contact with the metal plate among side surfaces using a metal;
前記突起電極が形成された前記金属板に、前記突起電極を被覆する前記金属を覆うように絶縁樹脂層を積層する工程と、Laminating an insulating resin layer on the metal plate on which the protruding electrode is formed so as to cover the metal covering the protruding electrode;
前記突起電極を被覆する前記金属が露出するように前記絶縁樹脂層をエッチングする工程と、Etching the insulating resin layer so that the metal covering the protruding electrode is exposed;
前記突起電極に対応する素子電極が設けられた半導体素子を前記絶縁樹脂層が形成された金属板に圧着して、前記突起電極と前記素子電極とを電気的に接続する圧着工程と、Crimping a semiconductor element provided with an element electrode corresponding to the protruding electrode to a metal plate on which the insulating resin layer is formed, and electrically connecting the protruding electrode and the element electrode;
前記金属板を選択的に除去して配線層を形成する工程と、Selectively removing the metal plate to form a wiring layer;
を含むことを特徴とする半導体モジュールの製造方法。A method for manufacturing a semiconductor module, comprising:
前記被覆工程において、前記金属は、前記突起電極の降伏応力の40%より大きく100%以下の降伏応力を有することを特徴とする請求項9ないし11のうちいずれか1項に記載の半導体モジュールの製造方法。 12. The semiconductor module according to claim 9 , wherein, in the covering step, the metal has a yield stress that is greater than 40% and less than or equal to 100% of the yield stress of the protruding electrode. Production method. 前記被覆工程において、前記金属は、前記突起電極の降伏応力の50%以上75%以下の降伏応力を有し、且つ前記突起電極の前記頂部面から前記配線層の前記突起電極が設けられた側の表面までの高さの1/2以下の領域を被覆することを特徴とする請求項9ないし11のうちいずれか1項に記載の半導体モジュールの製造方法。 In the covering step, the metal has a yield stress of 50% to 75% of a yield stress of the bump electrode, and a side of the wiring layer on which the bump electrode is provided from the top surface of the bump electrode the method as claimed in any one of claims 9 to 11, characterized in that covering less than half of the area of to the surface height. 前記絶縁樹脂層は、
加圧によって塑性流動を起こすことを特徴とする請求項9ないし13のいずれか1項に記載の半導体モジュールの製造方法。
The insulating resin layer is
The method as claimed in any one of claims 9 to 13, characterized in that causing plastic flow by pressure.
JP2008273591A 2007-11-08 2008-10-23 Device mounting substrate, semiconductor module, manufacturing method thereof, and portable device Expired - Fee Related JP4698722B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2008273591A JP4698722B2 (en) 2007-11-08 2008-10-23 Device mounting substrate, semiconductor module, manufacturing method thereof, and portable device
US12/266,907 US8129846B2 (en) 2007-11-08 2008-11-07 Board adapted to mount an electronic device, semiconductor module and manufacturing method therefor, and portable device
CN2008102463746A CN101488487B (en) 2007-11-08 2008-11-10 Board adapted to mount an element, semiconductor module and manufacturing method therefore, and portable device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2007291342 2007-11-08
JP2007291342 2007-11-08
JP2008273591A JP4698722B2 (en) 2007-11-08 2008-10-23 Device mounting substrate, semiconductor module, manufacturing method thereof, and portable device

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JP2010271794A Division JP5295211B2 (en) 2007-11-08 2010-12-06 Manufacturing method of semiconductor module

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JP2009135458A JP2009135458A (en) 2009-06-18
JP2009135458A5 true JP2009135458A5 (en) 2010-05-13
JP4698722B2 JP4698722B2 (en) 2011-06-08

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JP5002633B2 (en) * 2009-09-30 2012-08-15 三洋電機株式会社 Semiconductor module and portable device
US9455162B2 (en) 2013-03-14 2016-09-27 Invensas Corporation Low cost interposer and method of fabrication
JP6102398B2 (en) * 2013-03-26 2017-03-29 セイコーエプソン株式会社 Semiconductor device

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