JP2009130648A - Signal processing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that a signal band of an output signal is restricted by a switch for switching the output signal and an external load capacitor for receiving the output signal. <P>SOLUTION: A signal processing system includes: a first analog signal outputting part 10 to output a first analog signal synchronized with a clock; a second analog signal outputting part 12 to output a second analog signal that is not synchronized with the clock; an arithmetic circuit 2 for executing a prescribed arithmetic operation of an input signal and outputting the signal; and a control circuit 14 for changing an input to the arithmetic circuit 2 into the first analog signal or the second analog signal and changing the function of the arithmetic circuit 2 in synchronism with the change. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a signal processing system, and more particularly to a signal processing system that switches and outputs at least two analog signals.

  In an integrated circuit in which a large number of circuits having different functions are integrally formed, the input of signals to each circuit and the output of the signal processing results of each circuit are via pins (input / output terminals) provided on the package of the integrated circuit. Done. When the number of pins is smaller than the number of inputs / outputs, it is generally performed that a plurality of circuits share a pin by switching a signal to be input / output by providing a changeover switch circuit.

For example, a signal processing circuit described in Patent Document 1 is known as a method for switching the output by the changeover switch circuit as described above. The signal processing circuit according to Patent Document 1 is a circuit related to an automatic focus detection device, and only the part related to the switching of the output of the signal processing circuit is shown in FIG. Show.
Japanese Patent No. 2666274

  This signal processing circuit includes a clock synchronization circuit 100 including a sensing unit 104 (photoelectric conversion unit 15 in the original drawing), a first analog signal output circuit 110, a first arithmetic circuit 119, and a control circuit 114, and a second analog. A clock asynchronous circuit 120 including a signal output circuit 112 (temperature detection circuit 19 in the original diagram) and a second arithmetic circuit 121, a switch (SW1) 132 (analog switch AN4 in the original diagram), and a switch (SW2) 133 (analog in the original diagram) This is a sensor IC (Integrated Circuit) 1000 composed of a switch AN5), a switching circuit 130 including an inverter 131, and a load capacity (C1) 140 (not shown in the original drawing).

  The control circuit 114 outputs control signals phi (x), sh (x), str_sel, and ana_sel synchronized with the clock CLK input from the outside. The sensing unit 104 is a circuit that converts an optical signal into an electrical signal, and outputs a signal synchronized with the control signal phi (x) input from the control circuit 114. The first analog signal output circuit 110 receives the output of the sensing unit 104 and outputs a clock synchronization signal Vsc synchronized with the control signal sh (x) input from the control circuit 114. The first arithmetic circuit 119 receives the clock synchronization signal Vsc and outputs a signal synchronized with the control signal str_sel input from the control circuit 114. On the other hand, the second analog signal output circuit 112 is a circuit that generates a signal according to the ambient temperature, and outputs a clock asynchronous signal Vnsc that is not synchronized with the clock CLK. The second arithmetic circuit 121 receives the clock asynchronous signal Vnsc, and amplifies and outputs this signal.

  The switching circuit 130 is a circuit that selects and outputs one of two input signals. The control signal ana_sel is input from the control circuit 114 to the control terminal of the switch (SW1) 132, and the control signal ana_sel via the inverter 131 is input to the control terminal of the switch (SW2) 133. The output terminal of the clock synchronization circuit 100 is connected to one end of the switch (SW1) 132, and the output terminal of the clock asynchronous circuit 120 is connected to one end of the switch (SW2) 133. The other ends of the switch (SW1) 132 and the switch (SW2) 133 are connected in common, and this becomes an output terminal of the sensor IC 1000 and outputs an output signal Vout. The output signal Vout is input to the load capacitor (C1) 140. When the control signal ana_sel from the control circuit 114 becomes H level, the switch (SW1) 132 is turned on (closed), the switch (SW2) 133 is turned off (open), and a signal obtained by calculating and amplifying the clock synchronization signal Vsc is sent from the sensor IC1000. Is output. On the other hand, when the control signal ana_sel is switched to the L level, the switch (SW2) 133 is turned on (closed), the switch (SW1) 132 is turned off (open), and the clock asynchronous signal Vnsc unrelated to the clock CLK is calculated and amplified. The signal is output from the sensor IC 1000.

  In such a conventional signal processing circuit, the switch (SW1) 132 is connected to the output terminal of the first arithmetic circuit 119, and the switch (SW2) 133 is connected to the output terminal of the second arithmetic circuit 121. A high-frequency cutoff filter (low-pass filter) is formed by the ON resistance of the switch (SW1) 132 or the switch (SW2) 133 and the load capacitance (C1) 140. Therefore, when the switch (SW1) 132 is turned on (closed), the frequency band of the signal output from the clock synchronization circuit 100 is controlled by the on-resistance of the switch (SW1) 132 and the load capacitance (C1) 140. It had to be made lower than the cut-off frequency of the formed high-frequency cutoff filter. That is, the signal pass band is limited by the high-frequency cutoff filter, and it is difficult to improve the reading speed.

  The present invention has been made in view of such circumstances, and an object thereof is to provide a signal processing system capable of outputting two types of signals from one terminal without being restricted by a signal band due to load capacity. To do.

  In order to achieve the above object, a signal processing system according to a first aspect of the present invention includes a first analog signal output unit that outputs a first analog signal synchronized with a clock, and a second analog signal that is not synchronized with a clock. A second analog signal output unit for output, a calculation unit for executing a predetermined calculation on the input signal and outputting the result, and an input to the calculation unit is changed to the first analog signal or the second analog signal And a control unit that changes the function of the calculation unit in synchronization with the change.

  A signal processing system according to a second invention is the signal processing system according to the first invention, wherein the calculation unit includes an operational amplifier, a first capacitor, a second capacitor, a first switch, and a second switch. A third switch, and the first capacitor is connected between an inverting input terminal of the operational amplifier and a first output terminal of the first analog signal output unit, and the first switch is connected to the operational amplifier. Between the non-inverting input terminal of the operational amplifier and the second output terminal of the first analog signal output unit, and the second switch is an output of the non-inverting input terminal of the operational amplifier and the second analog signal output unit. The second capacitor and the third switch are connected in parallel between an inverting input terminal and an output terminal of the operational amplifier, and the control unit is configured by opening and closing the third switch. Calculation unit functions Further in synchronization, controls the first switch and the second switch.

The signal processing system according to a third aspect of the present invention is the signal processing system according to the first or second aspect, wherein the arithmetic unit outputs the signal related to the second analog signal output unit. The control unit stops the supply of the clock to the signal output unit.
The signal processing system according to a fourth aspect of the present invention is the signal processing system according to the first aspect, the second aspect, or the third aspect, wherein the first analog signal output unit is a CCD sensor circuit. The analog signal output unit 2 is a temperature detection circuit.

  A signal processing system according to a fifth aspect of the invention includes a first analog signal output unit that outputs a first analog signal synchronized with a clock, and a second analog signal output that outputs a second analog signal not synchronized with the clock. And the first analog signal output unit and the second analog signal output unit are connected to the output terminals of the first analog signal output unit and the second analog signal output unit to selectively switch between the first analog signal and the second analog signal for output. And a calculation unit to which either the first analog signal or the second analog signal selected by the switching unit is input, and the calculation unit selects the selection in the switching unit. Change the function according to

A signal processing system according to a sixth aspect of the present invention is the signal processing system according to the fifth aspect, wherein the arithmetic unit functions as an inverting amplifier circuit when the first analog signal is input, while the second analog signal Functions as a voltage follower circuit.
A signal processing system according to a seventh invention is the signal processing system according to the fifth invention, wherein the arithmetic unit is composed of an operational amplifier and a passive element, and an input capacitance is connected between the inverting input terminal of the operational amplifier and the switching unit. A switch and a feedback capacitor are connected in parallel between the inverting input terminal and the output terminal, and the function of the arithmetic unit is changed by switching the switch.

  A signal processing system according to an eighth aspect of the present invention is the signal processing system according to the fifth aspect, wherein the clock is stopped when the second analog signal is output.

  According to the first invention, by changing the function of the calculation unit according to the switching of the signal input to the calculation unit, without being subjected to bandwidth limitation due to the load capacity connected to the output side of the calculation unit, Different outputs can be obtained from one terminal.

  According to the second invention, the two switches connected to the non-inverting input terminal of the operational amplifier are exclusively switched, and the switch provided between the inverting input terminal and the output terminal of the operational amplifier in synchronization with the switching. By switching between opening and closing, the configuration of the calculation unit can be changed, and different outputs can be obtained from one terminal without being subjected to band limitation due to the load capacity connected to the output side of the calculation unit.

Furthermore, according to the third aspect, the supply of the clock to the first analog signal output unit is stopped while the signal related to the second analog signal is being output. For this reason, it is possible to reduce the superimposition of clock synchronization noise on the second analog signal being output.
Further, according to the fourth invention, in the signal processing system having the CCD sensor circuit and the temperature detection circuit, one output terminal can be shared by the results of the two signal processes.

  According to the fifth invention, the switching unit having a switch is provided between the first analog signal output unit and the second analog signal output unit and the calculation unit, and the analog signal input to the calculation unit is switched. Since the function of the calculation unit is changed accordingly, the load capacity connected to the output side of the calculation unit is not directly connected to the switch of the switching unit to form a high-frequency cutoff filter. Different outputs can be obtained from one terminal without being subjected to band limitation.

According to the sixth aspect of the present invention, the circuit configuration of the arithmetic unit can be changed to an inverting amplifier circuit during output of a clock-synchronized analog signal, and to a voltage follower circuit during output of a clock-synchronized analog signal.
According to the seventh aspect, the function of the calculation unit can be changed.

  According to the eighth aspect of the invention, the supply of the clock to the first analog signal output unit is stopped during the output of the second analog signal that is asynchronous with the clock. Therefore, the second analog signal being output is stopped. The superimposition of clock synchronization noise on the signal can be reduced.

(First embodiment)
Hereinafter, preferred embodiments of a signal processing system to which the present invention is applied will be described with reference to the drawings. 1 to 3 relate to a first embodiment of the present invention, FIG. 1 is a block diagram of a sensor IC 1 incorporating a signal processing circuit, and FIG. 2 is a block diagram of an arithmetic circuit 2 in the sensor IC 1. 3 is a diagram showing the relationship between the input / output signal and each control signal and the state of each switch.

  The sensor IC 1 includes a sensing unit 4, a first analog signal output unit 10, a second analog signal output unit 12, a switching circuit 11, an arithmetic circuit 2, and a control circuit 14. The switching circuit 11 includes a first switch (S 1) 41, a second switch (S 2) 42, and an inverter 29. The control circuit 14 generates and outputs control signals phi (x), sh (x), ana_sel, and str_sel synchronized with a clock ORG_CLK input from the outside. The control signal phi (x) is output to the sensing unit 4, the control signal sh (x) is output to the first analog signal output unit 10, the control signal ana_sel is output to the switching circuit 11, and the control signal str_sel is output to the arithmetic circuit 2, respectively. The The sensing unit 4 receives a control signal phi (x) synchronized with the clock ORG_CLK from the control circuit 14, and outputs a sensor signal Vfda in synchronization with the control signal phi (x).

  A control signal sh (x) synchronized with the sensor signal Vfda and the clock ORG_CLK is input to the first analog signal output unit 10. The first analog signal output unit 10 performs signal processing on the sensor signal Vfda, and outputs a clock synchronization signal Vsc1 and a reference signal Vsc2 in synchronization with the control signal sh (x). The clock synchronization signal Vsc1 is input to the arithmetic circuit 2 as the first input signal Vin1, and the reference signal Vsc2 is input to the first switch (S1) 41 of the switching circuit 11.

  The second analog signal output unit 12 does not require the control signal from the control circuit 14 and outputs the clock asynchronous signal Vnsc not related to the clock ORG_CLK to the second switch (S2) 42 of the switching circuit 11.

  The switching circuit 11 is a circuit for switching an input signal to the arithmetic circuit 2. The reference signal Vsc2 is input to one end of the first switch (S1) 41 and the one end of the second switch (S2) 42 is connected. Is supplied with a clock asynchronous signal Vnsc. The other ends of the first switch (S1) 41 and the second switch (S2) 42 are connected in common, and a signal output from the common end is input to the arithmetic circuit 2 as the second input signal Vin2. Therefore, the clock synchronization signal Vsc1 output from the first analog signal output unit 10 is input to the arithmetic circuit 2 as the first input signal Vin1, and the signal output from the switching circuit 11 is the second input signal Vin2. Is entered as Further, a control signal str_sel output from the control circuit 14 is input. The arithmetic circuit 2 has its arithmetic function changed according to the state of the control signal str_sel, and outputs the arithmetic result as the output signal Vout of the sensor IC1. A load capacitor (C1) 140 is connected to the output terminal of the output signal Vout.

  The opening and closing of the first switch (S1) 41 is controlled by a control signal ana_sel from the control circuit 14, and is turned on (closed) when the control signal ana_sel is at the H level, and is turned off (opened) when the control signal ana_sel is at the L level. It becomes. The opening / closing of the second switch (S2) 42 is controlled by a control signal ana_sel via the inverter 29. The control signal ana_sel is turned on (closed) when the control signal ana_sel is L level, and is turned off when the control signal ana_sel is H level ( Open). Therefore, the first switch (S 1) 41 and the second switch (S 2) 42 operate exclusively by the inverter 29.

  Next, details of the arithmetic circuit 2 will be described with reference to FIG. The arithmetic circuit 2 includes an operational amplifier 30, an input capacitor (Ci) 44, a feedback capacitor (Cf) 45, and a feedback switch (S 3) 43. One end of the input capacitor (Ci) 44 is connected to the input terminal of the first input signal Vin1, and the other end is connected to the inverting input terminal of the operational amplifier 30. The feedback capacitor (Cf) 45 and the feedback switch (S3) 43 are connected in parallel between the inverting input terminal and the output terminal of the operational amplifier 30. The non-inverting input terminal of the operational amplifier 30 is connected to the input terminal of the second input signal Vin2, and the output terminal of the operational amplifier 30 is connected to the output terminal of the output signal Vout. The control terminal of the feedback switch (S3) 43 is connected to the control signal str_sel.

  The feedback switch (S3) 43 is controlled to open and close by an input control signal str_sel. That is, when the control signal str_sel is at the H level, the feedback switch (S3) 43 is turned on (closed), and when the control signal str_sel is at the L level, the feedback switch (S3) 43 is turned off (open).

  Next, the operation of the first embodiment of the present invention thus configured will be described with reference to FIG. First, when the signal of the first analog signal output unit 10 is output, each control signal is set to the state shown in the upper part of FIG. 3 to control the open / close relationship of each switch.

  That is, by setting the control signal ana_sel to the H level, the first switch (S1) 41 is turned on (closed), and the second switch (S2) 42 is turned off (open). As a result, the clock synchronization signal Vsc1 is input to the first input signal Vin1 of the arithmetic circuit 2, and the reference signal Vsc2 is input to the second input signal Vin2. Further, the feedback switch (S3) 43 is turned off (opened) by setting the control signal str_sel to the L level. As a result, the arithmetic circuit 2 becomes an inverting amplifier circuit having an amplification factor determined by the capacitance ratio of the input capacitor (Ci) 44 and the feedback capacitor (Cf) 45. As a result, the arithmetic circuit 2 outputs a signal obtained by multiplying the difference between the clock synchronization signal Vsc1 and the reference signal Vsc2 by (Ci / Cf) as the output signal Vout.

  When the clock asynchronous signal Vnsc, which is the output of the second analog signal output unit 12, is output, each control signal is set to the state shown in the lower part of FIG. 3 to control the open / close relationship of each switch. That is, by setting the control signal ana_sel to the L level, the first switch (S1) 41 is turned off (opened), and the second switch (S2) 42 is turned on (closed). As a result, the clock synchronization signal Vsc1 is input to the first input signal Vin1 of the arithmetic circuit 2, and the clock asynchronous signal Vnsc is input to the second input signal Vin2.

  Further, the feedback switch (S3) 43 is turned on (closed) by setting the control signal str_sel to the H level. As a result, the inverting input terminal and the output terminal of the operational amplifier 30 are short-circuited, and the arithmetic circuit 2 operates as a voltage follower circuit. Since the inverting input terminal and the output terminal of the operational amplifier 30 are short-circuited, both ends of the feedback capacitor (Cf) 45 have the same potential. Therefore, no charge is accumulated in the feedback capacitor (Cf) 45, and the arithmetic circuit 2 does not operate as a switched capacitor type inverting amplifier circuit.

  In this way, the control signal ana_sel and the control signal str_sel are switched at the same time, the signal input to the arithmetic circuit 2 is changed, and the function of the arithmetic circuit 2 is changed so that the clock synchronization signal Vsc1 synchronized with the clock ORG_CLK and the reference signal Two different outputs of the signal obtained by calculating and amplifying the difference of Vsc2 and the signal obtained by calculating and amplifying the clock asynchronous signal Vnsc not synchronized with the clock ORG_CLK can be obtained by one operational amplifier 30. That is, in this embodiment, when outputting a signal synchronized with the clock ORG_CLK as an output signal, the arithmetic circuit 2 is an inversion having an amplification factor determined by the ratio of the feedback capacitor (Cf) 45 and the input capacitor (Ci) 44. When functioning as an amplifier circuit and outputting a signal asynchronous to the clock ORG_CLK as an output signal, the arithmetic circuit 2 functions as a voltage follower circuit.

  In the present embodiment, since the arithmetic circuit 2 is connected between the load capacity (C1) 140 and the first switch (S1) 41 and the second switch (S2) 42, In this way, the load capacity (C1) 140 and the first switch (S1) 41 or the second switch (S2) 42 are directly connected, and the first switch (S1) 41 or the second switch (S2) 42 The high-frequency cutoff filter is not formed by the on-resistance and the load capacitance (C1) 140, and therefore the signal band is not limited by the load capacitance (C1) 140.

(Second Embodiment)
Next, a signal processing system according to a second embodiment of the present invention will be described with reference to FIGS. FIG. 4 is a block diagram of the sensor IC 1 incorporating the signal processing circuit according to the second embodiment, and FIG. 5 is a diagram showing the relationship between the input / output signals and the control signals in the second embodiment. The block diagram shown in FIG. 4 is the same as the configuration of the block diagram according to the first embodiment shown in FIG. Therefore, the following description will focus on the control circuit 14, which is a difference.

  The control circuit 14 includes a clock generation circuit 13, a digital signal generation circuit 16, and a circuit configuration switching circuit 18. The clock generation circuit 13 receives the control signal ctrl and the first clock ORG_CLK from the outside, and outputs the second clock CLK. When the control signal ctrl is at H level, the second clock CLK has the same waveform as the first clock ORG_CLK. When the control signal ctrl is at L level, the second clock CLK is fixed at L level. Is done.

  The digital signal generation circuit 16 receives the second clock CLK, and outputs the control signal phi (x) to the sensing unit 4 and the control signal sh (x) to the first analog signal output unit 10. When the second clock CLK is the same as the first clock ORG_CLK, the control signals phi (x) and sh (x) have a waveform synchronized with the first clock ORG_CLK. On the other hand, when the second clock CLK is fixed at the L level, the control signals phi (x) and sh (x) are also fixed at the L level.

  The circuit configuration switching circuit 18 receives a control signal set from the outside, and outputs a control signal ana_sel to the switching circuit 11 and a control signal str_sel to the arithmetic circuit 2. When the control signal set is at H level, the control signal ana_sel is at L level and the control signal str_sel is at H level. Conversely, when the control signal set is at the L level, the control signal ana_sel is at the H level and the control signal str_sel is at the L level.

  Next, the operation of the second embodiment of the present invention configured as described above will be described with reference to FIG. First, when the signal of the first analog signal output unit 10 is output, the control signals are controlled to have the relationship shown in the upper part of FIG.

  That is, the control signal ctrl input to the clock generation circuit 13 becomes H level, and the second clock CLK that is the same as the first clock ORG_CLK is output from the clock generation circuit 13. The second clock CLK is input to the digital signal generation circuit 16, the control signal phi (x) synchronized with the second clock CLK from the digital signal generation circuit 16 is sent to the sensing unit 4, and the control signal sh (x) is the first signal. Are output to the analog signal output unit 10. Therefore, in synchronization with the second clock CLK, the sensor signal Vfda is output from the sensing unit 4, and the clock synchronization signal Vsc1 and the reference signal Vsc2 are output from the first analog signal output unit 10.

  Further, the control signal set input to the circuit configuration switching circuit 18 becomes L level, and the circuit configuration switching circuit 18 outputs an H level control signal ana_sel and an L level control signal str_sel. The control signal ana_sel is input to the switching circuit 11, and therefore, the first switch (S1) 41 is turned on (closed), and the second switch (S2) 42 is turned off (open). Therefore, the reference signal Vsc2 is output from the switching circuit 11. The control signal str_sel is input to the feedback switch (S3) 43 (see FIG. 2) of the arithmetic circuit 2, and the feedback switch (S3) 43 is turned off (opened). For this reason, the arithmetic circuit 2 functions as an inverting amplifier circuit.

  That is, as in the first embodiment, the clock synchronization signal Vsc1 is input as the first input signal Vin1 of the arithmetic circuit 2, and the reference signal Vsc2 is input as the second input signal Vin2. Therefore, from the arithmetic circuit 2, the difference (Vin2−Vin1) between the first input signal Vin1 and the second input signal Vin2 is an amplification factor determined by the ratio of the input capacitance (Ci) 44 and the feedback capacitance (Cf) 45. An amplified output signal Vout is output.

  Next, when outputting the signal of the 2nd analog signal output part 12, it controls so that each control signal becomes the relationship shown in the lower stage of FIG. At this time, the control signal ctrl input to the clock generation circuit 13 is at L level, and the second clock CLK that is the output from the clock generation circuit 13 is at L level. Therefore, the control signals phi (x) and sh (x) output from the digital signal generation circuit 16 are also at the L level. For this reason, in synchronization with the second clock CLK, there is no sudden current change that occurs because the transistors in the digital signal generation circuit 16 are turned on / off all at once, and the power supply / GND caused by this sudden current change is eliminated. No change in potential of the (ground) line occurs. That is, the output from the second analog signal output unit 12 is not affected by the potential change of the power supply / GND line generated in synchronization with the second clock CLK.

  Further, the control signal set input to the circuit configuration switching circuit 18 becomes H level, and the circuit configuration switching circuit 18 outputs an L level control signal ana_sel and an H level control signal str_sel. The control signal ana_sel is input to the switching circuit 11, and therefore, the first switch (S1) 41 is turned off (opened) and the second switch (S2) 42 is turned on (closed). Therefore, the clock asynchronous signal Vnsc is output from the switching circuit 11. The control signal str_sel is input to the feedback switch (S3) 43 of the arithmetic circuit 2, and the feedback switch (S3) 43 is turned on (closed). For this reason, the inverting input terminal and the output terminal of the operational amplifier 30 of the arithmetic circuit 2 are short-circuited.

  Therefore, the arithmetic circuit 2 functions as a voltage follower circuit, and the clock asynchronous signal Vnsc is input to the non-inverting input terminal of the operational amplifier 30. Further, by fixing the second clock CLK input to the digital signal generation circuit 16 to the L level and stopping the operation of the digital signal generation circuit 16, the potential fluctuation of the power supply / GND line does not occur. As a result, the second analog signal output unit 12 outputs the clock asynchronous signal Vnsc that is not affected by the potential change of the power supply / GND line, and is directly output as the output signal Vout by the voltage follower circuit.

  As described above, also in the second embodiment, the control signal ana_sel and the control signal str_sel are switched at the same time, the signal input to the arithmetic circuit 2 is changed, and the function of the arithmetic circuit 2 is changed to thereby synchronize with the clock ORG_CLK. One operational amplifier 30 can obtain two different outputs of a signal obtained by calculating and amplifying the difference between the synchronous signal Vsc1 and the reference signal Vsc2 and a signal obtained by calculating and amplifying the clock asynchronous signal Vnsc not synchronized with the clock ORG_CLK. In addition, since the load of the arithmetic circuit 2 is only the load capacity (C1) 140, the band is not limited by the high-frequency cutoff filter.

  In the second embodiment, when the clock asynchronous signal Vnsc is output, the second clock CLK output from the clock generation circuit 13 is fixed to the L level. Therefore, the control signals phi (x) and sh (x) output from the digital signal generation circuit 16 are also fixed to the L level, and the potential change of the power supply / GND line generated in synchronization with the second clock CLK is eliminated. Therefore, the output from the second analog signal output unit 12 is not affected by the potential change of the power supply / GND line generated in synchronization with the second clock CLK.

(Third embodiment)
Next, a signal processing system according to a third embodiment of the present invention will be described with reference to FIGS. FIG. 6 is a block diagram of the sensor IC 1 incorporating the signal processing circuit according to the third embodiment and its peripheral circuits, and FIG. 7 is a diagram showing the relationship between the input / output signals and the control signals in the third embodiment. 8 to 11 are timing charts showing waveforms of signals in the third embodiment. The block diagram shown in FIG. 6 shows a more specific circuit configuration based on the block diagram of FIG. 1 according to the first embodiment.

The sensor IC 1 in the third embodiment includes a clock synchronization circuit 8, a clock asynchronous circuit 9, and an arithmetic circuit 2. The clock synchronization circuit 8 includes a sensing unit 4, a first analog signal output unit 10, and a control circuit 14. The sensing unit 4 includes a CCD (Charge Coupled Device) transfer path 21, a gate unit 22, a PD unit (Photo
It includes a diode (Diode) 23 and an FDA (Floating Diffusion Amplification) circuit 24. The first analog signal output unit 10 includes a CDS (Correlated Double Sampling) circuit 25, a first SH (Sample and Hold) circuit 26, and a second SH circuit 27. The control circuit 14 includes a clock generation circuit 13, a digital signal generation circuit 16, a register circuit 17, and a circuit configuration switching circuit 18.

  The clock asynchronous circuit 9 includes a second analog signal output unit 12 and a switching circuit 11. The second analog signal output 12 includes a temperature detection circuit 15. The switching circuit 11 includes a first switch (S 1) 41, a second switch (S 2) 42, and an inverter 29. The arithmetic circuit 2 includes an operational amplifier 30, a feedback switch (S3) 43, an input capacitor (Ci) 44, and a feedback capacitor (Cf) 45. A microcomputer 6 and an A / D converter 7 are disposed outside the sensor IC 1.

  The microcomputer 6 generates a first clock ORG_CLK, a third clock IO_CLK, and a control signal ADT. The output terminal of the first clock ORG_CLK is connected to the clock generation circuit 13 in the control circuit 14. The output terminal of the third clock IO_CLK is connected to the register circuit 17 in the control circuit 14. The output terminal of the control signal ADT is connected to the A / D converter 7.

  The register circuit 17 in the control circuit 14 receives the third clock IO_CLK and generates a control signal ctrl and a control signal set. The output terminal of the control signal ctrl is connected to the clock generation circuit 13, and the output terminal of the control signal set is connected to the circuit configuration switching circuit 18 and the digital signal generation circuit 16.

  The clock generation circuit 13 generates a second clock CLK based on the first clock ORG_CLK input from the microcomputer 6 and the control signal ctrl input from the register circuit 17 and outputs the second clock CLK to the digital signal generation circuit 16. .

  The digital signal generation circuit 16 generates the control signals phitg, phi1, phi2, phir, shcds, shsc1, shsc2 in synchronization with the second clock CLK according to the control signal set input from the register circuit 17. The output terminal of the control signal phitg generated by the digital signal generation circuit 16 is controlled by the gate unit 22, the output terminals of the control signals phi1 and phi2 are controlled by the CCD transfer path 21, and the output terminal of the control signal phir is controlled by the FDA circuit 24. The output terminal of the signal shcds is connected to the CDS circuit 25, the output terminal of the control signal shsc1 is connected to the first SH circuit 26, and the output terminal of the control signal shsc2 is connected to the second SH circuit 27.

  The PD unit 23 is a one-dimensional or two-dimensional photodiode array composed of a plurality of photoelectric conversion elements that photoelectrically convert an image such as a subject image, and generates a signal charge corresponding to the amount of incident light. The gate unit 22 sends the signal charge generated in the PD unit 23 to the CCD transfer path 21 in synchronization with the control signal phitg. The CCD transfer path 21 sequentially transfers the signal charges sent through the gate unit 22 in synchronization with the control signals phi1 and phi2. The FDA circuit 24 converts the signal charge transferred from the CCD transfer path 21 into a signal voltage in synchronization with the control signal phir, and outputs a sensor signal Vfda as an output of the sensing unit 4.

  An input terminal of the CDS circuit 25 is an input terminal of the first analog signal output unit 10 and receives the sensor signal Vfda output from the sensing unit 4. The CDS circuit 25 performs noise removal and operational amplification on the input sensor signal Vfda in synchronization with the control signal shcds, and outputs the signal as a pixel signal Vcds. The output terminal of the CDS circuit 25 is connected to the first SH circuit 26 and the second SH circuit 27. The first SH circuit 26 samples and holds the pixel signal Vfda in accordance with the control signal shsc1, and outputs a clock synchronization signal Vsc1. Similarly, the second SH circuit 27 samples and holds the pixel signal Vfda in accordance with the control signal shsc2, and outputs the reference signal Vsc2.

  The temperature detection circuit 15 is a circuit that outputs a signal corresponding to the environmental temperature of the sensor IC 1, and outputs the clock asynchronous signal Vnsc regardless of the presence or absence of the first clock ORG_CLK and the third clock IO_CLK output from the microcomputer 6. Output.

  The reference signal Vsc2 is input to one end of the first switch (S1) 41, and the clock asynchronous signal Vnsc is input to one end of the second switch (S2). The other end of the first switch (S1) 41 and the other end of the second switch (S2) 42 are connected to each other, and a signal output from this connection end is input to the arithmetic circuit 2 as the second input signal Vin2. The The control terminal of the first switch (S 1) 41 is connected to the output terminal of the control signal ana_sel of the circuit configuration switching circuit 18, and the control terminal of the second switch (S 2) 42 is controlled via the inverter 29. It is connected to the output terminal of the signal ana_sel. Therefore, when the control signal ana_sel is at the H level, the first switch (S1) 41 is turned on (closed) and the second switch (S2) 42 is turned off (open), while the control signal ana_sel is at the L level. In this case, the first switch (S1) 41 is turned off (opened), and the second switch (S2) 42 is turned on (closed).

  In the arithmetic circuit 2, the clock synchronization signal Vsc1 output from the first analog signal output unit 10 is input as the first input signal Vin1, and the signal output from the switching circuit 11 is input as the second input signal Vin2. The A control signal str_sel is input from the circuit configuration switching circuit 18. The output terminal of the arithmetic circuit 2 is connected to the A / D converter 7 as an output terminal of the output signal Vout of the sensor IC1. Here, the A / D converter 7 corresponds to the load capacity (C1) 140 shown in the first and second embodiments. Since the arithmetic circuit 2 is the same as the configuration described with reference to FIG. 2 in the first embodiment, a detailed description thereof is omitted. The A / D converter 7 receives the output signal Vout of the sensor IC 1 and the control signal ADT from the microcomputer 6. The A / D converter 7 A / D converts the output signal Vout in synchronization with the control signal ADT.

  Next, the operation of the third embodiment of the present invention will be described with reference to FIGS. When the clock asynchronous signal Vnsc is output, that is, when the signal from the second analog signal output unit 12 is output, the control signals are controlled so as to have the relationship shown in the lower part of FIG. Since this state is the same as in the case of the second embodiment, the detailed description is omitted, but the arithmetic circuit 2 switches to the circuit configuration of the voltage follower circuit, and the second switch (S2) of the switching circuit 11 42 is turned on (closed), and the first switch (S1) 41 is turned off (open). Therefore, the output of the temperature detection circuit 15 in the second analog signal output unit 12 is output as the output signal Vout via the arithmetic circuit 2 that functions as a voltage follower circuit.

  Next, when a signal synchronized with the first clock ORG_CLK is output, that is, when a signal from the first analog signal output unit 10 is output, the control signals have the relationship shown in the upper part of FIG. To control. In this state, as in the case of the second embodiment, the arithmetic circuit 2 is switched to the circuit configuration of the inverting amplifier circuit, and the first switch (S1) 41 of the switching circuit 11 is turned on (closed). The switch (S2) 42 is turned off (opened). Therefore, the difference between the clock synchronization signal Vsc1 output from the first analog signal output unit 10 and the reference signal Vsc2 is amplified with an amplification factor determined by the ratio of the input capacitance (Ci) 44 and the feedback capacitance (Cf) 45, and the output signal Output as Vout.

  Hereinafter, the relationship between each control signal and each input / output signal will be described in detail with reference to timing charts shown in FIGS. FIG. 8 is a timing chart showing the state of each signal during accumulation and pixel readout, and FIGS. 9 to 11 are timing charts showing details during pixel readout. In FIG. 8, a clock asynchronous signal Vnsc that is a temperature output is output in the accumulation mode, and a signal obtained by calculating and amplifying the difference between the clock synchronization signal Vsc1 that is a pixel output and the reference signal Vsc2 is output in the pixel readout mode. ing. While the clock asynchronous signal Vnsc is being output, a control signal output at a specific timing is not required, and thus detailed description thereof is omitted. Hereinafter, the operation when the signal from the clock synchronization circuit 8 is output will be described in detail with reference to FIGS. 9 to 11.

  The PD unit 23 generates a signal charge corresponding to the amount of incident light by the photoelectric effect. The signal charges generated in the PD unit 23 are accumulated in the PD unit 23 while the control signal phitg is at the L level. When the control signal phitg is at the H level, the signal charges pass through the gate unit 22 as signal charges of each pixel. It is moved to the CCD transfer path 21.

  The CCD transfer path 21 sequentially transfers signal charges in accordance with the control signal phi 1 and the control signal phi 2 and inputs them to the FDA circuit 24. The FDA circuit 24 converts the signal charge transferred from the CCD transfer path 21 by the control signal phir into a signal voltage for each pixel or any number of pixels, and outputs it as a sensor signal Vfda (x).

The sensor signal Vfda (x) is formed by the charge transfer by the control signals phi1 and phi2 and the reset operation of the FDA circuit 24 by the control signal phir. Therefore, the sensor signal Vfda (x) is divided into three output periods, and these periods are referred to as a reset period t _R , a zero level period t ₀ , and a signal period t _S (see FIG. 9). Reset period t _R, the control signal phir is at the H level, the signal charge in the FDA circuit 24 in this period is returned to a certain value by charging and discharging. For this reason, the reset level Vr (x), which is a constant signal voltage, is output during the reset period.

Next, when the control signal phir changes from the H level to the L level, the FDA circuit 24 outputs a voltage different from the reset level Vr (x) due to the feedthrough component in the FDA circuit 24. A period until the control signal phir changes from the H level to the L level and then the control signal phi1 and the control signal phi2 change is defined as a zero level period t _0, and the signal voltage in this period is defined as a feedthrough level Vf (x). To do.

The third period, the signal period t _S , refers to the period after the zero level period t ₀ until the control signal phir becomes H level again, and the signal voltage during this period is defined as the signal level Vs (x). . This signal level Vs (x) is generated by the PD unit 23 and varies depending on the amount of charge transferred by the CCD transfer path 21. In FIG. 9, every time the control signal phi1 and the control signal phi2 change once, the control signal phir is set to the H level, and the signal level Vs (x) for each pixel is output.

  During the period when the control signal shcds is at the H level, the CDS circuit 25 holds the voltage of the input sensor signal Vfda (x) in the circuit. Thereafter, when the control signal shcds becomes L level, the CDS circuit 25 calculates and amplifies the difference between the voltage held in the circuit and the input sensor signal Vfda (x), and outputs it as a pixel signal Vcds (x). To do.

That is, the control signal shcds becomes H level during the zero level period t ₀ of the sensor signal Vfda (x), and the CDS circuit 25 holds the feedthrough level Vf (x) in the circuit. When the control signal shcds becomes L level, the CDS circuit 25 calculates and amplifies the difference between the feedthrough level Vf (x) held in the circuit and the input signal level Vs (x), and the pixel signal Vcds ( x) is output. A period during which the pixel signal Vcds (x) is output is referred to as a CDS calculation output period t _CDS (see FIG. 10). In FIG. 10, the waveform is described on the assumption that the CDS circuit 25 operates as an inverting amplifier circuit having an amplification factor Av1. The characteristic of the CDS circuit 25 is shown in the following formula 1.
Vcds (x) = − Av1 × (Vf (x) −Vs (x)) Equation 1

The first SH circuit 26 and the second SH circuit 27 are sample-and-hold circuits in which the control signal shsc1 and the control signal shsc2 are in the sample state at the H level and in the hold state at the L level. The first SH circuit 26 is controlled by the control signal shsc1, and the second SH circuit 27 is controlled by the control signal shsc2, and the pixel signal Vcds (x) is sampled during a period when each control signal is at the H level. Then, while the control signal shsc1 and the control signal shsc2 are at the L level, the first SH circuit 26 and the second SH circuit 27 continue to hold the sampled signal voltages. That is, the control signal shsc1 becomes H level during CDS calculation output period t _CDS for each pixel, the control signal shsc2 becomes H level during CDS calculation output period t _CDS particular pixel.

Therefore, the first SH circuit 26 outputs a clock synchronization signal Vsc1 (x) that is a signal for each pixel, and the second SH circuit 27 outputs a reference signal Vsc2 (y) as a reference. The period during which the first SH circuit 26 holds the voltage is referred to as a first hold period t _SH1, and the period during which the second SH circuit 27 holds the voltage is referred to as a second hold period t _SH2. I will do it.

  When the control signal ana_sel is at the H level, the first switch (S1) 41 and the second switch (S2) 42 are turned on (closed) while the second switch ( S2) 42 is turned off (opened), and when the control signal ana_sel is at L level, the first switch (S1) 41 is turned off (opened), and the second switch (S2) 42 is turned on (closed). become. The feedback switch (S3) 43 in the arithmetic circuit 2 is turned on (closed) when the control signal str_sel is at the H level, and turned off (opened) when the control signal str_sel is at the L level.

In the timing chart shown in FIG. 8, since the control signal ana_sel is at the H level and the control signal str_sel is at the L level when the operation mode is the pixel readout timing, the first switch (S1) 41 is turned on ( Closed), the second switch (S2) 42 is turned off (opened), and the feedback switch (S3) 43 is turned off (opened). Therefore, the arithmetic circuit 2 functions as an inverting amplifier circuit. At this time, the clock synchronization signal Vsc1 (x) held in the first SH circuit 26 is input as the first input signal Vin1, and the second input signal Vin2 is input. The reference signal Vsc2 (y) held in the second SH circuit 27 is input. Therefore, the arithmetic circuit 2 outputs an output signal obtained by amplifying the difference between the clock synchronization signal Vsc1 (x) and the reference signal Vsc2 (y) with an amplification factor Av2 determined by the ratio of the input capacitance (Ci) 44 and the feedback capacitance (Cf) 45. Vout (x) is output. The characteristic when the arithmetic circuit 2 functions as an inverting amplifier circuit is shown in the following formula 2.
Vout (x) = − Av2 × (Vsc2 (y) −Vsc1 (x)) Equation 2

That is, when the control signal str_sel changes from the H level to the L level, the arithmetic circuit 2 changes its function to an inverting amplifier circuit, and the clock synchronization signal Vsc1 (x) held in the first SH circuit 26 and the second An output signal Vout (x) obtained by amplifying the difference of the reference signal Vsc2 (y) held in the SH circuit 27 with an amplification factor Av2 determined by the ratio of the input capacitance (Ci) 44 and the feedback capacitance (Cf) 45 is output. In the output signal Vout (x), a period effective as an output is the same period as the first hold period t _SH1 (see FIG. 11), and this period is referred to as an effective output voltage period t _SIG. .

As described above, when the arithmetic circuit 2 functions as an inverting amplifier circuit, the output signal Vout (x) having periodicity is output in synchronization with the first clock ORG_CLK input from the outside. In the figure, x in Vr (x), Vf (x), Vs (x), Vfda (x), Vcds (x), Vsc1 (x), and Vout (x) indicates a pixel number. 9 to 11, x = 0 to 7. Further, y in Vsc2 (y) indicates another pixel number, and y = 0 in FIG. For example, in the case where the PD unit 23 is composed of two types of photodiode arrays, which are covered with an aluminum wiring layer and shielded from light and a non-shielded aperture pixel, the control signal shsc2 is output to the CDS calculation output period t of the light-shielded pixel. _The H level is set during _CDS , and the control signal shsc1 is set to H level during the CDS calculation output period t _CDS of each aperture pixel. As a result, the output signal from the light-shielded pixel becomes the reference signal Vsc2 (y), the output signal from the aperture pixel becomes the clock synchronization signal Vsc1 (x), and the difference is calculated and amplified to become the output signal Vout (x).

  Thus, in each embodiment of the present invention, switching is performed exclusively by opening and closing the first switch (S1) 41 and the second switch (S2) 42 connected to the non-inverting input terminal of the operational amplifier 30. The function of the arithmetic circuit 2 is changed by opening and closing the feedback switch (S3) 43 provided in the feedback section of the operational amplifier 30 in synchronization with this change. As a result, it is possible to obtain different outputs with one operational amplifier 30, and a high-frequency cutoff filter is not formed in the load of the arithmetic circuit 2, and the signal pass band is not limited. Further, when outputting an analog signal asynchronous to the clock ORG_CLK, the second clock CLK input to the digital signal generation circuit 16 is fixed to the L level. Therefore, noise generated in synchronization with the second clock CLK during the output of the clock asynchronous signal Vnsc can be reduced. Further, since the control signal set and the control signal ctrl output from the register circuit 17 are controlled by the third clock IO_CLK, the state of the control signal set is maintained. Therefore, even if the control signal ctrl is set to the L level and the operation of the digital signal generation circuit 16 is temporarily interrupted, the control signal ctrl is set to the H level and the operation is started again. 16 can be operated.

  In describing each embodiment of the present invention, the switching circuit 11 switches between the first analog signal and the second analog signal. However, the present invention is not limited to this, and three or more analog signals are switched. But of course it does n’t matter.

  As described above, the first to third embodiments of the present invention have been described. However, the present invention is not limited to the above-described embodiments as they are, and constituent elements are included in the implementation stage without departing from the scope of the invention. It can be transformed and embodied. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, you may delete some components of all the components shown by embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

It is a block diagram which shows the structure of the sensor IC incorporating the signal processing system concerning 1st Embodiment of this invention. It is a block diagram of the arithmetic circuit in sensor IC incorporating the signal processing system concerning 1st Embodiment of this invention. It is a figure which shows the relationship between the input / output signal of a sensor IC incorporating the signal processing system concerning 1st Embodiment of this invention, and each control signal. It is a block diagram which shows the structure of the sensor IC incorporating the signal processing system concerning 2nd Embodiment of this invention. It is a figure which shows the relationship between the input / output signal of a sensor IC incorporating the signal processing system concerning 2nd Embodiment of this invention, and each control signal. It is a block diagram which shows the structure of the sensor IC incorporating the signal processing system concerning 3rd Embodiment of this invention, and its peripheral device. It is a figure which shows the relationship between the input / output signal of a sensor IC incorporating the signal processing system concerning 3rd Embodiment of this invention, and each control signal. It is a timing chart which shows the relationship of the input-output waveform of each signal of the signal processing system concerning 3rd Embodiment of this invention. It is a timing chart which shows the relationship of the input-output waveform of each signal of the signal processing system concerning 3rd Embodiment of this invention. It is a timing chart which shows the relationship of the input-output waveform of each signal of the signal processing system concerning 3rd Embodiment of this invention. It is a timing chart which shows the relationship of the input-output waveform of each signal of the signal processing system concerning 3rd Embodiment of this invention. It is a block diagram which shows the structure of the circuit of the conventional signal processing system.

Explanation of symbols

1 ... Sensor IC
2 ... arithmetic circuit 4 ... sensing unit 6 ... microcomputer 7 ... A / D converter 10 ... first analog signal output unit 11 ... switching circuit 12 ... second Analog signal output unit 13 ... clock generation circuit 14 ... control circuit 15 ... temperature detection circuit 16 ... digital signal generation circuit 17 ... register circuit 18 ... circuit configuration switching circuit 21 ... CCD transfer path 22... Gate part 23... PD part 24... FDA circuit 25... CDS circuit 26... First SH circuit 27. 30... Operational amplifier 41... First switch (S1)
42 ... second switch (S2)
43 ... Feedback switch (S3)
44 ... Input capacity (Ci)
45 ... Return capacity (Cf)
DESCRIPTION OF SYMBOLS 100 ... Clock synchronization circuit 104 ... Sensing part 110 ... 1st analog signal output circuit 112 ... 2nd analog signal output circuit 114 ... Control circuit 119 ... 1st arithmetic circuit 120 ... clock asynchronous circuit 121 ... second arithmetic circuit 130 ... switching circuit 131 ... inverter 132 ... switch (SW1)
133... Switch (SW2)
140: Load capacity (C1)
1000 ... sensor IC

Claims (8)

A first analog signal output unit for outputting a first analog signal synchronized with a clock;
A second analog signal output unit that outputs a second analog signal not synchronized with the clock;
A calculation unit that performs a predetermined calculation on an input signal and outputs the calculated signal;
A control unit that changes the input to the calculation unit to the first analog signal or the second analog signal, and changes the function of the calculation unit in synchronization with the change,
A signal processing system comprising: The arithmetic unit includes an operational amplifier, a first capacitor, a second capacitor, a first switch, a second switch, and a third switch,
The first capacitor is connected between an inverting input terminal of the operational amplifier and a first output terminal of the first analog signal output unit,
The first switch is connected between a non-inverting input terminal of the operational amplifier and a second output terminal of the first analog signal output unit,
The second switch is connected between a non-inverting input terminal of the operational amplifier and an output terminal of the second analog signal output unit,
The second capacitor and the third switch are connected in parallel between an inverting input terminal and an output terminal of the operational amplifier,
2. The signal processing according to claim 1, wherein the control unit controls the first switch and the second switch in synchronization with a function change of the arithmetic unit caused by opening and closing of the third switch. system.   The control unit stops supply of a clock to the first analog signal output unit while the arithmetic unit outputs a signal related to the second analog signal output unit. The signal processing system according to claim 2.   4. The signal processing according to claim 1, wherein the first analog signal output unit is a CCD sensor circuit, and the second analog signal output unit is a temperature detection circuit. 5. system. A first analog signal output unit for outputting a first analog signal synchronized with a clock;
A second analog signal output unit that outputs a second analog signal not synchronized with the clock;
A switching unit that is connected to output terminals of the first analog signal output unit and the second analog signal output unit, and selectively switches and outputs either the first analog signal or the second analog signal. When,
An arithmetic unit to which either the first analog signal or the second analog signal selected by the switching unit is input;
Have
The signal processing system, wherein the arithmetic unit changes a function according to the selection in the switching unit.   The arithmetic unit functions as an inverting amplifier circuit when inputting the first analog signal, and functions as a voltage follower circuit when inputting the second analog signal. The signal processing system according to claim 5.   The arithmetic unit is composed of an operational amplifier and a passive element, an input capacitor is connected between the inverting input terminal of the operational amplifier and the switching unit, and between the inverting input terminal and the output terminal of the operational amplifier. 6. The signal processing system according to claim 5, wherein a switch and a feedback capacitor are connected in parallel, and the function of the arithmetic unit is changed by switching the switch.   The signal processing system according to claim 5, wherein the clock is stopped when the second analog signal is output.