JP6673310B2 - Imaging device and imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device and an electronic camera using the same.

  FIG. 3 of Patent Document 1 below discloses the configuration of the “CDS circuit 3a” for one column for the “pixel unit 20”.

  The “CDS circuit 3a” is provided with a “sample and hold switch sw1” that controls the input of an image signal output from the “pixel unit 20”. An output side of the “sample and hold switch sw1” is connected to a “capacitor (sample and hold capacitor) C31” for holding an image signal. On the opposite side of the “capacitor C31” from the “sample and hold switch sw1”, a “ramp signal supply source 31a” that supplies a ramp signal for changing the potential of the image signal held in the “capacitor C31” is connected. .

  The “connection point (node) n1” between the “sample and hold switch sw1” and the “capacitor C31” is connected to the non-inverting input terminal of the “differential amplifier 33a”. Further, a “capacitor C32” is provided between the inverting input terminal and GND. A “clamp switch sw2” is provided between the output terminal of the “differential amplifier 33a” and the “connection point n2” between the inverting input terminal and the “capacitor C32”.

JP 2008-11284 A

  When the conventional “CDS circuit 3a” is provided for each column of the “pixel unit 20”, one “lamp signal supply source 31a” is provided in common for the “CDS circuit 3a” of each column, and A ramp signal input section of the "capacitor C31" of the "CDS circuit 3a" in the column is commonly connected by a first wiring, and a "lamp signal supply source 31a" is connected on one side of the first wiring. The GND voltage input section (one electrode) of the “capacitor C32” of the “CDS circuit 3a” is commonly connected by a second wiring, and a GND voltage as a reference voltage is supplied to the second wiring. At this time, according to the technical common sense of the GND voltage supply method in the electric circuit design for improving the noise resistance, both sides of the second wiring are respectively supplied in order to supply the GND voltage to as many places as possible of the second wiring. It will be grounded. If both sides of the second wiring are grounded, noise on the second wiring due to disturbance or the like is reduced as compared with the case where the GND voltage is supplied to only one location of the second wiring. The noise resistance of the wiring is increased.

  However, as a result of the research by the present inventors, in this case, increasing the noise resistance of the second wiring may, on the contrary, cause an increase in the influence of noise appearing in an image obtained after processing. There was found. This point will be described later in detail in a description of a comparative example to be compared with the present invention.

  The present invention has been made in view of such circumstances, and provides a solid-state imaging device capable of reducing the influence of noise and obtaining a higher-quality image, and an electronic camera using the same. The purpose is to do.

  The following aspects are presented as means for solving the above problems. A solid-state imaging device according to a first aspect includes a plurality of pixels arranged two-dimensionally, a plurality of vertical signal lines provided for each column of the plurality of pixels, receiving signals from pixels in a corresponding column, and a lamp. A plurality of signal processing units that respectively process the signals of the plurality of vertical signal lines based on signals and a reference voltage, and a first input unit to which the ramp signal is input in the plurality of signal processing units are commonly connected. A first line to which the ramp signal is supplied on one side in the row direction, and a second input unit to which the reference voltage is input in the plurality of signal processing units, are commonly connected to each other; A second wiring to which the reference voltage is supplied on one side and the reference voltage is not supplied on the other side in the row direction.

  In the solid-state imaging device according to a second aspect, in the first aspect, each of the signal processing units includes a comparator that performs a comparison process based on the ramp signal and the reference voltage.

  In the solid-state imaging device according to a third aspect, in the second aspect, the comparator is configured by an operational amplifier, and each of the signal processing units is connected to a non-inverting input terminal of the comparator and is connected to a signal of the vertical signal line or A sampling switch for sampling a signal corresponding thereto, a first capacitor having one electrode connected to the non-inverting input terminal and the other electrode serving as the first input portion, and one electrode connected to the inverting terminal of the comparator. A second capacitor connected to the input terminal and having the other electrode serving as the second input unit, and a feedback switch for turning on and off between the inverting input terminal and the output terminal of the comparator. .

  The solid-state imaging device according to a fourth aspect is the solid-state imaging device according to the third aspect, wherein (i) when the signals of the plurality of vertical signal lines are reference signals, the sampling switch and the feedback switch of each of the signal processing units are once set. During a first period in which the plurality of vertical signal lines are simultaneously turned on and then simultaneously turned off, the ramp signal changes gradually. (Ii) After the first period, the signals of the plurality of vertical signal lines are output from the plurality of pixels. In the case of an optical signal containing optical information photoelectrically converted by at least one of the pixels, the sampling switch of each signal processing unit is once turned on while the feedback switch of each signal processing unit is kept off. The ramp signal gradually changes during a second period that has been turned off after being performed, and (iii) from the start of the change of the ramp signal during the first period. A count value corresponding to an elapsed time until a signal inversion of the output unit of the comparator of each signal processing unit during the first period; and a count value from a change start time of the ramp signal during the second period. A time counting unit that obtains a count value corresponding to an elapsed time until a signal inversion of the output unit of the comparator in each of the signal processing units during the period 2.

  In the solid-state imaging device according to a fifth aspect, in the fourth aspect, the clock unit counts a clock signal from a time point at which the ramp signal starts to change in the first period, and the ramp unit in the second period. A counter that counts a clock signal from the start of signal change; and a counter provided in each of the signal processing units, the count value of the counter being input, and the inversion of the signal of the output unit of the comparator in the first period. And a storage unit for storing the count value at the time of the inversion of the signal of the output unit of the comparator during the second period.

  The solid-state imaging device according to a sixth aspect is the solid-state imaging device according to the third aspect, wherein (i) when the signals of the plurality of vertical signal lines are reference signals, the sampling switch and the feedback switch of each of the signal processing units are once set. During a first period in which the plurality of vertical signal lines are simultaneously turned on and then simultaneously turned off, the ramp signal changes gradually. (Ii) After the first period, the signals of the plurality of vertical signal lines are output from the plurality of pixels. In the case of an optical signal containing optical information photoelectrically converted by at least one of the pixels, the sampling switch of each signal processing unit is once turned on while the feedback switch of each signal processing unit is kept off. The ramp signal gradually changes during a second period that is turned off after being performed, and (iii) each of the signal processing units determines whether or not the ramp signal has been changed during the first period. A count value is obtained by performing a count operation in one of a down mode and an up mode from a time point at which the conversion starts to a time point at which the output signal of the comparator of each signal processing unit inverts in the first period. The other of the down mode and the up mode is performed from the time when the ramp signal starts changing in the second period to the time when the signal output from the comparator of each signal processing unit is inverted in the second period. A counter for performing a counting operation from the count value in the mode.

  The solid-state imaging device according to a seventh aspect is the solid-state imaging device according to any one of the third to sixth aspects, wherein each of the signal processing units includes an amplification unit provided between the vertical signal line and the sampling switch. It is.

  In the solid-state imaging device according to an eighth aspect, in the seventh aspect, the amplifying unit may include a second operational amplifier, an input capacitance connected to an inverting input terminal of the second operational amplifier, and the second operational amplifier. A second feedback switch for turning on and off between the inverting input terminal of the operational amplifier and the output terminal of the second operational amplifier; and a second feedback switch for connecting the inverting input terminal of the second operational amplifier to the second operational amplifier. And a feedback capacitor connected between the output terminal and the output terminal.

An electronic camera according to a ninth aspect includes the solid-state imaging device according to any one of the first to eighth aspects.
The following aspects are also presented as means for solving the above problems. An imaging device having a first surface, a first signal processing unit having a first comparator for converting a first signal including a signal generated by the photoelectrically converted charge into a digital signal, and the first signal processing unit And a second signal processing unit having a second comparator for converting a second signal including a signal generated by the photoelectrically converted electric charge into a digital signal, the first signal processing unit and the second signal processing unit . A first contact portion for connecting to the first comparator, wherein the first contact portion is connected to a ramp signal generation circuit for generating a ramp signal , and is disposed outside the region where the two signal processing portions are disposed; a first wiring and a second contact portion for connection with a comparator, and the first signal processing unit and the second signal processing unit is arranged outside the region arranged, a predetermined voltage is supplied A second wiring having a third contact portion for connecting to the first comparator and a fourth contact portion for connecting to the second comparator, the second wire being connected to an electrode pad; In one wiring, the length of the wiring from the ramp signal generation circuit to the first contact portion is shorter than the length of the wiring from the ramp signal generation circuit to the second contact portion, and in the second wiring, The length of the wiring from the electrode pad to the third contact portion is shorter than the length of the wiring from the electrode pad to the fourth contact portion.
An image sensor according to a second surface is connected to the first signal processing unit on the first surface, is connected to a first signal line from which the first signal is output, and is connected to the second signal processing unit, And a second signal line from which the second signal is output.
The image sensor according to the third aspect is connected to the first signal line on the second aspect, and transfers a first photoelectric conversion unit that converts light into an electric charge and the electric charge converted by the first photoelectric conversion unit. A first pixel having a first transfer unit for transferring light, a second photoelectric conversion unit connected to the second signal line for converting light into electric charge, and transferring the electric charge converted by the second photoelectric conversion unit. And a control signal for controlling the first transfer unit and the second transfer unit connected to the first transfer unit and the second transfer unit. Control lines.
An imaging device according to a fourth aspect, wherein the second surface is connected to the first signal line, the first photoelectric conversion unit converts light into electric charge, the second photoelectric conversion unit converts light into electric charge, and A first transfer unit for transferring the charge converted by the first photoelectric conversion unit, a second transfer unit for transferring the charge converted by the second photoelectric conversion unit, and a charge from the first photoelectric conversion unit A first pixel block having a first floating diffusion for transferring charges from the second photoelectric conversion unit and a third photoelectric conversion unit connected to the second signal line for converting light into charges; To a charge, a third transfer unit for transferring the charge converted by the third photoelectric conversion unit, and a fourth transfer unit for transferring the charge converted by the fourth photoelectric conversion unit. A transfer unit and charges from the third photoelectric conversion unit and the fourth photoelectric conversion A second pixel block having a second floating diffusion for transferring charges from the first transfer unit and the third transfer unit, and controlling the first transfer unit and the third transfer unit. A first control line for outputting a control signal for the second transfer unit and the fourth transfer unit, and a control signal for controlling the second transfer unit and the fourth transfer unit is output. And a second control line.
In the imaging device according to a fifth aspect, in any one of the first to fourth aspects, the first comparator is configured by an operational amplifier, and the second comparator is configured by an operational amplifier.
In the imaging device according to the sixth aspect, in any one of the first to fifth aspects, the electrode pad is connected to a terminal arranged outside by a wire.
An imaging device according to a seventh aspect connects an imaging element according to any one of the first to fifth aspects, a package accommodating the imaging element, and the electrode pads and terminals arranged on the package. And a connection unit for the connection.
In the imaging device according to an eighth aspect, in the seventh aspect, the connection portion includes a wire that connects the electrode pad and the terminal.

  According to the present invention, it is possible to provide a solid-state imaging device capable of reducing the influence of noise and obtaining a higher-quality image, and an electronic camera using the same.

FIG. 1 is a schematic block diagram schematically illustrating an electronic camera according to a first embodiment of the present invention. FIG. 2 is a circuit diagram illustrating a schematic configuration of the solid-state imaging device in FIG. 1. FIG. 3 is a circuit diagram illustrating a pixel in FIG. 2. FIG. 9 is a circuit diagram illustrating a pixel according to a modification. 2 is a timing chart illustrating an example of an operation of the solid-state imaging device in FIG. 1. 6 is a timing chart showing an operation in a predetermined period in FIG. FIG. 3 is a schematic plan view schematically showing a specific example of a wiring pattern and the like constituting first and second wirings in FIG. 2. FIG. 2 is a schematic plan view schematically illustrating the solid-state imaging device in FIG. 1. FIG. 9 is a circuit diagram illustrating a schematic configuration of a solid-state imaging device according to a comparative example. FIG. 10 is a schematic plan view schematically illustrating wiring patterns and the like constituting first and second wirings in FIG. 9. FIG. 10 is a schematic plan view schematically showing the solid-state imaging device according to the comparative example shown in FIG. 9. FIG. 11 is a schematic plan view schematically showing a solid-state imaging device according to a modification. FIG. 9 is a circuit diagram illustrating a schematic configuration of a solid-state imaging device used in an electronic camera according to a second embodiment of the present invention.

  Hereinafter, a solid-state imaging device and an electronic camera according to the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a schematic block diagram schematically showing an electronic camera 1 according to the first embodiment of the present invention.

  Although the electronic camera 1 according to the present embodiment is configured as, for example, a single-lens reflex digital camera, the electronic camera according to the present invention is not limited to this, and is mounted on another electronic camera such as a compact camera or a mobile phone. It can also be applied to electronic cameras and the like.

  A photographing lens 2 is attached to the electronic camera 1. The focus and the aperture of the photographing lens 2 are driven by the lens control unit 3. In the image space of the photographing lens 2, an imaging surface of the solid-state imaging device 4 is arranged.

  The solid-state imaging device 4 is driven by a command from the imaging control unit 5 and outputs a digital image signal. The digital signal processing unit 6 performs image processing such as digital amplification, color interpolation processing, and white balance processing on a digital image signal output from the solid-state imaging device 4. The image signal processed by the digital signal processing unit 6 is temporarily stored in the memory 7. The memory 7 is connected to the bus 8. Also connected to the bus 8 are a lens control unit 3, an imaging control unit 5, a CPU 9, a display unit 10 such as a liquid crystal display panel, a recording unit 11, an image compression unit 12, an image processing unit 13, and the like. An operation unit 14 such as a release button is connected to the CPU 9. A recording medium 11a is detachably mounted on the recording unit 11.

  In the present embodiment, when a half-press operation of the release button of the operation unit 14 is performed, the CPU 9 in the electronic camera 1 calculates a defocus amount based on a detection signal from a focus detection sensor (not shown). The lens control unit 3 adjusts the photographing lens 2 so as to be in focus according to the focus amount. Further, the CPU 9 causes the lens control unit 3 to adjust the taking lens 2 so that the aperture is instructed in advance by the operation unit 14. Then, a digital image signal is read from the solid-state imaging device 4 by the CPU 9 controlling the solid-state imaging device 4 via the imaging control unit 5 in synchronization with a full-press operation of the release button of the operation unit 14. This image signal is temporarily stored in the memory 7 after being processed by the digital signal processing unit 6. After that, the CPU 9 performs desired processing on the image signal in the memory 7 as required by the image processing unit 13 and the image compression unit 12 based on a command from the operation unit 14, and sends the processed signal to the recording unit 11. A signal is output and recorded on the recording medium 11a.

  FIG. 2 is a circuit diagram showing a schematic configuration of the solid-state imaging device 4 in FIG. In the present embodiment, the solid-state imaging device 4 is configured as a CMOS type solid-state imaging device, but may be configured as another XY address type solid-state imaging device.

  As shown in FIG. 2, the solid-state imaging device 4 includes a pixel array unit 22 including a plurality of pixels 21 (in FIG. 2, 2 × 3 pixels 2 are shown) arranged two-dimensionally, and a plurality of pixels 21. A plurality of vertical signal lines 23 provided for each column of the pixels 21 for receiving signals from the pixels 21 of the corresponding column; a constant current source 24 provided for each vertical signal line 23; a vertical scanning circuit 25; A plurality of column circuits (signal processing units) 26 for respectively processing the signals of the plurality of vertical signal lines 23 based on Vramp and the reference voltage GND; a ramp signal generation circuit 27 for generating a ramp signal Vramp; a counter 28; A pulse generation circuit 29, a horizontal scanning circuit 30, a subtracter 31, and an output circuit 32 are provided.

  FIG. 3 is a circuit diagram showing one pixel 21 in FIG. Each pixel 21 includes, as in a general CMOS image sensor, a photodiode PD as a photoelectric conversion unit that generates and accumulates an electric charge according to incident light, and a charge voltage that receives the electric charge and converts the electric charge into a voltage. A floating diffusion FD as a conversion unit, an amplification transistor AMP as an amplification unit that outputs a signal corresponding to the potential of the floating diffusion FD, a transfer transistor TX that transfers electric charges from the photodiode PD to the floating diffusion FD, and a floating diffusion FD And a selection transistor SEL for selecting a read row, and are connected as shown in FIG. In FIG. 3, VDD is a power supply potential. Note that, in the present embodiment, the transistors AMP, TX, RES, and SEL of the pixel 21 are all nMOS transistors.

  The gate of the transfer transistor TX is commonly connected to a control line 41 for each row, and a control signal φTX for controlling the transfer transistor TX is supplied thereto from the vertical scanning circuit 25. The gate of the reset transistor RES is commonly connected to a control line 42 for each row, and a control signal φRES for controlling the reset transistor RES is supplied thereto from the vertical scanning circuit 25. The gate of the selection transistor SEL is commonly connected to a control line 43 for each row, and a control signal φSEL for controlling the selection transistor SEL is supplied thereto from the vertical scanning circuit 25. When discriminating each control signal φTX for each row, the control signal φTX in the n-th row is indicated by a symbol φTX (n). This is the same for the control signals φRES and φSEL.

  The photodiode PD of each pixel 21 generates a signal charge according to the amount of incident light (subject light). The transfer transistor TX turns on during the high level period of the control signal φTX, and transfers the charge of the photodiode PD to the floating diffusion FD. The reset transistor RES is turned on during a high level period (period of the power supply potential VDD) of the control signal φRES, and resets the floating diffusion FD.

  The amplification transistor AMP has a drain connected to the power supply potential VDD, a gate connected to the floating diffusion FD, a source connected to the drain of the selection transistor SEL, and a constant current source 24 (not shown in FIG. 2) as a load. The amplification transistor AMP outputs a read signal to the vertical signal line 23 via the selection transistor SEL according to the voltage value of the floating diffusion FD. The selection transistor SEL is turned on during the high level period of the control signal φSEL, and connects the source of the amplification transistor AMP to the vertical signal line 23.

  The vertical scanning circuit 25 outputs control signals φSEL, φRES, and φTX for each row of the pixels 21 to perform well-known control of the row address of the pixel array unit 22 and vertical scanning. By this control, the output signal (analog signal) of the pixel 2 in the corresponding column is supplied to each vertical signal line 23.

  The configuration of the pixel 21 is not limited to the configuration shown in FIG. For example, the configuration shown in FIG. 4 may be adopted as the configuration of the pixel 21. FIG. 4 is a circuit diagram showing a pixel 21 according to a modification. 4, elements that are the same as elements corresponding to those in FIG. 3 or that correspond to elements in FIG.

  The configuration shown in FIG. 4 differs from the configuration shown in FIG. 3 in that, for every two pixels 21 adjacent in the column direction, the two pixels 21 are a set of a floating diffusion FD, an amplification transistor AMP, a reset transistor RES, and a selection transistor RES. The point is that the transistor SEL is shared. In this modification, the vertical scanning circuit 25 is configured to output control signals φSEL, φRES, φTX1, φTX2 as shown in FIG. 4 instead of the control signals φSEL, φRES, and φTX as shown in FIG. You.

  In FIG. 4, two pixels 21 (21-1 and 21-2) sharing one set of the floating diffusion FD, the amplification transistor AMP, the reset transistor RES, and the selection transistor SEL are shown as a pixel block BL. In FIG. 3, the photodiode PD and the transfer transistor TX of the upper pixel 21-1 in the pixel block BL are denoted by PD1 and TX1, respectively, and the photodiode PD of the lower pixel 21-2 in the pixel block BL. And the transfer transistor TX are denoted by PD2 and TX2, respectively, to distinguish them from each other. Further, the control signal supplied to the gate of the transfer transistor TX1 is φTX1, and the control signal supplied to the gate electrode of the transfer transistor TX2 is φTX2 to distinguish them. In FIG. 3, n indicates a pixel row, but in FIG. 4, n indicates a row of the pixel block BL. One row of the pixel block BL corresponds to two rows of the pixels 21.

  In this modified example, the vertical scanning circuit 25 receives the control signal from the imaging control unit 5 in FIG. 1 and outputs the control signals φSEL, φRES, φTX1, and φTX2 for each row of the pixels 21. A read operation can be realized.

  As in the case of a general CMOS image sensor, the output signal of the pixel 21 includes an optical signal corresponding to an information signal including predetermined information and a dark signal corresponding to a reference signal including a reference component to be subtracted from the information signal. is there. The optical signal is a signal including optical information photoelectrically converted by the pixel 21. Specifically, in this embodiment, the dark signal is a signal output from the pixel 21 when the floating diffusion FD is reset, and the optical signal is a signal charge of the photodiode FD transferred to the floating diffusion FD. It is a signal output from the pixel 21 when it is performed, and is a signal on which a dark signal is superimposed.

  Each column circuit 26 has an amplification unit 51. In the present embodiment, the amplifying unit 51 includes an operational amplifier (second operational amplifier) OP, an input capacitance CA, a feedback capacitance CG, and a clamp control switch (second feedback switch) that is turned on / off in response to a clamp control signal φCARST. And (c) outputting an information signal and a reference signal corresponding to the signal of the corresponding vertical signal line 23 from the output terminal of the operational amplifier OP. The constant potential Vref is applied to the non-inverting input terminal (+ input terminal) of the operational amplifier OP by the potential supply unit 33. The vertical signal line 23 is connected to the inverting input terminal (−input terminal) of the operational amplifier OP via the input capacitance CA. A feedback capacitor CG and a clamp control switch CARST are connected in parallel between the inverting input terminal of the operational amplifier OP and the output terminal of the operational amplifier OP. The operational amplifier OP is configured using a differential amplifier circuit or the like. The control inputs of the clamp control switches CARRST of the column circuits 26 are commonly connected, and a clamp control signal φCARST is supplied from the control pulse generation circuit 29 to the control inputs. The clamp control switch CARRST turns on when the clamp control signal φCARST is at a high level, and turns off when the clamp control signal φCARST is at a low level.

  According to the amplifying unit 51, when the signal φCARST goes high, the clamp control switch CARST is turned on to short-circuit the inverting input terminal and the output terminal of the operational amplifier OP, and the output terminal of the operational amplifier OP has a predetermined potential. Clamped to Vref. Thereafter, when the voltage of the vertical signal line 23 changes by ΔV in a state where the signal φCARST is set to the low level and the clamp control switch CARST is turned off, the signal of the output terminal of the operational amplifier OP becomes ｛Vref− (CA / CG) × ΔV｝. As described above, when the clamp control switch CARST is turned off, an inversion gain (−CA / CG) is obtained by the ratio of the input capacitance CA and the feedback capacitance CG.

  As will be described later, φCARST is once set to a high level for a predetermined period, and φCARST is returned to a low level when a dark signal is output to the vertical signal line 23, and thereafter, an optical signal is output to the vertical signal line 23. Is done. In the following description, the output signal of the operational amplifier OP when φCARST is returned to a low level while a dark signal is being output to the vertical signal line 23 is also called a dark signal, and the signal and potential are indicated by Vd. An output signal of the operational amplifier OP when an optical signal is subsequently output to the vertical scanning circuit 25 is also called an optical signal, and its signal and potential are indicated by Vs.

  Elements other than the amplifying unit 51 in each column circuit 26 constitute an AD converter together with the ramp signal generation circuit 27 and the counter 28. One ramp signal generation circuit 27 and one counter 28 are provided in common for all columns. Therefore, in the present embodiment, one AD converter is provided for each of the vertical signal lines 23, but the ramp signal generation circuit 27 and the counter 28 among the components of each AD converter are provided. Is shared by all AD converters. The configuration and operation of the AD converter will be described later.

  The horizontal scanning circuit 30 supplies a control signal for horizontal scanning to a later-described data storage unit 52 of the column circuit 26 in each column, and outputs first and second m-bit data for each column obtained by each AD converter. 2 (the count values respectively stored in the latches A and B, which are independent storage areas of the data storage unit 52 of each column circuit 26), are sequentially converted to m-bit first and second horizontal signal lines 34. , 35 to the subtractor 31. The subtractor 31 obtains a difference between the received first and second digital values, obtains an m-bit digital value indicating the difference, and causes the output circuit 32 to transmit the digital value. The output circuit 32 converts the received digital value into a serial digital signal by, for example, performing parallel-serial conversion, and outputs the serial value to the outside (the digital signal processing unit 6 in FIG. 1).

  The control pulse generation circuit 29 generates a clock signal and timing necessary for each operation of the vertical scanning circuit 25, the AD converter, the horizontal scanning circuit 30, and the like based on a master clock (not shown) received from the imaging control unit 5 in FIG. Generate signals and supply these signals to the appropriate circuit parts.

  The basic configuration of the solid-state imaging device 4 according to the present embodiment, except for the configuration and operation of the AD converter (a part other than the amplification unit 51 in the ramp signal generation circuit 27, the counter 28, and the column circuit 26) in FIG. The typical operation is the same as that of a conventional general CMOS image sensor.

  The ramp signal generation circuit 27 generates a ramp signal Vramp as shown in FIG. 6 described later based on a signal from the control pulse generation circuit 29. The configuration of the ramp signal generation circuit 27 is not limited in any way. For example, a configuration using a DA converter that converts the count value of the counter 28 into a DA may be employed, or various other known configurations may be employed. Is also good.

  The counter 28 starts and stops the count operation in response to a command from the control pulse generation circuit 29, counts the clock signal from the control pulse generation circuit 29 during the count operation, and switches the n-bit signal line 36. The n-bit count value is supplied to the data storage unit 52 of each column circuit 26 via the input / output unit, via the control unit.

  Each column circuit 26 has a comparator COM that performs a comparison process based on the ramp signal Vramp and the reference voltage GND. The comparator COM is composed of an operational amplifier. Each of the column circuits 26 is connected to the non-inverting input terminal of the comparator COM and samples the output signal of the operational amplifier OP of the amplifying unit 51 (the signal corresponding to the signal of the optical signal 3 to the vertical scanning circuit 25); One electrode is connected to the non-inverting input terminal of the comparator COM and the other electrode receives a ramp signal Vramp. The first capacitor C1 has one electrode connected to the inverting input terminal of the comparator COM and the other electrode has a reference. It has a second capacitor C2 to which the voltage GND is input, and a feedback switch SW2 that turns on and off between the inverting input terminal of the comparator COM and the output terminal of the comparator.

  In the present embodiment, the other electrode of the first capacitor C1 of each column circuit 26 is a first input section of the column circuit 26 to which the ramp signal Vramp is input. The other electrode (first input section) of the first capacitor C1 of each column circuit 26 is commonly connected by a first wiring 61, to which a ramp signal Vramp is supplied from a ramp signal generation circuit 27. . The other electrode of the second capacitor C2 of each column circuit 26 is a second input section of the column circuit 26 to which the reference voltage GND is input. The other electrode (second input section) of the second capacitor C2 of each column circuit 26 is commonly connected by a second wiring 62, to which a reference voltage GND is supplied. In the present embodiment, the ground potential GND is supplied as the reference voltage, but another constant potential may be supplied as the reference voltage. The first and second wirings 61 and 62 and the supply status of the ramp signal Vramp and the reference voltage GND thereto will be described later in detail.

  The control inputs of the sampling switches SW1 of the respective column circuits 26 are commonly connected, and a control signal φSPL is supplied thereto from the control pulse generation circuit 29. The sampling switch SW1 turns on when the control signal φSPL is at a high level, and turns off when the control signal φSPL is at a low level.

  The control inputs of the feedback switches SW2 of the column circuits 26 are connected in common, and a control signal φADC is supplied from the control pulse generation circuit 29 to the control inputs. The feedback switch SW2 turns on when the control signal φADC is at a high level, and turns off when the control signal φADC is at a low level.

  Each column circuit 26 has a data storage unit 52. The data storage unit 52 has n-bit latches A and B as independent storage areas inside. The data storage unit 52 receives the output signal Vout of the comparator COM as a latch command signal, and latches the count value supplied from the counter 28 via the signal line 36 when the output signal Vout of the comparator COM is inverted. At this time, the data storage unit 52 responds to a control signal φLCH (a signal instructing which of the latches A and B is to be stored) from the control pulse generation circuit 29 to perform a first period t11-t12 in FIG. Is stored in the latch A at the time when the output signal Vout of the comparator COM is inverted, and the count value at the time when the output signal Vout of the comparator COM is inverted during the second period t17-t18 in FIG. Store it in B.

  In response to a command from the control pulse generation circuit 29, the counter 28 starts the counting operation from the change start time t11 of the ramp signal Vramp in the first period t11-t12 in FIG. 6, and the second period in FIG. The counting operation is started from a time point t17 at which the ramp signal Vramp changes from t17 to t18. Therefore, the count values stored in the latches A and B of the data storage unit 52 indicate the respective elapsed times from the change start points t11 and t17 of the ramp signal Vramp to the inversion point of the output signal Vout of the comparator COM. As described above, the data storage unit 52 and the counter 28 constitute a clock unit that obtains a count value according to the elapsed time. The data storage unit 52 receives the control signal from the horizontal scanning circuit 30, converts the count value stored in each of the latches A and B into an m-bit digital value, and converts the count value into an m-bit horizontal signal line 34, 35. To the subtractor 31 via

  FIG. 5 is a timing chart illustrating an example of the operation of the solid-state imaging device 4 according to the present embodiment. When the operation is started, after a mechanical shutter (not shown) is opened for a predetermined period (exposure period) T0, the readout period of the first row, the readout period of the second row,. .. Are performed, and the reading operation is sequentially repeated for each row from the first row to the last row. The readout period (one horizontal period) of each row includes a vertical transfer period (including an AD conversion period) of the row, and a subsequent horizontal transfer period (horizontal scanning period) of the row. In FIG. 5, T1 indicates the vertical transfer period of the readout period of the first row, T2 indicates the vertical transfer period of the readout period of the second row, and Tn indicates the vertical transfer period of the readout period of the nth row. As shown in FIG. 5, in the vertical transfer period of the readout period of each row, the control signal φSEL of the row is set to the high level, and the selection transistor SEL of the pixel 21 of the row is turned on.

  FIG. 6 is a timing chart showing the operation in the vertical transfer period Tn in the readout period of the n-th row in FIG. The vertical transfer period Tn starts at time t1 and ends at time t18.

  Until the time point t2 after the time point t1, the control signal φRES (n) is maintained at the high level, and the reset transistor RES of the pixel 21 in the n-th row is maintained in the ON state. At time t2, the control signal φRES (n) is set to low level, and the reset transistor RES of the pixel 21 in the n-th row is turned off. The off state of the reset transistor RES is maintained until time t16. During a period from time t2 to time t3, control signal φCARST is set to high level, and after time t3, control signal φCARST is set to low level. As a result, during the period from time t3 to time t8 described later, the output signal of the amplifier 51 becomes the dark signal Vd.

  Until time t9 after time t1, the ramp signal Vramp is at the ground potential GND. However, instead of the ground potential GND, another constant potential may be used.

  During the period from the time point t4 to the time point t7, the control signal φADC is set to the high level, the feedback switch SW2 is turned on, and the comparator COM functions as a voltage follower. After time t7, the control signal φADC is set to low level, the feedback switch SW2 is turned off, and the comparator COM functions as a comparator. During a period from time t5 after time t4 to time t6 before time t7, the control signal φSPL is set to the high level, and the sampling switch SW1 is turned on. After time t6, control signal φSPL is maintained at a low level until time t14.

  During the period t5-t6, the sampling switch SW1 is turned on, so that the dark signal Vd output from the amplifying unit 51 is sampled and accumulated in the first capacitor C1, and the dark signal Vd is output to the non-inverting input terminal of the comparator COM. Vd is supplied. The level of the dark signal Vd stored in the first capacitor C1 is determined at the time point t6, and this level is maintained after the time point t6. In the period t5 to t7, the dark signal Vd is supplied to the non-inverting input terminal of the comparator COM functioning as a voltage follower. The second capacitor C2 is also sampled on the path of SW2. At this time, a dark signal (Vd + Voff) on which the offset Voff of the comparator COM is superimposed is accumulated in the second capacitor C2, and is supplied to the inverting input terminal of the comparator COM. The level of the dark signal (Vd + Voff) stored in the second capacitor C2 is determined at the time point t7, and this level is maintained after the time point t7.

  During a period from time t8 after time t7 to time t10, the control signal φTX (n) in the n-th row is temporarily set to the high level, and the transfer transistor TX of the pixel 21 in the n-th row is turned on. As a result, the output signal of the amplifier 51 becomes the optical signal Vs. At this time, since the sampling switch SW1 is turned off, the output signal of the amplifier does not affect the sampling state of the dark signal Vd in the capacitors C1 and C2.

  At time t9 after time t7, ramp signal Vramp rises from ground potential GND to a predetermined potential, is maintained at the predetermined potential from time t9 to time t11, and gradually decreases from time t11 to time t12 in proportion to the elapsed time. Then, the potential at time t12 is maintained until time t13. At time t13, the potential is returned to the original ground potential GND, and is maintained at the ground potential GND until time t16. The reason for raising the level of the ramp signal Vramp at the time point t11 is to increase the AD conversion accuracy even when the dark signal Vd is close to the zero level.

  Consider now a period t9-t13 in which the ramp signal Vramp changes from the ground potential GND. In this period, since the dark signal Vd is accumulated in the first capacitor C1, the non-inverting input of the comparator COM is determined. The terminal is supplied with a superimposed signal (Vd + Vramp) of the ramp signal Vramp and the dark signal Vd, while the inverting input terminal of the comparator COM is supplied with a dark signal (Vd + Voff) having an offset Voff. When the input signal of the non-inverting input terminal of the comparator COM matches the input signal of the inverting input terminal of the comparator COM, the output signal Vout of the comparator COM is inverted. Therefore, when the ramp signal Vramp coincides with the offset Voff, the output signal Vout of the comparator COM is inverted. For this reason, the elapsed time from the change start time t11 of the ramp signal Vramp to the inversion time of the output signal Vout of the comparator COM indicates the offset Voff. The count value indicating the elapsed time (that is, the offset Voff) is stored in the latch A of the data storage unit 52.

  During the period t11-t12, the sampling switch SW1 of each column circuit 26 and the feedback are output when the output signal of the amplification unit 51 is the dark signal Vd (and the signal of the vertical signal line 23 is the dark signal (reference signal)). The first period in which the ramp signal Vramp gradually changes is a period in which the switch SW2 is simultaneously turned on and simultaneously turned off in the period t5 to t6. The length of the first period t11-t12 is determined in consideration of the variable range of the dark signal Vd so that the output signal Vout of the comparator COM is inverted during the first period t11-t12, and is wastefully. It is set so that it will not be long.

  During a period from time t14 after time t13 to time t15, the control signal φSPL is set to the high level, and the sampling switch SW1 is turned on. After time t15, control signal φSPL is maintained at a low level.

  Since the sampling switch SW1 is on in the period t4 to t15, the optical signal Vs output from the amplifier 51 is sampled and accumulated in the first capacitor C1. The level of the optical signal Vs stored in the first capacitor C1 is determined at the time point t15, and this level is maintained after the time point t15. On the other hand, the dark signal (Vd + Voff) with the offset Voff of the comparator COM remains stored in the second capacitor C2 and remains supplied to the inverting input terminal of the comparator COM.

  The ramp signal Vramp rises from the ground potential GND to a predetermined potential at a time t16 after the time t15, is maintained at the predetermined potential from a time t6 to a time t17, and gradually decreases in proportion to an elapsed time from a time t17 to a time t18. Then, at time t18, the potential is returned to the original ground potential GND. The reason for raising the level of the ramp signal Vramp at the time point t17 is to increase the AD conversion accuracy even when the dark signal Vd is close to the zero level.

  Consider now a period t16-t18 in which the ramp signal Vramp changes from the ground potential GND. In this period, since the optical signal Vs is accumulated in the first capacitor C1, the non-inverting input of the comparator COM is determined. A terminal is supplied with a superimposed signal (Vs + Vramp) of the lamp signal Vramp and the optical signal Vs, while a dark signal (Vd + Voff) with an offset Voff is supplied to the inverting input terminal of the comparator COM. When the input signal of the non-inverting input terminal of the comparator COM matches the input signal of the inverting input terminal of the comparator COM, the output signal Vout of the comparator COM is inverted. Therefore, when the ramp signal Vramp matches (Vd−Vs + Voff), the output signal Vout of the comparator COM is inverted. For this reason, the elapsed time from the change start time t17 of the ramp signal Vramp to the inversion time of the output signal Vout of the comparator COM indicates (Vd−Vs + Voff). The count value indicating the elapsed time (that is, (Vd−Vs + Voff)) is stored in the latch B of the data storage unit 52.

  The period t17 to t18 is equal to or shorter than the period of the first period t11 to t12 when the output signal of the amplification unit 51 is the optical signal Vs (therefore, when the signal of the vertical signal line 23 is the optical signal). A second period in which the ramp signal Vramp gradually changes, during a period in which the sampling switch SW1 of each column circuit 26 is once turned on during a period t14-t15 while the feedback switch SW2 is kept off and then turned off. It has become. The length of the second period t17-t18 is determined such that the output signal Vout of the comparator COM is inverted in the second period t17-t18 in consideration of the variable range of the optical signal Vs, and is wasteful. It is set so that it will not be long.

  When the vertical transfer period Tn of the n-th row readout period ends, the horizontal transfer period of the n-th row readout period follows. In this horizontal transfer period, the horizontal scanning circuit 30 performs horizontal scanning according to the control signal from the control pulse generation circuit 29, and stores the data in the latches A and B of the data storage unit 52 of the column circuit 26 in each column, which will be described later. The subtracted first and second count values are sequentially transmitted to the subtractor 31 via m-bit first and second horizontal signal lines 34 and 35. The subtractor 31 calculates a difference between the received first and second digital values (corresponding to a difference between the optical signal Vs and the dark signal Vd), obtains an m-bit digital value indicating the difference, and outputs the digital value. It is sent to the circuit 32. The output circuit 32 converts the received digital value into a signal of a predetermined signal format, and outputs it as image data to the outside (digital signal processing unit 6 in FIG. 1).

  Note that the subtractor 31 is removed, and the first and second digital values are output to the digital signal processing unit 6 in FIG. 1 via the output circuit 32, and the digital signal processing unit 6 outputs the first and second digital values. The difference between the digital values may be obtained.

  The reading period of the n-th row has been described above, but the operation of the reading period of the other rows is the same as the operation of the reading period of the n-th row.

  In the operation example described above, the reading periods (one horizontal period) of each row are sequentially performed without overlapping. However, the present invention is not limited to this, and the reading period of a certain row and the reading period of the next row may partially overlap. In this case, for example, in FIG. 6, the control signal φSEL (n) may be set to a low level after time t16, and the reading period of the next (n + 1) th row may be started from a time slightly after time t16.

  In the present embodiment, as shown in FIG. 2, the ramp signal generation circuit 27 is arranged on one side (the left side in FIG. 2) of the solid-state imaging device 4 in the row direction, and the first signal of each column circuit 26 is provided. The ramp signal Vramp is supplied to the left side in FIG. 2 of the first wiring 61 that connects the other electrode (first input section) of the capacitor C1 in common. Further, in the present embodiment, the reference voltage GND is provided on the left side in FIG. 2 of the second wiring 62 that commonly connects the other electrode (second input unit) of the second capacitor C2 of each column circuit 26. The reference voltage GND is not supplied to the right side in FIG. 2 of the second wiring 62.

  FIG. 7 is a schematic plan view schematically showing a specific example of the wiring patterns 61a, 61b, 62a, 62b and the like constituting the first and second wirings 61, 62 in FIG. The left and right in FIG. 7 correspond to the left and right in FIG. 2, and the left and right direction in FIG.

  In the example shown in FIG. 7, the first wiring 61 is connected to the main wiring pattern 61a by a contact portion 61c in a column direction (in FIG. 7) and a main wiring pattern 61a extending in the row direction (the left-right direction in FIG. 7). And the sub-wiring pattern 61b connected to the first capacitor C1 of each column circuit 26. In FIG. 7, the hierarchy of the sub wiring pattern 61b is different from the hierarchy of the main wiring pattern 61a, so the sub wiring pattern 61b is shown by a broken line. The left side of the main wiring pattern 61a in FIG. 7 is connected to the ramp signal generation circuit 27, and the left side of the main wiring pattern 61a in FIG. 7 is supplied with the ramp signal Vramp.

  In the example shown in FIG. 7, the second wiring 62 is connected to the main wiring pattern 62a by a main wiring pattern 62a extending in the row direction (left and right direction in FIG. 7) and the contact portion 62c, and is connected in the column direction (FIG. 7). And a sub-wiring pattern 62b connected to the second capacitor C2 of each column circuit 26. In FIG. 7, the hierarchy of the sub wiring pattern 62b is different from the hierarchy of the main wiring pattern 62a, so the sub wiring pattern 62b is shown by a broken line. The left side of the main wiring pattern 62a in FIG. 7 is connected to the electrode pad 63d for supplying the ground voltage GND, and the reference voltage GND is supplied to the left side of the main wiring pattern 62a in FIG. On the other hand, no electrode pad is connected to the right side of the main wiring pattern 62a in FIG.

  FIG. 8 is a schematic plan view schematically showing the solid-state imaging device 4 in FIG. 1 (that is, the solid-state imaging device 4 shown in FIG. 2). The solid-state imaging device 4 seals the chip 71 on which the circuit shown in FIG. 2 is mounted, a concave package body 72 having the opening 72a and containing the chip 71, and the opening 72a having predetermined light transmission characteristics. And a lid 73.

  As shown in FIG. 8, the chip 71 has electrode pads 63a to 63g formed thereon. The electrode pad 63d in FIG. 8 indicates the electrode pad 63d for supplying the ground voltage GND in FIG.

  The package body 72 is provided with internal terminals 73a to 73h and external terminals 74a to 74h that are electrically connected to the internal terminals 73a to 73h, respectively. The internal terminals 73a to 73g and the electrode pads 63a to 63g of the chip 71 are electrically connected by bonding wires 75, respectively. In this example, the internal terminal 73h and the external terminal 74h are not used as spares. Of course, the internal terminal 73h and the external terminal 74h may be used for transmitting and receiving a certain signal between inside and outside.

  FIG. 9 is a circuit diagram illustrating a schematic configuration of the solid-state imaging device 104 according to the comparative example, and corresponds to FIG. FIG. 10 is a schematic plan view schematically showing wiring patterns 61a, 61b, 62a, 62b and the like constituting the first and second wirings 61, 62 in FIG. 9, and corresponds to FIG. FIG. 11 is a schematic plan view schematically showing the solid-state imaging device 104 according to the comparative example shown in FIG. 9, and corresponds to FIG. 9 to 11, the same or corresponding elements as those in FIGS. 2, 7, and 8 are denoted by the same reference numerals, and redundant description will be omitted.

  The difference between the solid-state imaging device 104 according to the comparative example and the solid-state imaging device 4 of the present embodiment is as follows.

  As shown in FIGS. 2 and 9, in the solid-state imaging device 4 according to the present embodiment, the reference voltage GND is not supplied to the right side of the second wiring 62 in FIG. In the device 104, the reference voltage GND is supplied not only to the left side in FIG. 9 of the second wiring 62 but also to the right side in FIG. 9 in order to increase the noise resistance of the second wiring 62.

  To achieve this, as shown in FIGS. 7 and 10, in the solid-state imaging device 4 of the present embodiment, an electrode pad is connected to the right side of the main wiring pattern 62a of the second wiring 62 in FIG. In contrast, in the solid-state imaging device 104 according to the comparative example, an electrode pad 63h for supplying the ground voltage GND is connected to the right side of the main wiring pattern 62a of the second wiring 62 in FIG. As shown in FIGS. 8 and 9, in the solid-state imaging device 4 of the present embodiment, the chip 71 is not provided with the electrode pad 63 h, and the internal terminal 73 h and the external terminal 74 h are not used as spares. On the other hand, in the solid-state imaging device 104 according to the comparative example, the chip 71 is provided with the electrode pad 63h, the electrode pad 63h is electrically connected to the internal terminal 73h by the bonding wire 75, and the external terminal 74h is connected to the internal terminal 73h. The ground voltage GND is supplied to the electrode pad 63h via 73h.

  In both the comparative example and the present embodiment, since the ramp signal Vramp is supplied from the ramp signal generation circuit 27 to the left side of the first wiring 61 in the drawing, if noise is applied to the first wiring 61 due to disturbance or the like, The noise level on the left side of the first wiring 61 in the figure is relatively low, the noise level on the right side of the first wiring 61 in the figure is relatively high, and the noise level of the first wiring 61 at the center on the left and right in the figure is moderate. Becomes

  On the other hand, in the comparative example, since the reference voltage GND is supplied to both the left and right sides of the second wiring 62 in the drawing, if noise is applied to the second wiring 62 due to a disturbance or the like, the second wiring 62 The noise level on the left side in the figure is relatively low, the noise level on the right side in the figure of the second wiring 62 is also relatively low, and the noise level on the left and right center of the second wiring 62 in the figure is medium. Therefore, in the comparative example, the distribution state of the noise level in the second wiring 62 is different from the distribution state of the noise in the first wiring 61, and the noise level on the right side of the first wiring 61 in FIG. The difference from the noise level on the right side in FIG. For this reason, in the comparative example, in the column circuit 26 in the right column in the figure, the difference between the level of the noise on the ramp signal Vramp and the level of the noise on the reference voltage GND, and furthermore, the comparison is performed by the comparator COM for AD conversion. The difference between the levels of the noises of the two signals (the signal input to the non-inverting input terminal of the comparator COM and the signal input to the inverting input terminal of the comparator COM) increases. Therefore, in the comparative example, in the column circuit 26 in the right column in the figure, the error of the comparison result by the comparator COM for AD conversion increases, and the AD conversion error increases. As a result, a vertical streak affected by the noise appears in the obtained image, and the image quality deteriorates.

  On the other hand, in the present embodiment, the reference voltage GND is supplied to the left side of the second wiring 62 in the drawing, and the reference voltage GND is not supplied to the right side of the second wiring 62 in the drawing. , The noise level on the left side of the second wiring 62 in the figure is relatively low, the noise level on the right side of the second wiring 62 in the figure is relatively high, Has a medium noise level. Therefore, in the present embodiment, the distribution of the noise level in the second wiring 62 is the same as the distribution of the noise in the first wiring 61. The difference between the noise level of the wiring 61 and the noise level of the second wiring 62 becomes smaller. For this reason, in the present embodiment, in the column circuits 26 of any column in the figure, two signals (a signal input to the non-inverting input terminal of the comparator COM and a signal input to the non-inverting input terminal of the comparator COM) are compared for AD conversion. The difference in the level of the noise on each of the signals input to the inverting input terminal of COM becomes small. Therefore, in the present embodiment, the difference between the level of the noise on the ramp signal Vramp and the level of the noise on the reference voltage GND in any one of the column circuits 26 in any column, and furthermore, the comparison by the comparator COM for AD conversion The resulting error is reduced, and the AD conversion error is reduced. As a result, in the present embodiment, in the obtained image, the vertical streaks affected by the noise are reduced, and the image quality is improved.

  FIG. 12 is a schematic plan view schematically showing a solid-state imaging device 204 according to a modification that can be used in place of the solid-state imaging device 4 in the present embodiment, and corresponds to FIGS. 8 and 11.

  This solid-state imaging device 204 is the same as the solid-state imaging device 104 according to the comparative example except that the bonding wires 75 between the electrode pads 63h and the internal terminals 73h are removed from the solid-state imaging device 104 according to the comparative example. It is. The solid-state imaging device 204 can also realize the supply state of the reference voltage GND to the second wiring 62 shown in FIG.

  Further, in the present invention, the solid-state imaging device 104 according to the comparative example can be used instead of the solid-state imaging device 4 depending on how the solid-state imaging device 104 is used. That is, when the solid-state imaging device 104 according to the comparative example is used, the external terminals 74h are electrically floated on a wiring board or the like on which the solid-state imaging device 4 is mounted, without being connected to the location of the reference voltage GND. The supply state of the reference voltage GND to the second wiring 62 shown in FIG.

[Second embodiment]
FIG. 13 is a circuit diagram illustrating a schematic configuration of the solid-state imaging device 304 used in the electronic camera according to the second embodiment of the present invention, and corresponds to FIG. 13, elements that are the same as elements in FIG. 2 or that correspond to elements in FIG.

  The electronic camera according to the present embodiment differs from the electronic camera 1 according to the first embodiment in that a solid-state imaging device 304 is used instead of the solid-state imaging device 4. The solid-state imaging device 304 is different from the solid-state imaging device 4 in the following points.

  In the solid-state imaging device 304, as shown in FIG. 13, an up-down counter 81 is provided instead of the data storage unit 52 in each column circuit 26 in FIG. 2, the counter 28 and the subtractor 31 are removed, and the horizontal signal line A horizontal signal line 82 is provided instead of 34 and 35.

  In the present embodiment, the control pulse generating circuit 29 controls the up / down counter 81 of each column circuit 26 to instruct whether the up / down counter 81 operates in the down count mode or the up count mode. Signal φUD is input. The count clock φCLK is also input to the up / down counter 81 from the control pulse generation circuit 29. The control signal φUD and the count clock φCLK are commonly input to the up / down counter 81 of each column circuit 26. Further, the output signal of the corresponding comparator COM is also input to the up / down counter 81.

  The up-down counter 81 outputs the output signal Vout of the comparator COM in the first period t11-t12 from the change start time t11 of the ramp signal Vramp in the first period t11-t12 in the vertical transfer period Tn of the n-th row reading period. Until the inversion time, the count clock φCLK is counted in one of the down-count mode and the up-count mode, and the count value at the inversion time is held. The up-down counter 81 outputs the output of the comparator COM in the second period t17-t18 from the start point t17 of the change of the ramp signal Vramp in the second period t17-t18 in the vertical transfer period Tn of the reading period of the n-th row. Until the signal Vout is inverted, in the other of the down-count mode and the up-count mode, the count clock φCLK is counted from the previously held count value, and the count value at the time of the inversion is held. The held count value is equivalent to the difference between the count value stored in the latch A of the data storage unit 52 and the count value stored in the latch B of the data storage unit 52 in the first embodiment. .

  When the vertical transfer period Tn of the n-th row readout period ends, the horizontal transfer period of the n-th row readout period follows. In this horizontal transfer period, the horizontal scanning circuit 30 performs horizontal scanning according to the control signal from the control pulse generation circuit 29, and sequentially counts the count value held in the up / down counter 81 of the column circuit 26 of each column by m bits. To the output circuit 32 via the horizontal signal line 82. The output circuit 32 converts the received digital value into a signal of a predetermined signal format, and outputs it as image data to the outside (digital signal processing unit 6 in FIG. 1).

  The reading period of the n-th row has been described above, but the operation of the reading period of the other rows is the same as the operation of the reading period of the n-th row.

  According to this embodiment, advantages similar to those of the first embodiment can be obtained.

  Note that a modification similar to the above-described modification of the solid-state imaging device 4 may be applied to the solid-state imaging device 304 according to the present embodiment.

  The embodiments of the present invention and the modifications thereof have been described above, but the present invention is not limited to these.

  For example, in the first and second embodiments, a simple inverting amplifier may be used as an amplifying unit instead of the amplifying unit 51 in each column circuit 26. Further, for example, in each column circuit 26, the vertical signal line 23 may be directly connected to the sampling switch SW1 by removing the amplifying unit 51.

1 electronic camera 21 pixel 23 vertical signal line 26 column circuit (signal processing unit)
61 first wiring 62 second wiring COM comparator

Claims (8)

A first signal processing unit having a first comparator for converting a first signal including a signal generated by the photoelectrically converted charges into a digital signal;
A second signal processing unit that is arranged alongside the first signal processing unit and has a second comparator for converting a second signal including a signal generated by the photoelectrically converted charges into a digital signal;
A wiring disposed outside the region where the first signal processing unit and the second signal processing unit are disposed and connected to a ramp signal generation circuit for generating a ramp signal, and connected to the first comparator; A first wiring having a first contact portion and a second contact portion for connecting to the second comparator;
A wiring connected to an electrode pad provided outside the region where the first signal processing unit and the second signal processing unit are provided and supplied with a predetermined voltage , and connected to the first comparator; A second wiring having a third contact portion and a fourth contact portion for connecting to the second comparator,
In the first wiring, a length of the wiring from the ramp signal generation circuit to the first contact portion is shorter than a length of the wiring from the ramp signal generation circuit to the second contact portion,
In the second wiring, the length of the wiring from the electrode pad to the third contact portion is shorter than the length of the wiring from the electrode pad to the fourth contact portion. The imaging device according to claim 1,
A first signal line connected to the first signal processing unit and outputting the first signal;
A second signal line connected to the second signal processing unit and outputting the second signal;
An imaging device comprising: The imaging device according to claim 2,
A first pixel connected to the first signal line, the first pixel having a first photoelectric conversion unit configured to convert light into electric charge, and a first transfer unit configured to transfer the electric charge converted by the first photoelectric conversion unit;
A second pixel connected to the second signal line, the second pixel including a second photoelectric conversion unit that converts light into electric charge, and a second transfer unit that transfers the electric charge converted by the second photoelectric conversion unit;
A control line connected to the first transfer unit and the second transfer unit and configured to output a control signal for controlling the first transfer unit and the second transfer unit;
An imaging device comprising: The imaging device according to claim 2,
A first photoelectric conversion unit that is connected to the first signal line and converts light into electric charge, a second photoelectric conversion unit that converts light into electric charge, and a second photoelectric conversion unit that transfers the electric charge converted by the first photoelectric conversion unit. A second transfer unit for transferring the charges converted by the first transfer unit and the second photoelectric conversion unit; and a second transfer unit for transferring the charges from the first photoelectric conversion unit and the charges from the second photoelectric conversion unit. A first pixel block having one floating diffusion;
A third photoelectric conversion unit connected to the second signal line for converting light into electric charge, a fourth photoelectric conversion unit for converting light into electric charge, and a third photoelectric conversion unit for transferring the electric charge converted by the third photoelectric conversion unit. A third transfer unit for transferring the charges converted by the third transfer unit and the fourth photoelectric conversion unit; and a fourth transfer unit for transferring the charges from the third photoelectric conversion unit and the charges from the fourth photoelectric conversion unit. A second pixel block having two floating diffusions;
A first control line connected to the first transfer unit and the third transfer unit and configured to output a control signal for controlling the first transfer unit and the third transfer unit;
A second control line connected to the second transfer unit and the fourth transfer unit and configured to output a control signal for controlling the second transfer unit and the fourth transfer unit;
An imaging device comprising: The imaging device according to any one of claims 1 to 4,
The first comparator includes an operational amplifier,
The second comparator is an imaging device including an operational amplifier. The imaging device according to any one of claims 1 to 5,
The image pickup device wherein the electrode pad is connected to a terminal arranged outside by a wire. An imaging device according to any one of claims 1 to 5,
A package in which the image sensor is housed;
A connection unit for connecting the electrode pad and a terminal arranged on the package,
An imaging device comprising: The imaging device according to claim 7,
The imaging device, wherein the connection unit includes a wire connecting the electrode pad and the terminal.

Images