JP2009128721A - Plasma display device and driving method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a plasma display device capable of achieving interlace drive with one-line display and interlace drive with two-line display while switching both kinds of interlace drives without deteriorating display quality. <P>SOLUTION: In the plasma display device, the interlace drive with one-line display is performed by applying a sustain pulse to an even display line or an odd display line on the plasma display device on each frame, and the interlace drive with two-line display is performed by writing the same data while making the even display line and odd display line which are adjacent to each other upwards and downwards, and applying a sustain pulse. Therein, the interlace drive with one-line display and the interlace drive with two-line display are achieved such that resetting of all cells is performed one time per unit time when the interlace drive with two-line display is performed, thereby, the increase of the number of times of the resetting of all cells in the two-line display is suppressed and, as the result, the increase of background luminance can be prevented. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a plasma display device and a driving method thereof.

  In driving a plasma display panel (PDP), one frame (odd frame or even frame) is composed of a plurality of sub-frames, and gradation is determined by selecting which sub-frame is used to light a cell. Expression is realized. Each subframe corresponds to a reset period for initializing the wall charge state on the electrode, an address period for selecting a cell to be lit by adjusting the wall charge state based on display data, and display data. This is composed of a sustain period in which a cell is turned on (a cell selected according to display data is discharged to emit light).

  Further, the reset discharge performed during the reset period includes all-cell reset (all-cell simultaneous reset) and on-cell reset. In the all-cell reset, reset discharge is performed in both the cells that are lit in the sustain period of the immediately preceding subframe and the non-lighted cells, that is, all cells regardless of the presence or absence of the sustain discharge. In the on-cell reset, the reset discharge is performed only in the cells that are lit in the sustain period of the immediately preceding subframe, that is, the cells that have undergone the sustain discharge.

  In the plasma display panel, the display lines are divided into odd display lines and even display lines, and the odd display lines are lit in the odd frames and the even display lines are lit in the even frames. In addition, two adjacent lines, one odd display line and one even display line, are set as one set and the same one line data is written, and only one line is emitted or two lines are emitted simultaneously according to the display load factor. There has been proposed a technique for improving the luminance by interlaced driving by appropriately controlling whether or not to perform (see, for example, Patent Document 1).

International Publication No. 07/004305 Pamphlet

  In the conventional plasma display panel, all cell resets are always performed on the display line where the sustain discharge is performed in the first subframe among the plurality of subframes constituting the frame. The background luminance in the plasma display panel is generated by the discharge at the all cell reset.

  Therefore, as described above, when two adjacent lines are set as one set and the same one line of data is written to emit two lines simultaneously (two line display), the display is performed by alternately emitting light one line at a time. The number of all cell resets is increased and the background luminance is higher than in the case of performing (one line display). Further, when switching between the state where two lines are simultaneously emitted and the state where one line is alternately emitted, the background luminance changes and a switching shock occurs.

  An object of the present invention is to provide a plasma display device that can be realized by switching between interlaced driving in one-line display and interlaced driving in two-line display without degrading display quality.

The plasma display device of the present invention includes a plasma display panel in which display electrode pairs of even display lines and display electrode pairs of odd display lines are alternately arranged, and in the first mode, the even display lines are displayed in each frame. A sustain pulse is applied to one display electrode pair of the display electrode pair or the display electrode pair of the odd display line to perform interlace driving, and in the second mode, two of the even display line and the odd display line adjacent to each other in the vertical direction are driven. A pair of display electrodes for writing the same data and applying a sustain pulse to drive the interlace drive. When driving in the second mode, the wall charge state on the electrodes is initialized. All-cell reset in which reset discharge is performed in all cells is performed once per unit time including a plurality of frames. And wherein the door.
The driving method of the plasma display apparatus of the present invention is a driving method of a plasma display apparatus having a plasma display panel in which display electrode pairs of even display lines and display electrode pairs of odd display lines are alternately arranged. The display load factor of the display panel is detected, and the first mode or the second mode is selected according to the detected display load factor, and in the first mode, the display electrode pair of the even display line in each frame. Alternatively, a sustain pulse is applied to one of the display electrode pairs of the odd display line to perform interlace driving, and in the second mode, two displays of the even display line and the odd display line that are adjacent vertically are displayed. Write the same data with one pair of electrodes and apply a sustain pulse to drive the interlace. When driving in the second mode, all-cell reset in which reset discharge for initializing the wall charge state on the electrode is performed in all cells is performed once per unit time including a plurality of frames. It is characterized by.

  By applying a sustain pulse to one display electrode pair of an even display line or an odd display line in each frame, interlace driving in one line display can be performed, and an even display line and an odd display line adjacent to each other vertically. By writing the same data with the two display electrode pairs as one set and applying a sustain pulse, interlaced driving in two-line display can be performed. In addition, during interlaced driving in 2-line display, all-cell reset, in which reset discharge is performed in all cells, is performed once per unit time including multiple frames, so the number of all-cell resets increases. Can be prevented, the background luminance can be prevented from increasing, and the display quality can be prevented from deteriorating.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram illustrating a configuration example of a plasma display device according to an embodiment of the present invention. The plasma display device according to the present embodiment includes a plasma display panel 10, a Y electrode driver 20, an X electrode driver 30, an address driver 40, a halftone generation circuit 51, a subframe conversion circuit 52, a display load factor detection circuit 53, and a reset setting circuit. 54, a sustain pulse number setting circuit 55, and a drive signal generation circuit 56.

  The Y electrode driver 20 is a circuit that drives Y electrodes (scan electrodes, scan electrodes) Y1, Y2,... Among the display electrodes, and includes a scan circuit (even) 21, a scan circuit (odd) 22, a sustain circuit 23, and a reset circuit. A circuit 24 is included. In the following, each of the Y electrodes Y1, Y2,... Or their generic name is also referred to as a Y electrode Yi, and i means a subscript.

  The scan circuits 21 and 22 are circuits that select lines to be displayed by line-sequential scanning, and the sustain circuit 23 is a circuit that repeats sustain discharge (sustain discharge). A predetermined voltage is supplied to the plurality of Y electrodes Yi by the scan circuits 21 and 22 and the sustain circuit 23.

  The scan circuit (even) 21 is provided corresponding to the even-numbered Y electrodes Y2, Y4,... Related to the even-numbered display lines among the display lines, and supplies a drive voltage to the Y electrodes Y2, Y4,. The scan circuit (even) 21 applies scan pulses to the Y electrodes Y2, Y4,... Sequentially in the address period in at least the even frame for lighting the even display lines, and the sustain pulse (sustain discharge) from the sustain circuit 23 in the sustain period. The pulse) is applied to the Y electrodes Y2, Y4,.

  Similarly, the scan circuit (odd) 22 is provided corresponding to the odd-numbered Y electrodes Y1, Y3, Y5,... Related to the odd-numbered display lines, and the drive voltage is applied to the Y electrodes Y1, Y3, Y5,. Supply. The scan circuit (odd) 22 applies scan pulses to the Y electrodes Y1, Y3,... Sequentially in the address period in at least an odd frame for lighting the odd display lines, and the sustain pulse from the sustain circuit 23 is applied to the Y electrode in the sustain period. It operates to be applied simultaneously to Y1, Y3,.

  The scan circuit (even) 21 and the sustain circuit 23 are connected via a switch SW1, and the scan circuit (odd) 22 and the sustain circuit 23 are connected via a switch SW2. The switches SW1 and SW2 are independently turned on / off based on a control signal from the drive signal generation circuit 56 and the like.

  Whether or not the output from the sustain circuit 23 is supplied to the scan circuits 21 and 22 can be switched independently by the switches SW1 and SW2. Specifically, whether or not the output from the sustain circuit 23 is applied to the even-numbered Y electrodes Y2, Y4,... Can be switched by the switch SW1, and the output from the sustain circuit 23 is switched to the odd-numbered Y by the switch SW2. It can be switched whether to apply to the electrodes Y1, Y3,. In addition, by turning off the switches SW1 and SW2, the even-numbered Y electrodes Y2, Y4,... And the odd-numbered Y electrodes Y1, Y3,.

  The reset circuit 24 includes a circuit that initializes the wall charge state, and applies a predetermined voltage to the plurality of Y electrodes Yi. The reset circuit 24 is connected to the scan circuit (even) 21 via the switch SW3, and is connected to the scan circuit (odd) 22 via the switch SW4. The switches SW3 and SW4 are controlled to be turned on / off based on a control signal from the drive signal generation circuit 56, so that the reset circuit 24 sets the odd-numbered Y electrodes Y1, Y3,. A predetermined voltage is applied to any one of the set or even-numbered Y electrodes Y2, Y4,... Or a predetermined voltage is applied to all Y electrodes Y1, Y2, Y3, Y4,. Control to do.

  The X electrode driver 30 is a circuit that drives X electrodes (sustain electrodes) X1, X2,... Among the display electrodes, and includes a sustain circuit 31. Hereinafter, each of the X electrodes X1, X2,... Or their generic name is also referred to as an X electrode Xi, and i means a subscript. The sustain circuit 31 is a circuit that repeats sustain discharge (sustain discharge), and supplies a predetermined voltage to the X electrode Xi. One end of the X electrode Xi is commonly connected to the X electrode driver 30.

  The address driver 40 includes a circuit for selecting a column to be displayed, and supplies a predetermined voltage to the plurality of address electrodes A1, A2,. Hereinafter, each of the address electrodes A1, A2,... Or their generic name is also referred to as an address electrode Aj, where j means a subscript.

  The halftone generation circuit 51 receives a digital video signal S1 and generates a halftone by performing error diffusion processing, dither processing, and the like in order to display the video signal S1 with a limited lighting pattern. The subframe conversion circuit 52 selects a lighting pattern of the subframe based on the video signal output from the halftone generation circuit 51, and converts the video signal into a lighting pattern corresponding to the lighting pattern. In accordance with the lighting pattern output from the subframe conversion circuit 52, the address driver 40 generates a voltage to be applied to the address electrode Aj for selecting a subframe to be lit for each pixel.

  The display load factor detection circuit 53 calculates the display load factor for each field based on the lighting pattern output from the subframe conversion circuit 52. The display load factor is detected based on the number of pixels that emit light and the gradation value of the pixels that emit light. The display load factor when all pixels of the image are displayed with the maximum gradation value is 100%.

  The sustain pulse number setting circuit 55 selects whether to perform one-line display or two-line simultaneous display according to the display load factor detected by the display load factor detection circuit 53 and performs two-line simultaneous display. In this case, the mixing ratio between the period for displaying 1 line and the period for simultaneously displaying 2 lines is determined. This sets the number of sustain pulses to be applied to each display line in each subframe in the frame.

The reset setting circuit 54 sets a frame for performing all cell reset based on the output from the sustain pulse number setting circuit 55. That is, based on the output from the sustain pulse number setting circuit 55, the reset setting circuit 54 determines whether or not to perform all-cell reset, on-cell reset, or non-reset for each frame.
The drive signal generation circuit 56 generates drive signals related to the Y electrode driver 20 and the X electrode driver 30 according to the outputs of the reset setting circuit 54 and the sustain pulse number setting circuit 55.

  In the plasma display panel 10, the Y electrode Yi and the X electrode Xi constituting the display electrode pair form a row extending in parallel in the horizontal direction, and the address electrode Aj forms a column extending in the vertical direction. The Y electrode Yi and the X electrode Xi are arranged in a predetermined arrangement pattern in the vertical direction and in parallel with each other (the arrangement pattern of the display electrodes will be described later with reference to FIG. 3). The address electrode Aj is arranged in a direction substantially perpendicular to the Y electrode Yi and the X electrode Xi. The Y electrode Yi and the address electrode Aj form a two-dimensional matrix with i rows and j columns.

  Here, in the plasma display panel 10 according to this embodiment, a display electrode pair including two electrodes (a pair of Y electrode Yi and X electrode Xi) is arranged for one display line, and the adjacent display lines are arranged. The display electrode is not shared. That is, with p as a natural number, an odd display line in the display line is configured by a set of Y electrode Y (2p-1) and X electrode X (2p-1), and Y electrode Y (2p) and X electrode X (2p) ) To form an even display line. For example, a first display line is configured by a set of Y electrode Y1 and X electrode X1, and a second display line is configured by a set of Y electrode Y2 and X electrode X2.

  The cell Cij is formed by the intersection of the Y electrode Yi and the address electrode Aj and the corresponding X electrode Xi adjacent thereto. This cell Cij corresponds to, for example, red, green, and blue subpixels, and one pixel is constituted by these three subpixels. The panel 10 displays an image by lighting a plurality of pixels arranged two-dimensionally. The scan circuits 21 and 22 in the Y electrode driver 20 and the address driver 40 determine which cell is to be lit, and the sustain circuit 23 in the Y electrode driver 20 and the sustain circuit 31 in the X electrode driver 30 repeatedly discharge. Thus, the display operation is performed.

  FIG. 2 is an exploded perspective view showing a configuration example of the plasma display panel 10 in the present embodiment.

  A display electrode (also referred to as a sustain electrode) including a bus electrode (metal electrode) 12 and a transparent electrode 13 is formed on the front glass substrate 11. The display electrodes (12, 13) correspond to the Y electrode Yi and the X electrode Xi shown in FIG. A dielectric layer 14 is provided on the display electrodes (12, 13), and an MgO (magnesium oxide) protective layer 15A is further provided thereon. Further, a priming particle release layer 15B is provided on the MgO protective layer 15A. That is, the display electrodes (12, 13) disposed on the front glass substrate 11 are covered with the dielectric layer 14, and the surface thereof is further covered with the MgO protective layer 15A, and the surface thereof is the priming particle emitting layer 15B. Covered.

  Address electrodes 17R, 17G, and 17B are formed on the rear glass substrate 16 disposed to face the front glass substrate 11 in a direction orthogonal to the display electrodes (12, 13). The address electrodes 17R, 17G, and 17B correspond to the address electrode Aj shown in FIG. A dielectric layer 18 is provided on the address electrodes 17R, 17G, and 17B.

  Further, on the dielectric layer 18, closed barrier ribs (ribs) 19 arranged in a lattice pattern, that is, partitioning the discharge space for each cell, and red (R), green (G) for color display, Phosphor layers PR, PG, and PB that emit blue (B) visible light are formed. The phosphor layers PR, PG, and PB are excited by ultraviolet rays generated by surface discharge between the paired display electrodes (12, 13), and each color emits light.

  The barrier ribs 19 include vertical barrier ribs (vertical ribs) formed in the direction in which the address electrodes 17R, 17G, and 17B extend, and horizontal barrier ribs (horizontal ribs) formed in the direction in which the display electrodes (12, 13) extend. That is, the plasma display panel 10 according to the present embodiment has a closed partition structure.

  In the phosphor layers PR, PG, and PB, a phosphor layer PR that emits red light is formed above the address electrode 17R, and a phosphor layer PG that emits green light is formed above the address electrode 17G. A phosphor layer PB that emits blue light is formed above. In other words, the address electrodes 17R, 17G, and 17B are arranged so as to correspond to the red, green, and blue phosphor layers PR, PG, and PB applied to the inner surface of the partition wall 19 corresponding to the cell.

  In the plasma display panel 10, the front glass substrate 11 and the rear glass substrate 16 are sealed so that the protective film 15 and the partition wall 19 are in contact with each other, and the inside thereof (discharge space between the front glass substrate 11 and the rear glass substrate 16). And a discharge gas such as Ne-Xe is enclosed.

  Here, the priming particle emitting layer 15B is a functional film for supplying priming particles and speeding up the address discharge performed in the address period. Constructed using particle release material. Note that the priming particle emitting layer 15B is not limited to being on the MgO protective layer 15A, but may be disposed anywhere in the discharge space so as to be exposed to the discharge space. By providing the priming particle emitting layer 15B, the discharge delay of the address discharge can be suppressed even when the rest period from the previous discharge to the address discharge is long.

  As an example, the effect of suppressing the discharge delay of the address discharge in the plasma display in which the priming particle emitting layer 15B is formed using MgO crystal added with fluorine will be described below.

First, the priming particle release layer 15B was formed as follows.
MgO crystal (Ube Materials Co., Ltd., trade name: high-purity ultrafine powder magnesia (2000A)) and MgF ₂ (magnesium fluoride) (Furuuchi Chemical Co., Ltd., purity: 99.99%) Using a mortar and pestle, it was pulverized into powder. Then, the aggregated and crushed MgO crystal and MgF ₂ were weighed and mixed with a tumbler mixer so that the mixed amount (mol%) of MgF ₂ was 0.01.
Next, the mixture was fired at 1450 ° C. in the air for 1 hour, and then the fired powder was agglomerated and pulverized into a powder form to obtain an MgO crystal to which fluorine was added. In addition, as a result of measuring by combustion ion chromatograph analysis, the addition amount of the fluorine was 80 ppm.

The MgO crystal added with fluorine prepared as described above is mixed at a ratio of 2 g to 1 L of IPA (manufactured by Kanto Chemical Co., Ltd., for electronics industry), and dispersed with an ultrasonic disperser for coagulation disintegration. To prepare a slurry. This slurry was spray-coated on the MgO protective layer 15A using a spray gun for coating, and then a process of spraying dry air and drying it was repeated several times to form a priming particle release layer 15B. The priming particle emitting layer 15B was formed so that the weight of the MgO crystal to which fluorine was added was ² g per 1 m ² .

Other configurations of the plasma display panel were as follows.
Display electrode 12 width: 95 μm
Display electrode 13 width: 270 μm
Discharge gap width: 100 μm
Dielectric layer 14: formed by coating and firing a low melting glass paste, thickness: 30 μm
MgO protective layer 15A: formed by electron beam evaporation, thickness: 7500 mm
Address electrode 17 width: 70 μm
Dielectric layer 18: formed by coating and firing a low melting glass paste, thickness: 10 μm
The thickness of the phosphor layer right above the address electrode 17: 20 μm
Phosphor layer material: Zn ₂ SiO ₄ : Mn (green phosphor)
Partition wall height: 140 μm Top width: 50 μm
Partition pitch 19: 360 μm
Discharge gas: Ne96% -Xe4%, 500 Torr

Next, a discharge delay test was performed on the manufactured plasma display panel.
The discharge delay test was performed using the voltage waveform for measurement shown in FIG. In the reset discharge period, a reset discharge is caused between the X electrode Xi and the Y electrode Yi to initialize the charge state of the dielectric layer, thereby removing the influence of the previous discharge. In the preliminary discharge period, after a specific cell was selected, a discharge was generated between the X electrode Xi and the Y electrode Yi to excite the priming particle emitting material. Thereafter, after the rest period, a voltage was applied to the address electrode Aj during the address discharge period, and the time from when this voltage was applied until when the discharge was actually started was measured. The time until the start of discharge was measured 1000 times, and the time when the cumulative discharge probability was 90% was defined as the discharge delay.

  The results obtained in this way are shown in FIG. FIG. 16 is a graph showing the relationship between the rest period and the discharge delay for a plasma display panel manufactured using an MgO crystal to which fluorine is added. For comparison, FIG. 16 also shows the relationship between the rest period and the discharge delay for a plasma display panel manufactured using an MgO crystal without addition of fluorine (no addition).

  As is clear from FIG. 16, in the plasma display panel manufactured using the MgO crystal body added with fluorine (fluorine addition amount 80 ppm), the plasma display panel manufactured using the MgO crystal body not added with fluorine is used. In comparison, it can be seen that the discharge delay is short even when the rest period is long. It can be seen that in the plasma display panel manufactured using the MgO crystal with the fluorine addition amount of 80 ppm, the discharge delay does not deteriorate significantly until the rest period is about 100 ms.

FIG. 3 is a diagram for explaining the arrangement of display electrodes in the plasma display panel 10 according to the present embodiment.
Vertical barrier ribs 19A are formed on both sides of an address electrode Aj (not shown), and horizontal barrier ribs 19B are formed so as to intersect with the vertical barrier ribs 19A. Discharge spaces are partitioned by the vertical barrier ribs 19A and the horizontal barrier ribs 19B to form cells, and display lines are formed by a plurality of cells arranged in the horizontal direction (the direction in which the horizontal barrier ribs 19B extend).

  A display electrode composed of the bus electrode 12 and the transparent electrode 13 is formed in the direction in which the horizontal partition wall 19B extends, and a pair (two) of display electrodes (for each display line) without sharing the display electrode with the adjacent display line ( 12, 13) are arranged. The display electrodes (12, 13) are arranged such that the arrangement positions of the X electrode and the Y electrode are reversed with respect to adjacent display lines. For example, as shown in FIG. 3, if the X electrode X (2n + 1) and the Y electrode Y (2n + 1) are arranged in this order on the (2n + 1) th display line, the (2n + 2) th display line adjacent to the X electrode X (2n + 1) , Y electrode Y (2n + 2), and X electrode X (2n + 2) are arranged in this order. That is, X electrodes or Y electrodes in adjacent display lines are arranged adjacent to each other across the horizontal partition wall 19B.

  FIG. 4 is a diagram for explaining an example of a driving method of a general plasma display panel. One frame (odd frame or even frame) is composed of a plurality of subframes (SF). Although FIG. 4 illustrates a configuration in which one frame is composed of six subframes SF1, SF2, SF3, SF4, SF5, and SF6 for convenience of drawing, it is usually composed of 10 to 12 subframes. The configuration is common.

  Each subframe SF1 to SF6 includes a reset period, an address period, and a sustain period. In the reset period, initialize the wall charge state on the electrode, select the cell to be lit by adjusting the wall charge state based on the display data in the address period, and turn on the cell corresponding to the display data in the sustain period (The cell selected according to the display data is caused to discharge light). By selecting which subframes SF1 to SF6 are lit, gradation expression is realized.

  FIG. 5 is a diagram for explaining an example of a driving method of the plasma display device in the present embodiment. In FIG. 5, interlace driving in one-line display, that is, in odd frames, odd display lines are lit and even display lines are not lit, and in even frames, even display lines are lit and odd display lines are not lit. An example is shown.

  FIG. 5A is a diagram illustrating an example of a driving configuration of the plasma display device in the present embodiment. In FIG. 5A, for the convenience of drawing, the odd-numbered frame and the even-numbered frame are configured by four subframes.

In the interlace drive with one line display in this embodiment, in the odd frame in which the sustain discharge is performed only for the odd display lines and only the odd display lines are lit, the reset is performed in all cells with respect to the odd display lines in the first subframe. All cell reset R _ALL to be discharged is performed. In subframes other than the first subframe, an on-cell reset R _ON is performed in which reset discharge is performed only in cells that are lit in the sustain period of the previous subframe, that is, cells that have undergone sustain discharge.

In the even frame where only the even display lines are subjected to sustain discharge and only the even display lines are lit, the all cell reset R _ALL is performed on the even display lines in the first subframe, and the subframes other than the first subframe are subsidized. An on-cell reset R _ON is performed in the frame.

That is, in interlaced driving in one-line display, as shown in FIG. 5B, in odd-numbered frames n + 1, n + 3, n + 5,. All-cell reset R _ALL is performed, and on-cell reset R _ON is performed except for the first subframe. In the odd frames n + 1, n + 3, n + 5,..., The even display lines are in a resting state.

Similarly, in even frames n + 2, n + 4, n + 6,... With even frame numbers, all-cell reset R _ALL is performed once for each frame with respect to even display lines, and on-cell reset R is performed except for the first subframe. _Turn on. In the even frames n + 2, n + 4, n + 6,..., The odd display lines are in a resting state.

  FIG. 6 is a diagram for explaining another example of the driving method of the plasma display device in the present embodiment. FIG. 6 shows an example in which interlace driving is performed in a 2-line display, and more specifically, a 2-line display is partially performed. That is, in the example shown in FIG. 6, in the odd frame, the odd display line is lit and the even display line is lit in a partial period, and in the even frame, the even display line is lit and in a partial period. Turn on odd display lines. Note that the partial period may be the whole of an arbitrary subframe among the subframes constituting the frame, or may be a part of the subframe.

  FIG. 6A is a diagram showing another example of the driving configuration of the plasma display device in the present embodiment. In FIG. 6A, for the convenience of drawing, the odd-numbered frame and the even-numbered frame are configured by four subframes.

  In the example shown in FIG. 6A, in the odd frame, the same display data is written to the (2n + 1) th line which is an odd display line and the (2n + 2) th line which is an even display line. The same display data is written to the (2n + 3) th line as the display line and the (2n + 4) th line as the even display line. In the even frame, the same display data is written to the (2n + 2) th line which is an even display line and the (2n + 3) th line which is an odd display line.

In the example of interlace driving in the two-line display shown in FIG. 6, in the case of an odd frame, the all-cell reset R _ALL is performed on the odd display line in the first subframe. On-cell reset _RON is performed in subframes other than the first subframe for odd display lines and in all subframes for even display lines.

Similarly, in the case of an even frame, all cell reset R _ALL is performed on the even display line in the first subframe. On-cell reset _RON is performed in subframes other than the first subframe for even display lines, and in all subframes for odd display lines.

That is, in the interlace driving in the two-line display, as shown in FIG. 6B, in the odd frames n + 1, n + 3, n + 5,. All-cell reset R _ALL is performed, but only on-cell reset R _ON is performed for even display lines. On the other hand, in even frames n + 2, n + 4, n + 6,... With even frame numbers, all-cell reset R _ALL is performed once for each frame for even display lines, but on-cell reset is performed for odd display lines. Do only R _ON .

That is, in the example shown in FIG. 6, the odd display lines all-cell reset R _ALL is performed for the odd frame and the even display line all-cell reset R _ALL is performed to even-numbered frame. Thereby, even if it is the interlace drive in 2 line display, it can suppress that the frequency | count of all the cell resets increases, it can prevent that background luminance becomes high and can suppress the fall of display quality. In addition, when all-cell reset R _ALL is performed as shown in FIG. 6, the number of times of all-cell reset R _ALL per unit time is the same as the interlace drive in one line display shown in FIG. Therefore, even if the 1-line display state and the 2-line display state are switched while the display operation is continued, the background luminance does not change and the occurrence of switching shock can be prevented, and an image display without a sense of incongruity can be performed. it can.

Note that the execution of the all-cell reset R _ALL in the interlace drive in the two-line display shown in FIG. 6 is an example, and the present invention is not limited to this, and various modifications are possible. For example, the all-cell reset R _ALL may be performed on both the odd display line and the even display line in the first subframe of one of the odd frame and the even frame. You may make it perform one all-cell reset _RALL with respect to each display line at random during the period which match | combined the even frame.

  FIG. 7 is a diagram for explaining another example of the driving method of the plasma display device in the present embodiment. FIG. 7 shows another example of interlace driving in a two-line display. FIG. 7A shows another example of the driving configuration of the plasma display device in the present embodiment, and FIG. 7B shows the reset setting in the driving configuration shown in FIG. 7A.

In the example shown in FIG. 7, all-cell reset R _ALL is performed on both the odd display line and the even display line in the first subframe of the odd frame, and the subframe and even frame other than the top of the odd frame are performed. On-cell reset R _ON is performed in all the subframes. Even if it is shown in FIG. 7, it can suppress that the frequency | count of all the cell resets increases, it can prevent that background brightness | luminance becomes high and can suppress the fall of display quality. In addition, since the number of all cell resets R _ALL per unit time is the same as that for interlaced driving in one line display, the background can be switched between the one line display state and the two line display state while continuing the display operation. Luminance does not change, and switching shock can be prevented.

In the above-described example, the all-cell reset R _ALL is performed in the first subframe in one of the odd frame and the even frame, but the present invention is not limited to this. That is, the present invention is not limited to performing all cell reset R _ALL once in a period of two frames including an odd frame and an even frame, but one cell per arbitrary unit time including a plurality of frames. A reset R _ALL may be performed.

As shown in FIG. 16, in the plasma display panel in which the discharge delay is not greatly deteriorated until the rest period from the previous discharge to the address discharge is about 100 ms, all the frames up to 6 frames (1 frame time is 16.6 ms) Even if the cell reset is not performed and the black display (cell non-lighting) continues and the on-cell reset does not operate, it can be driven normally. That is, for example, even if the all-cell reset R _ALL is performed once per time of 6 frames, it can be driven normally.

  8A and 8B are diagrams illustrating examples of driving waveforms of the plasma display device according to the present embodiment. FIG. 8A and FIG. 8B show driving waveforms of interlaced driving in a two-line display, and show examples of driving waveforms related to the X electrode Xi, the Y electrode Yi, and the address electrode Aj in an odd frame. FIG. 8A shows drive waveforms in the first subframe (first subframe) SF1 and the second subframe SF2 of the odd-numbered frame, and FIG. 8B shows the third waveform of the odd-numbered frame following FIG. 8A. The drive waveforms after subframe SF3 are shown. 8A and 8B, ADD is a voltage waveform related to the address electrode Aj, Yo is a voltage waveform related to the Y electrode Yi of the odd display line, X is a voltage waveform related to the X electrode Xi, and Ye is Y of the even display line. The voltage waveform concerning the electrode Yi is shown.

In the reset period of the first subframe SF1, a reset pulse of voltage (2Vs + Vw) is applied to the Y electrode Yi of the odd display line, whereby the all cell reset R _ALL is performed on the odd display line. On the other hand, by applying a reset pulse (Vw> low Vw) of voltage (2Vs + low Vw) to the Y electrode Yi of the even display line, an on-cell reset _RON is performed for the even display line. In each reset period after the second subframe SF2, a reset pulse of voltage (2Vs + low Vw) is applied to the Y electrodes Yi of the odd display lines and the even display lines, thereby turning on each display line. Cell reset R _ON is performed.

  In the example shown in FIGS. 8A and 8B, in the first and second subframes SF1 and SF2, the Y electrode Yi of the even display line is in a high impedance state, and one line display is performed only by the odd display line. Yes. In the third and subsequent subframes, the sustain electrodes are applied to the Y electrodes Yi of the even display lines in the first half of the sustain period, and the high impedance state is set in the second half. Therefore, in the third and subsequent subframes, two-line display is performed using the odd display lines and even display lines in the first half of the sustain period, and one line display is performed using only odd display lines in the second half of the sustain period. ing.

In FIG. 8A, an on-cell reset R _ON is performed for the even display line by applying a reset pulse of voltage (2Vs + low Vw) to the Y electrode Yi of the even display line in the reset period of the first subframe SF1. However, as shown in FIG. 8C, the Y electrode Yi of the even display line may be set in a high impedance state.

  As described above, two lines are displayed by applying a sustain pulse to the Y electrodes Yi of the odd display lines and even display lines in the first period of the sustain period, and odd display lines or even numbers in the second period. When one line display is performed by applying a sustain pulse only to the Y electrode Yi of one of the display lines, the switch SW1 for connecting the scan circuit (even) 21 and the sustain circuit 23 in the sustain period. The switch SW2 for connecting the scan circuit (odd) 22 and the sustain circuit 23 may be appropriately controlled.

  That is, the switch SW2 is turned on when the sustain pulse is applied to the Y electrode Yi of the odd display line, and the switch SW2 is turned off when the high impedance state is set. When the sustain pulse is applied to the Y electrode Yi of the even display line, the switch SW1 is turned on, and when the high impedance state is set, the switch SW1 is turned off.

  By performing the two-line display as described above, higher luminance can be obtained than the interlace driving by the one-line display. In addition, when a two-line display is partially performed, an intermediate image between the one-line display and the two-line display is obtained. Here, in the case where partial 2-line display is performed, the ratio of the smaller number of sustain discharges to the other discharge number, in other words, the time ratio of the first period of the sustain period to the sustain period, and the 2-line display Let α be the mixing ratio indicating the ratio of (2-line simultaneous lighting). 0 <α <1.

  In other words, as shown in FIG. 9 in which the drive configuration extracted by one subframe is shown, when the luminance when the line that does not reduce the number of sustain discharges is fully lit in one subframe is L, the other line is fully lit. The luminance at this time is αL. Even if there is a manufacturing variation, α is desirably 0.05 or more in order to obtain an improvement in luminance. In order to obtain the effect of improving the brightness, α is preferably 0.2 or more. On the other hand, in order to obtain the effect of improving the resolution, α is preferably 0.8 or less, and more preferably α is 0.5 or less.

Hereinafter, an example of a method for setting the mixing ratio α will be described.
In the example shown below, the mixing rate α is linearly changed with respect to the change in the display load factor of the plasma display panel. It may be non-linear.

(1) As shown in FIG. 10, when the display load factor of the plasma display panel is higher than a certain value (first threshold value), the mixing rate α for two-line lighting is set to 0, and the first Below the threshold, the mixing rate α is gradually increased as the display load factor decreases.

  When performing two-line display, the luminance per unit sustain period increases in proportion to the mixing rate α of two-line lighting, but the luminous efficiency is substantially equal. On the other hand, in an ordinary plasma display panel, APC (automatic power control) control as shown in FIG. 11 is performed.

  Hereinafter, APC control in the plasma display panel will be described. Since the essence of the discussion is not changed, for the convenience of explanation, the power consumption of the plasma display panel is only the power consumed in the sustain period. Here, the power consumed in the sustain period is composed of discharge power that directly contributes to light emission and reactive power consumed when charging and discharging the capacitance between the electrodes. FIG. 11 shows the relationship between the maximum luminance (the luminance at the maximum gradation) and the power consumption with respect to the display load factor. The maximum brightness and reactive power are approximately proportional to the sustain frequency, and below the APC point (usually the display load factor is 10% to 20%), the sustain frequency (maximum brightness and reactive power) is kept constant. Above, the sustain frequency (maximum luminance and reactive power) decreases with increasing display load factor. On the other hand, the total power increases as the display load factor increases below the APC point, and the total power remains constant above the APC point. The above is the usual APC control.

  Therefore, even if 2-line lighting is performed in a region with a high display load factor (for example, a region above the APC point) in which control is performed so as to keep the total power constant, the brightness is reduced only by the resolution being reduced with respect to 1-line lighting. There is almost no rise effect. This is because the luminance per sustain cycle is approximately doubled by turning on the two lines, but the power consumption also increases. Therefore, under the control that the total power is constant, the sustain frequency when the two lines are turned on is 1. This is because the maximum luminance is hardly increased as a result because it is lower than the sustain frequency at the time of line lighting.

  Due to such circumstances, the two-line lighting control is performed when the display load factor of the plasma display panel is equal to or lower than the first threshold value. As an example, in a region where the display load factor is lower than the APC point, the maximum luminance (maximum gradation) with respect to the display load factor when control is performed so as to increase the mixing rate α of 2-line lighting as the display load factor decreases. The luminance at the time) and the mixing ratio α are shown in FIG. In a region where the display load factor is lower than the APC point, the maximum luminance is also increased by increasing the mixing rate α of the two-line lighting in accordance with the display load factor.

(2) As shown in FIG. 13, the two-line lighting control is not performed in the lower subframe with a lighter luminance weight (FIG. 13A), and the two-line lighting control is performed only in the upper subframe with a higher luminance weight. (FIG. 13B). In other words, in the lower subframe, the mixing rate α for two-line lighting is always 0 regardless of the display load factor of the plasma display panel. In the upper subframe, when the display load factor is higher than a certain value (first threshold value), the mixing rate α for lighting the two lines is set to 0, and the display load factor is less than the first threshold value. The mixing rate α is gradually increased as it decreases.

  In the setting method (1) described above, the mixing rate α for two-line lighting is controlled uniformly in all subframes, but the number of sustain discharges (the number of sustain pulses) is small in the lower subframe with a light luminance weight. For this reason, the effect of performing the two-line lighting is small (the driving time does not increase much even if the total number of pulses is increased to increase the luminance while the one-line lighting is maintained). Rather than performing two-line lighting in the lower subframe, reducing the minimum luminance is more important for fine gradation output. Therefore, in the lower subframe, the control of the two-line lighting is not performed as shown in FIG. 13A, and the two-line lighting in accordance with the display load factor is shown in the upper subframe as shown in FIG. Take control.

(3) As shown in FIG. 14, when the display load factor of the plasma display panel is equal to or lower than the first threshold value, the mixing rate α is gradually increased as the display load factor decreases and is higher than the first threshold value. Below the second threshold value, the mixing rate α for 2-line lighting is set to 0, and when it is higher than the second threshold value, the mixing rate α is gradually increased as the display load factor increases.

  In the high display load factor region, as described above, in APC control, control is performed so as to keep the total power constant. Therefore, there is no significant luminance improvement due to lighting of two lines. However, when one line is lit, there is reactive power consumption due to charging / discharging to the line capacity even if the non-lighting line is not lit. Therefore, when the two-line lighting is performed, the value of the reactive power with respect to the number of lighting cells is reduced, so that the luminance can be increased by the reactive power reduction. Further, in the region where the display load factor is near 100%, the entire screen is close to a white color, so that the resolution is not so necessary.

  Therefore, in a region where the display load factor that does not require so much resolution is in the vicinity of 100%, the reactive power can be reduced and the luminance can be improved by increasing the mixing rate α of the two-line lighting according to the display load factor. Become.

  Moreover, in the example mentioned above, although the mixing rate (alpha) can take all the values of the range of 0-1, this invention is not limited to this. For example, the mixing ratio α may be controlled so as not to be a value of 0.2 or less, or may be controlled so as not to be a value of 0.8 or more.

  In addition, each of the above-described embodiments is merely an example of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

It is a figure which shows the structural example of the plasma display apparatus by embodiment of this invention. It is a figure which shows the structural example of the plasma display panel in this embodiment. It is a figure for demonstrating arrangement | positioning of the display electrode in the plasma display panel in this embodiment. It is a figure for demonstrating the drive method of a plasma display panel. It is a figure for demonstrating an example of the drive method of the plasma display apparatus in this embodiment. It is a figure for demonstrating the other example of the drive method of the plasma display apparatus in this embodiment. It is a figure for demonstrating the other example of the drive method of the plasma display apparatus in this embodiment. It is a figure which shows an example of the drive waveform of the plasma display apparatus in this embodiment. It is a figure which shows an example of the drive waveform of the plasma display apparatus in this embodiment. It is a figure which shows the other example of the drive waveform of the reset period in this embodiment. It is a figure for demonstrating the structure of the sub-frame in this embodiment. It is a figure which shows an example of the mixing rate control of 2 line lighting. It is a figure for demonstrating APC control. It is a figure which shows an example of the mixing rate control of 2 line lighting. It is a figure which shows the other example of the mixing rate control of 2 line lighting. It is a figure which shows the other example of the mixing rate control of 2 line lighting. It is a figure which shows the voltage waveform used for the discharge delay test. It is a figure which shows the relationship between an idle period and a discharge delay about the plasma display panel manufactured using the MgO crystal | crystallization which added the fluorine.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Plasma display panel 20 Y electrode driver 21, 22 Scan circuit 23 Sustain circuit 24 Reset circuit 30 X electrode driver 31 Sustain circuit 40 Address driver 51 Halftone generation circuit 52 Sub-frame conversion circuit 53 Display load factor detection circuit 54 Reset setting circuit 55 Sustain pulse number setting circuit 56 Drive signal generation circuit SW1, SW2 switch

Claims (10)

A plasma display panel in which display electrode pairs of even display lines and display electrode pairs of odd display lines are alternately arranged;
In the first mode, in each frame, a sustain pulse is applied to one of the display electrode pairs of the even display lines or the display electrode pair of the odd display lines to perform interlace driving, and in the second mode, A drive unit for interlaced driving by applying a sustain pulse and writing the same data with two display electrode pairs of the even display line and the odd display line adjacent to each other as a set;
When driving in the second mode, all-cell reset in which reset discharge for initializing the wall charge state on the electrode is performed in all cells is performed once per unit time including a plurality of frames. A plasma display device. A display load factor detecting unit for detecting a display load factor of the plasma display panel;
2. The plasma display panel is driven by selecting the first mode or the second mode according to a display load factor detected by the display load factor detector. Plasma display device.   When the display load factor detected by the display load factor detector is higher than a threshold value, the first mode is selected, and when the display load factor is less than the threshold value, the second mode is selected. The plasma display device according to claim 2.   4. The plasma display device according to claim 1, wherein the number of executions of the all-cell reset per unit time is the same in the first mode and the second mode. 5. . The frame is composed of a plurality of subframes,
When driving in the second mode, the frame for performing the all-cell reset and the frame for performing only the on-cell reset for performing the reset discharge only with the cells lit in the immediately preceding sub-frame are alternated. The plasma display device according to claim 1, wherein the plasma display device is driven.   The all-cell reset is performed only for the odd-numbered display lines in an odd frame, and the all-cell reset is performed only for the even-numbered display lines in an even frame. 2. The plasma display device according to item 1.   7. The plasma display panel according to claim 1, further comprising a priming particle emission layer disposed so as to be exposed to a discharge space between two substrates sealed opposite to each other. The plasma display device described.   8. The plasma display device according to claim 7, wherein the priming particle emitting layer includes a magnesium oxide crystal to which 1 to 10,000 ppm of a halogen element is added.   9. The plasma according to claim 1, wherein when driving in the first mode, the scan electrode of the other display electrode pair to which the sustain pulse is not applied is set to a high impedance state. Display device. A driving method of a plasma display device having a plasma display panel in which display electrode pairs of even display lines and display electrode pairs of odd display lines are alternately arranged,
Detecting the display load factor of the plasma display panel, and selecting the first mode or the second mode according to the detected display load factor;
In the first mode, in each frame, a sustain pulse is applied to one of the display electrode pair of the even display line or the display electrode pair of the odd display line to perform interlace driving,
In the second mode, the same data is written with two display electrode pairs of the even-numbered display line and the odd-numbered display line adjacent to each other as a set, and a sustain pulse is applied to perform interlace driving.
In the case of driving in the second mode, all-cell reset in which reset discharge for initializing the wall charge state on the electrode is performed in all cells is performed once per unit time including a plurality of frames. A driving method of a plasma display device.

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