JP2009123905A - Method of manufacturing multilayer wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a multilayer wiring board in which a conductor layer can be uniformly formed on an external insulating layer by electrolytic plating with good operability without causing a defect such as a flaw. <P>SOLUTION: When the external insulating layer 30 is laminated on at least one surface of an internal layer circuit board 10, the end of the internal layer circuit board is extended out beyond the edge of an external insulating layer, an exposed conductor portion 20 is formed at the extended end, and one or more vias 47 reaching the conductor wiring circuit pattern of the internal layer circuit board are formed in an external layer substrate 55', a conductive layer 52 connected to the conductor wiring circuit pattern of the internal layer circuit board is formed on the internal surface of the via, and a feeding conductor layer 52A connecting the exposed conductor portion or conductor wiring electrically connected to the exposed conductor portion to an external layer board surface is formed. Electric power is fed from the exposed conductor portion of the feeding internal layer circuit board through the conductor layer for electric power feeding, and the via internal surface and the surface of the external layer substrate are subjected to electrolytic plating. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a multilayer wiring board configured by laminating one or more outer layer circuit boards on an inner layer circuit board.

  In recent years, electrical devices have been reduced in size and weight, and the wiring boards used therefor are also required to be reduced in size and mounted in high density. As a conventional wiring board of this type, for example, a build-up method for manufacturing a multilayer wiring board by alternately stacking insulating layers and conductor layers (wiring layers) is known.

  The general build-up method will be described. An outer layer insulating layer and a conductor layer are sequentially stacked on an inner layer circuit board formed by forming a circuit pattern on the inner layer insulating substrate, and the circuit pattern is formed on the outer layer insulating layer and the conductor layer. A via that communicates with is formed. Then, the inner circumference of the via is made conductive by means such as electroless plating, and electrolytic plating is performed while energizing the conductor layer and the inner circumference of the via by the power feeding means. By removing unnecessary portions of the electrolytic plating layer thus obtained by etching or the like, a predetermined conductor pattern is formed, and a multilayer wiring board is manufactured.

  By the way, when the outer layer substrate is configured by laminating necessary members such as the outer layer insulating layer on the inner layer circuit substrate, the inner layer circuit substrate is hidden by the outer layer substrate, and is applied to the conductor layer of the outer layer substrate for electrolytic plating. When energizing, it was necessary to carry out from the outer substrate side. For this reason, for example, in a method of supplying power to the conductor layer of the outer substrate via a metal clip or the like, or in a manufacturing method using a so-called roll-to-roll method, a method of supplying power by bringing the power supply roller into contact with the surface of the conductor layer of the outer substrate Is adopted.

For example, Patent Document 1 below discloses a flexible multilayer wiring board having blind via holes in which insulating layers made of an organic insulating material and conductor layers (wiring layers) made of a conductive material are alternately stacked and connect the upper and lower conductor layers. Disclosed is a roll-to-roll continuous electrolytic plating apparatus that is formed by filling blind via holes with plating metal. Power is supplied by sandwiching the upper and lower surfaces of the conductor layer by a pair of upper and lower power supply rollers, and electrolytic plating is performed. The application is described.
JP 2005-101035 A

  In the case of the above electrolytic plating, if the connection part such as a metal clip is connected to the conductor layer of the outer substrate in the plating solution, the connection part such as the metal clip is also plated. This results in irregularities in the layer. In this case, when a photoresist layer is formed so as to form a predetermined conductor pattern, it may cause flipping, remaining bubbles, unevenness, and the like, thereby hindering normal pattern formation.

  In addition, when the outer layer substrate is not continuously formed on the inner layer substrate and is formed in a plurality of islands, the power feeding means must be connected to each island, which is complicated and efficient. There wasn't. In addition, when the conductor layer is continuously formed, it is possible to take a part out of the plating solution and to supply power from that part. Since plating is not performed, it becomes a useless area | region.

  Furthermore, in the manufacturing method by the roll-to-roll method, the electrolytic plating is continuously performed while being conveyed from the unwinding roll to the winding roll. At this time, as described above, the outer layer substrate is used. Is formed in an island shape, it is not easy to individually connect the power feeding means to the conductor layer of the outer substrate, and power feeding becomes difficult.

  On the other hand, when the continuous outer layer substrates are stacked, as in Patent Document 1, power can be supplied to the conductor layer of the outer layer by a power supply roller provided in the middle of conveyance. However, in this case, the power feeding roller is brought into contact with the outer surface of the conductor layer, and the power feeding roller continuously contacts the conductor layer. Since the feed roller is applied with a cathode voltage, dirt is particularly likely to adhere and accumulate as represented by the deposition of metal ions, which may cause damage to the conductor layer and the electrolytic plating layer and transfer of contamination. As a result, a conductor pattern formed by appropriately etching the conductor layer and the electroplating layer laminated thereon may cause a defect in the conductor pattern. In addition, when the wiring pattern is formed by a semi-additive method in which electrolytic plating is performed on the portion where the conductive pattern is to be formed, the feeding roller contacts the conductive layer in a state where the resist layer is partially formed, Not only does the power supply become unstable, but the resist layer is damaged due to contact with the power supply roller, conversely, the power supply roller is contaminated by the adhesion of the resist, and retransfer of the adhering resist occurs. Many factors occur that inhibit formation.

  Accordingly, an object of the present invention is to provide a method for manufacturing a multilayer wiring board in which a conductor layer by electrolytic plating can be formed on an outer layer substrate and in a via with good workability and without causing defects such as scratches. There is to do. Furthermore, the objective of this invention is providing the manufacturing method of the multilayer wiring board which enabled it to form continuously the high quality electroplating conductor layer corresponding to fine wiring on an outer layer board | substrate by the roll-to-roll process. .

  To achieve the above object, the present invention provides an inner layer circuit board in which a conductor wiring circuit pattern is formed on at least one side of an inner layer insulating substrate, and an outer layer circuit in which a conductor wiring circuit pattern is formed on at least one side of an outer layer insulating layer. A multilayer wiring board in which one or more outer layer circuit boards are stacked on at least one side of the inner layer circuit board, and the outer insulating layer is stacked on at least one side of the inner layer circuit board. In this case, an end portion of the inner layer circuit board is extended outward from an edge of the outer layer insulating layer, and an exposed conductor portion is formed on the extended end portion, and at least the outer layer insulating layer is laminated. One or more vias reaching the conductor wiring circuit pattern of the inner layer circuit board are formed in the outer layer board formed, and the inner surface of the via is connected to the conductor wiring circuit pattern of the inner layer circuit board. Forming a conductive layer for feeding between the exposed conductor portion or the conductor wiring electrically connected to the exposed conductor portion and the outer layer substrate surface, and feeding power from the exposed conductor portion of the inner layer circuit board. The present invention provides a method for manufacturing a multilayer wiring board, wherein the inner surface of the via and the surface of the outer layer substrate are electroplated by energizing through a power supply conducting layer.

  According to the present invention, an exposed conductor layer is formed on an end portion of the inner layer circuit board that extends outward from the edge of the outer insulating layer, and is formed on at least the outer substrate on which the outer insulating layer is laminated. A conductive layer connected to the conductor wiring circuit pattern of the inner layer circuit board is formed on the inner surface of the via, and the exposed conductor portion of the inner layer circuit board or the conductor wiring electrically connected to the exposed conductor portion and the outer layer substrate surface Since the conductive layer for power supply to be connected is formed, the power is supplied from the exposed conductor portion of the inner layer circuit board and the current is supplied through the conductive layer for power supply, so that the electrolytic plating is performed. It is possible to form a uniform electrolytic plating layer without any defects. In addition, since the power feeding means does not contact the surface of the outer layer substrate, it is possible to prevent the pattern forming portion of the outer layer substrate from being damaged and causing defects. Furthermore, it is formed on the conductor layer or conductive layer on the surface of the outer layer substrate and further on the inner surface of the via through the conductive layer for power supply that connects the exposed conductor portion or the conductor wiring electrically connected to the exposed conductor portion and the surface of the outer layer substrate. Thus, even if the outer substrate is separated into islands, it is possible to energize through the conductive layer for power supply from the exposed conductor.

  In a preferred aspect of the present invention, the outer substrate has a conductor layer on the outer surface of the outer insulating layer, penetrates the conductor layer, forms the via in the outer insulating layer, and includes at least the via. The conductive layer is formed on the inner surface, and a power supply conductive layer is formed to connect the exposed conductor portion or the conductor wiring electrically connected to the exposed conductor portion and the conductor layer on the outer layer substrate surface. According to this aspect, since a conductor layer previously formed on an insulating layer can be used, a conductor layer formed with the best forming means can be used with few restrictions, and the adhesion strength is high and durable. This makes it easier to make good outer layer conductor wiring with few defects.

  According to another preferred embodiment of the present invention, the outer substrate does not have a conductor layer on the outer surface of the outer insulating layer, and after the via is formed, on the inner surface of the via and the surface of the outer substrate. In addition to forming the conductive layer, a power supply conductive layer is formed which is continuous with the conductive layer formed on the surface of the outer substrate and connects the exposed conductor portion or the conductor wiring electrically connected to the exposed conductor portion. According to this aspect, an insulating layer without a conductor layer can be used as the outer layer substrate, and since it is not necessary to form a conductor layer in advance, the total process can be simplified.

  In another preferred aspect of the present invention, the conductive layer for power feeding is formed on a part or the whole of the outer peripheral surface of the outer layer board in contact with the exposed conductor part of the inner layer circuit board, and the exposed conductor part of the inner layer circuit board. More power is supplied, and current is supplied through the power supply conductive layer on the outer peripheral surface of the outer substrate. According to this aspect, the power supply conductive layer can be formed simultaneously with the conductive layer forming step in the via without taking any special means, and a sufficiently wide power supply path from the exposed conductor portion can be obtained.

  In another preferred aspect of the present invention, an inner layer conductor wiring electrically connected to the exposed conductor portion is provided, and a via is formed through the inner layer conductor wiring and the outer layer substrate surface. A conductive layer for power supply is formed to connect the wiring and the surface of the outer layer substrate. Electricity is supplied from the exposed conductor portion of the inner layer circuit board and is supplied through the conductive layer for power supply in the via. According to this aspect, it is possible to obtain a power feeding path from the exposed conductor portion simultaneously with the conductive layer forming step in the via. For example, from the exposed conductor portion formed only on one surface of the inner layer substrate, both of the inner layer substrate can be obtained. It is possible to deal with various configurations such as supplying power to the outer substrate formed on the surface.

  In the present invention, the step of performing electrolytic plating on the inner surface of the via and the outer layer substrate is performed by a roll-to-roll method by supplying power from the exposed conductor portion of the inner layer circuit board and energizing through the conductive layer for power supply. The substrate is preferably made of a tape drawn continuously from the take-up roll, and it is preferable to apply electroplating by energizing through a power supply roller in contact with the exposed conductor formed on both sides of the tape. According to this aspect, since it can be energized by the power supply roller without contacting the outer layer surface with respect to the moving tape, it is possible to suppress the occurrence of contamination and scratches, particularly to suppress the occurrence of contamination and scratches on the outer layer surface, It can be applied to a roll-to-roll system with high productivity and stable processing quality. Note that the term “base material” as used herein refers to a state in which the outer layer substrate is laminated on the inner layer circuit substrate in the above-described step and the conductive layer (including the power supply conductive layer) is formed.

  In addition, it is preferable that the power supply roller is an introduction portion and / or a lead-out portion with respect to the plating bath, and is brought into contact with the exposed conductor layer at a position not in contact with the plating solution. According to this aspect, since the power supply roller does not contact the plating solution, durability is improved, and an unnecessary plating layer can be prevented from being formed due to the contact of the power supply roller with the plating solution. As a result, it is possible to prevent power supply failure and damage to the outer layer substrate surface due to the roughening of the power supply roller.

  In a further preferred aspect of the present invention, the step of forming the conductive layer is performed by electroless metal plating or direct plating. According to this aspect, it is possible to efficiently form a conductive layer necessary for electrolytic plating by energization. When an outer layer substrate having a conductor layer on the outer surface of the outer layer insulating layer is used, the conductive layer may be formed on the inner surface of the via or the outer surface of the outer layer substrate (the feed path is in the thickness direction). The direct plating method, which is slightly expensive but has a low environmental impact and is easy to process, is particularly suitable. When an outer insulating layer without a conductor layer is used for the outer substrate, a conductive layer is formed over a wide area of the outer substrate surface. Since it is necessary, electroless metal plating with low electric resistance can be used particularly suitably.

  In the present invention, it is preferable that the via is formed by drilling, and a cleaning process for residues in the via generated by the drilling is performed by physical cleaning. According to this, by performing physical cleaning, the processing residue remaining on the inner surface of the via can be removed, and the inner surface of the via can be cleaned. As a result, for example, the conductive layer can be formed in a state of being firmly adhered to the inner surface of the via.

  Furthermore, the physical cleaning method is preferably selected from a wet blast method, a deep ultraviolet light irradiation method of 250 nm or less, and a plasma treatment method. According to this, it is possible to efficiently clean the via by appropriately selecting a cleaning method according to the purpose.

  The present invention also includes an inner layer circuit board in which a conductor wiring circuit pattern is formed on at least one side of the inner layer insulating substrate, and an outer layer circuit board in which a conductor wiring circuit pattern is formed on at least one side of the outer layer insulating layer. In the method of manufacturing a multilayer wiring board in which one or more outer layer circuit boards are stacked on at least one side of the inner layer circuit board, the outer layer insulating layer is stacked on at least one side of the inner layer circuit board. An outer layer substrate in which an end portion of an inner layer circuit board is extended outward from an edge of the outer layer insulating layer, an exposed conductor is formed on the extended end portion, and at least the outer layer insulating layer is laminated. Forming one or more vias leading to the conductor wiring circuit pattern of the inner layer circuit board, and forming a conductive layer connected to the conductor wiring circuit pattern of the inner layer circuit board on the inner surface of the via And forming a conductive layer for feeding to connect the exposed conductor portion and the outer layer substrate surface to a part or the whole of the outer peripheral surface of the outer layer substrate in contact with the exposed conductor portion of the inner layer circuit board, and from the take-up roll to the tape An exposed conductor portion of the inner layer circuit board through a feed roller that contacts the exposed conductor portion formed on both sides of the tape while the tape is conveyed by a roll-to-roll method in which the base material is continuously drawn. It is preferable to continuously perform electrolytic plating on the inner surface of the via and the surface of the outer layer substrate by supplying more power and supplying current through the conductive layer for power supply. According to this method for manufacturing a multilayer wiring board, it is not necessary to take any special means, and a conductive layer for feeding can be formed on the outer peripheral surface.

  The present invention also includes an inner layer circuit board in which a conductor wiring circuit pattern is formed on at least one side of the inner layer insulating substrate, and an outer layer circuit board in which a conductor wiring circuit pattern is formed on at least one side of the outer layer insulating layer. In the method of manufacturing a multilayer wiring board in which one or more outer layer circuit boards are stacked on at least one side of the inner layer circuit board, the outer layer insulating layer is stacked on at least one side of the inner layer circuit board. An outer layer substrate in which an end portion of an inner layer circuit board is extended outward from an edge of the outer layer insulating layer, an exposed conductor is formed on the extended end portion, and at least the outer layer insulating layer is laminated. Is laminated so as to cover a part of the exposed conductor part so that a part of the outer peripheral surface is in contact with the exposed conductor part, and one or more vias reaching the conductor wiring circuit pattern of the inner layer circuit board are formed on the outer layer board. And a conductive layer connected to the conductor wiring circuit pattern of the inner layer circuit board is formed on the inner surface of the via and exposed to a part or the whole of the outer peripheral surface of the outer layer board in contact with the exposed conductor portion of the inner layer circuit board. A conductive layer for power supply that connects the conductor part and the outer layer substrate surface is formed, and the base material made of tape is continuously drawn from the take-up roll, and the tape is conveyed to both sides of the tape while being transported. By supplying power from the exposed conductor portion of the inner layer circuit board through the feeding roller that contacts the formed exposed conductor portion and energizing through the conductive layer for feeding, the inner surface of the via and the surface of the outer layer substrate are continuously provided. It is preferable to apply electrolytic plating. With this multilayer wiring board manufacturing method, it is not necessary to take any special measures, and a conductive layer for power feeding can be formed on the outer peripheral surface, and the metal of the inner layer is removed except for a part of the inner layer. Is superior to.

  Furthermore, the outer layer substrate has a conductor layer on the outer surface of the outer layer insulating layer, and has a portion where the distance between the outer peripheral surface not in contact with the exposed conductor portion and the exposed conductor portion is 10 times or more the thickness of the outer layer substrate. The conductive layer and the power supply conductive layer are preferably formed by a direct plating method. By using this method for manufacturing a multilayer wiring board, it is not necessary to take any special means, and a conductive layer for power feeding can be formed on the outer peripheral surface, and the inner layer metal is removed except for a part of the inner layer, and the exposed conductor layer Electrolytic plating is suppressed by increasing the resistance value of the portion (inner layer insulating layer exposed portion) that is in contact with the outer layer substrate that is not in contact with the substrate, and the rigidity is reduced, which is advantageous for RtoR conveyance.

  According to the method for manufacturing a multilayer wiring board of the present invention, power is supplied from an exposed conductor layer formed at an end portion of the inner layer circuit board that is extended outward from the edge of the outer insulating layer, and through the feeding conductive layer. Since the inner surface of the via and the surface of the outer layer substrate are energized and subjected to electrolytic plating, a uniform electrolytic plating layer without unevenness can be formed on the inner surface of the via and the outer layer substrate, and pattern formation of the outer layer substrate It is possible to prevent the occurrence of defects such as scratches and contamination in the part, and even if the outer layer substrate is separated into islands, the via inner surface and the outer layer substrate It becomes possible to energize the surface.

  Hereinafter, with reference to FIGS. 1-8, one embodiment of the manufacturing method of the multilayer wiring board by this invention is demonstrated. However, this invention is not restrict | limited by the following embodiment.

  FIG. 1 shows a schematic cross-sectional view of a multilayer wiring board 1 manufactured by the method for manufacturing a multilayer wiring board of the present invention. In this embodiment, the multilayer wiring board 1 includes an inner layer circuit board 10 in which inner layer wiring patterns 15 and 15 are formed on both front and back surfaces of an inner layer insulating substrate 11, and an adhesive layer 25 provided on both front and back surfaces of the inner layer circuit board 10. , 25, outer layer insulating layers 30, 30 laminated on the front and back sides of the inner layer circuit board 10 via the adhesive layers 25, 25, and outer layers formed on the surfaces of the outer layer insulating layers 30, 30, respectively. The wiring patterns 40 and 40 are included.

  With reference to FIG. 1 and FIG. 6, the configuration of each layer of the multilayer wiring board 1 will be described in more detail. First, the inner layer circuit board 10 will be described. Conductor wirings 13 and 13 are respectively formed on the front and back surfaces of the inner layer insulating substrate 11, and a predetermined inner layer wiring pattern 15 is provided thereby. Further, a round hole-shaped via 17 (see FIG. 6) is formed through a predetermined portion of the inner layer insulating substrate 11, and the inner layer insulating substrate 11 is connected via a connection portion 18 provided in the via 17. Inner layer wiring patterns 15, 15 formed on both front and back surfaces are electrically connected.

The inner layer circuit board 10 is typically a copper-clad laminate, a so-called CCL (copper), in which a conductor material such as a copper foil is laminated on an inner layer insulating board 11 made of an insulating material such as a resin film described later. Clad Laminate) is used as a core base material, and an unnecessary portion of a conductive material such as copper foil is etched by a subtractive method or the like to form a predetermined inner layer wiring pattern 15 leaving a necessary conductive wiring 13 The shape is made. As described above, the inner layer circuit board 10 is typically formed by a subtractive method using an etching process, but may be formed by a semi-additive method using electrolytic plating, and the like. Is not to be done. The inner layer circuit board 10 may be formed with an inner layer wiring pattern 15 composed of a plurality of conductor wirings 13 only on one side of the inner layer insulating substrate 11, but on both front and back surfaces of the inner layer insulating substrate 11 as in this embodiment. It is particularly advantageous from the viewpoint of increasing the density if a plurality of conductor wirings 13 are provided and are electrically connected via the connecting portions 18 in the vias 17. The inner diameter of the round hole-shaped via 17 is appropriately set according to the purpose, but it is preferably 10 to 100 μm from the viewpoint of high density, and 20 to 100 μm from the viewpoint of stable via connection. More preferred. In addition, a round hole shape is desirable from the viewpoint of stress dispersion, but a shape other than a round shape such as a square hole may be used depending on the design.

  The material of the inner layer insulating substrate 11 is not particularly limited, but the inner layer insulating substrate 11 is formed of a component containing a synthetic resin, and the plurality of conductor wirings 13 constituting the inner layer wiring pattern 15 formed on the front and back surfaces thereof are as follows. Generally, it is made of a metal material. As the inner layer insulating substrate 11, for example, a polyimide film, a polyamide film, a liquid crystal film, an aramid, a glass epoxy material or the like can be used. Particularly, those using a polyimide film for the insulating layer are excellent in heat resistance and dimensional stability, Not only is it thin and strong and suitable for high density, but also has flexibility, it is suitable for a wide range of applications. Moreover, as CCL which used the polyimide for the inner-layer insulation board | substrate 11, what heat-pressed the copper foil to the polyimide film through the meltable polyimide layer, the thing which cast and heated the polyimide precursor to copper foil, a polyimide Examples of the film include surface treatment of the film, sputtering a seed layer such as nichrome as a seed layer, sputtering copper, and electrolytic copper plating thereon to form a copper foil layer.

  On the other hand, the conductor material of the conductor wiring 13 that forms the inner layer wiring pattern 15 includes a metal foil such as copper, aluminum, gold, silver, nickel, and stainless steel, a metal plating layer (preferably a deposited metal underlayer-metal plating layer or Many known techniques such as a chemical metal plating layer can be applied), and the like is laminated on the inner insulating substrate 11 in the form of a foil, or the surface of the inner insulating substrate 11 is sputtered. In this case, a metal mainly composed of copper is most commonly used. In addition, when the said conductor material laminated | stacked on the inner-layer insulation board | substrate 11 is 5-35 micrometers in comparatively thick foil, it is used for a subtractive method, and the same conductor material is 0.5-5 micrometers ultra-thin foil. In this case, it is suitable for the semi-additive method or the case where electrolytic metal plating is stacked and used, such as when the conductor wirings 13 and 13 on both sides are connected via the via 17. In addition, it is also possible to use an ultrathin copper foil having a removable carrier layer that is thermocompression bonded to a polyimide film via a fusion layer, particularly in the case of an ultrathin copper foil of 0.5 to 3 μm. Since the total thickness of the conductor can be suppressed even when the electrolytic copper plating is stacked, it is suitable for forming fine wiring with a pitch of 40 μm or less.

  The inner layer insulating substrate 11 or the inner layer circuit substrate 10 on which a conductor layer or a wiring pattern is formed can be used in any form as long as it can be used without any problem in this manufacturing method. It is preferable to use a tape shape, a film shape, a sheet shape or the like. In particular, a long substrate that can be wound around rolls 101 and 107 (see FIG. 8) having a diameter of about 250 mm, which will be described later, is preferably employed. More specifically, the thickness of the inner insulating substrate 11 constituting the inner layer circuit board 10 is 5 to 150 μm, and the thickness of the outer insulating layer 30 described later is 5 to 50 μm. It is preferable to perform continuous treatment by the roll-to-roll method shown in FIG. 8 in order to increase productivity and maintain stable quality.

  As shown in FIG. 1, outer insulating layers 30, 30 are connected to both front and back surfaces of the inner circuit board 10 through adhesive layers 25, 25. The adhesive layer 25 is formed by applying a liquid adhesive resin on the inner layer circuit board 10 by a method such as coating, printing, or coating, or by laminating or pressing a bonding sheet in which the adhesive resin is previously formed into a film. Etc., and may be formed on the inner layer circuit board 10 without any particular limitation. In the outer layer substrate 55 ′ in this embodiment, the adhesive layer 25 is bonded as a bonding sheet on the back side of a so-called single-sided CCL in which the conductor layer 45 is bonded to the surface side of the outer insulating layer 30 ( (Refer FIG.2 (b)). In addition, as the adhesive resin, epoxy, acrylic, urethane, siloxane, or the like is used, and those that are filled and bonded by thermoplasticity or those that use both thermoplasticity and thermosetting properties are employed. Here, the term “thermosetting” does not necessarily include a thermal cross-linking component or the like, but includes a substance that substantially loses thermoplasticity due to gelation or natural cross-linking by heating and has the same effect. A combination of thermoplasticity and thermosetting is a press machine that uses thermoplasticity to heat and press in vacuum for a short time to ensure filling between the inner layer wiring and then heat and cure in an oven for a specified time. It is advantageous to obtain a sufficient adhesion strength with a short occupation time. Further, the thickness of the adhesive layer 25 may be any thickness as long as the inner circuit board 10 and the outer insulating layer 30 described later can be bonded together. Preferably used.

  Next, the outer layer insulating layers 30 and 30 are formed on the front and rear surfaces of the inner layer circuit board 10 through the adhesive layers 25 and 25, and the outer layer wiring pattern formed by being laminated on the surface of the outer layer insulating layers 30 and 30, respectively. 40 will be described. As the outer insulating layer 30, for example, a polyimide film, a polyamide film, a liquid crystal film, an aramid, a glass epoxy material, or the like is used similarly to the inner insulating substrate 11 constituting the inner circuit board 10 described above. As described above, the thickness of the outer insulating layer 30 is preferably 5 to 50 μm from the viewpoint of employing the roll-to-roll method shown in FIG.

  On the other hand, in this embodiment, the outer layer wiring pattern 40 formed on each outer layer insulating layer 30, 30 has conductor layers 45, 45 respectively formed in a predetermined pattern on the surface of the outer layer insulating layer 30, 30. The conductor layers 45 are formed of plated conductor layers 50 and 50 formed on the conductor layers 45 and 45. In addition, a round hole-shaped via 47 is provided at a predetermined position of each outer insulating layer 30, and the via 47 further penetrates the adhesive layers 25, 25 to form an inner circuit board. The inner layer wiring patterns 15 and 15 provided on the front and back surfaces of the inner layer 10 are formed at a depth reaching each. A conductive layer 52 is formed on the inner periphery of the via 47, and a plated conductor layer 50 is formed in the via 47 from the conductor layer 45. One end of the plated conductor layer 50 is formed on the inner layer wiring pattern 15. The outer layer wiring pattern 40 and the inner layer wiring pattern 15 are electrically connected to each other. The inner diameter of the round hole-shaped via 47 is appropriately set, and is preferably 10 to 100 μm from the viewpoint of increasing the density, and more preferably 20 to 100 μm from the viewpoint of stable via connection. In addition, a round hole shape is desirable from the viewpoint of stress dispersion, but a shape other than a round shape such as a square hole may be used depending on the design. In this embodiment, a plurality of vias 47 are formed for increasing the density of each outer layer insulating layer 30, and a plurality of outer layer wiring patterns 40 are provided for the inner layer wiring pattern 15 of the inner layer circuit board 10. Electrically connected at points.

  Each conductor layer 45 is made of, for example, a metal foil such as copper, aluminum, gold, silver, nickel, stainless steel or the like, preferably 0.5 to 35 μm, like the conductive material of the conductor wiring 13 of the inner layer circuit board 10. A thickness of 3 to 35 μm is preferable from the viewpoint of ensuring electrical and mechanical characteristics, because a high wiring density can be easily formed together with the thickness of the plated conductor layer 50 described later. In this embodiment, as shown in FIG. 2B, a so-called single-sided CCL formed by attaching a conductor layer 45 to the surface side of the outer insulating layer 30 is used. Further, as described above, the adhesive layer 25 is bonded to the back surface side of the outer insulating layer 30 as a bonding sheet.

  Here, the method of separately preparing the outer insulating layers 30 and 30 and the adhesive layers 25 and 25 has been described. However, the adhesive layer 25 can be maintained if necessary characteristics in the design of the substrate can be maintained in a state of being laminated on the inner substrate. May also serve as the outer insulating layer 30. It is also possible to use a so-called copper foil with resin (RCC) in which an adhesive resin layer is formed on a copper foil.

  Further, the plating conductor layer 50 laminated on the surface of the conductor layer 45 is subjected to various platings such as gold, silver, copper, nickel, etc. In this embodiment, the copper plating is applied. Yes. The plated conductor layer 50 made of copper plating is applied to a thickness of 1 to 25 μm, and is applied so as to be approximately 3 to 35 μm together with the thickness of the conductor layer 45 described above.

  Next, a process for manufacturing the multilayer wiring board 1 having the above-described configuration by the method for manufacturing a multilayer wiring board of the present invention will be described. 2 to 5 are schematic configuration sectional views showing an embodiment of the manufacturing method of the present invention in the order of steps.

  In this manufacturing method, the manufacturing apparatus 100 shown in FIG. 8 is used (the power supply roller portion is simplified and only the portion in contact with the exposed conductor portion is shown). The manufacturing apparatus 100 performs electroplating with an unwinding roll 101 on which a predetermined tape material (in this embodiment, a base material in which a laminated body 55 described later is laminated on a tape-like inner layer circuit board 10) is wound. A plurality of plating baths 103, a plurality of upper and lower power supply rollers 105, 105 for supplying electricity to the tape material, and a winding material for winding up the tape material. A take-up roll 107 is provided. That is, an outer layer substrate 55 ′ composed of the adhesive layer 25, the outer layer insulating layer 30 and the conductor layer 45 is formed on the inner layer circuit substrate 10, the via 47 is processed, and the conductive layer 52 (including the power supply conductive layer 52 A). In this state, the tape material wound around the unwinding roll 101 is subjected to electrolytic plating while being continuously conveyed, and is wound up by the winding roll 107 to form the target plated conductor layer 50. A so-called roll-to-roll method is employed. In addition, although not shown in figure, the secondary process as needed, such as washing | cleaning and drying, is performed in the upstream and / or downstream side of the plating bath 103, conveying.

  7 shows details of a cross-sectional view of the main part of the manufacturing apparatus 100. The pair of upper and lower power supply rollers 105, 105 are transported from the tape material (in this embodiment, the outer layer on the inner circuit board 10). The exposed conductor portions 20 and 20 (described later) projecting from the peripheral portion of the outer layer substrate 55 ′ laminated on the inner circuit board 10. To be sandwiched between them. That is, each power supply roller 105 does not contact the conductor layers 45, 45 but contacts each exposed conductor portion 20 provided at a position protruding on both the left and right sides of the inner layer circuit board 10.

  Each power supply roller 105 is rotatably supported, and one or more of the power supply rollers 105 are rotated by a conveying means (not shown), and the tape material is fed by a predetermined amount at a predetermined conveying speed. It can be sent out. Further, as shown in FIG. 7, a cathode electrode is connected to the lower power supply roller 105, and a cathode electrode is also connected to the upper power supply roller 105 via a guide 106 described later. The portion 20 is applied so as to be on the cathode side (cathode side). In addition, guides 106 and 106 are respectively arranged outside the power supply rollers 105 and 105 located above the power supply rollers 105 positioned on the left and right of the tape material. The guide 106 has a lower end extending through both side surfaces of the inner layer circuit board 10 to reach the power supply rollers 105, 105 positioned below. When the tape material is transported, the guide 106 The lateral shift of the material is prevented, and the tape material is transported without being detached from the transport path.

  In the case of this embodiment, the plating bath 103 stores an electrolytic copper plating solution in which copper sulfate, chloride ions, and an additive for smoothing the surface are dissolved in sulfuric acid. In the bath 103, an anode side (anode side) electrode of a power source in which the power supply roller 105 is applied to the cathode side is disposed, and a plating solution is applied to the anode side.

  Referring back to FIG. 2 again, as shown in FIG. 2A, the inner layer circuit board 10 has an inner layer wiring pattern 15 comprising a plurality of conductor wirings 13 on both the front and back surfaces of the inner layer insulating substrate 11, as described above. Are formed and are electrically connected through vias 17. In the present invention, as shown in FIG. 2B, the inner layer circuit board 10 is formed so as to be larger than a laminated body 55 formed by laminating the adhesive layer 25, the outer insulating layer 30, and the conductor layer 45. (Ie, larger than the outer insulating layer 30 and the conductor layer 45), and has a shape protruding from the outer peripheral substrate 55 ′, that is, the peripheral portions on both the left and right sides of the outer insulating layer 30 and the conductor layer 45, by a predetermined length. In the projecting state shown in FIG. 1, the exposed conductor portions 20 to be cut and removed are provided on the protruding portions at both the left and right positions of the inner insulating substrate 11 and on both the front and back surfaces. ing. In addition, alignment marks 22, 22 that can be used as a reference when forming the vias 47 and the outer layer wiring pattern 40 in the outer layer insulating layer 30 are formed on the left and right ends of the inner layer circuit board 10. Further, in the roll-to-roll method, generally, so-called sprget holes 14 (see FIG. 6) are formed on the left and right ends of the inner substrate together with alignment marks for the purpose of conveyance and positioning, and this region is exposed conductors. This is preferable because a new area is not required.

  Next, as shown in FIG. 2B, the conductor layer 45 before the predetermined pattern is formed is laminated on the front surface side of the outer insulating layer 30, and the adhesive layer 25 is pasted as a bonding sheet on the back surface side. The laminated body 55 is disposed at predetermined positions on both the front and back sides of the inner layer circuit board 10. At this time, each laminated body 55 is disposed so as to cover at least a part of the inner layer wiring patterns 15, 15 without covering the alignment marks 22, 22 of the inner layer circuit board 10. Here, the laminated body 55 is laminated so as to cover a part of the exposed conductors 20 and 20 so that a part of the outer peripheral surface of the outer layer substrate 55 ′ is in contact with the exposed conductor.

  In the present specification, the laminated body 55 is referred to as an outer layer substrate 55 ′ when representing a state of being laminated and integrated with the inner layer circuit board 10, and the outer layer substrate 55 ′ includes a case where the outer layer substrate 55 ′ does not have a conductor layer. Although the case where a wiring pattern is formed is included, the one in which the outer layer wiring pattern is completed is particularly called an outer layer circuit board.

  In the above state, as shown in FIG. 2 (c), the inner layer circuit board 10 is sandwiched between the laminated bodies 55, 55, and the outer layer insulating layer 30 and the inner layer circuit board 10 are bonded to both front and back surfaces via the adhesive layers 25, 25. A conductor layer 45 is laminated. In FIG. 2C, the stacked bodies 55 and 55 are stacked so as to cover all the inner layer wiring patterns 15 and 15 on both surfaces of the inner layer circuit board 10, but a part of the inner layer wiring pattern 15 is covered. The laminated bodies 55 and 55 may be laminated, one side of the inner layer circuit board 10 may cover a part of the inner layer wiring pattern 15, and the remaining one side of the inner layer circuit board 10 may be covered.

Further, as shown in FIGS. 2B and 2C, the laminated body 55 only needs to be composed of the adhesive layer 25, the outer insulating layer 30, and the conductor layer 45. For example,
1) a base material in which the adhesive layer 25, the outer insulating layer 30 and the conductor layer 45 are laminated in advance;
2) The adhesive layer 25 and the outer insulating layer 30 having the conductor layer 45 on one side are formed as separate films,
3) An adhesive layer 25 provided in advance on the inner circuit board 10 and an outer insulating layer 30 having a conductor layer 45 on one side laminated on the adhesive layer 25;
4) What formed the adhesive resin layer which served as the adhesive layer 25 and the outer-layer insulating layer 30 inside the conductor layer 45,
Etc. can be used.

  In this embodiment, a so-called single-sided CCL formed by attaching a conductor layer 45 to the surface side of the outer insulating layer 30 is used and is laminated on the inner circuit board 10 via the adhesive layer 25. It has become. Here, the lamination to the inner layer circuit board 10 may be carried out so that the adhesive layer 25, the outer layer insulating layer 30, and the conductor layer 45 are laminated in this order on at least one inner layer wiring pattern 15 forming surface of the inner layer circuit board 10. Although there is no limitation, for example, a liquid adhesive may be applied to the inner layer wiring pattern 15 forming surface of the inner layer circuit board 10 and the CCL may be stacked and press cured so that the outer insulating layer 30 side is in contact. Alternatively, a bonding sheet may be overlapped between the CCL outer layer insulating layer 30 and the inner layer insulating substrate 11 so as to cover a part or all of the inner layer wiring pattern 15 and heated and pressed in a vacuum. In particular, a bonding sheet is previously laminated on the outer insulating layer 30 side of the CCL, for example, with a roll laminator, and the outer shape processed as needed is temporarily attached to the inner circuit board 10 and heated in a vacuum. Then, it is possible to stack various stacked bodies 55 accurately and efficiently. Moreover, in the case of roll-to-roll conveyance, the inner layer circuit board 10 and the laminate 55 may be continuously laminated on the inner layer circuit board 10 with a roll laminator in a vacuum. Conversely, the bonding sheet laminated on the inner layer circuit board 10 in a vacuum with a roll laminator may be laminated with a roll laminator or a press device so that the outer insulating layer 30 side of the CCL is in contact with the bonding sheet. In addition, when laminating the stacked bodies 55, 55 on both the front and back surfaces of the inner layer circuit board 10, the above method may be repeated, and until the middle, for example, until temporary bonding or heating press in vacuum is performed individually on the front and back sides. Subsequent steps may be performed simultaneously. Further, in the case of roll-to-roll conveyance, both the inner layer circuit board 10 and the laminate 55 may be continuously laminated with a roll laminator in a vacuum at the same time. In addition, additional heat curing of the adhesive layer can be performed in an oven or the like as necessary.

  The process described above is the first process of laminating the insulating layer and the conductor layer so as to cover part or all of the circuit pattern on the circuit pattern forming surface of the inner insulating substrate in the present invention.

  Next, when the laminated body 55 is laminated on the inner layer circuit board 10 by the above-described steps, the outer layer board is formed as shown in FIG. 3A with reference to the alignment marks 22 and 22 provided on the left and right ends of the inner layer circuit board 10. Round hole-shaped vias 47 and 47 are formed at predetermined positions of 55 ′ (adhesive layer 25, outer insulating layer 30, and conductor layer 45), respectively. In this embodiment, an alignment mark 57 different from the alignment mark 22 of the inner circuit board 10 is formed on each outer substrate 55 '. At this time, it is preferable to form the alignment mark 57 simultaneously with the formation of the via 47 because the position accuracy of the conductor pattern 40 can be improved when forming the conductor pattern 40 described later. In the case of forming the via 47, two steps may be used in which a hole is first formed in the conductor layer 45 and then a hole is formed in the outer insulating layer 30 and the adhesive layer 25, or the conductor layer 45, the outer insulating layer 30 and One step of making a hole in the adhesive layer 25 at a time may be used.

  The vias 47 and the alignment marks 57 can be formed by a known method, and it is particularly preferable to process using a laser beam. The laser beam used here is typified by carbon dioxide laser (wavelength 9.3 to 10.6 μm), YAG laser (wavelength 1064 nm), and harmonics of YAG laser (third harmonic: wavelength 355 nm, fourth harmonic: wavelength 266 nm). In addition, an excimer laser (wavelength varies depending on the gas type) using various gases may be used.

  The carbon dioxide laser is easy to obtain a large power at present, but is a light different from the wavelength band absorbed by the metal. For this reason, surface treatment such as blackening is performed when the metal is directly processed. That is, the surface of the conductor layer 45 of the outer layer substrate 55 ′ is blackened, and then the portion where the via 47 is formed is irradiated with pulsed laser light with a narrowed beam diameter to bond the conductor layer 45 to the outer layer insulating layer 30 and the bonding. Layer 25 is removed and vias 47 are formed sequentially. Alternatively, the portion where the via 47 is formed may be selectively blackened, and the laser light may be scanned to remove the conductor layer 45, the outer insulating layer 30, and the adhesive layer 25. Here, the conductor layer 45, the outer insulating layer 30, and the adhesive layer 25 may be removed at one time. However, when it is necessary to reduce thermal damage, the conductor layer 45 is first removed, and then the laser beam is removed. The outer layer insulating layer 30 and the adhesive layer 25 can be removed by lowering the power density. As another method, the conductive layer 45 in the portion where the via 47 is formed may be selectively removed by etching or the like, and the adhesive layer 25 and the outer insulating layer 30 may be removed by scanning with laser light.

  Ultraviolet laser light typified by the harmonics of the YAG laser belongs to a wavelength band that is absorbed by the metal, so that the metal can be directly processed. In addition, it is considered that the effect of directly cutting the molecular bonds of the outer insulating layer 30 and the adhesive layer 25 mainly made of an organic material contributes, and the processed shape is better than that of a carbon dioxide laser that is mainly removed thermally. In addition, solid excitation lasers represented by YAG have a good beam shape, and the harmonics are short in wavelength with ultraviolet light, so that the beam can be narrowed down and suitable for forming a small diameter via 47 having an inner diameter of 50 μm or less. Yes. The via 47 is formed by irradiating a portion of the outer layer substrate 55 ′ where the via 47 is processed from the surface of the conductor layer 45 with a laser beam pulse narrowed down to a small diameter so that the conductor layer 45, the outer insulating layer 30, and the adhesive layer are formed. 25 is removed and a via 47 is formed. At this time, the pulse may be irradiated by a plurality of shots, or in the case of a hole larger than the beam diameter, for example, scanning may be performed spirally for each shot. In addition, the conductor layer 45, the outer insulating layer 30, and the adhesive layer 25 may be removed at a time. However, when the damage needs to be reduced, the conductor layer 45 is first removed mainly, and then the laser beam is removed. The adhesive layer 25 and the outer insulating layer 30 may be removed by lowering the power density. The conductor remaining after the conductor layer 45 is removed is used as a mask to irradiate the laser beam out of focus to adhere to the outer insulating layer 30. When layer 25 is removed, a particularly good hole shape can be obtained. This operation is sequentially repeated by changing the position for each hole.

  The excimer laser is a gas laser, which emits deep ultraviolet light, although the oscillation wavelength varies depending on the gas type, and is irradiated with a mask to remove the conductor layer 45, the outer insulating layer 30, and the adhesive layer 25, and to have a small diameter. Hole drilling is possible, but because of the high running cost, it is for expensive products.

  Further, when the stacked bodies 55 and 55 are formed on both the front and back surfaces of the inner layer circuit board 10, the hole processing of the via 47 may be repeated for each front and back.

  Further, here, description is made on the processing up to the surface of the inner layer wiring pattern 15 of the inner layer circuit board 10, that is, the formation of a standard blind via, by removing the conductor layer 45, outer layer insulating layer 30, and adhesive layer 25 of the outer layer substrate 55 ′. However, vias to the back surface side of the inner layer circuit board 10, or vias to the back surface of the conductor layer 45 of the outer layer substrate 55 'on the back surface side of the inner layer circuit board 10, or through holes may be used. You may adjust it appropriately by the number.

  Moreover, when the conductor layer 45 of the laminated body 55 is an ultrathin metal foil with a carrier layer, the via 47 may be formed after the carrier layer is peeled off, or may be formed before peeling. In the former case, the metal foil can be processed with a relatively weak laser power, so it is easy to obtain a good hole shape. In the latter case, the laser power is required to remove the entire carrier, but the metal foil surface is protected. Therefore, contamination of the surface by laser processing can be prevented.

  The process described above constitutes the second process of forming one or more hole-shaped vias communicating with the circuit pattern in the insulating layer and the conductor layer in the present invention.

  As described above, as shown in FIG. 3A, after the vias 47 are formed in the outer substrate 55 ′, the alignment marks 57 and the vias 47 are made of a permanganate solution or the like. Clean by chemical cleaning or physical cleaning such as wet blasting. This is a so-called desmear process, and the adhesion between the plating conductor layer 50 and the conductive layer 52 for electrically connecting the inner layer wiring pattern 15 of the inner layer circuit board 10 and the conductor layer 45 of the multilayer body 55. In particular, the contamination in the via 47 caused by laser processing is removed. The contamination is mainly caused by adhesion of the resin component of the adhesive layer 25 melted by the laser, the resin component of the outer insulating layer 30 and their alterations, and the molten conductor layer 45, and the inner layer is formed particularly by the formation of the via 47. Contamination due to the resin component in the exposed part of the wiring pattern 15 lowers the adhesion of the conductive layer 52 and the plating conductor layer 50 and causes a poor electrical connection. Further, when the outer insulating layer 30 and the adhesive layer 25 have different components, if either one of them is excessively eroded in the chemical desmear process, it may cause poor conduction due to poor adhesion or residual bubbles in the subsequent process. Become. In order to prevent these problems, in this embodiment, cleaning of the hole in the via 47 is physically performed. Since there is no chemical action in physical cleaning, it is possible to prevent one from being excessively eroded. Of course, there is a slight difference due to differences in hardness, but there is virtually no problem because the physical removal amount is also small.

  Specific physical cleaning methods include irradiation with deep ultraviolet light of 250 nm or less typified by excimer light, plasma treatment, drive blast treatment, and wet blast treatment. In the plasma treatment, a resin is etched by plasma generated by discharging a gas under a low pressure, and a complicated vacuum process is required. Further, since the etching rate of the resin is slow, it cannot cope with severe contamination. Drive-last treatment is a method of polishing by blowing abrasive powder together with high-pressure air, and it is possible to treat even fine holes, but there is a stall after injection, the polishing force is somewhat weak, and a large amount of dust is generated. However, it is difficult to use in a clean room. Wet blasting is a method of spraying a slurry mixed with abrasive grains and water with high-pressure air. The fine holes are also treated, and abrasives with high hardness and high polishing power such as water-insoluble alumina particles and zirconia particles. It is sprayed with fine water droplets using grains and has little stall. Therefore, a sufficient polishing force can be generated, which is particularly desirable as a physical cleaning method.

  As the wet blasting apparatus, for example, a mounting portion formed of a magnet for mounting the target object shown in FIG. 3A in which vias 47 and alignment marks 57 are formed, and the target object And a mask having a window hole of a desired shape that allows liquid containing abrasive grains to pass therethrough and a mask formed of a material that is magnetized in the mounting portion. . In the wet blasting apparatus, as a mask, a rubber member such as urethane rubber that contacts the upper surface of the object to be processed is provided below the metal member magnetized by the magnet. What provided the mask in which the window hole of the desired shape which allows the liquid which mixed the said abrasive grain to pass through was formed is preferable. Such a wet blasting apparatus is described in, for example, Japanese Patent Laid-Open No. 9-295266.

  In the wet blasting method, it is preferable to simultaneously remove burrs generated by drilling and cleaning the vias 47 and the alignment marks 57. For example, a liquid containing abrasive grains (preferably 5 to 5 abrasive grains). 20% by volume), preferably using abrasive grains having a high hardness and high polishing power, such as alumina particles and zirconia particles, and using abrasive grains having a diameter of about 1 to 10 [mu] m, The object to be processed is processed by high-pressure jetting at a flow rate of about 10 m to about 300 m / second, preferably about 20 to about 100 m / second, more preferably about 30 to about 70 m / second, together with the processing air toward the hole. Can do. When the outer layer substrate 55 ′ is formed on both the front and back surfaces of the inner layer circuit board 10, the outer substrate 55 ′ may be carried in the air and subjected to the above physical cleaning at the same time or repeated on both sides.

  When the alignment mark 57 and the via 47 are cleaned as described above, the conductive layer 45 is electrically connected to the conductor layer 45 and the inner layer wiring pattern 15 of the inner circuit board 10 prior to electroplating described later. Process. That is, as shown in FIG. 3B, at least a part of or the entire outer peripheral surface of the outer layer substrate 55 ′ laminated on the inner peripheral surface of each via 47 and typically both the front and back surfaces of the inner layer circuit substrate 10. The conductive layer 52 is generated by electroless metal plating, direct plating, or the like, whereby the conductor layer 45 and the inner layer wiring pattern 15 of the inner layer circuit board 10 are electrically connected, and at the same time, the conductor layer 45 and the exposed conductor portion 20 are electrically connected. The power supply conduction layer 52A is formed to form a preferable power supply path for electrolytic plating. Here, a conductive layer 52A for feeding is formed on the outer peripheral surface of the outer layer substrate 55 ′ laminated on both the front and back surfaces of the inner layer circuit board 10 to electrically connect the conductor layer 45 on the surface of the outer layer substrate 55 ′ and the exposed conductor portion 20. Thus, a power supply path for electrolytic plating is formed. Here, among the conductive layers 52, the conductive layers used exclusively for securing the power supply path from the exposed conductor portion 20 to the surface of the outer layer substrate 55 'are distinguished from each other and are particularly expressed as a power supply conductive layer 52A. FIG. 14A shows an enlarged view of the power feeding unit. At this time, all of the outer peripheral surface of the outer layer substrate 55 ′ may be in contact with the exposed conductor portion 20, but a part of the outer peripheral surface of the outer layer substrate 55 ′ is in contact with the exposed conductor portion 20 as shown in FIG. Further, the power feeding conductive layer 52A may be formed at least on the outer peripheral surface of the contacted portion. In the case of roll-to-roll conveyance, the latter is particularly preferable because rigidity can be suppressed and conveyance can be performed smoothly. In addition, in order to suppress the rigidity after electrolytic plating (described later), the outer peripheral surface of the outer layer substrate and the exposed portion of the inner layer insulating substrate that do not come into contact with the exposed conductor are protected in advance or subjected to an inactivation process. The formation of the conductive layer 52A may be restricted to prevent the electrolytic plating from depositing. Alternatively, the distance between the outer peripheral surface that is not in contact with the exposed conductor portion and the exposed conductor portion (that is, the portion where the inner layer insulating substrate surface is exposed) is sufficiently wide compared to the thickness of the outer layer substrate 55 ′ and the depth of the via ( If the conductivity of the conductive layer for power supply is appropriately suppressed, the necessary parts of the power supply path such as the outer peripheral surface of the outer substrate and the inner peripheral surface of the via are short distances so that the resistance is sufficiently low. On the other hand, since the portion where the surface of the inner insulating substrate is exposed has a long distance, even if a conductive layer is formed, the resistance becomes high and precipitation of electrolytic plating is suppressed, and the same effect can be obtained. In this case, it is particularly suitable to form a conductive layer by direct plating because an appropriate resistance can be easily obtained.

  As another form of forming the power supply conductive layer 52A, a via is formed through the conductor wiring electrically connected to the exposed conductor and the outer layer surface, and the power supply conductive layer 52A is formed on the inner surface of the via. A feeding path may be formed in the conductor layer on the outer layer surface. In FIG. 14B, vias communicating with the surface of the outer layer are formed in the conductor wiring routed from the exposed conductor portion formed on one side of the inner layer substrate, and a feeding conductive layer 52A is formed on the inner side surface of the via. A back surface wiring is electrically connected to the exposed conductor portion by a via formed in advance on the substrate, a via that connects the back surface wiring and the back surface outer layer surface is formed, and a power supply conductive layer 52A is formed on the inner peripheral surface of the via. In this way, power supply for electrolytic plating can be applied to the conductor layer on the front and back outer surface. In FIG. 14C, vias communicating with the front and back outer layer surfaces are formed in the conductor wiring routed from the exposed conductor portion on one side of the inner layer substrate, and a power supply conductive layer 52A is formed on the inner peripheral surfaces of both vias. Thus, power supply for electrolytic plating can be applied to the conductor layer on the front and back outer surface.

  In FIG. 3B, the conductive layer 52 including the power supply conductive layer 52 </ b> A is formed only on the inner peripheral surface of each alignment mark 57, the outer peripheral surface of the outer layer substrate 55 ′, and the inner peripheral surface of each via 47. However, if there is no problem in properties such as adhesion to the conductor layer and etching property at the time of pattern formation, it may be applied on the conductor layer 45.

  As described above, the conduction step is performed by a general electroless metal plating step or direct plating step, and these can be simultaneously processed on both sides.

  Various known processes such as nickel and copper can be applied to the electroless metal plating. However, since the adhesiveness with the electrolytic copper plating frequently used for thickening the conductor layer 45 is excellent, the via plating of the wiring board is mainly used. Suitable for electroless copper plating.

  Materials used for the direct plating method include graphite-based and palladium-based materials, which are particularly desirable processes because the process is short and chemical management is relatively easy. In particular, when polyimide is used for the outer insulating layer 30, a direct plating method that can obtain a palladium-tin film using a palladium-tin colloidal catalyst is preferable because of excellent adhesion and less adverse effects on the environment. It is.

  In the palladium-tin colloidal direct plating method, monoethanolamine, nonionic surfactant, cationic surfactant, etc. are used to degrease the metal and polyimide film and adhesive layer surface in the hole, and the surface state is colloidal. Is then adsorbed easily, and then soft-etched using sodium persulfate soda, and then pre-diped into sodium chloride, hydrochloric acid and the like. After these steps, a palladium-tin film is formed by an activating step of immersing in a palladium-tin colloid solution, and finally, in an alkali accelerator bath and an acidic accelerator bath containing sodium carbonate, potassium carbonate and copper ions. What is necessary is just to add a reducing agent to the alkaline accelerator bath used for activation at the time of activation. A conductive film mainly composed of palladium is formed by the above process. In addition, this process treats both surfaces simultaneously by processing a base material in a liquid.

  As described above, after the inner wiring pattern 15 and the conductor layer 45 are made conductive and the power supply path from the exposed conductor portion 20 to the conductor layer 45 is formed, the exposed portion and the front and back of the inner layer circuit board 10 are exposed. Electroplating is performed on the conductor layer and the conductive layer forming portion of the outer substrate 55 ′ laminated on both surfaces. That is, as shown in FIG. 3B, FIG. 7 and FIG. 8, the exposed conductor portions 20 provided on the protruding portions on both sides of the inner layer circuit board 10 that protrude from the peripheral portions on the left and right sides of the outer layer substrate 55 ′, A pair of upper and lower parts are sandwiched between power supply rollers 105 and 105 provided on the left and right sides, and each power supply roller 105 is brought into contact with each exposed conductor portion 20. Then, the exposed conductor portion 20 of the inner layer circuit board 10 is applied to the cathode side via the feeding roller 105 connected to the cathode electrode, and the feeding conductive layer 52A on the outer peripheral surface of the outer layer substrate 55 ′ is applied to the exposed conductor portion 20. The conductive layer 45 on the surface of the outer layer substrate 55 ′ that is conducted through the conductive layer 45, and the conductive layer 52 in the via 47 that conducts to the conductive layer and the via bottom are applied to the cathode side.

  In this state, a tape comprising an inner layer circuit board 10 and an outer layer board 55 'laminated on both sides thereof in a plating bath shown at 103 in FIG. 8 in which an ionized electrolytic copper plating solution is stored by disposing an anode electrode. Then, copper ions adhere to the exposed portion of the inner layer circuit board 10 and the surface of the conductive layer 52 and the conductor layer 45 of the outer layer board 55 ′, which are applied to the cathode side by the power supply roller 105, and are plated conductors. Layer 50 is formed. As a result, the inner layer wiring pattern 15 is electrically connected to the conductor layer 45 of the outer substrate 55 ′ and the plating conductor layer 50 formed on the conductor layer via the plating conductor layer 50 formed on the inner peripheral surface of the via 47. . Then, by patterning the plated conductor layer 50 and the underlying conductor layer 45, an outer layer wiring pattern 40 described later is formed.

  As described above, according to the method for manufacturing a multilayer wiring board of the present invention, the inner layer circuit board 10 is formed larger than the outer layer board 55 ′, and at least a part is projected from the peripheral edge of the outer layer board 55 ′. The exposed conductor portion 20 is provided in the portion, and the conductive layer 52A for feeding that connects the exposed conductor portion 20 or the conductor wiring electrically connected to the exposed conductor portion and the conductor layer 45 on the surface of the outer layer substrate 55 ′ is formed, An inner layer wiring pattern is formed by connecting power supply means including the power supply roller 105 to the exposed conductor portion 20, supplying electricity from the power supply unit 20, and subjecting at least the outer surface of the conductor layer 45 and the inner peripheral surface of the via 47 to electrolytic plating. 15 and the outer layer wiring pattern 40 are electrically connected (see FIG. 3C). That is, the power supply roller 105 is not directly brought into contact with the conductor layer 45 or the plated conductor layer 50 on the conductor layer 45, but power is supplied to the conductor layer 45 through the exposed conductor portion 20. The plated conductor layer 50 formed thereon can be prevented from being damaged or contaminated, and the inner layer wiring pattern 15 and the outer layer wiring pattern 40 can be electrically and reliably connected to each other. The occurrence of defects at the time can be suppressed.

  Furthermore, according to the manufacturing method of the present invention, the step of performing electrolytic plating on the inner surface of the via 47 and the surface of the outer substrate 55 ′ is performed by a roll-to-roll method, and the base material is continuously drawn from the unwinding roll 101. A current is applied through a power supply roller 105 that is in contact with the exposed conductors 20 formed on both sides of the tape and is subjected to electrolytic plating. In other words, since the moving tape can be energized by the feeding roller without contacting the surface of the outer layer, the surface of the outer layer 55 'is contaminated or scratched even in a roll-to-roll process with high productivity and stable processing quality. Accordingly, the plated conductor layer 50 suitable for forming a high-definition wiring pattern can be formed.

  In the electroplating step, the current density when supplying power is set to 0.1 to 50 A / dm 2, and particularly preferably set to 0.5 to 10 A / dm 2 to prevent so-called irregularities and roughness. A good plating finish can be obtained. At this time, if the total thickness of the conductor layer 45 and the plated conductor layer 50 is set to approximately 20 μm or less, the influence of side etching can be suppressed during the etching described later, so that a fine pitch pattern of 60 μm pitch or less can be easily formed. Can do. In particular, when a total thickness of the conductor layer 45 and the plated conductor layer 50 is set to approximately 10 μm or less by using an ultrathin copper foil of 0.5 to 3 μm for the conductor layer 45, it is easy to form fine wiring with a pitch of 40 μm or less. In the electrolytic plating solution, anode balls made of phosphorous copper may be installed at opposite positions on both sides, and copper ions may be supplied together with the anode current. Also in this step, the outer layer substrate 55 ′ laminated on both the front and back surfaces of the inner layer circuit board 10 is processed simultaneously on both sides (see FIG. 8).

  Next, as shown in FIG. 4A, alignment marks 57 are formed on the outer surfaces of the plated conductor layers 50 and 50 formed by the electrolytic plating step on the outer layer substrate 55 ′ on both the front and back surfaces of the inner layer circuit board 10. , 57 are laminated without covering each other. The resist layer 60 is necessary for forming the outer layer wiring pattern 40, and generally a photoresist is used. Photoresist typically has a liquid coating and drying, and a dry film type may be laminated. In general, the former has many positive types and the latter has many negative types. The dry film type resist is particularly suitable because the formation process is easy and the protection of the via 47 is reliable. The dry film resist is generally wound in a roll shape with one surface covered with a protective film and the other surface covered with a carrier protective film. And while peeling off a protective film with the roll part of a roll laminator, the peeled side is piled up on the surface of each plating conductor layer 50 and 50, and it pastes applying appropriate temperature and pressure. Here, the inside of the via 47 is protected by so-called tenting covering the periphery of the via 47.

  After laminating the resist layer 60 as described above, a photomask on which a desired conductor pattern is drawn is aligned with reference to the alignment marks 57 and 57 formed on the outer substrate 55 ′, for example, high pressure mercury. The conductor pattern is transferred to the resist layer 60 by exposure with a projection exposure machine or contact exposure machine using a lamp as a light source. For example, when using a negative dry film resist, the photomask of the portion where the conductor pattern is formed is drawn so as to transmit light, and the conductor is applied to the resist layer 60 by irradiating an appropriate exposure amount. The pattern is exposed. Then, the protective carrier film of the photoresist is peeled off and, for example, a sodium carbonate aqueous solution is sprayed and developed to remove the unnecessary resist layer 60. As shown in FIG. Only the resist layer 60 having the conductor pattern to be left is left. In the case of a negative photoresist, the resist layer 60 is removed from the unexposed portion, that is, the portion where no pattern is formed, to obtain the target resist layer 60.

  At this time, exposure and development may be performed using a photomask with the alignment mark 22 provided on the inner layer circuit board 10 as a reference, but by exposure and development with the alignment mark 57 provided on the outer layer substrate 55 ′ as a reference, Rather than using the alignment mark 22, it is less susceptible to the difference in expansion and contraction of the base material between the portion with and without the outer layer substrate 55 'due to an intermediate process or storage environment, and improves the position accuracy of the outer layer wiring pattern 40. This is preferable.

  After the resist layer 60 is formed into a target conductor pattern in the above process, as shown in FIG. 5 (a), an unnecessary layer formed on the inner layer circuit board 10 and the outer layer board 55 'laminated on both the front and back surfaces. Etching is performed to remove the plating conductor layer 50 and the conductor layer 45. That is, the plated conductor layer 50 and the conductor layer 45 other than the plated conductor layer 50 and the conductor layer 45 covered with the resist layer 60 are removed. This etching is performed by, for example, spraying an etching solution typified by a ferric chloride solution or immersing it in the etching solution to remove unnecessary plating conductor layer 50 and conductor layer 45, As a result, as shown in FIG. 5A, outer layer wiring patterns 40 and 40 composed of the conductor layer 45 and the plated conductor layer 50 are formed.

  After forming the desired outer layer wiring pattern 40 in the above process, as shown in FIG. 5B, the resist layer 60 used as an etching mask is removed with a strong alkaline stripping solution such as a sodium hydroxide solution, for example. The outer layer circuit board is completed. This resist removal is performed by dipping in a stripping solution or spraying. Although it is possible to use an organic solvent system as the stripping solution, an inorganic alkaline aqueous solution is desirable because measures against vapor and environmental measures are required. In addition, when a positive resist is used, it can be reliably peeled off by irradiating with ultraviolet rays prior to the peeling treatment.

  As described above, in this embodiment, the outer layer wiring pattern 40 is formed by the subtractive method, but the outer layer wiring pattern 40 may be formed by semi-additive. That is, after the resist layer 60 is formed in a portion where the outer layer wiring pattern 40 is not desired to be formed, electrolytic plating is performed on the portion where the conductor pattern in which the resist layer 60 is not formed is formed, so that the plated conductor layer 50 is formed. In this method, a desired outer layer wiring pattern 40 is formed. In this case, after the conducting step described above, the resist layer formation, the exposure step, and the development step are performed in the same manner as the above steps. Thereafter, in the same manner as in the electrolytic plating step, power is supplied from the exposed conductor portion 20 through the conductive layer 52A for feeding, and the plated conductor layer 50 is formed, while simultaneously forming the outer layer wiring pattern portion and the plated conductor layer 50 inside the via. The inner layer wiring pattern 15 and the outer layer wiring pattern 40 of the inner layer circuit board 10 are electrically connected through the via 47. And after performing the said resist peeling process, the exposed unnecessary conductor layer 45 is removed by flash etching, and the outer layer wiring pattern 40 is formed. Here, flash etching can be performed by spraying or dipping a weak etching solution represented by, for example, sulfuric acid hydrogen peroxide solution, persulfate, or a thin aqueous ferric chloride solution, and these solutions are suitable additives. There are a number of products that are added to the market, and an appropriate solution may be selected and used.

  As described above, as shown in FIG. 5B, the resist layer 60 is removed from the target outer layer wiring pattern 40, and then it is not necessary for the portion of the inner layer circuit board 10 protruding from the peripheral edge of the outer layer circuit board or the product. By appropriately cutting and removing these parts, the multilayer wiring board 1 having a four-layer structure shown in FIG. 1 can be manufactured.

  In addition, as said process, you may punch to a product shape using a metal mold | die, and you may cut | disconnect by laser processing. Further, here, the outer shape processing is performed immediately after the formation of the four-layer structure, but it may be cut when actually used, after the pattern protective layer formation or after electrode plating such as nickel gold plating or tin plating, Furthermore, it may be cut after mounting the components, and may be cut at a time convenient for mounting. In particular, in roll-to-roll conveyance, after mounting a component such as an IC chip, it is also possible to mount a chip protection member and cut it into individual pieces that can be used as a component.

  Although the example of the double-sided wiring board is described here as the inner layer board, the effect is the same when the multilayer wiring board prepared in advance is further multilayered in the same process as the inner layer board, and is within the scope of the present invention. is there.

  9 to 13 show another embodiment of the method for manufacturing a multilayer wiring board according to the present invention. Note that substantially the same parts as those in the manufacturing method of the multilayer wiring board of the above-described embodiment are denoted by the same reference numerals and description thereof is omitted.

  As shown in FIG. 9, in the multilayer wiring board 1a manufactured according to this embodiment, the conductor layer 45 is not laminated in advance on the surface of the outer insulating layer 30, and the outer layer is formed in the conduction process for the via conduction. At the same time, the surface of the insulating layer 30 is made conductive, and then a conductive layer composed of the plated conductive layer 50 is formed, and this is the outer layer wiring pattern 40. Is different.

  10 to 13 show the manufacturing method in the order of steps, and the steps are almost the same as the manufacturing method described above. Explaining in the order of steps, first, as shown in FIG. 10A, the inner layer circuit board 10 in which inner layer wiring patterns 15 and 15 electrically connected via the vias 17 are formed on both the front and back surfaces of the inner layer insulating substrate 11. As shown in FIG. 10B, a laminated body 55A composed of outer insulating layers 30, 30 having a bonding layer 25 attached as a bonding sheet on the back side is disposed on both the front and back surfaces.

The laminated body 55A only needs to be composed of the adhesive layer 25 and the outer insulating layer 30, for example,
1) a base material in which an adhesive layer 25 and an outer insulating layer 30 are laminated in advance;
2) The adhesive layer 25 and the outer insulating layer 30 are formed as separate films,
3) The adhesive layer 25 is provided on the inner layer circuit board 10 in advance, and the outer insulating layer 30 is laminated on the adhesive layer 25;
4) It is possible to use an adhesive resin that serves as the adhesive layer 25 and the outer insulating layer 30 in the form of a sheet.

  In the above state, as shown in FIG. 10C, the inner layer circuit is formed by sandwiching the inner layer wiring patterns 15 and 15 of the inner layer circuit board 10 and sandwiching the outer layer insulating layers 30 and 30 and applying pressure as appropriate. The outer insulating layers 30 and 30 are laminated on both the front and back surfaces of the substrate 10 via the adhesive layers 25 and 25 to form an outer substrate 55A ′.

  After the above steps, as shown in FIG. 11A, a via 47 for conducting the inner layer wiring and the outer layer wiring is formed by a laser or the like. At this time, if the alignment mark 57 is formed simultaneously with the formation of the via 47, it is preferable because the positional accuracy of the conductor pattern 40 described later can be improved.

  Thereafter, at least the inside of the via 47 is cleaned chemically or physically preferably by physical cleaning. In this embodiment, since the conductor layer 45 is not formed in advance as compared with the previous embodiment, the via 47 can be formed with relatively weak energy, and in particular, in the outer insulating layer 30 and the adhesive layer 25. In the case where there is no reinforcement with an inorganic material such as glass fiber, processing can be performed with particularly weak energy. In this case, since the processing residue in the via 47 is small and the adhesiveness is weak, the surface of the outer insulating layer 30 is subjected to irradiation with deep ultraviolet light of 250 nm or less typified by excimer light or physical cleaning by a plasma processing method. It is preferably employed because it causes less damage.

  After the via 47 is cleaned as described above, a conduction process according to the above-described invention is performed as a pre-process for performing electrolytic plating. That is, as shown in FIG. 11B, a conductive layer 52 is formed on the surface and outer peripheral surface of the outer layer substrate 55A ′ and the inner peripheral surface of each via 47 by electroless metal plating or the like, and the outer layer substrate 55A. A base of outer layer wiring that is electrically connected to the inner layer wiring pattern 15 of the inner layer circuit board 10 is formed on the surface of '. At this time, the conductive layer 52 on the surface of the outer layer substrate 55A ′ is electrically connected to the exposed conductor portion 20 by the power supply conductive layer 52A, and a preferable power supply path for electrolytic plating is formed. Here, the conductive layer 52 on the surface of the outer layer substrate 55A ′ and the exposed conductor portion 20 are electrically connected by the power supply conductive layer 52A formed on the outer peripheral surface of the outer layer substrate 55A ′ laminated on both the front and back surfaces of the inner layer circuit board 10. Thus, a power supply path for electrolytic plating is formed.

  As another form of forming the conductive layer 52A for power feeding, vias communicating with the surface of the outer layer substrate 55A ′ are formed on the conductor wiring electrically connected to the exposed conductor portion as in the above embodiment, and the via inner surface is formed on the inner surface of the via. The power supply conduction layer 52A may be formed to form a power supply path to the conductive layer 52 on the outer layer surface.

  The inner peripheral surface of the alignment mark 57 and the inner peripheral surface of the alignment mark 22 may be formed with a conductive layer or not with any protective means.

  Various known processes such as nickel and copper can be applied to the above electroless metal plating. However, after electroless nickel plating or electroless metal oxide plating as a barrier layer or buffer layer is performed, no process is performed. It is preferable to perform electrolytic copper plating since the adhesion to the outer insulating layer 30 can be increased and the adhesion can be further maintained. Electroless copper plating includes a method of reducing and precipitating copper ions by adding a catalyst. When a metal such as nickel is used for the buffer layer, replacement copper plating that replaces the metal surface with copper can be used. . In particular, when a ceramic-modified or pseudo-ceramic-modified polyimide film is used on the surface of the outer insulating layer 30, the method of performing electroless copper plating following electroless metal oxide plating or electroless nickel plating is an adhesive property. It is particularly preferable from the viewpoint of retention and reliability.

The method of performing electroless metal plating on the pseudo-ceramic-modified polyimide film is performed, for example, by the method disclosed in JP-A-2005-225228, specifically,
1) As a degreasing / surface conditioning step, for example, a surface conditioning agent is used for immersion treatment at 25 to 80 ° C. for 15 seconds to 30 minutes,
2) As the catalyst application step, for example, a sensitizer such as 1 to 50 g / L of a water-soluble stannous salt such as tin chloride, 5 to 100 mL of an acid such as hydrochloric acid, and a solution having a pH of 1 to 5 is used. Containing 0.01 to 1 g / L of a water-soluble Pd salt such as Pd chloride, 0.01 to 1 mL / L of hydrochloric acid or the like, and 10 to 10% of a palladium activation solution having a pH of 1 to 5 Immerse at 50 ° C. for 5 seconds to 5 minutes, or / and soak in water-activated Ag salt (silver nitrate, etc.) 0.1-2 g / L, pH 5-8 silver activation solution at 10-50 ° C. for 5 seconds to 5 minutes. Catalyst,
3) As a base treatment layer forming step for electroless plating, a process containing 0.001 to 5 mol / L of zinc ions (such as zinc nitrate) and 0.00001 to 0.1 mol / L of indium ions (such as indium nitrate), respectively. It is processed by immersing in a liquid at 50 to 90 ° C. for 1 minute or more to form a zinc-containing indium oxide underlayer, and then a conductive layer is formed by a general electroless copper plating step.
4) As the catalyst application step, for example, an aqueous solution of a water-soluble metal salt such as a water-soluble Pd salt (such as Pd chloride) having a concentration of 0.01 to 1 g / L and a pH of 1 to 5 at 10 to 80 ° C. for 5 seconds to Touch for 5 minutes by dipping, spraying, coating,
5) As an electroless metal plating step, for example, a water-soluble metal salt such as copper sulfate 0.01 to 0.5 mol / L, a reducing agent 0.1 to 1 mol / L such as formaldehyde, a complexing agent such as EDTA 0. Electroless metal plating is applied to the pseudo-ceramic modified polyimide film by immersing it in a solution containing 01-1 mol / L and pH 9-14 at 10-70 ° C. for 5-60 minutes. .

  After the above-described steps, as shown in FIG. 11B, the exposed conductor portions 20 and 20 protruding from the peripheral portions on the left and right sides of the outer substrate 55A ′ are sandwiched by the power supply means including the pair of upper and lower power supply rollers 105 and 105. Each power supply roller 105 is brought into contact with each exposed conductor portion 20, and electricity is supplied through the power supply roller 105. Then, the conductive layer 52 formed on the outer peripheral substrate 55A ′ surface and the inner peripheral surface of each via 47, and the inner layer that is the bottom of the via through the feeding conductive layer 52A on the outer peripheral surface of the outer layer in contact with the exposed conductor portion 20 A voltage on the cathode side is applied to the conductor exposed portion, and copper ions in the plating bath 103 adhere to each surface to form the plating conductor layer 50 (see FIG. 11C).

  Thus, also in the manufacturing method of the multilayer wiring board of this embodiment, the inner layer circuit board 10 is formed larger than the outer layer board 55A ′, and at least a part is projected from the peripheral edge portion of the outer layer board 55A ′. The exposed conductor portion 20 is provided in the part, the conductive layer 52 is generated on the surface of the outer layer substrate 55A ′ and the inner peripheral surface of each via 47, and the base of the outer layer wiring connected to the inner layer wiring pattern 15 is formed on the surface of the outer layer substrate. The conductive layer 52 on the surface of the outer layer substrate is electrically connected to the exposed conductor portion 20 by the power supply conductive layer 52A, and a power feeding means including a power feeding roller 105 is connected to the exposed conductor portion 20 to supply electricity therefrom. Thus, a conductor layer made of the plated conductor layer 50 can be formed on at least the outer surface of the outer layer substrate 55A ′ and the inner peripheral surface of each via 47. The power feeding roller 105 is not directly brought into contact with the conductive layer on the surface of the outer substrate 55A ′ or the plated conductor layer 50 formed thereon, but the power is supplied to the conductive layer 52 on the surface of the outer substrate 55A ′ via the exposed conductor portion 20. Therefore, it is possible to prevent the conductive layer 52 on the surface of the outer layer substrate 55A ′ and the plated conductor layer 50 formed thereon from being damaged or contaminated, and the inner layer wiring pattern 15 and the outer layer wiring can be prevented. The pattern 40 can be securely connected to the pattern 40, and the occurrence of defects during pattern formation can be suppressed.

  After the above-described steps, as shown in FIG. 12A, a resist layer 60 is laminated on the plated conductor layer 50, and this is exposed using a photomask to obtain a target pattern, and then developed and developed. Unnecessary resist layer 60 is removed as shown in FIG. After that process, as shown in FIG. 13A, unnecessary plating conductor layer 50 and conductive layer 52 are removed by etching to form a desired conductor pattern 40. Further, as shown in FIG. 13B, the resist layer 60 used as an etching mask is removed with a strong alkali stripping solution, and unnecessary portions of the inner circuit board 10 and the outer circuit board are cut and removed. The multilayer wiring board 1a shown in FIG. 9 can be manufactured.

  Here, the outer layer wiring pattern 40 is formed by the subtractive method, but, of course, the outer layer wiring pattern 40 may be formed by the semi-additive method as described above. In this case, after the conductive layer 52 (including the power supply conductive layer 52A) is formed by the above-described electroless metal plating or the like, the resist layer formation, the exposure step, and the development step are performed in the same manner as the above steps. Thereafter, in the same manner as in the electrolytic plating step, power is supplied from the exposed conductor portion 20 through the conductive layer 52A for feeding, and the plated conductor layer 50 is formed, while simultaneously forming the outer layer wiring pattern portion and the plated conductor layer 50 inside the via. The inner layer wiring pattern 15 and the outer layer wiring pattern 40 of the inner layer circuit board 10 are electrically connected through the via 47. And after performing the said resist peeling process, the exposed unnecessary conduction | electrical_connection layer 52 is removed by flash etching, and the outer layer wiring pattern 40 is formed.

1 is a schematic cross-sectional view of a multilayer wiring board manufactured by a method for manufacturing a multilayer wiring board according to an embodiment of the present invention. It is a schematic structure sectional view showing the first process of the manufacturing method of the multilayer wiring board. FIG. 3 is a schematic cross-sectional view showing a step subsequent to the step shown in FIG. 2 in the method for manufacturing the multilayer wiring board. FIG. 4 is a schematic cross-sectional view showing a step subsequent to the step shown in FIG. 3 in the method for manufacturing the multilayer wiring board. FIG. 5 is a schematic cross-sectional view showing a step subsequent to the step shown in FIG. 4 in the method for manufacturing the multilayer wiring board. It is a principal part top view of the manufacturing method of the same multilayer wiring board. It is principal part sectional drawing of the manufacturing apparatus used for the manufacturing method of the same multilayer wiring board. It is a schematic block diagram of the manufacturing apparatus. FIG. 6 is a schematic cross-sectional view of a multilayer wiring board manufactured by a method for manufacturing a multilayer wiring board according to another embodiment of the present invention. It is a schematic structure sectional view showing the first process of the manufacturing method of the multilayer wiring board. FIG. 11 is a schematic cross-sectional view showing a step subsequent to the step shown in FIG. 10 in the method for manufacturing the multilayer wiring board. FIG. 12 is a schematic cross-sectional view showing a step subsequent to the step shown in FIG. 11 in the method for manufacturing the multilayer wiring board. FIG. 13 is a schematic cross-sectional view showing a step subsequent to the step shown in FIG. 12 in the method for manufacturing the multilayer wiring board. It is an enlarged view of the conduction | electrical_connection conductive layer formation part of this invention.

Explanation of symbols

1, 1a Multilayer wiring board 10 Inner layer circuit board 11 Inner layer insulation board 13 Conductor wiring 14 Sprocket hole 15 Circuit pattern 17 Via 18 Connection part 20 Exposed conductor part 22 Alignment mark 25 Adhesive layer 30 Outer insulation layer 40 Conductor pattern 45 Conductor layer 47 Via 50 plated conductor layer 52 conductive layer 52A feeding conductive layer 55 laminated body 55 ′ outer layer substrate 55A laminated body 55A ′ outer layer substrate 57 alignment make 60 resist layer 100 manufacturing apparatus 101 unwinding roll 103 plating bath 105 feeding roller 106 guide 107 winding roll

Claims (10)

  An inner layer circuit board in which a conductor wiring circuit pattern is formed on at least one side of the inner layer insulating substrate, and an outer layer circuit board in which a conductor wiring circuit pattern is formed on at least one side of the outer layer insulating layer, In the method of manufacturing a multilayer wiring board in which one or more outer layer circuit boards are laminated on at least one side, when the outer layer insulating layer is laminated on at least one side of the inner layer circuit board, an end portion of the inner layer circuit board is The outer layer insulating layer is extended outward from the edge, an exposed conductor is formed at the extended end, and at least the outer layer substrate on which the outer layer insulating layer is laminated has a conductor of the inner layer circuit board. One or more vias reaching the wiring circuit pattern are formed, a conductive layer connected to the conductor wiring circuit pattern of the inner layer circuit board is formed on the inner surface of the via, and the exposed conductor portion Alternatively, a conductive layer for feeding that connects the conductor wiring electrically connected to the exposed conductor part and the surface of the outer layer substrate is formed, and power is supplied from the exposed conductor part of the inner layer circuit board and energized through the conductive layer for feeding. A method of manufacturing a multilayer wiring board, wherein electrolytic plating is performed on the inner surface of the via and the surface of the outer layer substrate.   The outer layer substrate has a conductor layer on the outer surface of the outer layer insulating layer, penetrates the conductor layer, forms the via in the outer layer insulating layer, and forms the conductive layer at least on the inner surface of the via. The method of manufacturing a multilayer wiring board according to claim 1, further comprising forming a conductive layer for feeding that connects the exposed conductor portion or the conductor wiring electrically connected to the exposed conductor portion and the conductor layer on the surface of the outer layer substrate.   The outer layer substrate does not have a conductive layer on the outer surface of the outer layer insulating layer, and after forming the via, the conductive layer is formed on the inner surface of the via and the surface of the outer layer substrate, and the outer layer substrate surface 2. The method for manufacturing a multilayer wiring board according to claim 1, wherein a conductive layer for feeding is formed which is continuous with the conductive layer formed on the conductive layer and connects the exposed conductor portion or the conductive wiring electrically connected to the exposed conductor portion.   The power supply conductive layer is formed on a part or the whole of the outer peripheral surface of the outer layer substrate in contact with the exposed conductor portion of the inner layer circuit board, and is fed from the exposed conductor portion of the inner layer circuit substrate to supply power to the outer peripheral surface of the outer layer substrate. The manufacturing method of the multilayer wiring board as described in any one of Claims 1-3 which supplies with electricity through the conduction | electrical_connection layer.   An inner layer conductor wiring electrically connected to the exposed conductor portion is formed, and a via is formed through the inner layer conductor wiring and the outer layer substrate surface. The multilayer wiring board according to any one of claims 1 to 3, wherein a conductive layer is formed, power is supplied from an exposed conductor portion of the inner layer circuit board, and current is supplied through a power supply conductive layer in the via. Method.   The process of applying electrolytic plating to the inner surface of the via and the surface of the outer layer substrate is performed by a roll-to-roll method by feeding power from the exposed conductor portion of the inner layer circuit board and energizing through the conductive layer for feeding. It consists of a tape continuously drawn from a roll, energizes through a feed roller that contacts the exposed conductor formed on both sides of the tape, and performs electroplating. Manufacturing method of multilayer wiring board.   The method for manufacturing a multilayer wiring board according to claim 6, wherein the power supply roller is an introduction portion and / or a lead-out portion with respect to the plating bath, and is brought into contact with the exposed conductor layer at a position not in contact with the plating solution.   The manufacturing method of the multilayer wiring board as described in any one of Claims 1-7 which performs the process of forming the said conduction | electrical_connection layer by electroless metal plating or direct plating.   The method for manufacturing a multilayer wiring board according to claim 1, wherein the via is formed by drilling, and a cleaning process for residues in the via generated by the drilling is performed by physical cleaning.   The method for manufacturing a multilayer wiring board according to claim 9, wherein the physical cleaning method is selected from a wet blast method, a deep ultraviolet light irradiation method of 250 nm or less, and a plasma treatment method.

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