JP2009117654A - Coupling wiring substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a coupling wiring substrate which can prevent reduction in quality due to its substrate surface damages, such as, cracks and peel offs. <P>SOLUTION: The semiconductor packaged coupling wiring substrate 100, having a plurality of wiring substrate regions includes a plurality of wiring substrate regions 22, each of which has the same wiring pattern 28 and cut-out portions in separating the coupling wiring substrate 100 into the respective wiring substrate regions 22; a plurality of slots 101 of the cut-out portions are provided in the boundary region of each wiring substrate 100; and the wiring patterns 28 are formed in a region of each wiring substrate region 22, except a region which does not have a plurality of slots 101. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a connection wiring board, and more particularly to a connection wiring board including a plurality of wiring board regions to be packaged in a semiconductor package.

  Semiconductor packages are mounted on many electronic devices. In recent years, the demand for high-density mounting on semiconductor packages has increased due to the development of electronic devices such as mobile phones and mobile devices. In order to meet the demand, semiconductor packages are changed from lead frame type packages such as QFP (quad flat package) and SOP (small outline package) to area arrays such as BGA (ball grid array) and CSP (chip size package). It is moving to a semiconductor package called. Many semiconductor packages called area arrays include an organic substrate made of a resin containing glass fibers and a semiconductor element mounted on the organic substrate.

Hereinafter, the structure of the semiconductor package 70 will be described with reference to the drawings.
FIG. 8 is a diagram for explaining the structure of a conventional semiconductor package. In FIG. 8, a semiconductor package 70 includes a semiconductor element 71 that performs electrical signal processing, and a wiring substrate 72 that is electrically connected to the semiconductor element 71 and on which the semiconductor element 71 is disposed. The semiconductor element 71 is sealed with a low thermal expansion sealing resin 73.

The semiconductor package 70 is formed as follows.
First, in the wiring board 72, for example, copper foil is etched to form a wiring pattern 78 (not shown).

  Next, the semiconductor element 71 is bonded to the wiring substrate 72 by, for example, a paste. The semiconductor element 71 is electrically connected to the wiring board 72 by a bonding technique such as wire bonding.

  Next, the semiconductor element 71 is, for example, transfer molded. That is, the semiconductor element 71 disposed and electrically connected to the wiring substrate 72 is sealed with the low thermal expansion sealing resin 73.

  The process of forming the semiconductor package 70 described above is performed in the state of the connection wiring board 700 in which a plurality of wiring boards 72 are arranged.

  FIG. 9 is a plan view showing a connection wiring board 700 in which a plurality of wiring boards 72 are arranged. FIG. 9A shows an example in which four wiring boards 72 are arranged. As shown in FIG. 9A, in the connection wiring board 700, slots 701 are formed in the vicinity of the four periphery of each wiring board 72, and on the long side of the connection wiring board 700 on the boundary of each wiring board 72. Is formed with a hole 702.

  The semiconductor package 70 is formed in a state of a connection wiring board 700 in which a plurality of wiring boards 72 constituting the semiconductor package 70 are arranged, and is completed by being separated from the connection wiring board 700. Here, the connection wiring substrate 700 is divided into four semiconductor packages 70.

  The connection wiring board 700 is cut into pieces by a punching method using a press die. Cutting by the punching method is performed along the cutting line 705. The cutting line 705 passes through the inner edge of the slot 701.

  FIG. 9B shows a wiring pattern 78 present in a cut portion near the cutting line 705 near the end of the slot 701. Here, the wiring pattern 78 is a wiring that electrically connects the semiconductor package 70 and the outside, and the wiring pattern 78 is formed by plating, for example.

  However, when cutting by the punching method, the wiring pattern 78 such as a plating bath existing in the cut portion makes the holding of the wiring board 72 unstable. For this reason, damage such as cracks and peeling is likely to occur on the surface of the wiring board 72, leading to a deterioration in the quality of the semiconductor package 70.

  Thus, a semiconductor package structure that reduces damage such as burrs, cracks on the surface of the wiring board, and peeling has been proposed (see, for example, Patent Document 1).

In Patent Document 1, burrs generated along the outer shape of the final semiconductor package can be reduced by minimizing the amount of substrate material that is cut while the semiconductor package is separated from the connection wiring board. .
Japanese Patent Laid-Open No. 10-027861

  However, in the above-mentioned Patent Document 1, it is impossible to prevent the quality of the semiconductor package 70 from being deteriorated.

  FIG. 10 is a diagram schematically illustrating a state in which the connection wiring board 700 is fixed by the punching tool 800 when the wiring board 72 is punched from the connection wiring board 700.

  FIG. 10 schematically shows a state where the connection wiring substrate 700 is fixed by the punching tool 800 in the region Z shown in FIG. 9, that is, in the region near the cutting line 705 of the wiring pattern 78. 10A is a diagram when the region Z shown in FIG. 9 is viewed from the A direction, and FIG. 10B is a diagram when the region Z illustrated in FIG. 9 is viewed from the B direction.

  As shown in FIG. 10A, the punching tool 800 gets on the wiring pattern 78, and the entire surface of the wiring board 72 cannot be stably fixed. Therefore, when the connection wiring board 700 is cut, damage such as cracking or peeling occurs on the surface of the wiring board 72 due to stress at the time of cutting the wiring board 72.

  As described above, in the wiring substrate 72 constituting the semiconductor package 70 in the above-mentioned Patent Document 1, when individual elements are cut and separated from the connection wiring substrate 700 by punching with a press die, they exist at the cut portions. The wiring substrate 72 is unstablely held by the wiring pattern 78 such as a plating bath. Therefore, damages such as cracks and peeling occurring on the substrate surface due to stress at the time of cutting the wiring substrate 72 cannot be sufficiently reduced. That is, it is impossible to prevent the quality of the semiconductor package 70 from being deteriorated.

  The present invention solves the above-described problems, and an object of the present invention is to provide a connection wiring board that can prevent deterioration in quality due to damage to the surface of the wiring board such as cracking and peeling.

  In order to solve the above problems, a connection wiring board according to the present invention is a connection wiring board having a plurality of wiring board regions to be packaged in a semiconductor package, and a plurality of wiring board regions having the same wiring pattern; A plurality of slots, which are cut out portions, are provided in a boundary region of each wiring substrate region including a cut portion when each wiring substrate region is singulated, and the wiring pattern includes the boundary It is characterized by being formed in a region and a region excluding the region where the plurality of slots are not formed.

  With this configuration, there is no wiring pattern that forms a step in the region where the connection wiring board is fixed. Therefore, when separating the connecting wiring boards into individual wiring board sizes, the connecting wiring boards can be cut after being stably fixed firmly. Occurrence of damage such as peeling is suppressed. Thereby, the connection wiring board which can prevent the quality degradation by damage to the wiring board surface, such as a crack and peeling, is realizable.

  Moreover, the end part connected to the boundary area in the wiring pattern may be terminated in the plurality of slots.

  With this configuration, the wiring pattern is formed so that the end thereof is connected to the slot portion. Therefore, the wiring pattern is formed on the cutting line when dividing the connection wiring board into individual wiring board sizes. not exist. That is, the wiring pattern can be formed without forming a step in the region where the connection wiring board is fixed.

  The connection wiring board further includes a solid pattern that is electrically separated from the wiring pattern, and the solid pattern is formed in a region in the boundary region where the plurality of slots are not formed. May be.

  Each of the wiring board regions may be a rectangle, and the solid pattern may be located in a corner area of each of the wiring board regions.

  In this configuration, a solid pattern is formed so as not to cause a step in the region where the connection wiring board is fixed. As a result, when separating the connection wiring board into individual wiring board sizes, the connection wiring board can be cut after being stably fixed firmly, so that cracks on the surface of the wiring board due to stress during cutting And damage such as peeling can be suppressed.

  A method for manufacturing a connection wiring board according to the present invention is a method for manufacturing a connection wiring board having a plurality of wiring board regions that become semiconductor packages when separated into pieces, wherein a wiring pattern is formed on the connection wiring board. 1 forming step, and a second forming step of forming a plurality of slots by cutting out into a boundary region of each wiring board region including a cut portion when each wiring board region is singulated. The first forming step includes forming the wiring pattern in a region other than the region where the plurality of slots are not formed in the boundary region.

  As a result, there is no wiring pattern that forms a step in the region where the connection wiring board is fixed. Therefore, when separating the connecting wiring boards into individual wiring board sizes, the connecting wiring boards can be cut after being stably fixed firmly. Occurrence of damage such as peeling is suppressed.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to provide the connection wiring board which can prevent the quality degradation by damage to the wiring board surface, such as a crack and peeling.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The following embodiment is an example embodying the present invention, and does not limit the technical scope of the present invention.

(First embodiment)
FIG. 1 is a diagram showing a connection wiring board 100 in which a plurality of wiring boards 22 are arranged according to the first embodiment of the present invention. FIG. 1A is a plan view of the connection wiring board 100, and FIG. 1B is a partially enlarged view of the connection wiring board 100.

  As shown in FIG. 1A, the connection wiring board 100 has slots 101 formed in the boundary regions of the wiring boards 22. In the connection wiring substrate 100, a hole 102 is formed on the long side of the connection wiring substrate 100 at a boundary where the wiring substrates 22 are adjacent to each other.

  Further, as shown in FIG. 1B, a wiring pattern 28 is formed on the connection wiring substrate 100.

  The connection wiring board 100 is formed in a state where a plurality of wiring boards 22 are arranged. Then, each of the wiring boards 22 is separated into individual pieces, whereby the semiconductor package 20 is formed. That is, the semiconductor package 20 is formed in the state of the connection wiring board 100 in which a plurality of wiring boards 22 constituting the semiconductor package 20 are formed.

  The semiconductor package 20 is completed by being cut into pieces of each wiring board 22 by cutting the connecting wiring board 100 along the cutting line 105 on the connecting wiring board 100. Here, an example is shown in which one connection wiring board 100 is divided into four semiconductor packages 20.

  FIG. 2 is a diagram for explaining the structure of the semiconductor package 20 according to the first embodiment of the present invention. In FIG. 2, the semiconductor package 20 includes a semiconductor element 21 that performs electrical signal processing, and a wiring substrate 22 that is electrically connected to the semiconductor element 21 and is disposed by bonding the semiconductor element 21. Then, the semiconductor element 21 is sealed with a low thermal expansion sealing resin 23.

  As shown in FIG. 2, the semiconductor element 21 is mounted on the wiring board 22. In addition, the wiring board 22 on which the semiconductor elements 21 are mounted is formed so as to be arranged in a matrix in a region of a certain predetermined size frame (connection wiring board 100), as shown in FIG. The FIG. 1A shows an example in which four wiring boards 22 are arranged in a row in the region of the connection wiring board 100.

  FIG. 1B is a diagram showing a wiring pattern 28 present at a cutting portion near the cutting line 105 near the end of the slot 101. Here, the wiring pattern 28 is a wiring for electrically connecting the semiconductor package 20 and the outside.

  The wiring pattern 28 is formed on the wiring board 22 as shown in FIG. The wiring pattern 28 is formed, for example, by etching a copper foil.

  The wiring pattern 28 is a cutting portion in the process of dividing the connection wiring substrate 100 into pieces of the size of the wiring substrate 22 to be the semiconductor package 20, that is, a boundary region including the cutting line 105 on the connection wiring substrate 100 (wiring substrate 22. And a region excluding the region where the slot 101 is formed.

  Further, the wiring pattern 28 needs to be drawn out of the semiconductor package 20. Therefore, the wiring pattern 28 is formed so that the end portions thereof are gathered in the slot 101 portion and connected.

  The surface of the joint portion on the wiring pattern 28 is first plated with nickel and then plated with gold. As a result, electrical connection is possible. Nickel plating or gold plating on the surface of the joint on the wiring pattern 28 is usually formed by electrolytic plating. The surfaces other than the joint portion of the wiring pattern 28 are protected by a solder resist. In addition, the joint part of the wiring pattern 28 to which gold plating is applied is led to the outside of the product as a plating bath.

  The slot 101 is formed by being elongated and cut in a position corresponding to the size of the completed semiconductor package 20, that is, in a boundary region of each wiring board 22. Here, four slots 101 are formed in the boundary region of each wiring board 22. The slot 101 is formed in the final step in manufacturing the substrate using, for example, a drill called a router.

  The hole 102 is formed as a reference hole required when assembling the semiconductor package 20.

Next, a method for manufacturing the semiconductor package 20 will be described below.
First, a paste material or the like is applied to the wiring substrate 22 in advance at a predetermined position provided on the wiring substrate 22.

  Next, the semiconductor element 21 is bonded to a predetermined position on the wiring board 22 to which a paste material or the like is applied.

  Next, the semiconductor element 21 is electrically connected to the wiring board 22 by wire bonding using, for example, Au wire.

  2 shows an example in which the electrical connection between the semiconductor element 21 and the wiring substrate 22 is performed by wire bonding, but the flip chip method may be used. Here, the flip-chip method is a method in which bumps are formed in advance at predetermined positions on the surface of the semiconductor element 21 and the bump portions formed via a bonding material such as ACF are mounted on the wiring board 22.

  Next, the semiconductor element 21 is, for example, transfer molded. That is, the semiconductor elements 21 arranged and electrically connected to the wiring board 22 are collectively sealed with the low thermal expansion sealing resin 23.

  Next, the semiconductor including the semiconductor element 21 encapsulated in the sealing resin 23 and the wiring board 22 (semiconductor package 20) are separated from the connection wiring board 100 by punching and cutting. Specifically, the semiconductor element 21 encapsulated in the sealing resin 23 and the wiring board 22 on which the semiconductor element 21 is mounted are cut along the cutting line 105 on the connecting wiring board 100 so that the connecting wiring board 100 is connected. The wiring board 100 is divided into pieces of the size of the wiring board 22. Thereby, each semiconductor package 20 is completed.

  Here, although the connection wiring board 100 is cut by punching with a press die, it is necessary to firmly fix the vicinity of the cutting line 105 at that time. If the fixing is insufficient, the wiring board 22 may be lifted due to stress when the connection wiring board 100 is cut. That is, insufficient fixing may cause damage such as cracks or peeling on the surface of the wiring board 22.

  FIG. 3 schematically shows a state in which the connection wiring board 100 is fixed by the punching tool 800 when the wiring board 22 is punched from the connection wiring board 100 according to the first embodiment of the present invention. FIG.

  FIG. 3 schematically shows a state in which the wiring board 22 in the connection wiring board 100 is fixed by the punching tool 800. In FIG. 3, the area near the cutting line 105 of the wiring pattern 28 (near the area X shown in FIG. 1) and the slot 101 are fixed by the punching tool 800. 3A shows a view when the region Y shown in FIG. 1 is viewed from the A direction, and FIG. 3B shows a view when the region X shown in FIG. 1 is viewed from the B direction. Show.

  In the connection wiring board 100 of the present invention, the wiring pattern 28 that needs to be drawn out to the outside such as a plating bath is formed outside the boundary region of the wiring board 22 so as to be collected and connected to the slot 101 portion. In other words, the wiring pattern 28 is formed so as to be collected in the slot 101 portion so as not to exist on the cutting line 105 and the peripheral band region of the cutting line 105 (in the boundary region of the wiring substrate 22). Therefore, as shown in FIG. 3, when the connecting wiring board 100 is separated into individual wiring boards 22 with the punching tool 800, there is a step in a region where the punching tool 800 fixes the connecting wiring board 100. The wiring pattern 28 does not exist. Therefore, the punching tool 800 can stably and firmly fix the wiring board 22 that becomes the semiconductor package 20 after being singulated.

  Thereby, it is possible to suppress the occurrence of damage such as cracks or peeling on the surface of the wiring board 22 due to stress when cutting the wiring board 22 from the connection wiring board 100.

  FIG. 4 is a top plan view of the semiconductor package 20 according to the first embodiment of the present invention, in which the wiring board 22 is punched from the connection wiring board 100 and separated into pieces.

  As shown in FIG. 4, the semiconductor package 20 is divided into pieces with the size of the wiring board 22. The semiconductor package 20 is formed on a semiconductor element 21 (not shown), a wiring board 22 on which the semiconductor element 21 is bonded, a sealing resin 23 that collectively seals the semiconductor elements 21, and the wiring board 22. Wiring pattern 28 is provided.

  In the boundary region of each wiring substrate 22 in the semiconductor package 20, four cutout regions that are the slots 101 in the connection wiring substrate 100 are provided.

  As shown in FIG. 4, the wiring pattern 28 is located on the outer peripheral portion of the sealing resin 23 in the semiconductor package 20. The wiring pattern 28 is formed so that the end thereof is connected to the notch region that was the slot 101 in the connection wiring substrate 100. The wiring pattern 28 is formed in a region excluding protruding portions of the corner areas (corner regions) of the four corners of the wiring board 22 in the semiconductor package 20 shown in FIG. 4, that is, the cutting line 105 on the connection wiring board 100 shown in FIG. Is formed in a region excluding the peripheral band region (in the boundary region of the wiring substrate 22) and the region where the slot 101 is formed, and further, one end thereof is formed so as to be connected to the slot 101 in the connection wiring substrate 100. The

  As described above, the wiring pattern 28 is formed in a region excluding the peripheral band region of the cutting line 105 on the connection wiring substrate 100 (in the boundary region of the wiring substrate 22) and the region where the slot 101 is formed. One end is formed to be continuous with the slot 101 in the connection wiring substrate 100. Therefore, when the connection wiring substrate 100 is separated into the semiconductor package 20, the wiring substrate 22 in the connection wiring substrate 100 is stably and firmly fixed by the punching tool 800. Therefore, the occurrence of damage such as cracks and peeling on the surface of the wiring board 22 due to stress during cutting can be suppressed.

  As a result, it is possible to realize a connected wiring board that can prevent deterioration in quality due to damage to the surface of the wiring board such as cracks and peeling.

(Second Embodiment)
Next, a second embodiment will be described with reference to the drawings.

  FIG. 5 is a diagram showing a connection wiring board 200 in which a plurality of wiring boards 42 are arranged according to the second embodiment of the present invention. FIG. 5A is a plan view of the connection wiring board 200, and FIG. 1B is a partially enlarged view of the connection wiring board 200.

  As shown in FIG. 5A, in the connection wiring board 200, slots 201 are formed in the vicinity of the four periphery of each of the wiring boards. In the connection wiring board 200, a hole 202 is formed on the long side of the connection wiring board 200 at a boundary where the wiring boards 42 are adjacent to each other.

  As shown in FIG. 1B, the wiring pattern 28 and the solid pattern 206 are formed on the connection wiring board 200 in the four corner regions on each wiring board 42.

  The connection wiring board 200 shown in FIG. 5 is different from the connection wiring board 100 according to the first embodiment in that a solid pattern 206 is formed near the cutting line 205. The connection wiring board 200, the slot 201, the hole 202, the cutting line 205, the wiring board 42, and the wiring pattern 48 are the connection wiring board 100, the slot 101, the hole 102, the cutting line 105, the wiring according to the first embodiment. Since the elements are essentially the same as those of the substrate 22 and the wiring pattern 28, detailed description thereof is omitted.

  An end of the wiring pattern 48 that extends to the boundary region is formed so as to continue to the slot 201. In addition, the wiring pattern 48 is formed in a region excluding the region (in the boundary region of the wiring substrate 42) excluding the peripheral band region of the cutting line 205 on the connection wiring substrate 200 and the region where the slot 201 is formed.

  The solid pattern 206 has a constant height in the four corner areas on the wiring board 42 and in the peripheral band area of the cutting line 205 on the connection wiring board 200 (in the boundary area of the wiring board 42). A metal band is formed in an L shape, for example. The solid pattern 206 is not connected to the wiring pattern 48. That is, the solid pattern 206 is electrically independent from the wiring pattern 48.

  FIG. 6 schematically shows the state where the connection wiring board 200 is fixed by the punching tool 800 when the wiring board 42 is punched from the connection wiring board 200 according to the second embodiment of the present invention. FIG.

  FIG. 6 schematically shows how the wiring board 22 in the connection wiring board 100 is fixed by the punching tool 800. In FIG. 6, the region near the cutting line 105 (near the region Y shown in FIG. 5) of the wiring pattern 28 and the slot 201 are fixed by the punching tool 800. 6A shows a view when the region Y shown in FIG. 5 is viewed from the A direction, and FIG. 6B shows a view when the region Y shown in FIG. 5 is viewed from the B direction. Show.

  In the connection wiring board 200 of the present invention, the wiring pattern 48 such as a plating bath that needs to be drawn to the outside is gathered in the slot 201 portion and is formed to be continuous. Further, a solid pattern 206 is formed on a cutting line 205 that connects the ends of adjacent slots 201 in the area of the wiring board 42. That is, the wiring pattern 48 does not exist in the cutting line 205 excluding the slot 201 and the peripheral band area of the cutting line 205 (in the boundary area of the wiring board 22), and a solid pattern 206 having a constant height is formed. ing. That is, as shown in FIG. 6, when the connecting wiring board 200 is separated into individual wiring boards 42 with the punching tool 800, a wiring pattern 48 that forms a step is formed in a region where the connecting wiring board 100 is fixed. A solid pattern 206 is formed so that it does not exist and does not become a step. Therefore, the punching tool 800 can stably and firmly fix the wiring substrate 42 that becomes the semiconductor package 40 after separation into individual pieces via the solid pattern 206.

  Thereby, it is possible to suppress the occurrence of damage such as cracks or peeling on the surface of the wiring board 22 due to stress when cutting the wiring board 22 from the connection wiring board 100.

  FIG. 7 is a top plan view of the semiconductor package 40 according to the second embodiment of the present invention, in which the wiring board 42 is punched from the connection wiring board 200 and separated into pieces.

  As shown in FIG. 7, the semiconductor package 40 is separated into pieces with the size of the wiring board 42. The semiconductor package 40 is formed on a semiconductor element 41 (not shown), a wiring substrate 42 on which the semiconductor element 41 is bonded, a sealing resin 43 that collectively seals the semiconductor element 41, and the wiring substrate 42. The wiring pattern 48 and the solid pattern 206 are provided.

  Further, on the outer periphery of the wiring substrate 42 of the semiconductor package 40, a notch region that is the slot 201 in the connection wiring substrate 200 and a solid pattern 206 are provided.

  As shown in FIG. 7, the wiring pattern 48 is located on the outer peripheral portion of the sealing resin 43 in the semiconductor package 40. The wiring pattern 48 is formed so as to be continuous with a notch region whose end portion is the slot 201 in the connection wiring substrate 200. The wiring pattern 48 is cut in a region excluding protruding portions of the four corner regions (corner regions) of the wiring substrate 42 in the semiconductor package 40 shown in FIG. 7, that is, on the connection wiring substrate 200 shown in FIG. It is formed in a region excluding the peripheral band region (boundary region of the wiring board 42) of the line 205.

  As described above, the wiring pattern 48 is formed in a region excluding the peripheral band region (within the boundary region of the wiring substrate 42) of the cutting line 205 on the connection wiring substrate 200 and the region where the slot 201 is formed. The end portion is formed continuously with the slot 201 in the connection wiring board 200. A solid pattern 206 is formed on the cutting line 205 that connects the slots 201. Therefore, when the connection wiring board 200 is separated into the semiconductor package 40, the wiring board 42 in the connection wiring board 200 is stably and firmly fixed by the punching tool 800 through the solid pattern 206. Therefore, the occurrence of damage such as cracks and peeling on the surface of the wiring board 42 due to stress during cutting can be suppressed.

  As mentioned above, according to this invention, it becomes possible to implement | achieve the connection wiring board which can prevent the quality degradation by damage on the wiring board surface, such as a crack and peeling.

  As described above, the connection wiring board of the present invention has been described based on the embodiment, but the present invention is not limited to this embodiment. Unless it deviates from the meaning of this invention, the form which carried out the various deformation | transformation which those skilled in the art can think to this embodiment, and the structure constructed | assembled combining the component in different embodiment is also contained in the scope of the present invention. .

  INDUSTRIAL APPLICABILITY The present invention can be used for a connection wiring board, and in particular, can be used for a semiconductor package using an organic substrate mounted on a product such as a home appliance or a mobile device.

It is a figure which shows the connection wiring board by which multiple wiring boards which concern on the 1st Embodiment of this invention are arrange | positioned. It is a figure for demonstrating the structure of the semiconductor package based on the 1st Embodiment of this invention. It is a figure which shows typically a mode that the connection wiring board was fixed with the punching tool at the time of punching a wiring board from the connection wiring board based on the 1st Embodiment of this invention. 1 is a top plan view of a semiconductor package according to a first embodiment of the present invention, in which a wiring board is punched from a connection wiring board and separated into individual pieces. It is a figure which shows the connection wiring board by which the wiring board based on the 2nd Embodiment of this invention is arranged in multiple numbers. It is a figure which shows typically a mode that the connection wiring board was fixed with the punching tool at the time of punching a wiring board from the connection wiring board based on the 2nd Embodiment of this invention. FIG. 10 is a top plan view of a semiconductor package according to a second embodiment of the present invention, in which a wiring board is punched from a connection wiring board and separated into pieces. It is a figure for demonstrating the structure of the conventional semiconductor package. It is a top view which shows the connection wiring board by which multiple wiring boards are arrange | positioned. It is a figure which shows typically a mode when a connection wiring board is fixed with the punching tool at the time of a wiring board being punched from a connection wiring board.

Explanation of symbols

20, 40, 70 Semiconductor package 21, 41, 71 Semiconductor element 22, 42, 72 Wiring board 23, 43, 73 Sealing resin 28, 48, 78 Wiring pattern 100, 200, 700 Connection wiring board 101, 201, 701 Slot 102, 202, 702 Hole 105, 205, 705 Cutting line 206 Solid pattern 800 Punching tool

Claims (5)

A connection wiring board comprising a plurality of wiring board regions to be packaged in a semiconductor package,
A plurality of wiring board regions having the same wiring pattern;
A plurality of slots, which are cut out portions, are provided in a boundary region of each wiring board region, including a cut portion when each wiring board region is singulated.
The connection wiring board, wherein the wiring pattern is formed in a region excluding a region where the plurality of slots are not formed in the boundary region. The connection wiring board according to claim 1, wherein an end portion of the wiring pattern that leads to the boundary region terminates in the plurality of slots. The connection wiring board further includes a solid pattern that is electrically separated from the wiring pattern,
The connection wiring board according to claim 2, wherein the solid pattern is formed in a region in the boundary region where the plurality of slots are not formed. Each wiring board region is rectangular,
The connection wiring board according to claim 3, wherein the solid pattern is located in a corner area of each wiring board area. A method of manufacturing a connection wiring board comprising a plurality of wiring board regions to be packaged in a semiconductor package,
A first forming step of forming a wiring pattern on the connection wiring substrate;
A second forming step of forming a plurality of slots by cutting out into a boundary region of each wiring board region including a cut portion when each wiring board region is singulated;
In the manufacturing method, the first forming step forms the wiring pattern in a region other than the region where the plurality of slots are not formed in the boundary region.

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