JP2009116627A - Design method of integrated circuit device, design support system for the integrated circuit device, design support program of the integrated circuit device, integrated circuit device, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-reliability design method, or the like, of an integrated circuit device, in which a simulation with a higher degree of precision is performed, in an integrated circuit device where a digital circuit and an analog circuit are mounted, in a mixed manner. <P>SOLUTION: At least one repeater cell is connected between a digital circuit block and an analog circuit block, and connection information of the overall circuit is created (step S14). Then, layout information of the overall circuit is created (step S16). Delay time due to the wiring load of a net connected to the repeater cell is calculated, based on the connection information and the layout information of the overall circuit, and delay time information is created (step S20). Based on the connection information of the overall circuit, a digital and analog mixed simulation is performed on the overall circuit (step S22). Finally, a logic simulation is performed, based on the delay time information for the digital circuit block and the repeater cell, and a circuit simulation is performed with respect to the analog circuit block. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an integrated circuit device design method, an integrated circuit device design support system, an integrated circuit device design support program, an integrated circuit device, and an electronic apparatus.

Conventionally, as a method of verifying operation at the design stage of an IC in which a digital circuit and an analog circuit are mixedly mounted, a logic simulation and a circuit simulation are executed at the block level separately for each of the digital circuit block and the analog circuit block to perform detailed operation verification. A method of checking the connection between the digital circuit block and the analog circuit block in the entire circuit has been taken. However, in recent years, the processing capability of computers has improved, and it has become possible to perform detailed operation verification by a digital-analog mixed simulator in an entire circuit including a digital circuit block and an analog circuit block.
JP 2004-157872 A Japanese Patent Laid-Open No. 5-6404

  The digital-analog mixed simulator executes logic simulation for a digital circuit block and executes circuit simulation for an analog circuit block. A signal propagating through each net is expressed as a digital signal in the logic simulation and an analog signal in the circuit simulation. Therefore, the digital-analog mixed simulator performs a conversion process between a digital signal and an analog signal by using a resistance map for the net at the boundary between the digital circuit block and the analog circuit block. Here, for the inside of the digital circuit block, a highly accurate logic simulation is performed in consideration of the delay time information (SDF) of each cell and each net calculated based on the wiring parasitic resistance and wiring parasitic resistance extracted from the layout data. can do.

  However, accurate delay time information cannot be easily reflected on the boundary part between the digital circuit block and the analog circuit block. -It was difficult to perform mixed analog simulation.

  The present invention has been made in view of the above problems. In an integrated circuit device in which a digital circuit and an analog circuit are mixedly mounted, a more accurate simulation is executed, and a more reliable integrated circuit device is provided. The purpose is to provide a design method.

(1) The present invention
An integrated circuit device design method including a digital circuit block and an analog circuit block,
Whole circuit connection information creation for connecting at least one repeater cell between the digital circuit block and the analog circuit block and creating connection information of the whole circuit including the digital circuit block, the analog circuit block, and the repeater cell Steps,
An overall circuit layout information creating step for arranging the digital circuit block, the analog circuit block, and the repeater cell, wiring each net, and creating layout information of the entire circuit;
A delay time information creating step of calculating a delay time due to a wiring load of a net connected to the repeater cell based on the connection information and the layout information of the entire circuit, and creating delay time information including the delay time;
An entire circuit simulation execution step for executing a digital / analog mixed simulation for the entire circuit based on the connection information of the entire circuit;
In the overall circuit simulation execution step,
A logic simulation based on the delay time information is executed for the digital circuit block and the repeater cell, and a circuit simulation is executed for the analog circuit block.

  The integrated circuit device may include a plurality of digital circuit blocks or may include a plurality of analog circuit blocks.

  The repeater cell may be any cell that can relay a signal, and its logic is not limited. The logic of the repeater cell may be, for example, buffer logic or inverter logic. Also, several types of repeater cells of the same logic having different input gate capacities and drive capacities may be prepared. Also, a plurality of repeater cells may be connected in series between the digital circuit block and the analog circuit block, or a repeater cell is connected to each of a plurality of ports of the digital circuit block or a plurality of ports of the analog circuit block. May be. When there are a plurality of repeater cells, the plurality of repeater cells do not have to be the same repeater cells having the same logic, drive capability, and the like.

  In the entire circuit connection information creation step, the repeater cell is connected to all nets for propagating either the signal supplied from the digital circuit block to the analog circuit block or the signal supplied from the analog circuit block to the digital circuit block. Alternatively, repeater cells may be connected to only some of the nets that are to be simulated by accurately reflecting the delay time.

  The entire circuit may be a circuit including a digital circuit block, an analog circuit circuit block, and a repeater cell, and may be a TOP circuit of an integrated circuit device, for example.

  The whole circuit connection information is used to identify cells (including repeater cells) and blocks (including digital circuit blocks and analog circuit blocks) included in the whole circuit, and to identify nets connected to these cells and blocks. Enough information. For example, the connection information of the entire circuit may be a net list described in Verilog.

  The layout information of the entire circuit specifies the physical position (arrangement) of cells (including repeater cells) and blocks (including digital circuit blocks and analog circuit blocks) included in the entire circuit, and these cells and blocks Information sufficient to specify the wiring shape (wiring length or wiring width) of the net to be connected is sufficient.

  The wiring load may be a wiring load considering the parasitic capacitance or parasitic resistance of the wiring, or may be a wiring load considering both the parasitic capacitance and the parasitic resistance. Moreover, the wiring load which considered the parasitic inductance may be sufficient.

  The delay time information includes, for example, the time from when the input of each cell changes until the output changes (signal propagation time inside the cell, hereinafter also referred to as cell delay) and each of two or more cells connected to each other. The delay time due to the net wiring load (hereinafter also referred to as wiring delay) may be included. The delay time information may be, for example, an SDF format file (SDF file).

  According to the present invention, at least one repeater cell is connected between the digital circuit block and the analog circuit block in the entire circuit, and the logic simulation is executed for the digital circuit block and the repeater cell in the digital / analog mixed simulation of the entire circuit. To do. The logic simulation is executed based on delay time information including the wiring delay of the net connected to the repeater cell. Therefore, the wiring delay of the net connected to the repeater cell is reflected in the logic simulation. Compared to the case where the digital circuit block and the analog circuit block are directly connected without using the repeater cell, the digital / analog mixed simulation of the entire circuit is performed. Accuracy can be improved. As a result, in the design stage of the integrated circuit device, it becomes easy to find a defect related to the signal propagation timing of the interface portion of the digital circuit block and the analog circuit block, and a highly reliable integrated circuit device can be provided. Moreover, the increase in the man-hour and cost by ECO can be suppressed.

(2) An integrated circuit device design method of the present invention includes:
Overall circuit wiring load information for creating wiring load information of the entire circuit including information on parasitic resistance and parasitic capacitance of wiring of each net included in the entire circuit based on the connection information and the layout information of the entire circuit Including creation steps,
In the delay time information creating step,
A delay time due to a wiring load of a net connected to the repeater cell is calculated based on the wiring load information of the entire circuit.

  According to the present invention, since the delay time is calculated based on both the parasitic resistance and the parasitic capacitance as the wiring load, the accuracy of the delay time information can be improved. Accordingly, it is possible to improve the accuracy of the digital / analog mixed simulation of the entire circuit.

(3) An integrated circuit device design method of the present invention includes:
Digital circuit block wiring for creating wiring load information of the digital circuit block including information on parasitic resistance and parasitic capacitance of wiring of each net included in the digital circuit block based on connection information and layout information of the digital circuit block Including load information creation step,
In the delay time information creating step,
Based on the wiring load information of the entire circuit and the wiring load information of the digital circuit block, a delay time due to a load of each wiring including a net wiring connected to the repeater cell is calculated.

  The connection information of the digital circuit block may be information sufficient to identify each cell included in the digital circuit block and to identify a net connected to these cells. For example, the connection information of the digital circuit block may be a net list described in Verilog.

  Digital circuit block layout information is used to identify the physical position (placement) of cells included in the digital circuit block and to identify the wiring shape (wiring length and width) of the net connected to these cells. It only needs to be enough information.

  According to the present invention, not only the cell delay and wiring delay of the entire circuit, but also the cell delay and wiring delay inside the digital circuit block are considered in consideration of the parasitic resistance and parasitic capacitance, and the delay time calculation accuracy is improved and the delay time is improved. Create information. Therefore, in the digital / analog mixed simulation of the entire circuit, a highly accurate simulation can be executed for the inside of the digital circuit block, so that the accuracy of the digital / analog mixed simulation of the entire circuit can be further improved.

(4) A method for designing an integrated circuit device of the present invention includes:
In the overall circuit layout information creation step,
The entire circuit includes a plurality of repeater cells connected to the analog circuit block, and the repeater cells are connected to the analog circuit block so that the wiring length of each net is included in a predetermined range. A cell is arranged.

  For example, the repeater cells are arranged such that the difference between the length of the wiring of each net connecting each of the repeater cells and the analog circuit block with respect to a predetermined reference value is within a certain range (for example, a range of ± 5%). Also good.

  Further, for example, the repeater cell may be arranged so that the distance between the terminal of each repeater cell and the port of the analog circuit block connected to the terminal is included in a predetermined range.

  According to the present invention, the repeater cells are arranged so that the wiring length of each net connecting each of the repeater cells and the analog circuit block is included in a predetermined range. Therefore, the difference in wiring delay between these nets can be kept within a predetermined range. As a result, the accuracy of the digital / analog simulation hardly deteriorates even if the digital signal and the analog signal are converted using the same resistance value for each net connecting each of the repeater cells and the analog circuit block. Therefore, it is possible to reduce the labor of setting the resistance values for these nets and to execute a highly accurate digital-analog simulation.

(5) An integrated circuit device design method of the present invention includes:
In the overall circuit layout information creation step,
The repeater cells are arranged so that the wirings of the nets have the same length.

  For example, the repeater cell may be arranged so that the distance between the terminal of each repeater cell and the port of the analog circuit block connected to the terminal is the same.

  According to the present invention, the repeater cells are arranged so that each of the repeater cells and the wiring of each net connecting the analog circuit block have the same length. Therefore, the wiring delay of these nets can be made substantially the same. As a result, the accuracy of the digital / analog simulation hardly deteriorates even if the digital signal and the analog signal are converted using the same resistance value for each net connecting each of the repeater cells and the analog circuit block. Therefore, it is possible to reduce the labor of setting the resistance values for these nets and to execute a highly accurate digital-analog simulation.

(6) An integrated circuit device design method of the present invention includes:
In the overall circuit layout information creation step,
The repeater cell connected to the analog circuit block is arranged near a port to which the repeater cell of the analog circuit block is connected.

  For example, the repeater cell may be arranged so that the length of the net wiring connecting the repeater cell and the analog circuit block is a predetermined value or less.

  Further, for example, the repeater cell may be arranged so that the distance between the terminal of the repeater cell and the port of the analog circuit block connected to the terminal is not more than a predetermined value.

  According to the present invention, the wiring of each net connecting each of the repeater cells and the analog circuit block can be made extremely short. As a result, the wiring delay of these nets can be ignored. Therefore, it is possible to eliminate the trouble of setting a resistance value for each net connecting each of the repeater cells and the analog circuit block, and it is possible to execute a highly accurate digital-analog simulation.

(7) The present invention
A design support system for supporting the design of an integrated circuit device including a digital circuit block and an analog circuit block,
Whole circuit connection information generation for connecting at least one repeater cell between the digital circuit block and the analog circuit block and generating connection information of an entire circuit including the digital circuit block, the analog circuit block, and the repeater cell Means,
An entire circuit layout information generating means for arranging the digital circuit block, the analog circuit block, and the repeater cell, wiring each net, and generating layout information of the entire circuit;
Delay time information generating means for calculating a delay time due to a wiring load of a net connected to the repeater cell based on the connection information and the layout information of the entire circuit, and generating delay time information including the delay time;
Based on the connection information of the whole circuit, and a whole circuit simulation execution means for executing a digital / analog mixed simulation for the whole circuit,
The overall circuit simulation execution means includes:
A logic simulation based on the delay time information is executed for the digital circuit block and the repeater cell, and a circuit simulation is executed for the analog circuit block.

(8) The present invention
A design support program for supporting the design of an integrated circuit device including a digital circuit block and an analog circuit block,
Whole circuit connection information generation for connecting at least one repeater cell between the digital circuit block and the analog circuit block and generating connection information of an entire circuit including the digital circuit block, the analog circuit block, and the repeater cell Means,
An entire circuit layout information generating means for arranging the digital circuit block, the analog circuit block, and the repeater cell, wiring each net, and generating layout information of the entire circuit;
Delay time information generating means for calculating a delay time due to a wiring load of a net connected to the repeater cell based on the connection information and the layout information of the entire circuit, and generating delay time information including the delay time;
Based on the connection information of the entire circuit, to cause the computer to function as an entire circuit simulation execution means for executing a digital / analog mixed simulation for the entire circuit,
The overall circuit simulation execution means includes:
A logic simulation based on the delay time information is executed for the digital circuit block and the repeater cell, and a circuit simulation is executed for the analog circuit block.

(9) The present invention
Designed and manufactured using the integrated circuit device design method described above, the integrated circuit device design support system described above, or the integrated circuit device design support program described above. Is an integrated circuit device.

(10) The present invention
An integrated circuit device as described above;
Data input means to be processed by the integrated circuit device;
An electronic device comprising: output means for outputting data processed by the integrated circuit device.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Moreover, not all of the configurations described below are essential constituent requirements of the present invention.

1. Integrated Circuit Device Design Method, Integrated Circuit Device FIGS. 17A to 17C are diagrams for explaining a conventional integrated circuit device design method.

  As shown in FIG. 17A, the integrated circuit device 1 'includes a digital circuit block 10' and an analog circuit block 20 '. The output port 14'-1 of the digital circuit block 10 'and the input port 24'-1 of the analog circuit block 20' are connected by the wiring 30'-1, and the input port 14'-2 of the digital circuit block 10 ' The output port 24′-2 of the analog circuit block 20 ′ is connected by the wiring 30′-2.

  The digital circuit block 10 'includes logic cells 12'-1, 12'-2 (buffer cells, AND cells, OR cells, etc.). The output terminal of the logic cell 12′-1 and the output port 14′-1 of the digital circuit block 10 ′ are connected by the wiring 16′-1, and the input terminal of the logic cell 12′-2 and the digital circuit block 10 ′ are connected. The input port 14′-2 is connected by the wiring 16′-2.

  The analog circuit block 20 'includes analog cells 22'-1, 22'-2 (level shifter, latch, etc.). The input port 24′-1 of the analog circuit block 20 ′ and the input terminal of the analog cell 22′-1 are connected, and the output port 24′-2 of the analog circuit block 20 ′ and the output terminal of the analog cell 22′-2. Is connected.

  FIGS. 17B and 17C show signal waveforms of a mixed digital / analog simulation for the entire circuit of the integrated circuit device 1 ′ of FIG. 17A. In the digital-analog mixed simulation for the entire circuit of the integrated circuit device 1 ′, the digital circuit block 10 ′ is designated as the object of the logic simulation, and the analog circuit block 20 ′ is designated as the object of the circuit simulation. That is, the wirings 30 ′-1 and 30 ′-2 become the boundary portion between the logic simulation target and the circuit simulation target.

  FIG. 17B is a diagram showing simulation waveforms for the logic cell 12'-1 and the analog cell 22'-1.

When the input signal of the logic cell 12 '- 1 transitions from the L level to the H level at time T _1, a transition from an output signal of the logic cell 12' - 1 e.g. L level to H level at time T _2, accordingly. Here, in the digital-analog mixed simulation of the entire circuit of the integrated circuit device 1 ′, the digital circuit block 10 ′ is designated as the target of the logic simulation. Therefore, the logic simulation is performed on the cells inside the digital circuit block 10 ′. Executed. For a cell subject to logic simulation, the time (cell delay + wiring delay) required from the input signal level change to the output signal level change is calculated based on the wiring load connected to the output terminal. The The logic cell 12′-1 included in the digital circuit block 10 ′ has a delay time (based on the wiring load of the wiring 16′-1 between the output terminal and the output port 14′-1 of the digital circuit block 10 ′. T ₂ −T ₁ ) is calculated. However, the wiring 30′-1 that connects the output port 14′-1 of the digital circuit block 10 ′ and the input port 24′-1 of the analog circuit block 20 ′ is a boundary portion between the target of the logic simulation and the target of the circuit simulation. Since it is wiring, the influence of the wiring load of wiring 30'-1 is not reflected in logic simulation. That is, the wiring delay of the wiring 30′-1 is not considered (treated as 0).

At times T _{2 to} T ₃ , the input signal of the analog cell 22′-1 changes from L level to H level. Here, in the digital-analog mixed simulation of the entire circuit of the integrated circuit device 1 ′, the analog circuit block 20 ′ is designated as the target of the circuit simulation. Therefore, the circuit simulation is performed for the cells inside the analog circuit block 20 ′. Executed. In the circuit simulation, when a digital signal is input as an input signal of the analog circuit block 20 ′, an analog input signal is generated by adding a waveform rounding based on a resistance map to the digital signal. That is, the input signal of the analog cell 22′-1 is converted into a digital signal (output signal of the logic cell 12′-1) input to the input port 24′-1 of the analog circuit block 20 ′ at the time T _{2 to} T ₃ . It is obtained by adding waveform rounding. However, the wiring 30′-1 that connects the output port 14′-1 of the digital circuit block 10 ′ and the input port 24′-1 of the analog circuit block 20 ′ is a boundary portion between the target of the logic simulation and the target of the circuit simulation. Since it is a wiring, even if the parasitic capacitance and parasitic resistance of the wiring 30'-1 are extracted in the entire circuit, they are not described in the netlist for circuit simulation. Therefore, the influence of the wiring load of the wiring 30′-1 is not reflected in the circuit simulation.

Thereafter, similarly to the time _T 1 through T _4, with the H-level of the logic cell 12 '- 1 input signal to transition to the L level at time _{T 5,} the logic cell 12' - 1 output signal at time _{T 6} There was a transition from the H level to the L level, the input signal of the analog cells 22'-1 changes from H level to L level at time _T 6 through T _7.

On the other hand, in the real chip of the integrated circuit device 1 ′, when the wiring 30′-1 is long, the logic cell 12′-1 is affected by the wiring load of the wiring 30′-1 if the drive capacity of the logic cell 12′-1 is small. −1 of the output signal (that is, the input signal of the analog cell 22′-1) increases. Thus, for example, the input signal of the analog cells 22'-1, whereas changes at time _T 2 through T ₄ and the time _T 6 through T ₈ is the waveform of the real chip, the waveform of the circuit simulation time _T 2 ~ both do not coincide because changes in T ₃ and time _T 6 through T _7.

  FIG. 17C is a diagram showing simulation waveforms for the analog cell 22'-2 and the logic cell 12'-2.

When the output signal of the analog cells 22'-2 transitions from the L level to the H level at time T ₁ through T _2, the input signal of the logic cell 12 '-2 is changed from L level to H level at time T ₃ with it . For the logic cell 12′-2, the delay time (T ₃ −T ₂ ) is calculated based on the wiring load of the wiring 16′-2 between the input terminal and the input port 14′-2 of the digital circuit block 10 ′. Is done. However, the wiring 30′-2 connecting the input port 14′-2 of the digital circuit block 10 ′ and the output port 24′-2 of the analog circuit block 20 ′ is a boundary portion between the target of the logic simulation and the target of the circuit simulation. Since it is a wiring, the influence of the wiring load of wiring 30'-2 is not reflected. That is, the wiring delay of the wiring 30′-2 is not considered (treated as 0). Similarly, the time _T 5 through T with the H level of the output signal of the analog cells 22'-2 to transition to the L level at _6, L-level input signal of the logic cell 12 '- 2 from the H level at time _{T 7} Transition to.

On the other hand, in the actual chip of the integrated circuit device 1 ′, when the wiring 30′-2 is long, the analog cell 22′-2 is affected by the wiring load of the wiring 30′-2 if the driving capability of the analog cell 22′-2 is small. -2 output signal (that is, the input signal of the logic cell 12'-2) becomes larger. Thus, for example, the output signal of the analog cells 22'-2, whereas changes at time _T 1 through T ₄ and time _T 5 through T ₈ is the waveform of the real chip, the waveform of the circuit simulation time _T 1 ~ both do not coincide because changes in T ₂ and time _T 5 through T _6.

  As described with reference to FIGS. 17A to 17C, in the digital-analog mixed simulation of the entire circuit of the integrated circuit device 1 ′, the boundary between the digital circuit block 10 ′ and the analog circuit block 20 ′ is highly accurate. There is a problem that verification cannot be performed. Note that the setting of the waveform rounding to be added by changing the resistance value according to the wiring load of the wiring 30′-1 is adjusted, or the wiring loads corresponding to the wiring loads of the wirings 30′-1 and 30′-2 are each analog. Although the above problem can be solved by adding to the input of the cell 22′-1 and the output of the analog cell 22′-2, the number of wirings between the digital circuit block 10 ′ and the analog circuit block 20 ′ is large. If each wiring load is different, not only will the work man-hour be increased, but there is also a risk that a verification error will occur due to a setting error.

  FIG. 1 is a flowchart showing an example of a method for designing an integrated circuit device according to the present embodiment.

  First, a digital circuit block and an analog circuit block are designed, and connection information (net list) and layout information are created (step S10).

  Next, based on the connection information (net list) and layout information of the digital circuit block created in step S10, the wiring of the digital circuit block including information on the parasitic resistance and parasitic capacitance of the wiring of each net included in the digital circuit block Load information is created (digital circuit block wiring load information creation step (step S12)).

  Next, at least one repeater cell is connected between the digital circuit block and the analog circuit block, and connection information (net list) of the entire circuit including the digital circuit block, the analog circuit block, and the repeater cell is created (the entire circuit). Connection information creation step (step S14)).

  Next, the digital circuit block, the analog circuit block, and the repeater cell are arranged, the net that connects the digital circuit block and the repeater cell is wired, the net that connects the analog circuit block and the repeater cell is wired, and the layout information of the entire circuit (Whole circuit layout information creation step (step S16)).

  If the entire circuit includes a plurality of repeater cells connected to the analog circuit block in the process of step S16, the wiring length of each net connecting each of the repeater cells and the analog circuit block is within a predetermined range. Repeater cells may be arranged to be included. For example, the repeater cell may be arranged so that the wiring length of each net is included in a range of a predetermined reference value ± 5%, or the repeater cell so that all the wirings of each net have the same length. May be arranged. By arranging the repeater cells in this way, the delay time due to the wiring load of each net connecting each of the repeater cells and the analog circuit block can be made substantially the same. As a result, the digital signal and the analog signal may be converted using the same resistance value for each net connecting each repeater cell and the analog circuit block. Therefore, it is possible to reduce the labor of setting the resistance value for each net connecting each of the repeater cells and the analog circuit block, and it is possible to execute a highly accurate digital-analog simulation.

  In the process of step S16, the repeater cell connected to the analog circuit block may be arranged near the port to which the repeater cell of the analog circuit block is connected. By arranging the repeater cells in this manner, the wiring of the net connecting the analog circuit block and the repeater cell can be made extremely short. As a result, the delay time due to the wiring load of the net connecting the analog circuit block and the repeater cell can be ignored, so that a more accurate digital-analog simulation can be executed.

  Next, based on the connection information (net list) of the whole circuit created in step S14 and the layout information of the whole circuit created in step S16, information on the parasitic resistance and parasitic capacitance of the wiring of each net included in the whole circuit is obtained. The entire circuit wiring load information (wiring RC information) is created (whole circuit wiring load information creation step (step S18)).

  Next, the delay time due to the wiring load of the net connected to the repeater cell is calculated based on the connection information (net list) of the entire circuit created in step S14 and the layout information of the entire circuit created in step S18. Delay time information (SDF) including time is created (delay time information creation step (step S20)). In the process of step S20, the delay time due to the wiring load of the net connected to the repeater cell may be calculated based on the wiring load information (wiring RC information) of the entire circuit created in step S18. Further, in the process of step S20, connection to the repeater cell is performed based on the wiring load information (wiring RC information) of the entire circuit created in step S18 and the wiring load information (wiring RC information) of the digital circuit block created in step S12. It is also possible to calculate the delay time due to the load of each wiring including the net wiring.

  Finally, based on the connection information (net list) of the entire circuit created in step S14, a digital / analog mixed simulation for the entire circuit is executed (overall circuit simulation execution step (step S22)). In the process of step S22, a logic simulation based on the delay information is executed for the digital circuit block and the repeater cell, and a circuit simulation is executed for the analog circuit block.

  2A to 2C are diagrams for describing an integrated circuit device designed by the integrated circuit device design method of the present embodiment.

  As shown in FIG. 2A, the integrated circuit device 1 includes a digital circuit block 10, an analog circuit block 20, and repeater cells 32-1 and 32-2. The output port 14-1 of the digital circuit block 10 and the input terminal of the repeater cell 32-1 are connected by the wiring 34-1. The output terminal of the repeater cell 32-1 and the input port 24-1 of the analog circuit block 20 are connected. They are connected by wiring 36-1. The input port 14-2 of the digital circuit block 10 and the output terminal of the repeater cell 32-2 are connected by a wiring 34-2, and the input terminal of the repeater cell 32-2 and the output port 24- of the analog circuit block 20 are connected. 2 are connected by wiring 36-2. As will be described later, in order to shorten the wirings of the wirings 36-1 and 36-2 to such an extent that the wiring loads of the wirings 36-1 and 36-2 can be ignored, the repeater cells 32-1 and 32-2 are respectively connected to analog circuits. It is preferable to arrange the block 20 in the vicinity of the input port 24-1 and the output port 24-2.

  The digital circuit block 10 includes logic cells 12-1 and 12-2 (buffer cells, AND cells, OR cells, etc.). The output terminal of the logic cell 12-1 and the output port 14-1 of the digital circuit block 10 are connected by the wiring 16-1, and the input terminal of the logic cell 12-2 and the input port 14-2 of the digital circuit block 10 are connected. They are connected by wiring 16-2.

  The analog circuit block 20 includes analog cells 22-1 and 22-2 (level shifter, latch, etc.). The input port 24-1 of the analog circuit block 20 and the input terminal of the analog cell 22-1 are connected, and the output port 24-2 of the analog circuit block 20 and the output terminal of the analog cell 22-2 are connected.

  FIGS. 2B and 2C show signal waveforms of a mixed digital-analog simulation for the entire circuit of the integrated circuit device 1 of FIG. In the digital-analog mixed simulation for the entire circuit of the integrated circuit device 1, the digital circuit block 10 and the repeater cells 32-1 and 32-2 are designated as the logic simulation target, and the analog circuit block 20 is designated as the circuit simulation target. The That is, the wirings 36-1 and 36-2 become a boundary portion between the logic simulation target and the circuit simulation target.

  FIG. 2B is a diagram showing simulation waveforms for the logic cell 12-1, the repeater cell 32-1, and the analog cell 22-1.

When the input signal of the logic cell 12-1 is changed from L level to H level at time T _1, a transition from an output signal of the logic cell 12-1, for example L level to H level at time T _2, accordingly. In the logic simulation, the wiring load of the wiring 16-1 between the output terminal of the logic cell 12-1 and the output port 14-1 of the digital circuit block 10, and between the output port 14-1 and the input terminal of the repeater cell 32-1. The delay time (T ₂ −T ₁ ) is calculated on the basis of the wiring load of the wiring 34-1. Since the repeater cell 32-1 is subject to the logic simulation, the delay time since the wiring load is also taken into consideration wiring 34-1 _(T 2 -T ₁₎ FIG. 17 (B) Delay time in _(T 2 -T ₁ ) Is larger than.

The output signal of the logic cell 12-1 at time _{T 2} (i.e., the input signal of the repeater cell 32-1) When a transition from L level to H level, the output signal of the repeater cell 32-1 at time _{T 3} with it is L Transition from level to H level. Here, since the repeater cell 32-1 is a target of logic simulation, the cell delay of the repeater cell 32-1 is calculated. However, since the wiring 36-1 connecting the repeater cell 32-1 and the analog circuit block 20 is a wiring at the boundary between the logic simulation target and the circuit simulation target, the wiring delay of the wiring 36-1 is not taken into consideration (as 0). Treated). That is, only the cell delay of the repeater cell 32-1 to the delay time _(T 3 -T ₂₎ is reflected.

At times T _{3 to} T ₄ , the input signal of the analog cell 22-1 transitions from L level to H level. In the circuit simulation, the input signal of the analog cell 22-1 is a waveform round at time T _{3 to} T ₄ to a digital signal (output signal of the repeater cell 32-1) input to the input port 24-1 of the analog circuit block 20. Is obtained. However, since the wiring 36-1 is a wiring at the boundary between the logic simulation target and the circuit simulation target, even if the parasitic capacitance and the parasitic resistance of the wiring 36-1 are extracted in the entire circuit, the wiring 36-1 is included in the circuit simulation netlist. Is not described. Therefore, the influence of the wiring load of the wiring 36-1 is not reflected in the circuit simulation.

Thereafter, likewise, with the H level of the input signal of the logic cell 12-1 to the transition to the L level at time _{T 5,} the input of the output signal (repeater cell 32-1 of logic cells 12-1 at time _{T 6} signal) shifts from H level to L level, the output signal of the repeater cell 32-1 shifts from H level to L level at time _{T 7,} the input signal of the analog cell 22-1 at time _T 7 through T ₈ is Transition from the H level to the L level.

On the other hand, in the actual chip of the integrated circuit device 1, when the wiring 36-1 connecting the repeater cell 32-1 and the analog circuit block 20 is short, the wiring delay of the wiring 36-1 can be ignored. As a result, the input signal of the analog cell 22-1, the waveform of the real chip also changes at time _T 3 through T ₄ and the time _T 7 through T ₈ similarly to the waveform of the circuit simulation. Therefore, it is possible to guarantee a highly accurate digital-analog mixed simulation in the entire circuit of the integrated circuit device 1. As described above, the repeater cell 32-1 is disposed in the vicinity of the input port 24-1 of the analog circuit block 20 in order to shorten the wiring 36-1 so that the wiring delay of the wiring 36-1 can be ignored. Is preferred.

  FIG. 2C is a diagram showing simulation waveforms for the analog cell 22-2, the repeater cell 32-2, and the logic cell 12-2.

When the output signal of the analog cell 22-2 is changed from L level to H level at time _T 1 through T _2, the input signal of the repeater cell 32-2 is changed from L level to H level at time _{T 2,} accordingly. Here, the influence of the wiring load of the wiring 36-2 connecting the input terminal of the repeater cell 32-2 and the output port 24-2 of the analog circuit block 20 is not reflected in the logic simulation and the circuit simulation.

Input signal of the logic cell 12-2 is changed from L level to H level at time _{T 3.} Regarding the logic cell 12-2, the wiring load of the wiring 16-2 between the input terminal and the input port 14-2 of the digital circuit block 10, and the wiring 34- between the input port 14-2 and the repeater cell 32-2. The delay time (T ₃ -T ₂ ) is calculated based on the wiring load of ₂ .

Thereafter, likewise, with the transition from H level of the output signal of the analog cell 22-2 to the L level at time _T 4 through T _5, the input signal is H level repeater cell 32-2 at time _{T 6} L transition level, the input signal of the logic cell 12-2 is changed from H level to L level at time T _6.

On the other hand, in the actual chip of the integrated circuit device 1, when the wiring 36-2 is short, the wiring delay of the wiring 36-2 can be ignored. As a result, the output signal of the analog cell 22-2 is changed at time _T 1 through T ₂ and time _T 4 through T ₅ as with the waveform of the waveform of the real chips circuit simulation. Therefore, it is possible to guarantee a highly accurate digital-analog mixed simulation in the entire circuit of the integrated circuit device 1. As described above, the repeater cell 32-2 is arranged in the vicinity of the output port 24-2 of the analog circuit block 20 in order to shorten the wiring 36-2 so that the wiring delay of the wiring 36-2 can be ignored. Is preferred.

  If the repeater cells 32-1 and 32-2 cannot be arranged in the vicinity of the input port 24-1 and output port 24-2 of the analog circuit block 20 due to layout restrictions or the like, respectively, the wirings 36-1 and 36- The wiring delay of 2 cannot be ignored. In this case, the setting of the waveform rounding added to the input of the analog cell 22-1 is adjusted according to the wiring load of the wiring 36-1, or the wiring load corresponding to the wiring load of the wirings 36-1 and 36-2 is adjusted. By adding to the input of the analog cell 22-1 and the output of the analog cell 22-2, respectively, a highly accurate digital-analog mixed simulation can be guaranteed.

  When the number of wirings between the digital circuit block 10 and the analog circuit block 20 is large, repeaters are inserted into all the wirings. Each repeater cell should be placed near each input port of the connected analog circuit block so that the influence of wiring load can be ignored for all wiring between the output terminal of the repeater cell and the input port of the analog circuit block. preferable. When all the repeater cells cannot be arranged in the vicinity of each input port of the analog circuit block, the wiring between the output terminal of each repeater cell and each input port of the analog circuit block is made substantially equal (for example, It is preferable that all the wirings have substantially the same length). By doing so, the same waveform rounding can be added to all the input ports of the analog circuit block, so that an increase in work man-hours can be suppressed.

  According to the design method of the integrated circuit device of the present embodiment, the wiring delay of the net connected to the repeater cell is reflected in the logic simulation, so that the digital circuit block and the analog circuit block are directly connected without going through the repeater cell. Compared to the case, the accuracy of the mixed digital-analog simulation of the entire circuit can be improved. As a result, in the design stage of the integrated circuit device, it becomes easy to find a defect related to the signal propagation timing of the interface portion of the digital circuit block and the analog circuit block, and a highly reliable integrated circuit device can be provided. Moreover, the increase in the man-hour and cost by ECO can be suppressed.

2. Design Environment FIG. 3 is a diagram for explaining an example of a design environment for applying the design method of the integrated circuit device of the present embodiment. Hereinafter, FIG. 3 will be described with reference to the integrated circuit device 1 described with reference to FIG.

  The digital block netlist 50 is a file in which connection information of the digital circuit block 10 included in the integrated circuit device 1 is described. The digital block net list 50 is a file described in Verilog, for example.

  The placement and routing & RC extraction tool 60 receives the digital block net list 50 as an input, automatically places each cell (logic cells 12-1 and 12-2, etc.) and automatically routes each net (wirings 16-1, 16-2, etc.). And the layout information (digital block layout information 70) of the digital circuit block 10 is output. Further, if there is a timing violation as a result of the placement and routing & RC extraction tool 60, the circuit connection is corrected and the placement and routing is executed again, and the layout information after correction (digital block layout information 70) And the corrected netlist (digital block netlist 80) is output. The digital block net list 80 is a file described in Verilog, for example. Furthermore, the placement and routing & RC extraction tool 60 extracts the parasitic resistance and parasitic capacitance of each wiring (wirings 16-1 and 16-2, etc.) based on the layout information after placement and routing (digital block layout information 70). The digital block RC information 90 is output. The digital block RC information 90 is a file described in a dspf format, for example.

  The TOP circuit netlist 100 describes connection information of a TOP circuit (overall circuit) configured to include the digital circuit block 10, the analog circuit block 20, the repeater cells 32-1 and 32-2, and other cells and blocks. File. The TOP circuit netlist 100 is a file described in Verilog, for example. In the TOP circuit netlist 100, circuit description is made so that repeater cells 32-1 and 32-2 are connected between the digital circuit block 10 and the analog circuit block 20.

  The floor plan tool 110 receives the TOP circuit netlist 100 as input, and arranges the digital circuit block 10, the analog circuit block 20, the repeater cells 32-1 and 32-2, and other cells and blocks. In addition, the floor plan tool 110 includes wiring of each net (wirings 34-1 and 34-2, 34-2, 34-2) connecting the digital circuit block 10, the analog circuit block 20, the repeater cells 32-1 and 32-2, and other cells and blocks. 36-1 and 36-2, etc.) and outputs the TOP circuit layout information (TOP circuit layout information 120).

  The RC extraction tool 130 receives the TOP circuit layout information 120, extracts the parasitic resistance and parasitic capacitance of each wiring of the TOP circuit, and outputs the TOP circuit RC information 140. Here, the parasitic resistance and parasitic capacitance of the wirings 34-1, 34-2, 36-1, and 36-2 connected to the repeater cells 32-1 and 32-2 are also output to the TOP circuit RC information 140. The TOP circuit RC information 140 is a file described in a dspf format, for example.

  The delay time calculation tool 150 receives the digital block RC information 90, the TOP circuit RC information 140, and the digital library information 160 as inputs, and the cell delay of each cell (logic cells 12-1, 12-2, etc.) of the digital circuit block 10 The wiring delay of each net (wirings 16-1, 16-2) and the cell delay of each cell (repeater cell 32-1, 32-2, etc.) of each TOP circuit or each net (34-1, 34-2, 36-) 1, 36-2, etc.) and delay time information 170 is output. Here, the TOP circuit RC information 140 also describes the parasitic resistances and parasitic capacitances of the wirings 34-1, 34-2, 36-1, and 36-2 connected to the repeater cells 32-1 and 32-2. Therefore, the cell delay of the repeater cells 32-1 and 32-2, and the wiring delay of the input / output nets (wirings 34-1, 34-2, 36-1, and 36-2) of the repeater cells 32-1 and 32-2 are also included. The delay time information 170 is output. The delay time information 170 is a file described in SDF, for example.

  The digital-analog mixed simulator 200 includes a TOP circuit netlist (Verilog netlist) 100, a TOP circuit netlist (spice netlist) 102, a digital block netlist 80, an analog block netlist 180, partitioning information 190, and a TOP circuit RC. Information 140, delay time information 170, digital library information 160, analog library information 162, simulation model information 300, and test input information 350 are input, a digital-analog mixed simulation is executed, and an execution result (simulation result information 250) is output. To do. The digital-analog mixed simulator 200 includes, for example, a simulation netlist generation processing unit 210, a logic simulation execution processing unit 220, and a circuit simulation execution processing unit 230.

  Based on the partitioning information 190, the simulation netlist generation processing unit 210 generates a logic simulation netlist 212 by selecting cells and blocks to be subjected to logic simulation, and generates cells and blocks to be subjected to circuit simulation. Is selected to generate a circuit simulation netlist 214. The partitioning information 190 is a file in which information for selecting whether each cell or block included in the TOP circuit is a logic simulation target or a circuit simulation target is described. Here, the partitioning information 190 describes that the digital circuit block 10 and the repeater cells 32-1 and 32-2 are subjected to logic simulation, and the analog circuit block 10 is subjected to circuit simulation. Connection information of the digital circuit block 10 is described in the digital block netlist 80 (Verilog description), and connection information of the digital circuit block 10 and the repeater cells 32-1 and 32-2 is described in the TOP circuit netlist 100 (Verilog). The simulation netlist generation processing unit 210 extracts the connection information from each netlist and generates a logic simulation netlist 212 (Verilog netlist). On the other hand, since the connection information of the analog circuit block 20 is described (spice description) in the analog block netlist 180, the simulation netlist generation processing unit 210 extracts the connection information of the analog circuit block 20 from the analog block netlist 180. Then, a circuit simulation net list 214 (spice net list) is generated. In addition, information on the parasitic capacitance and the parasitic resistance described in the TOP circuit RC information 140 is added to the description of the circuit simulation net list 214 (spice net list).

  The logic simulation execution processing unit 220 includes a digital library information 160 in which logic information of cells (logic cells 12-1, 12-2, etc.) is described, and test input information (test bench) 350 (command file 352, data file 354). Logic simulation for a simulation environment configured by connecting the logic simulation netlist 212 and the simulation model information 300 (external host (MPU) model 310, memory model 320, internal module model 330, etc.) Execute. Here, the logic simulation execution processing unit 220 reads the delay time information 170 (SDF file), and performs the logic simulation in consideration of the cell delay of each cell described in the logic simulation netlist 212 and the wiring delay of each net. Execute.

  The circuit simulation execution processing unit 230 reads the analog library information 162 in which the characteristics of the transistors included in the analog cells 22-1 and 24-1 are described, and executes circuit simulation on the circuit simulation netlist 214.

  The logic simulation execution processing unit 220 and the circuit simulation execution processing unit 230 execute the simulation while synchronizing with each other. That is, for the nets (wirings 36-1 and 36-2) at the boundary between the logic simulation netlist 212 and the circuit simulation netlist 214, the logic simulation execution processing unit 220 generates an analog signal generated by the circuit simulation execution processing unit 230. The circuit simulation execution processing unit 230 converts the digital signal generated by the logic simulation execution processing unit 220 into an analog signal and executes the circuit simulation. Here, the wiring delay of the boundary nets (wirings 36-1 and 36-2) is described in the delay time information 170 (SDF file), but is not reflected in the logic simulation and is treated as 0. Therefore, the repeater cells 32-1 and 32-2 are placed near the ports 24-1 and 24-2 of the analog circuit block 20 in the TOP circuit layout so that the wiring delay due to the wirings 36-1 and 36-2 can be ignored. Each is preferably arranged.

  4A and 4B are diagrams illustrating examples of information included in the digital library information 160 described with reference to FIG. 4A and 4B show delay time information for calculating the wiring delay of each cell. The digital library information 160 includes the logic of each cell, drive capability, cell delay, Information such as input gate capacitance is also included.

4A shows the rising transition time (from L level to H level) of the input of each cell (logic cells 12-1, 12-2, repeater cells 32-1, 32-2, etc. in FIG. 2A). Transition time) and output load capacitance (parasitic capacitance of wiring, input gate capacitance of connection destination cell, etc.) as parameters. For example, the delay time of the output signal when the load capacitance is _{c L1} at the rise transition time _{t I1} (interconnect delay) is _{t r11.} Similarly, FIG. 4B shows the input falling transition time (transition time from H level to L level) of each cell and output load capacitance (parasitic capacitance of wiring, input gate capacitance of connected cell, etc.) ) Is a library information expressing the output signal delay time in a table format. For example, the delay time of the output signal when the falling transition time load capacity _{t I1} is _{c L1} (interconnect delay) is _{t f11.}

  The delay time calculation tool 150 refers to the digital library information 160 and changes the input of the logic cell 12-1 based on, for example, the drive capability and output load capacity of the preceding cell that supplies the input signal to the logic cell 12-1. The time is calculated, the parasitic capacitance of the wiring 16-1 described in the digital block RC information 90 (dspf file), the parasitic capacitance of the wiring 34-1 described in the TOP circuit RC information 140 (dspf file), and digital library information The load capacity of the output of the logic cell 12-1 is calculated from the input gate capacity of the repeater cell 32-1 described in 160, and the wiring delay of the output signal of the logic cell 12-1 is calculated.

  By preparing repeater cell delay information in the digital library information 160, the delay time calculation tool 150 can also output the cell delay and wiring delay of the repeater cell to the delay time information 170 (SDF file). However, as described above, even if the wiring delay of the wiring 36-1 connected to the output terminal of the repeater cell 32-1 is described in the delay time information 170 (SDF file), it is reflected in the mixed digital / analog simulation. Not. It is to be noted that repeater cell delay information (delays of FIGS. 4 (A) and 4 (B)) is performed by executing circuit simulation of the repeater cell while changing two parameters of the input signal transition time and the output load capacitance. Information).

  5A and 5B are diagrams illustrating other examples of information included in the digital library information 160 described with reference to FIG. FIGS. 5A and 5B show logical information for defining the logic of each cell.

  FIG. 5A is a diagram illustrating an example of logical information of each cell expressed as a logical expression, and FIG. 5B is a diagram illustrating an example of logical information of each cell expressed as a truth table. . 5A and 5B show an example of the logic of the repeater cell (buffer logic). The logical expression in FIG. 5A indicates that the output Q of the repeater cell always matches the input I. In the truth table of FIG. 5B, the output Q matches the input I when the input I is logic 0, logic 1, and indefinite value X, but the output Q is indefinite when the input I is high impedance Z. X is shown. In general, the truth table format is easier to express complex logic.

  By preparing the logic information of the repeater cell in the digital library information 160, the logic simulation execution processing unit 220 of the mixed digital / analog simulator 200 can also execute the logic simulation for the repeater cell.

  FIG. 6 is a diagram illustrating an example of a simulation environment of a mixed digital / analog simulator. In FIG. 6, the same components as those in FIG.

  The external host (MPU) model 310 is connected to the outside of the actual chip of the integrated circuit device 1 described with reference to FIG. 2A, and transmits and receives data and control signals for setting internal registers of the digital circuit block 10. It is a simulation model of (Micro Processor Unit). The external host (MPU) model 310 reads a command file 352 in which commands for register setting and the like are listed, analyzes each command, and inputs register setting data and the like to the input of the logic simulation netlist 212 (digital circuit block 10). Supply interface signals. Further, the external host (MPU) model 310 performs processing for reading register setting data via the output of the logic simulation netlist 212.

  The memory model 320 is a simulation model of a storage device such as a RAM or a ROM connected to the outside of the actual chip of the integrated circuit device 1. The memory model 320 reads a data file 354 in which initial data of each memory cell is listed, and reads / writes data from / to the logic simulation netlist 212 (digital circuit block 10). The data in the memory may be updated by overwriting the data file 354 at the end of the simulation.

  The internal module model 330 is a simulation model of a module inside the integrated circuit device 1. For example, in order to speed up the circuit simulation of the analog circuit block 20 of the integrated circuit device 1, the timing control circuit of the analog circuit block 20 included in the digital circuit block 10 may be replaced with a simulation model (internal module model 330). .

  As described above, the digital-analog mixed simulator 200 described with reference to FIG. 3 uses a simulation environment in which the logic simulation netlist 212, the circuit simulation netlist 214, the various simulation model information 300, and the test input information 350 are combined. Thus, the simulation can be executed under a situation very close to the environment of the actual device.

  7 is a diagram showing an example of the command file 352, and FIG. 8 is a diagram for explaining a configuration example of the external host (MPU) model 310. As shown in FIG.

  MODE indicated by C0 in FIG. 7 is a command for designating an interface mode. The command analysis unit 312 of the external host (MPU) model 310 shown in FIG. 8 analyzes the interface mode specified by MODE in the command file 352 and generates a mode code 317. The output signal generation unit 314 of the external host (MPU) model 310 generates a mode selection signal 366 by decoding the mode code 317 and supplies the mode selection signal 366 to the host (MPU) interface circuit 370 described in the logic simulation netlist 212. .

  Cmd1 shown in C1 of FIG. 7 is a data setting command for a predetermined register (for example, register 1) included in the register file described in the logic simulation netlist 212. The command analysis unit 312 illustrated in FIG. 8 generates a command code 313 and a parameter 315 by analyzing the command and parameter specified by Cmd1 of the command file 352. The output signal generation unit 314 generates an interface signal for setting the parameter 315 in the register 1 specified by the command code 313. Here, for example, if the mode code 317 specifies the parallel interface mode, the output signal generation unit 314 generates the parallel interface signal 362. If the mode code 317 specifies the serial interface mode, the output signal generation unit 314 generates the serial interface signal 364. MPU) interface circuit 370.

  Cmd2 indicated by C2 in FIG. 7 is a data setting command for a predetermined register (for example, register 2) included in the register file described in the logic simulation netlist 212. Thus, the external host (MPU) model 310 sequentially analyzes the commands listed in the command file 352 to generate an interface signal, and repeats the process of supplying the interface signal to the host (MPU) interface circuit 370.

3. Application Example FIG. 9 shows a configuration example of a display driver which is an example of an integrated circuit device to which the design method of this embodiment is applied. The design target integrated circuit device is not limited to the display driver, and the design method of this embodiment can be applied to various integrated circuit devices including a digital circuit block and an analog circuit block. For example, the integrated circuit device to be designed may be a host device such as a baseband engine, an application processor, or an image processing controller.

  The display panel 500 connected to the outside of the display driver 400 includes a plurality of data lines (source lines), a plurality of scanning lines (gate lines), and a plurality of pixels specified by the data lines and the scanning lines. A display operation is realized by changing the optical characteristics of the electro-optical element (in a narrow sense, a liquid crystal element) in each pixel region.

  The display driver 400 includes a digital circuit block 410 and an analog circuit block 450. The digital circuit block 410 includes a display memory 420, an internal interface circuit block 430, and a control circuit block 440. The analog circuit block 450 includes a source driver 460, a gate driver 470, a gradation voltage generation circuit 480, and a power supply circuit 490.

  The display memory 420 (RAM) stores image data. The memory cell array 422 includes a plurality of memory cells and stores image data (display data) for at least one frame (one screen). A row address decoder 424 (MPU / LCD row address decoder) performs a decoding process on the row address and performs a word line selection process of the memory cell array 422. A column address decoder 426 (MPU column address decoder) performs a decoding process on the column address, and performs a selection process of a bit line of the memory cell array 422. The write / read circuit 428 (MPU write / read circuit) performs image data write processing to the memory cell array 422 and image data read processing from the memory cell array 422.

  The control circuit block 440 includes an overall control circuit 442 and a display timing control circuit 444. The overall control circuit 442 generates various control signals and controls the entire apparatus. The display timing control circuit 444 generates a display timing control signal and controls reading of image data from the display memory 420 to the display panel 500 side.

  The internal interface circuit block 430 includes a host interface circuit 432 and an RGB interface circuit 434 that perform interface processing with an external device (such as a host device). The host (MPU) interface circuit 432 implements a host interface that generates an internal pulse for each access from the host and accesses the display memory 420. The RGB interface circuit 434 realizes an RGB interface that writes moving image RGB data to the display memory 420 using a dot clock.

  The source driver 460 is a circuit that generates a data signal for driving the data lines of the display panel 500. Specifically, the source driver 460 receives gradation data as image data from the display memory 420 and receives a plurality of (for example, 64 levels) gradation voltages (reference voltages) from the gradation voltage generation circuit 480. Then, a voltage corresponding to the gradation data is selected from the plurality of gradation voltages and is output to each data line of the display panel 500 as a data signal (data voltage).

  The gate driver 470 is a circuit that generates a scanning signal for driving the scanning lines of the display panel 500. Specifically, a signal (enable input / output signal) is sequentially shifted in a built-in shift register, and a signal obtained by converting the level of the shifted signal is output to each scanning line of the display panel 500 as a scanning signal (scanning voltage). To do.

  The gradation voltage generation circuit 480 (γ correction circuit) is a circuit that generates gradation voltages. Specifically, the built-in voltage dividing circuit (selection voltage generating circuit) generates a divided voltage, and the built-in gradation voltage generating circuit has, for example, 64 (64 gradations) among the generated divided voltages. A gradation voltage is selected and output to the source driver 460.

  The power supply circuit 490 is a circuit that generates various power supply voltages. Specifically, the input power supply voltage (power supply input 402) and the internal power supply voltage are boosted by a charge pump method using a boosting capacitor and a boosting transistor included in a built-in boosting circuit. Then, the voltage obtained by the boosting is supplied to the source driver 460, the gate driver 470, and the gradation voltage generation circuit 480 as a power supply voltage.

  The internal interface circuit block 430 and the control circuit block 440 can be formed by automatic placement and routing such as a gate array (G / A), for example. Therefore, the internal interface circuit block 430 and the control circuit block 440 are described in the digital block netlist 50 (Verilog file) described with reference to FIG. 3, and the digital block RC information 90 (dspf file) is obtained by the placement and routing & parasitic capacitance extraction tool 60. Is generated, the delay time calculation tool 150 generates delay time information 170 (SDF file).

  Since the actual circuit configuration of the display memory 420 (at least the memory cell array 422) is described at the transistor level, it cannot be a target of logic simulation. Therefore, the display memory 420 can be a logical simulation target by replacing it with a simulation model (internal module model 330) described in Verilog. In this simulation model, accurate delay information (which may be a delay time with a margin added) obtained by actual measurement is also described for the delay time of writing and reading with respect to each memory cell included in the memory cell array 422. In addition, as the digital library information 160, information on the input gate capacity and delay time information (delay time information in a table format depending on the output load) for each memory cell is prepared. Can be accurately reflected in the simulation. When the simulation model of the display memory 420 is used, information on the parasitic resistance and parasitic capacitance of the wiring between the display memory 420 and the control circuit block 440 is the block (the internal interface circuit block 430 and the target of automatic placement and routing). Included in the digital block RC information 90 for the control circuit block 440) and the TOP circuit RC information 140 for the display driver 400. Therefore, the delay time calculation tool 150 can also calculate the delay time of the wiring between the display memory 420 and the control circuit block 440 with high precision (highly accurate delay time information (SDF) 170 can be created). .

  The digital circuit block 410 (the display memory 420, the internal interface circuit 430, and the control circuit 440) is subjected to logic simulation in the digital-analog mixed simulation of the TOP circuit (overall circuit) of the integrated circuit device 1 as shown in FIG. It is described in the partitioning information 190. 3 is described in the partitioning information 190 of FIG. 3 so that a repeater cell connected between the digital circuit block 410 and the analog circuit block 450 is also a target of logic simulation.

  The analog circuit block 450 (source driver 460, gate driver 470, gradation voltage generation circuit 480, and power supply circuit 490) is an object of circuit simulation in the digital-analog mixed simulation of the TOP circuit (overall circuit) of the integrated circuit device 1. Thus, it is described in the partitioning information 190 of FIG.

  FIG. 10 is a diagram for explaining a wiring layout between the digital circuit block 410 and the analog circuit block 450 (source driver 460) of the display driver 400 by a conventional integrated circuit device design method.

  In the source driver cell 460 included in the analog circuit block 450, driver cells that drive the data lines of the display panel 500 are arranged in the horizontal direction. For example, if the display panel 500 has 176 data lines, 176 driver cells 462-1 to 462-176 are arranged to form source driver cells 460. Each of the driver cells 462-1 to 462-176 includes data latch circuits 464-1 to 464-176. The driver cells 462-1 to 462-176 latch the gradation data supplied from the digital circuit block 410 (display memory 420) in the data latch circuits 464-1 to 464-176. Here, since the width of the source driver 460 is longer than the width of the digital circuit block 410, the data line 412 for supplying gradation data to the data latch circuits 464-1 to 464-176 as shown in FIG. A large difference occurs in the wiring lengths of 1-412-176. For example, the wiring of the data line 412-88 (shortest wiring) connected to the data latch circuit 464-88 included in the driver cell 462-88 disposed almost in the middle of the source driver 460 and the end of the source driver 460. Difference in wiring length of data lines 412-1 and 412-176 connected to data latch circuits 464-1 and 464-176 included in driver cells 462-1 and 462-176 arranged (longest wiring) Is very big. Therefore, the difference between the wiring delay of the data lines 412-88 and the wiring delay of the data lines 412-1 and 412-176 is very large.

For example, as shown in FIG. 11A, in the actual chip of the display driver 400, the data is supplied to the data latch circuits 464-1 and 464-176 via the data lines 412-1 and 412-176 having the largest wiring load. The gradation data 1 and the gradation data 176 to be shifted from the L level to the H level from time T _{1 to} T ₅ . The gradation data 2 supplied to the data latch circuits 464-2 through large data line 412-2 of the next line load, for example, over a time _T 1 through T ₄ changes from L level to H level. Most gradation data 88 supplied to the data latch circuit 464-88 wiring through a small load data line 412-88, for example over a time _T 1 through T ₂ changes from L level to H level.

  On the other hand, the data latch circuits 464-1 to 464-176 latch each gradation data by a common latch signal. Therefore, the latch signal line 414 for supplying the latch signal is commonly connected to the data latch circuits 464-1 to 464-176. Therefore, the timing at which the latch signal reaches the data latch circuits 464-1 to 464-176 is almost the same.

For example, as shown in FIG. 11A, in the actual chip of the display driver 400, the latch signals supplied to the data latch circuits 464-1 to 464-176 via the latch signal line 414 are time T _{2 to} T Transitions from L level to H level over ₃ . At times T _{2 to} T ₃ when the latch signal transitions from the L level to the H level, the data latch circuits 464-1 and 464-176 latch the gray level data 1 and the gray level data 176 at the L level, and the data latch circuit 464. -2 and 464-88 latch the H level gradation data 2 and the gradation data 88. That is, for the gradation data 1 and the gradation data 176, since the wiring delay of the data lines 412-1 and 412-176 is large, the setup time is insufficient, and the H level data that should originally be latched cannot be latched.

On the other hand, FIG. 11B shows a waveform in a digital-analog simulation of the TOP circuit of the display driver 400. In the digital-analog simulation of the TOP circuit of the display driver 400, the wiring delay of the data lines 412-1 to 412-176 connecting the digital circuit block 410 and the analog circuit block 450 is not considered (wiring delay is regarded as 0). As a result, in the circuit simulation of the analog circuit block 450, all the gradation data 1 to gradation data 176 transition from the L level to the H level from the time T _{1 to} T ₂ . On the other hand, since the latch signal transitions from the L level to the H level from time T _{2 to} T ₃ , the data latch circuits 464-1 to 464-176 all latch the H level grayscale data. Therefore, since it is determined that the display driver 400 operates normally from the result of the digital-analog simulation of the TOP circuit (entire circuit) of the display driver 400, a defect is discovered only in the evaluation of the prototype of the actual chip.

  FIG. 12 is a diagram for explaining a wiring layout between the digital circuit block 410 and the analog circuit block 450 (source driver 460) of the display driver 400 according to the integrated circuit device design method of the present embodiment.

  The repeater cells 416-1 to 416-176 are connected to the digital circuit block 410 by data lines 412-1 to 412-176, respectively, and data latch circuits 464-1 to 464 are connected to the data lines 417-1 to 417-176. -176, respectively. The repeater cells 418-1 to 418-176 are connected in common to the digital circuit block 410 via a latch signal line 414, and are connected to the data latch circuits 464-1 to 464-176 via data lines 419-1 to 419-176. Each is connected.

  Accordingly, the repeater cells 416-1 to 416-176, the repeater cells 418-1 to 418-176, and the digital circuit block 410 are designated as targets for logic simulation, and the digital-analog of the TOP circuit (overall circuit) of the display driver 400 is designated. By executing the simulation, it is possible to execute a simulation in consideration of the wiring delay of the data lines 412-1 to 412-176 and the latch signal line 414.

  Here, in the digital-analog simulation of the TOP circuit (entire circuit) of the display driver 400, the repeater cells 416-1 to 416-176 and the repeater cells 418-1 to 418-176 are data lines 417-1 to 417-176. In addition, the wiring delay of the data lines 419-1 to 419-176 is not taken into consideration (the wiring delay is regarded as 0). Therefore, the repeater cells 416-1 to 416-176 and the repeater cells 418-1 to 418-176 are arranged so that the data lines 417-1 to 417-176 and the data lines 419-1 to 419-176 have the same wiring length. You may make it arrange | position to. By arranging in this way, the wiring delays of the data lines 417-1 to 417-176 and the data lines 419-1 to 419-176 can be made substantially the same. That is, the waveform rounding of signals input to the data latch circuits 464-1 to 464-176 via the data lines 417-1 to 417-176 and the data lines 419-1 to 419-176 can be regarded as substantially the same. . For this reason, the same resistance value is set or the same capacitance value is connected so that the same waveform rounding is added to the input of the data latch circuits 464-1 to 464-176 to be subjected to circuit simulation. Thus, a highly accurate digital-analog simulation can be executed. Therefore, it is not necessary to individually set resistance values or capacity values for the inputs of the data latch circuits 464-1 to 464-176 according to the wiring load, thereby reducing the number of work steps and setting errors. The occurrence of defects can be prevented.

  In addition, the repeater cells 416-1 to 416-176 and the repeater cells 418-1 to 418-176 are arranged so that the wirings of the data lines 417-1 to 417-176 and the data lines 419-1 to 419-176 are as short as possible. May be arranged in the vicinity of the input ports of the data latch circuits 464-1 to 464-176. By arranging in this way, the wiring delay of the data lines 417-1 to 417-176 and the data lines 419-1 to 419-176 can be ignored. Accordingly, it is possible to set a resistance value for adding waveform rounding to the input of the data latch circuits 464-1 to 464-176 to be subjected to circuit simulation, or to eliminate the trouble of connecting a capacitance value. A highly accurate digital-analog simulation can be performed.

  FIG. 13 shows an example of waveforms in the digital-analog simulation of the TOP circuit (overall circuit) of the display driver 400. Repeater cells 416-1 to 416-176, repeater cells 418-1 to 418-176, and digital circuit block 410 are designated as logic simulation targets, and analog circuit block 450 is designated as a circuit simulation target. A digital-analog simulation of the TOP circuit (overall circuit) is executed.

  For the gradation data 1 to gradation data 176 supplied to the data signal lines 412-1 to 412-176 and the latch signal supplied to the latch signal line 414, the repeater cells 416-1 to 416-176 and the repeater cell 418- The cell delays from 1 to 418-176 are almost the same. The waveform rounding by the resistance map added to the data latch circuits 464-1 to 464-176 is also the same.

On the other hand, the wiring delays of the data signal lines 412-1 to 412-176 and the latch signal line 414 are different. The wiring delay of the data signal line 412-1 and the data line 412-176 (gradation data 1 and gradation data 176) is the largest. The wiring delay of the data signal line 412-2 (gradation data 2) is the next largest. The wiring delay of the data signal lines 412 to 88 (gradation data 88) is the smallest. Therefore, the data latch circuits 464-2 and 464-88 can latch an H level signal at the latch timings of the times T ₁ and T ₂ , but the data latch circuits 464-1 and 464-176 have a setup time. L level signal is latched due to shortage. That is, in the digital-analog simulation stage of the TOP (overall circuit) circuit of the display driver 400, a highly accurate simulation reflecting the wiring delay of the data signal lines 412-1 to 412-176 and the latch signal line 414 is executed. Therefore, it is possible to find defects before making an actual chip prototype.

4). Integrated Circuit Device Design Support System, Integrated Circuit Device Design Support Program FIG. 14 is a diagram for explaining an integrated circuit device design support system and a design support program according to this embodiment. The integrated circuit device design support system 600 of this embodiment may have a configuration in which some of the components (each unit) are omitted.

  The integrated circuit device design support system 600 of this embodiment is a design support system that supports the design of an integrated circuit device including a digital circuit block and an analog circuit block.

  The operation unit 630 is for inputting user operations and the like as data, and the function can be realized by hardware such as a keyboard and a mouse.

  The storage unit 640 serves as a work area for the processing unit 610, the communication unit 680, and the like, and its function can be realized by hardware such as a RAM.

  The storage unit 640 includes a library information storage unit 642.

  The library information storage unit 642 stores library information (logic circuit information, layout information, connection information) obtained from design data.

  An information storage medium 650 (a computer-readable medium) stores programs, data, and the like, and functions as an optical disk (CD, DVD, etc.), a magneto-optical disk (MO), a magnetic disk, a hard disk, and a magnetic disk. It can be realized by hardware such as a tape or a memory (ROM).

  In addition, the information storage medium 650 stores a program that causes the computer to function as each unit of the present embodiment and auxiliary data (additional data).

  The processing unit 610 performs various processes of the present embodiment based on a program (design support program) stored in the information storage medium 650, data read from the information storage medium 650, and the like. That is, the information storage medium 650 stores a program for causing a computer to function as each unit of the present embodiment (a program for causing a computer to execute processing of each unit).

  The display unit 660 outputs an image generated according to the present embodiment, and functions thereof are a CRT display, an LCD (liquid crystal display), an OELD (organic EL display), a PDP (plasma display panel), and a touch panel display. It can be realized by hardware such as.

  The sound output unit 670 outputs the sound generated by the present embodiment, and the function can be realized by hardware such as a speaker or headphones.

  The communication unit 680 performs various controls for communicating with the outside (for example, a server device or another terminal), and functions thereof include hardware such as various processors or communication ASICs, It can be realized by a program.

  The processing unit 610 (processor) performs various processes based on operation data, programs, and the like from the operation unit 630. The processing unit 610 performs various processes using the storage unit 640 as a work area. The functions of the processing unit 610 can be realized by hardware such as various processors (CPU, DSP, etc.), ASIC (gate array, etc.), application programs, and OS (for example, general-purpose OS).

  The processing unit 610 includes an entire circuit connection information generation unit 612, an entire circuit layout information generation unit 614, a delay time information generation unit 616, and an entire circuit simulation execution unit 618. The processing unit 610 may further include an entire circuit wiring load information generation unit 620 and a digital circuit block wiring load information generation unit 622.

  The entire circuit connection information generating unit 612 connects at least one repeater cell between the digital circuit block and the analog circuit block, and connection information (net list) of the entire circuit including the digital circuit block, the analog circuit block, and the repeater cell. Process to generate.

  The entire circuit layout information generation means 614 arranges the digital circuit block, the analog circuit block, and the repeater cell, wires each net, wires the net connecting the analog circuit block and the repeater cell, and generates the layout information of the entire circuit. Perform the process.

  In addition, when the entire circuit includes a plurality of repeater cells connected to the analog circuit block, the entire circuit layout information generation unit 614 has a wiring length of each net that connects each of the repeater cells and the analog circuit block. The repeater cells may be arranged so as to be included in a predetermined range, or the repeater cells may be arranged so that the wirings of the respective nets have the same length.

  Further, the entire circuit layout information generating unit 614 may arrange the repeater cell connected to the analog circuit block in the vicinity of the port of the analog circuit block to which the repeater cell is connected.

  The delay time information generation means 616 calculates a delay time due to the wiring load of the net connected to the repeater cell based on the connection information (net list) and layout information of the entire circuit, and delay time information (SDF including the delay time). ) Is generated.

  Further, the delay time information generating unit 616 may calculate the delay time due to the wiring load of the net connected to the repeater cell based on the wiring load information (wiring RC information) of the entire circuit.

  Further, the delay time information generating means 616 includes wirings of nets connected to the repeater cell based on wiring load information (wiring RC information) of the entire circuit and wiring load information (wiring RC information) of the digital circuit block. You may make it calculate the delay time by the load of wiring.

  The entire circuit simulation execution means 618 performs processing for executing a digital / analog mixed simulation for the entire circuit based on connection information (net list) of the entire circuit. The overall circuit simulation execution means 618 executes a logic simulation based on the delay information for the digital circuit block and the repeater cell, and executes a circuit simulation for the analog circuit block.

  The entire circuit wiring load information generation unit 620 includes the wiring load of the entire circuit including information on the parasitic resistance and parasitic capacitance of the wiring of each net included in the entire circuit based on the connection information (net list) and layout information of the entire circuit. A process of generating information (wiring RC information) is performed.

  The digital circuit block wiring load information generation means 622 is a digital circuit including information on parasitic resistance and parasitic capacitance of wiring of each net included in the digital circuit block based on connection information (net list) and layout information of the digital circuit block. A process of generating the wiring load information (wiring RC information) of the block is performed.

  According to the design support system or the design support program for the integrated circuit device of this embodiment, the wiring delay of the net connected to the repeater cell is reflected in the logic simulation, so the digital circuit block and the analog circuit block are connected via the repeater cell. Therefore, the accuracy of the mixed digital / analog simulation of the entire circuit can be improved as compared with the case of direct connection. As a result, in the design stage of the integrated circuit device, it becomes easy to find a defect related to the signal propagation timing of the interface portion of the digital circuit block and the analog circuit block, and a highly reliable integrated circuit device can be provided. Moreover, the increase in the man-hour and cost by ECO can be suppressed.

  Note that a program (design support program) for causing a computer to function as each unit of the present embodiment is an information storage medium 650 (storage unit 640) from an information storage medium included in a host device (server) via a network and communication unit 680. ). Use of the information storage medium of such a host device (server) can also be included in the scope of the present invention.

5). Electronic Device FIG. 15 shows an example of a block diagram of the electronic device of this embodiment. The electronic apparatus 800 includes a microcomputer (integrated circuit device) 810, an input unit 820, a memory 830, a power generation unit 840, an LCD 850, a sound output unit 860, and an LCD driver (integrated circuit device) 870.

  Here, the input unit 820 is for inputting various data. The microcomputer 810 performs various processes based on the data input by the input unit 820. The memory 830 serves as a work area for the microcomputer 810 and the like. The power generation unit 840 is for generating various power sources used in the electronic device 800. The LCD 850 is for outputting various images (characters, icons, graphics, etc.) displayed by the electronic device. The LCD driver 870 is for driving the LCD 850 to display an image. For example, the LCD driver 870 may be the display driver 400 described with reference to FIG.

  The sound output unit 860 is for outputting various sounds (sound, game sound, etc.) output from the electronic device 800, and the function can be realized by hardware such as a speaker.

  The microcomputer 810 and the LCD driver 870 are configured to include a digital circuit block and an analog circuit block, and are integrated circuit devices designed and manufactured by the integrated circuit device design method of this embodiment.

  FIG. 16A illustrates an example of an external view of a cellular phone 950 that is one of electronic devices. The cellular phone 950 includes a dial button 952 that functions as an input unit, an LCD 954 that displays a telephone number, a name, an icon, and the like, and a speaker 956 that functions as a sound output unit and outputs sound.

  FIG. 16B illustrates an example of an external view of a portable game device 960 that is one of electronic devices. The portable game device 960 includes an operation button 962 that functions as an input unit, a cross key 964, an LCD 966 that displays a game image, and a speaker 968 that functions as a sound output unit and outputs game sound.

  FIG. 16C illustrates an example of an external view of a personal computer 970 that is one of electronic devices. The personal computer 970 includes a keyboard 972 that functions as an input unit, an LCD 974 that displays characters, numbers, graphics, and the like, and a sound output unit 976.

  By incorporating the integrated circuit device of this embodiment into the electronic devices in FIGS. 16A to 16C, a highly reliable electronic device can be provided in a short period of time.

  Note that electronic devices that can use this embodiment include, in addition to those shown in FIGS. 16A to 16C, portable information terminals, pagers, electronic desk calculators, devices equipped with touch panels, projectors, Various electronic devices such as a word processor, a viewfinder type or a monitor direct-view type video tape recorder, and a car navigation device can be considered.

  In addition, this invention is not limited to this embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention.

  For example, in the flowchart of FIG. 1, the process of creating the wiring load information (wiring RC information) of the digital circuit block (the process of step S12) is performed after the digital circuit block design (the process of step S10) is completed This can be performed at an arbitrary timing before the information (SDF) is created (step S20).

  The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same objects and effects). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

6 is a flowchart illustrating an example of a method for designing an integrated circuit device of the present embodiment. FIGS. 2A to 2C are diagrams for explaining an integrated circuit device designed by the integrated circuit device design method of this embodiment. The figure for demonstrating an example of the design environment for applying the design method of the integrated circuit device of this embodiment. FIGS. 4A and 4B are diagrams showing examples of information included in the digital library information. FIG. 5A and FIG. 5B are diagrams showing another example of information included in the digital library information. The figure which shows an example of the simulation environment of a digital-analog mixed simulator. The figure which shows an example of a command file. The figure for demonstrating the structural example of an external host (MPU) model. 1 is a diagram showing a configuration example of a display driver that is an example of an integrated circuit device to which a design method according to an embodiment is applied. The figure for demonstrating the wiring layout between the digital circuit block and analog circuit block of a display driver by the design method of the conventional integrated circuit device. FIG. 11A is a diagram showing an example of a signal waveform in a real chip of a display driver according to a conventional integrated circuit device design method, and FIG. 11B is a display driver according to a conventional integrated circuit device design method. It is a figure which shows the example of the signal waveform in the digital-analog simulation of. FIG. 4 is a diagram for explaining a wiring layout between a digital circuit block and an analog circuit block of a display driver by the integrated circuit device design method according to the embodiment. FIG. 6 is a diagram illustrating an example of signal waveforms in a digital-analog simulation of a display driver by the integrated circuit device design method of the present embodiment. 1 is a diagram for explaining a design support system and a design support program for an integrated circuit device according to an embodiment. FIG. 1 is an example of a block diagram of an electronic device including an integrated circuit device. 16A to 16C are examples of external views of various electronic devices. FIG. 17A to FIG. 17C are diagrams for explaining a conventional method of designing an integrated circuit device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Integrated circuit device, 10 Digital circuit block, 12-1 logic cell, 12-2 Logic cell, 14-1 Output port, 14-2 Input port, 16-1 wiring, 16-2 wiring, 20 Analog circuit block, 22 -1 analog cell, 22-2 analog cell, 24-1 input port, 24-2 output port, 32-1 repeater cell, 32-2 repeater cell, 34-1 wiring, 34-2 wiring, 36-1 wiring, 36-2 wiring, 50 digital block netlist, 60 placement and routing & RC extraction tool, 70 digital block layout information, 80 digital block netlist, 90 digital block RC information, 100 TOP circuit netlist (Verilog), 102 TOP circuit netlist (Spice), 110 Floor plan tool, 120 OP circuit layout information, 130 RC extraction tool, 140 TOP circuit RC information, 150 delay time calculation tool, 160 digital library information, 162 analog library information, 170 delay time information, 180 analog block netlist, 190 partitioning information, 200 digital -Analog mixed simulator, 210 simulation netlist generation processing unit, 212 logic simulation netlist, 214 circuit simulation netlist, 220 logic simulation execution processing unit, 230 circuit simulation execution processing unit, 250 simulation result information, 300 simulation model Information, 310 External host (MPU) model, 312 Command analysis unit, 313 Command code, 3 4 Output signal generation unit, 315 parameters, 317 mode code, 320 memory model, 330 internal module model, 350 test input information (test bench), 352 command file, 354 data file, 362 parallel I / F signal, 364 serial I / F signal, 366 mode selection signal, 370 host (MPU) interface circuit, 400 display driver, 402 power input, 410 digital circuit block, 412-1 to 412-176 data line, 414 latch signal line, 416-1 to 416 176 Repeater cell, 417-1 to 417-176 Data signal line, 418-1 to 418-176 Repeater cell, 419-1 to 419-176 Latch signal line, 420 Display memory, 422 Memory cell array, 424 -Address decoder, 426 Column address decoder, 428 Write / read circuit, 430 Internal interface circuit block, 432 Host interface circuit, 434 RGB interface circuit, 440 Control circuit block, 442 Overall control circuit, 444 Display timing control circuit, 450 Analog circuit Block, 460 source driver, 462-1 to 462-176 driver cell, 464-1 to 464-176 data latch circuit, 470 gate driver, 480 gradation voltage generation circuit, 490 power supply circuit, 500 display panel, 600 design support system , 610 processing unit, 612 overall circuit connection information generation means, 614 overall circuit layout information generation means, 616 delay time information generation means, 618 overall circuit simulation Execution means, 620 Overall circuit wiring load information generation means, 622 Digital circuit block wiring load information generation means, 630 operation section, 640 storage section, 642 library information storage section, 650 information storage medium, 660 display section, 670 sound output section, 680 communication unit, 800 electronic device, 810 microcomputer (integrated circuit device), 820 input unit, 830 memory, 840 power generation unit, 850 LCD, 860 sound output unit, 870 LCD driver (integrated circuit device), 950 mobile phone, 952 Dial button, 954 LCD, 956 speaker, 960 portable game device, 962 operation button, 964 cross key, 966 LCD, 968 speaker, 970 personal computer, 972 keyboard, 974 LCD, 976 sound output unit

Claims (10)

An integrated circuit device design method including a digital circuit block and an analog circuit block,
Whole circuit connection information creation for connecting at least one repeater cell between the digital circuit block and the analog circuit block and creating connection information of the whole circuit including the digital circuit block, the analog circuit block, and the repeater cell Steps,
An overall circuit layout information creating step for arranging the digital circuit block, the analog circuit block, and the repeater cell, wiring each net, and creating layout information of the entire circuit;
A delay time information creating step of calculating a delay time due to a wiring load of a net connected to the repeater cell based on the connection information and the layout information of the entire circuit, and creating delay time information including the delay time;
An entire circuit simulation execution step for executing a digital / analog mixed simulation for the entire circuit based on the connection information of the entire circuit;
In the overall circuit simulation execution step,
A design method for an integrated circuit device, wherein a logic simulation based on the delay time information is executed for the digital circuit block and the repeater cell, and a circuit simulation is executed for the analog circuit block. In claim 1,
Overall circuit wiring load information for creating wiring load information of the entire circuit including information on parasitic resistance and parasitic capacitance of wiring of each net included in the entire circuit based on the connection information and the layout information of the entire circuit Including creation steps,
In the delay time information creating step,
A design method of an integrated circuit device, wherein a delay time due to a wiring load of a net connected to the repeater cell is calculated based on the wiring load information of the entire circuit. In claim 2,
Digital circuit block wiring for creating wiring load information of the digital circuit block including information on parasitic resistance and parasitic capacitance of wiring of each net included in the digital circuit block based on connection information and layout information of the digital circuit block Including load information creation step,
In the delay time information creating step,
An integration characterized in that a delay time due to a load of each wiring including a net wiring connected to the repeater cell is calculated based on the wiring load information of the entire circuit and the wiring load information of the digital circuit block. Circuit device design method. In any one of Claims 1 thru | or 3,
In the overall circuit layout information creation step,
The entire circuit includes a plurality of repeater cells connected to the analog circuit block, and the repeater cells are connected to the analog circuit block so that the wiring length of each net is included in a predetermined range. A method for designing an integrated circuit device, comprising arranging cells. In claim 4,
In the overall circuit layout information creation step,
A design method for an integrated circuit device, wherein the repeater cells are arranged so that wirings of the nets have the same length. In any one of Claims 1 thru | or 5,
In the overall circuit layout information creation step,
A design method for an integrated circuit device, wherein the repeater cell connected to the analog circuit block is disposed in the vicinity of a port to which the repeater cell of the analog circuit block is connected. A design support system for supporting the design of an integrated circuit device including a digital circuit block and an analog circuit block,
Whole circuit connection information generation for connecting at least one repeater cell between the digital circuit block and the analog circuit block and generating connection information of an entire circuit including the digital circuit block, the analog circuit block, and the repeater cell Means,
An entire circuit layout information generating means for arranging the digital circuit block, the analog circuit block, and the repeater cell, wiring each net, and generating layout information of the entire circuit;
Delay time information generating means for calculating a delay time due to a wiring load of a net connected to the repeater cell based on the connection information and the layout information of the entire circuit, and generating delay time information including the delay time;
Based on the connection information of the whole circuit, and a whole circuit simulation execution means for executing a digital / analog mixed simulation for the whole circuit,
The overall circuit simulation execution means includes:
A design support system for an integrated circuit device, wherein a logic simulation based on the delay time information is executed for the digital circuit block and the repeater cell, and a circuit simulation is executed for the analog circuit block. A design support program for supporting the design of an integrated circuit device including a digital circuit block and an analog circuit block,
Whole circuit connection information generation for connecting at least one repeater cell between the digital circuit block and the analog circuit block and generating connection information of an entire circuit including the digital circuit block, the analog circuit block, and the repeater cell Means,
An entire circuit layout information generating means for arranging the digital circuit block, the analog circuit block, and the repeater cell, wiring each net, and generating layout information of the entire circuit;
Delay time information generating means for calculating a delay time due to a wiring load of a net connected to the repeater cell based on the connection information and the layout information of the entire circuit, and generating delay time information including the delay time;
Based on the connection information of the entire circuit, to cause the computer to function as an entire circuit simulation execution means for executing a digital / analog mixed simulation for the entire circuit,
The overall circuit simulation execution means includes:
A design support program for an integrated circuit device, wherein a logic simulation based on the delay time information is executed for the digital circuit block and the repeater cell, and a circuit simulation is executed for the analog circuit block.   An integrated circuit device design method according to any one of claims 1 to 6, an integrated circuit device design support system according to claim 7, or an integrated circuit device design program according to claim 8. An integrated circuit device characterized by being designed and manufactured. An integrated circuit device according to claim 9;
Data input means to be processed by the integrated circuit device;
And an output means for outputting data processed by the integrated circuit device.