CN107203676A - To the method and data handling system of the timing performance for lifting IC design - Google Patents
To the method and data handling system of the timing performance for lifting IC design Download PDFInfo
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Abstract
A kind of method and data handling system to lift the timing performance of IC design, the method for timing performance that should be to lift an IC design includes：Set the multiple set parameters and its correspondence reference index on timing performance；The sequential analysis report on IC design is obtained, wherein IC design includes multiple paths and Time-Series analysis report includes a timing information in each path；According to timing information, an at least critical path is determined from path；The multiple parameter values of the set parameter of an at least critical path are captured, and according to parameter value and corresponding reference index, determine multiple anomaly parameters；According to anomaly parameter, a diagnostic result is produced；And according to diagnostic result, an Optimizing Suggestions information is produced, so as to lift the timing performance of an at least critical path according to Optimizing Suggestions information.
Description
Technical field
The present invention is related to Time-Series analysis and diagnosis, is espespecially related to be lifted the timing performance of an IC design
Method.
Background technology
Electric design automation synthetics (EDA tools) is the important auxiliary tool of current semiconductor designs.
Today of high-effect circuit design is being emphasized, electric design automation synthetics is except assisting chip designer's processing million to count
Outside the transistor for measuring the above, with greater need for the evolution of manufacture of semiconductor technology and Making programme, import appropriate algorithm with
Lifting circuit performance reduces product development cost simultaneously.
In design implementation process, the wiring of delay and estimation to an actual functional capability block designed is needed in the mapped
Delay carries out Time-Series analysis, and after placement-and-routing, the functional block delay and practical wiring that also connected up to practical layout are delayed
Carry out Time-Series analysis.Traditional eda tool can provide the sequential address of critical path.
However, the sequential address that traditional EDA instrument is only capable of providing critical path is referred to for designer, it is impossible to provide timing
The reason for be able to not being lifted, it is impossible to provide Optimizing Suggestions, when circuit needs to optimize, designer needs manually to analyze one by one
Reason simultaneously carries out manual modification optimization, therefore take considerable time and manpower.
Accordingly, it would be desirable to which a kind of can automatically analyze the method that sequential can not lift reason and provide Optimizing Suggestions.
The content of the invention
In view of this, the present invention provides a kind of method and its dependency number to lift the timing performance of IC design
According to processing system.
One embodiment of the invention provides a kind of method to lift the timing performance of an IC design, above-mentioned side
Method comprises the following steps：Set the multiple set parameters and its correspondence reference index on timing performance；Obtain on above-mentioned collection
Into a sequential analysis report of circuit design, wherein said integrated circuit design includes multiple paths and above-mentioned Time-Series analysis is reported
Include a timing information in each above-mentioned path；According to above-mentioned timing information, an at least critical path is determined from above-mentioned path；
The multiple parameter values of the above-mentioned set parameter of an above-mentioned at least critical path are captured, and according to above-mentioned parameter value and above-mentioned corresponding ginseng
Index is examined, multiple anomaly parameters are determined；According to above-mentioned anomaly parameter, a diagnostic result is produced；And according to above-mentioned diagnostic result,
An Optimizing Suggestions information is produced, so as to lift the timing performance of an above-mentioned at least critical path according to above-mentioned Optimizing Suggestions information.
Another embodiment of the present invention provides a kind of data handling system, at least including a storage element and a processor.
Storage element is to store multiple set parameters and its correspondence reference index on timing performance.It is single that processor is coupled to storage
Member, for obtaining the sequential analysis report on an IC design, wherein said integrated circuit design includes multiple roads
Footpath and above-mentioned Time-Series analysis report include a timing information in each above-mentioned path, according to above-mentioned timing information, from above-mentioned path
A middle decision at least critical path, the multiple parameter values of the above-mentioned set parameter of the above-mentioned at least critical path of acquisition, and according to
Above-mentioned parameter value and above-mentioned corresponding reference index, determine multiple anomaly parameters, according to above-mentioned anomaly parameter, produce a diagnosis knot
Really；And according to above-mentioned diagnostic result, an Optimizing Suggestions information is produced, so that above-mentioned extremely according to the lifting of above-mentioned Optimizing Suggestions information
The timing performance of a few critical path.
The above method of the present invention can be implemented via the device or system of the present invention, and it is the hard of executable specific function
Part or firmware, can also be embodied in a recording medium by procedure code mode, and combine specific hardware to implement.Work as procedure code
When being loaded into and performed by electronic installation, processor, computer or machine, electronic installation, processor, computer or machine become to use
To carry out the device or system of the present invention.
Brief description of the drawings
Fig. 1 is the hardware structure schematic diagram of the data handling system according to the embodiment of the present invention.
Fig. 2 is the software architecture schematic diagram of the data handling system according to the embodiment of the present invention.
Fig. 3 shows the flow chart of the method for the timing performance to lift IC design of one embodiment of the invention.
Fig. 4 shows the flow of the method for the timing performance to lift IC design of another embodiment of the present invention
Figure.
Fig. 5 A are the schematic diagram extracted according to the optimization tool analytical parameters of the embodiment of the present invention.
Fig. 5 B are the optimization tool analytical parameters and the analyze data schematic diagram of reference index according to the embodiment of the present invention.
Fig. 5 C are the analyze data schematic diagram of the optimization tool analytical parameters according to the embodiment of the present invention.
Fig. 6 is the analyze data schematic diagram of the logical design analytical parameters according to the embodiment of the present invention.
Fig. 7 is the schematic diagram of the optimization tool analytical parameters according to another embodiment of the present invention.
Wherein, symbol is simply described as follows in accompanying drawing：
100~data handling system；110~storage device；120~processor；130~display device；210~critical path
Footpath acquisition module；220~parameter acquisition module；230~Optimizing Suggestions information-generation module；S302、S304、S306、S308、
S310~step；S402, S404, S406, S408, S410, S412, S414, S416~step；And 502,504,512,514,
602nd, 604,606~supplemental characteristic.
Embodiment
For objects, features and advantages of the present invention can be become apparent, especially exemplified by going out Examples below, and coordinate institute's accompanying drawing
Formula, is described in detail below.It is noted that the embodiment that this section is described be intended to indicate that embodiments of the present invention and
It is not used to limit protection scope of the present invention, any one skilled in the art is not departing from the spirit and scope of the present invention
Interior, when can do a little change and retouching, therefore protection scope of the present invention is when being defined of being defined of claims.It should be understood that under
Row embodiment can be realized via software, hardware, firmware or above-mentioned any combination.
The embodiment of the present invention provides the extraction of key path time sequence performance parameter, reason in a kind of Design of Digital Integrated Circuit and examined
The disconnected automatic mode with Optimizing Suggestions, parameter needed for being extracted automatically from sequential address and database, and then examine automatically
The reason for disconnected key path time sequence performance can not be lifted, finds out timing performance lifting bottleneck and provides Optimizing Suggestions automatically.
Fig. 1 shows the hardware structure schematic diagram of the data handling system 100 according to the embodiment of this exposure one.In some implementations
Example in, data handling system 100 can for desktop PC, be integrally formed (All-In-One, AIO) computer, general pen electricity,
Stylus electricity or a portable apparatus or hand-held device, e.g. personal digital assistant (PDA), smart mobile phone (smart
Phone), tablet PC (tablet), mobile phone, mobile Internet device (Mobile Internet Device,
MID), mobile computer, vehicular computer, digital camera, digital media player, game device or any kind of movement
Computing device, however, those skilled in the art should be appreciated that the present invention is not limited thereto.
As shown in figure 1, the hardware structure of data handling system 100 can at least include storage device 110, processor 120 with
And display device 130.Storage device 110 is the computer readable storage media of non-transient (non-transitory), can be
Nonvolatile storage medium is (for example：It is read-only storage (Read-Only Memory, ROM), flash memory (Flash memory), hard
Disk, CD etc.), volatile storage media (for example：Random access memory (Radom Access Memory, RAM)) or both
Any combination, to store related data, such as the intermediate data in calculating process and implementing result data.Storage device
110 also can be used to store the instruction set and/or procedure code program module for being available for processor 120 to perform.In general, program module
Include Chang Xu (routines), program (program), object (object), element (component) etc..Storage device 110 is also
Required each item data can be stored, for example：Each parameter and its reference index and the knowledge for including every reference Optimizing Suggestions
Storehouse etc..Wherein, above-mentioned parameter is the parameter sets that possible impacted to timing performance, and knowledge base then includes various exceptions
One group corresponding to reason refers to Optimizing Suggestions.In the present invention, can rule of thumb count in advance may influence timing performance
Numerous parameters, and the abnormal cause according to represented by each parameter proposes according to conventional design experiences or via machine learning
The feasible program of abnormal cause is solved as Optimizing Suggestions are referred to, above-mentioned knowledge base is produced with construction.Specific parameter and its ginseng
Examine index and the details with reference to Optimizing Suggestions refers to the explanation of following embodiment.
Processor 120 is coupled to storage device 110 and display device 130, can be loaded into and perform from storage device 110 and refers to
Order collection and/or procedure code, it is of the present invention to carry to perform with the running of display device 130 to control storage device 110
The method for rising timing performance.Processor 120 can be general processor, microprocessor (Micro-Control Unit, MCU), figure
Shape processor (Graphics Processing Unit, GPU) or digital signal processor (Digital Signal
Processor, DSP) etc., to provide data analysis, processing and the function of computing.The above-mentioned method to lift timing performance
Comprise the following steps：Obtain each critical path during a sequential analysis report of a circuit design, sequentially crawl Time-Series analysis are reported
The corresponding anomaly parameter in footpath, and according to the corresponding abnormal cause of each anomaly parameter, corresponding Optimizing Suggestions information is produced, so that logical
The timing performance that Optimizing Suggestions information lifts each critical path is crossed, its details will be illustrated after.
Those skilled in the art are when it is understood that the circuit logic in processor 120 generally may include multiple transistors, being used to
The running of the circuit logic is controlled with the function needed for providing and operation.Further, the specific structure of transistor and its it
Between connection relationship be typically determined by compiler, for example：Register transfer language (Register Transfer
Language, RTL) compiler can be operated by processor, the instruction shelves (script) of similar compositional language code is compiled into suitable
For designing or manufacturing the form needed for the circuit logic.
Display device 130 can show related data, and e.g. word, figure, interface and/or various information such as shows or is in
Existing result etc..Display device 130 can be used to present the picture of result, for example：Liquid crystal display (LCD).It should be understood that in one
In a little embodiments, display device 130 combines the screen of touch inductor (not shown).Touch control induction device has a touch-control table
Face, it includes the sensor of at least dimension to detect near or at an input tool such as finger or stylus in touch-control surface
Deng contact and action in its surface.Therefore, user can be carried out touch-control input order or be believed by display device 130
Number.
When it will be appreciated that the element shown in Fig. 1 is only to provide the example of an explanation, and it is not used to the limitation present invention's
Protection domain.For example, though not illustrating, data handling system 100 can also further comprise other functional units, for example：One
Or multiple buttons, keyboard, mouse, Contact plate, video lens, microphone and/or loudspeaker etc., to as man-machine interface with
User is interactive, and the present invention is not subject to the limits.
Fig. 2 shows the architecture diagram of data handling system 100 according to embodiments of the present invention.Data handling system 100
Software architecture include a critical path acquisition module 210, a parameter acquisition module 220 and an Optimizing Suggestions information and produce mould
Block 230.Critical path acquisition module 210, parameter acquisition module 220 and Optimizing Suggestions information-generation module 230 can be stored
In data handling system 100 storage device 110 (for example：Memory) in, and can be by the processor of data handling system 100
120 are loaded into and perform the method to lift timing performance of the present invention in opportune moment.
Particularly, processor 120 can be by controlling critical path acquisition module 210, parameter acquisition module 220 and excellent
Change the running of advisory information generation module 230 to perform the method to lift timing performance of the present invention.Specifically, handle
Device 120 can receive the sequential analysis report on a circuit design, further according to sequential by critical path acquisition module 210
The sequential relevant information of mulitpath in analysis report, determines one or more critical path, is picked by parameter acquisition module 220
Take all parameters of each critical path, and by the parameter value of all parameters, corresponding reference index is compared one by one, sentences
Break and to have abnormal anomaly parameter, and by Optimizing Suggestions information-generation module 230, above-mentioned anomaly parameter is considered as obstruction
The reason for timing performance is lifted, then corresponding Optimizing Suggestions information is for reason given above produced one by one, so as to lift each critical path
The timing performance in footpath.Parameter acquisition module 220 first rule of thumb can may influence the various parameters conduct of sequential with modeling decision
Above-mentioned set parameter, and it is used as using the reasonable value scope of each set parameter the corresponding reference index of the parameter value.For example,
Due to rule of thumb understanding, the line length long timing performance that may result in path can not be lifted further, therefore can will represent one
The long data of bus of the actual bus length in path are used as it as wherein one set parameter, and using the reasonable value scope of total line length
Reference index, for example, can set from the most short track lengths between a starting point in the path and terminating point as referring to line length,
And reference index is used as with the ratio with reference to line length using actual line length.Optimizing Suggestions information-generation module 230 can be according to different
Abnormal cause corresponding to normal parameter, corresponding one group is found out from the knowledge base of storage device 110 and refers to Optimizing Suggestions, and profit
With above-mentioned reference Optimizing Suggestions, the Optimizing Suggestions information is produced.
It will be appreciated that above-mentioned each element or module are a device with corresponding function, there can be appropriate hardware electricity
Road or element are to perform corresponding function, however, the device with entity not to be limited, it must also be corresponded to for virtual having
The program of function, software, or with handling, run the program, the device of software capability.And the side of above-mentioned each element running
Formula, can further refer to the explanation of following corresponding method.
Fig. 3 shows the flow chart of the method for the timing performance to lift IC design of one embodiment of the invention.
Referring to Fig. 1, Fig. 2 and Fig. 3.The method of timing performance to lift IC design according to embodiments of the present invention
Go for a data handling system, for example, be applicable to Fig. 1 data handling system 100 and added by processor 120
To perform.In this embodiment, it is assumed that storage device 110 preset on timing performance multiple set parameters and its
Correspondence reference index.
First, such as step S302, processor 120 obtains the Time-Series analysis report on an IC design to be analyzed
Accuse, wherein IC design includes multiple paths and Time-Series analysis report includes a timing information in each path.Yu Yishi
Apply in example, Time-Series analysis report can be provided by an eda tool, and processor 120 can receive the sequential point produced by eda tool
Analysis report.In another embodiment, processor 120 can also include above-mentioned eda tool, therefore processor 120 is when can produce above-mentioned
Sequence analysis report.
After Time-Series analysis report is obtained, such as step S304, processor 120 according to the timing information in each path, from
An at least critical path is determined in all paths.Particularly, Time-Series analysis report includes the timing information of mulitpath, locates
Reason device 120 Time-Series analysis can be reported in all paths timing information and the preset standard sequential that includes default sequential target
Information is compared, and judges critical path according to comparison result and a judgment criterion.In an embodiment, when certain all the way
The path just can be considered as a critical path by the timing information in footpath when being unsatisfactory for above-mentioned default sequential target.In another embodiment
In, when the timing information in a certain path is unsatisfactory for above-mentioned default sequential target and is just considered as the path during more than a specified range
One critical path, but the present invention is not limited thereto.
Then, such as step S306, processor 120 captures the parameter value of multiple set parameters of an at least critical path, and
According to the corresponding reference index of parameter value, multiple anomaly parameters are determined.In an embodiment, set parameter may include one first
Parameter and processor 120 are according to the parameter value and corresponding reference index of set parameter, and the step of determining above-mentioned anomaly parameter is also wrapped
Include：Compare the first parameter one first parameter value whether more than the first parameter one first corresponding reference index, if so, determining
One parameter is anomaly parameter.If on the contrary, first correspondence reference of the first parameter value of the first parameter not less than the first parameter refers to
Mark, the first parameter can be considered normal parameter, therefore can be excluded.
Particularly, processor 120 first rule of thumb can may influence numerous parameters of sequential with modeling decision, and with each
The reasonable value scope of parameter is as the corresponding reference index of the parameter value, and another one refers to the parameter value of each parameter with corresponding
Index is contrasted, and judges each parameter with the presence or absence of exception, and then obtain above-mentioned anomaly parameter.Above-mentioned parameter includes (but not limiting
In) below at least one：The long data of one bus, a front back logic series difference data, a transit time data, a unit are close
Degrees of data, a wiring degree of congestion data, a clock bias data, a piece of upper fluctuation data, a crosstalk delay data, Yi Jiyi
Maximum drive capacity unit ratio data etc..For example, due to rule of thumb understanding, path line length is long when may result in
Sequence be able to not can be lifted further, thus can the path total line length as a wherein parameter, and with the reasonable number of total line length
Value scope is used as its reference index.
In an embodiment, above-mentioned parameter can at least include a technology library analytical parameters, a logical design analytical parameters with
And optimization tool analytical parameters, wherein technology library analytical parameters are relevant with the technique Sink Characteristics used of IC design, patrol
Volume design analytical parameters it is relevant with the logical design of IC design, optimization tool analytical parameters are relevant with an eda tool.Lift
For example, technology library analytical parameters can be maximum drive capacity unit ratio data, and logical design analytical parameters can be front stage
Logic series difference data, optimization tool analytical parameters can be for the long data of bus, transit time data etc., but not limited to this.Its
In, the excessive explanation technology library of maximum drive capacity unit ratio is not complete enough in critical path, lacks the list of bigger driving force
Member.
After determining to be possible to anomaly parameter, such as step S308, processor 120 according to above-mentioned possible anomaly parameter,
A diagnostic result is produced, afterwards, such as step S310, processor 120 produces an Optimizing Suggestions information according to above-mentioned diagnostic result.
In some embodiments, anomaly parameter includes one first parameter (for example：The long data of bus), above-mentioned parameter includes the above-mentioned first ginseng
Count and associate multiple second parameters of above-mentioned first parameter (for example：Cell density data and wiring degree of congestion data
Deng), then processor 120 is according to above-mentioned anomaly parameter, and the step of producing above-mentioned diagnostic result also includes processor 120 and produce correspondence
Multiple analysis information of above-mentioned second parameter, and according to above-mentioned analysis information, produce corresponding above-mentioned the above-mentioned of first parameter and examine
Disconnected result.In an embodiment, anomaly parameter can be a technology library analytical parameters and processor 120 can be according to above-mentioned technology library point
Parameter is analysed, the Optimizing Suggestions information of the technology library optimization based on IC design is produced.In another embodiment, anomaly parameter
It can be produced according to above-mentioned logical design analytical parameters and be based on integrated circuit for a logical design analytical parameters and processor 120
The Optimizing Suggestions information of the logical design optimization of design.In another embodiment, anomaly parameter can analyze ginseng for an optimization tool
Count and processor 120 can produce the Optimizing Suggestions information based on eda tool angle according to above-mentioned optimization tool analytical parameters.
Particularly, in step S308 and step S310, processor 120 can further analyze each of anomaly parameter correlation
Parameter is planted, it is determined that the reason for timing performance is lifted is hindered, and it is corresponding or similar according to being found out the reason for finding out from knowledge base
One group produces Optimizing Suggestions information with reference to Optimizing Suggestions, from every side such as optimization design, modified technique storehouse, guidance tool optimization
In terms of provide corresponding Optimizing Suggestions automatically, and designer just can adjust each critical path according to above-mentioned Optimizing Suggestions information
Design, complies with reference index, so as to lift the timing performance of over all Integration circuit design.
Fig. 4 shows the flow of the method for the timing performance to lift IC design of another embodiment of the present invention
Figure.Referring to Fig. 1, Fig. 2 and Fig. 4.Timing performance to lift IC design according to embodiments of the present invention
Method goes for a data handling system, for example, be applicable to Fig. 1 data handling system 100 and by processor
120 are performed.In this embodiment, it is assumed that the timing information in each path in being reported according to Time-Series analysis of processor 120,
Determine multiple critical paths in all paths reported from Time-Series analysis.As an example it is assumed that showing in Time-Series analysis report
Show and 10 paths for being unsatisfactory for default sequential target are had in 100 paths, then this 10 paths can be considered as critical path.
First, processor 120 chooses a critical path (step S402).Then, processor 120 captures selected pass
One parameter (step S404) in key path, and compare whether this parameter exceedes its correspondence index (step S406), if so, representing
There is exception in this parameter, then be anomaly parameter (step S408) by this reference record, then perform step S410.
If this parameter is not less than its correspondence index (step S406's is no), it is normal to represent this parameter, and processor 120 is then
Perform step S410.In step S410, processor 120 judges whether the complete all parameters of inspected.Assuming that still thering is parameter not yet to examine
(step S410's is no) is looked into, then repeats abovementioned steps S404 to step S408, another ginseng of the selected critical path of crawl
Number, and compare whether the parameter exceedes its correspondence index, if so, being then anomaly parameter by the reference record, until all parameters
Untill all inspected is finished.
When all inspected is finished all parameters (step S410's be), then processor 120 lists selected key
All anomaly parameters (step S412) in path and the Optimizing Suggestions (step S414) for listing selected critical path.Clearly come
Say, processor 120 can find out be possible to anomaly parameter, further according to above-mentioned possible anomaly parameter, produce a diagnostic result, it
Afterwards, further according to above-mentioned diagnostic result, produce an Optimizing Suggestions information and via display device 130 list all anomaly parameters and
Above-mentioned Optimizing Suggestions information is listed as the Optimizing Suggestions of selected critical path, to be supplied to relevant design personnel to refer to,
Subsequently optimized.
Then, processor 120 judges whether the complete all critical paths (step S416) of inspected.Not yet checked assuming that still having
Critical path (step S416's is no), then processor 120 repeat abovementioned steps S402 to step S414, choose next key
Path, then capture the corresponding index of each parameter of selected critical path one by one and be compared, all anomaly parameters are recorded,
List all anomaly parameters of the critical path of each selection one by one again and list the Optimizing Suggestions of selected critical path, directly
Untill all critical paths are all selected and checked and finished.When all inspected is finished all critical paths (step S416's
It is), just terminate whole flow process.
The method of an application present invention is exemplified below to diagnose the embodiment that CPU core timing performance lifts bottleneck, is used to
Illustrate embodiment as the thin portion that the diagnostic analysis such as parameter extraction, cause diagnosis and Optimizing Suggestions is carried out to timing path, when can
Understand, the present invention is not limited thereto.In this embodiment, when mainly with total line length, front back logic series difference and transition
Between three parameters timing path is examined respectively as the example of optimization tool analytical parameters and logical design analytical parameters
Disconnected analysis.Mainly point three steps, are parameter extraction, cause diagnosis and Optimizing Suggestions respectively.
In first embodiment, parameter is the long data of an optimization tool analytical parameters such as bus and its corresponding cell density
Data and wiring degree of congestion data etc..It may result in timing performance because line length is long can not further be lifted, therefore
Timing performance can be judged whether by the long influence of line length according to the long data of bus.First, processor 120 is first by path
1 actual bus length is extracted from design to obtain the parameter value of the long data of bus, as shown in Fig. 5 A line segment 502.For
Convenient explanation, it is assumed that the timing path of critical path has a starting point A and a terminating point B and starting point A position coordinates table
It is shown as (X1, Y1), terminating point B position coordinates is expressed as (X2, Y2).Then, with reference to line length from the starting point A of timing path with
Terminating point B location is calculated and obtained, as shown in Fig. 5 A line segment 504.Specifically, as shown in Figure 5A, due to from timing path
The most short track lengths that starting point A reaches terminating point B are | X2-X1 |+| Y2-Y1 |, this line of shortest length length can be chosen as reference line
Long (reference indexs of the long data of bus).When actual line length is much larger than reference line for a long time (for example：Actual line length is more than reference line
When long 1.5 times), expression there may be roundabout (detour) phenomenon of coiling, cause timing performance not lifted further, it is necessary to
Designer is modified.For example, choosing a paths 1, its starting point A position coordinates is (853,342), terminating point B position
Coordinate is put for (1168,547).Calculate obtained reference line a length of 520 microns (um), and the reality in the path 1 extracted from design
Border line length is 1205 microns (um).Fig. 5 B are the optimization tool analytical parameters according to the embodiment of the present invention and the analysis of reference index
The schematic diagram of data, wherein transverse axis represent sequential (slack), and the longitudinal axis represents path line length.In this example, due to actual line length
(as shown in Figure 5 B 512) it is more than 1.5 times with reference to line length (as shown in Figure 5 B 514), that is, total line length parameter is joined more than it
Index is examined, it may thus be appreciated that the long data of the bus in path 1 are one of anomaly parameter.On the contrary, in another embodiment, if actual line
When length is not more than 1.5 times with reference to line length, the long data of bus in path 1 are to be considered as normal parameter.
Then, processor 120 carries out cause diagnosis just according to anomaly parameter, produces a diagnostic result.It is right in this example
In path 1, it is possible to determine that roundabout coiling is to cause one of the reason for paths timing performance can not be lifted further, is then entered
The reason for analysis of one step causes coiling roundabout phenomenon.Anomaly parameter " the long data of bus " corresponding parameter includes a standard density
(STD density) data and wiring degree of congestion (congestion) data.Wherein, standard density data represent A, B
Standard density in the rectangle frame that point is surrounded, if the value of standard density data is bigger, represents that standard density is bigger at position,
Too conference causes the roundabout phenomenon of coiling；Wiring degree of congestion parameter then represents the density connected up between A, B point, if journey is blocked in coiling
The value for spending parameter is bigger, represents that local obstruction is very serious, will also result in the roundabout phenomenon of coiling.Fig. 5 C are according to the embodiment of the present invention
Optimization tool analytical parameters analyze data schematic diagram, wherein transverse axis represents sequential (slack), and the longitudinal axis represents standard density.
In this example, by capturing the standard density (STD density) in the rectangle frame that A, B point are surrounded, the mark in rectangle frame is found
Quasi- density is 93% 80% (reference value rule of thumb chosen) for being higher than reference value.That is, because path institute is in place
Put place's standard density too big, cause the roundabout phenomenon of coiling.Then, processor 120 produces corresponding anomaly parameter for " bus long number
According to " diagnostic result be " local standard density is too high at path 1, reaches 93%, causes coiling roundabout ".
Afterwards, processor 120 can produce the Optimizing Suggestions information for path 1, for designer according to above-mentioned diagnostic result
With reference to.In this example, Optimizing Suggestions information may include the Optimizing Suggestions information below based on eda tool angle：" it is recommended that：(1) please
The floor planning of { (853,342) (1168,547) } areas adjacent is adjusted, to reduce local standard density；And/or (2) (853,
342) (1168,547) } the maximum standard density constraint of region setting ".Therefore, designer just simply can build with reference to above-mentioned optimization
Information is discussed, the local standard density of { (853,342) (1168,547) } areas adjacent is reduced and/or maximum standard density is set about
The exception that the design methods such as beam cause the long problem of line length that solves path 1, so that the timing performance in path 1 is carried
Rise.
In second embodiment, parameter is a logical design analytical parameters such as front back logic series (logic level)
Difference data etc..Timing performance is also resulted in because logic series is long can not further to be lifted, therefore can be patrolled according to front stage
Series difference data is collected to judge whether timing performance by the unbalanced influence of front back logic series.Fig. 6 is according to this hair
The analyze data schematic diagram of the logical design analytical parameters of bright embodiment, wherein transverse axis represent sequential (slack), and the longitudinal axis represents to patrol
Collect series.As shown in fig. 6, to obtain above-mentioned front back logic series difference data, extracting choose the previous of timing path respectively
Level (N-1) (curve 602 as shown in Figure 6), this level (N) (curve 604 as shown in Figure 6), rear stage (N+1) are (as shown in Figure 6
Curve 606) logic series.For example for path 2, the logic series level (N-1) of previous stage is 16, the logic of this grade
Series level (N) is 30, and the logic series level (N+1) of rear stage is 22.In this example, the level (N) in path 2-
Level (N-1)=30-16=14 and level (N)-level (N+1)=30-22=8, therefore its front back logic series is poor
Value is set to the maximum difference in both, i.e., 14 grade.Because the front back logic series difference in path 2 exceedes 10 grades of reference index,
It may thus be appreciated that the front back logic series difference data in path 2 is one of anomaly parameter.
Then, processor 120 carries out cause diagnosis just according to anomaly parameter, produces a diagnostic result.It is right in this example
In path 2, processor 120 can be determined that logic series is unbalanced and cause the paths timing performance not lifted further
One of reason.Then, produce and tied on the corresponding anomaly parameter in path 2 for a diagnosis of " front back logic series difference data "
Be really " path 2 and the logic series of front stage are unbalanced, and 16/30/22 ".
Afterwards, processor 120 can produce the Optimizing Suggestions information for path 2, for designer according to above-mentioned diagnostic result
With reference to.In this example, Optimizing Suggestions information may include the information of the logical design optimization below based on IC design：" build
View：The streamline at path 2 please be redesign, so that logic series is balanced ".
In 3rd embodiment, parameter is another optimization tool analytical parameters such as transit time (transition time)
Data etc..Similarly, delay is also resulted in because transit time is long excessive, causes timing performance not lifted further, because
This can also judge whether that timing performance is influenceed by transition overlong time according to transit time data.Fig. 7 is according to this hair
The schematic diagram of the optimization tool analytical parameters of bright embodiment, wherein transverse axis represent sequential (slack), and the longitudinal axis represents transit time.
To obtain above-mentioned transit time data, transit time value in path to be analyzed at each pin and rule of thumb is extracted respectively
80ps is chosen as with reference to transit time (reference index).As an example it is assumed that for path 3, the transition at pin u509/i0
Time is 116ps, more than transit time 80ps is referred to, then the transit time data in path 3 can be considered as into one of anomaly parameter.
For path 3, processor 120 can be determined that transit time long causes the paths timing performance can not be further
One of the reason for lifting, then, it is " u509/i0 in path 3 to produce on a diagnostic result of the anomaly parameter including path 3
The transit time at place is excessive, 116ps ".Afterwards, processor 120 can be produced for path base below 3 according to above-mentioned diagnostic result
In the Optimizing Suggestions information of eda tool angle, referred to for designer：" it is recommended that：(1) the maximum transit time at u509/i0 is checked
Constraint；(2) line length at u509/i0 is reduced；(3) driving force of increase u509/i0 driver element；(4) increase before u509/i0
Plus driver element ".
Therefore, at according to the method and its related data of the timing performance to lift an IC design of the present invention
Reason system, can carry out the parameter extraction of critical path automatically according to the Time-Series analysis report on IC design, and can be fast
It is fast automatic the reason for be diagnosed to be obstruction key path time sequence performance boost, and from design in itself, technology library and instrument optimization energy
Optimizing Suggestions are provided in terms of power, instruct user to be quickly and efficiently modified optimization, so as to save significantly on time and manpower.
The method of the present invention, or specific modality or part thereof, can exist with the form of procedure code.Procedure code can be included
In tangible media, such as floppy disk, disc, hard disk or any other machine-readable (such as embodied on computer readable) storage medium,
Also or the computer program product of external form is not limited to, wherein, when procedure code is by machine, when such as computer is loaded into and performed,
This machine becomes to participate in the device of the present invention.Procedure code also can by some transmission medium, such as electric wire or cable, optical fiber,
Or any transmission form is transmitted, wherein, when procedure code is by machine, when such as computer is received, is loaded into and performs, this machine
Become to participate in device of the invention.When implementing in general service image processor, procedure code combination image processor is carried
The unique apparatus of application particular logic circuit is similar to for an operation.
Present pre-ferred embodiments are the foregoing is only, so it is not limited to the scope of the present invention, any to be familiar with sheet
The personnel of item technology, without departing from the spirit and scope of the present invention, further can be improved and be changed on this basis, because
This protection scope of the present invention is defined when the scope defined by following claims.
Claims (16)
1. a kind of method to lift the timing performance of IC design, it is characterised in that the above method includes following step
Suddenly：
Set the multiple set parameters and its correspondence reference index on timing performance；
Obtain on said integrated circuit design Time-Series analysis report, wherein said integrated circuit design include multiple paths and
Above-mentioned Time-Series analysis report includes the timing information in each above-mentioned path；
According to above-mentioned timing information, an at least critical path is determined from above-mentioned path；
Capture the multiple parameter values of the above-mentioned set parameter of an above-mentioned at least critical path, and according to above-mentioned parameter value with it is above-mentioned right
Reference index is answered, multiple anomaly parameters are determined；
According to above-mentioned anomaly parameter, diagnostic result is produced；And
According to above-mentioned diagnostic result, Optimizing Suggestions information is produced, so as to lift above-mentioned at least one according to above-mentioned Optimizing Suggestions information
The timing performance of critical path.
2. according to the method described in claim 1, it is characterised in that above-mentioned anomaly parameter includes the first parameter, above-mentioned set ginseng
Number includes multiple second parameters of above-mentioned first parameter and above-mentioned first parameter of association, and above-mentioned according to above-mentioned anomaly parameter
The step of producing above-mentioned diagnostic result also includes：
Produce multiple analysis information of above-mentioned second parameter of correspondence；And
According to above-mentioned analysis information, the above-mentioned diagnostic result of corresponding above-mentioned first parameter is produced.
3. according to the method described in claim 1, it is characterised in that above-mentioned anomaly parameter includes technology library analytical parameters, logic
Design analytical parameters and optimization tool analytical parameters, above-mentioned technology library analytical parameters and said integrated circuit design technique used
The characteristic in storehouse is relevant, and above-mentioned logical design analytical parameters are relevant with the logical design that said integrated circuit is designed, above-mentioned optimization work
Have analytical parameters relevant with eda tool.
4. method according to claim 3, it is characterised in that also include：
According to above-mentioned technology library analytical parameters, the above-mentioned Optimizing Suggestions of the technology library optimization designed based on said integrated circuit are produced
Information.
5. method according to claim 3, it is characterised in that also include：
According to above-mentioned logical design analytical parameters, the above-mentioned optimization of the logical design optimization designed based on said integrated circuit is produced
Advisory information.
6. method according to claim 3, it is characterised in that also include：
According to above-mentioned optimization tool analytical parameters, the above-mentioned Optimizing Suggestions information based on above-mentioned eda tool angle is produced.
7. according to the method described in claim 1, it is characterised in that above-mentioned set parameter include data below at least one：Always
Line length data, front back logic series difference data, transit time data, cell density data, wiring degree of congestion data, when
Data, crosstalk delay data and maximum drive capacity unit ratio data are fluctuated on clock deviation data, piece.
8. according to the method described in claim 1, it is characterised in that above-mentioned set parameter includes the first parameter, and above-mentioned
According to above-mentioned parameter value and above-mentioned corresponding reference index, the step of determining above-mentioned anomaly parameter also includes：
Whether the first parameter value for comparing above-mentioned first parameter exceedes the first corresponding reference index of above-mentioned first parameter；And
If so, determining that above-mentioned first parameter is above-mentioned anomaly parameter.
9. a kind of data handling system, it is characterised in that at least include：
Storage element, to store multiple set parameters and its correspondence reference index on timing performance；And
Processor, is coupled to above-mentioned storage element, for obtaining the Time-Series analysis report on IC design, wherein above-mentioned
IC design includes multiple paths and above-mentioned Time-Series analysis report includes the timing information in each above-mentioned path, according to above-mentioned
Timing information, determines an at least critical path from above-mentioned path, captures the above-mentioned set parameter of an above-mentioned at least critical path
Multiple parameter values, and according to above-mentioned parameter value and above-mentioned corresponding reference index, multiple anomaly parameters are determined, according to above-mentioned exception
Parameter, produces diagnostic result；And according to above-mentioned diagnostic result, Optimizing Suggestions information is produced, so that according to above-mentioned Optimizing Suggestions
Information lifts the timing performance of an above-mentioned at least critical path.
10. data handling system according to claim 9, it is characterised in that also including display device, above-mentioned display device
Above-mentioned processor is coupled to, to show above-mentioned diagnostic result and above-mentioned Optimizing Suggestions information including above-mentioned anomaly parameter.
11. data handling system according to claim 9, it is characterised in that above-mentioned anomaly parameter includes the first parameter, on
Multiple second parameters of the set parameter including above-mentioned first parameter and above-mentioned first parameter of association are stated, and above-mentioned processor is also
Produce multiple analysis information of above-mentioned second parameter of correspondence and according to above-mentioned analysis information, produce corresponding above-mentioned first parameter
Above-mentioned diagnostic result.
12. data handling system according to claim 9, it is characterised in that above-mentioned anomaly parameter is analyzed including technology library
Parameter, logical design analytical parameters and optimization tool analytical parameters, above-mentioned technology library analytical parameters are set with said integrated circuit
The technique Sink Characteristics used of meter are relevant, and above-mentioned logical design analytical parameters are relevant with the logical design that said integrated circuit is designed,
Above-mentioned optimization tool analytical parameters are relevant with eda tool.
13. data handling system according to claim 12, it is characterised in that above-mentioned anomaly parameter is above-mentioned technology library point
Parameter is analysed, and above-mentioned processor produces the technique designed based on said integrated circuit always according to above-mentioned technology library analytical parameters
The above-mentioned Optimizing Suggestions information of storehouse optimization.
14. data handling system according to claim 12, it is characterised in that above-mentioned anomaly parameter is above-mentioned logical design
Analytical parameters, and above-mentioned processor produces what is designed based on said integrated circuit always according to above-mentioned logical design analytical parameters
The above-mentioned Optimizing Suggestions information of logical design optimization.
15. data handling system according to claim 12, it is characterised in that above-mentioned anomaly parameter is above-mentioned optimization tool
Analytical parameters, and above-mentioned processor is always according to above-mentioned optimization tool analytical parameters, produces based on the upper of above-mentioned eda tool angle
State Optimizing Suggestions information.
16. data handling system according to claim 9, it is characterised in that above-mentioned set parameter includes data below extremely
Few one：The long data of bus, front back logic series difference data, transit time data, cell density data, wiring obstruction journey
Degrees of data, clock bias data, fluctuation data, crosstalk delay data and maximum drive capacity unit ratio data on piece.
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