JP2009111423A - Gan crystal substrate and manufacturing method therefor, and semiconductor device and manufacturing method therefor - Google Patents

Gan crystal substrate and manufacturing method therefor, and semiconductor device and manufacturing method therefor Download PDF

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JP2009111423A
JP2009111423A JP2009013402A JP2009013402A JP2009111423A JP 2009111423 A JP2009111423 A JP 2009111423A JP 2009013402 A JP2009013402 A JP 2009013402A JP 2009013402 A JP2009013402 A JP 2009013402A JP 2009111423 A JP2009111423 A JP 2009111423A
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gan crystal
crystal substrate
back surface
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gan
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JP4380791B2 (en
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Jinko Tanaka
仁子 田中
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Sumitomo Electric Industries Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a GaN crystal substrate and a manufacturing method therefor which enable the growth of a semiconductor layer with fine crystallinity on a crystal growth surface, and to provide a semiconductor device and a manufacturing method therefor. <P>SOLUTION: The GaN crystal substrate 10 has a back surface opposite to the crystal growth surface 10c. The back surface shows a warp w<SB>(R)</SB>per the length of the back surface of 5.08 cm that is calculated at -35 μm≤w<SB>(R)</SB>≤45 μm, which represents the sum of the distance from a maximum displacement of a warped surface toward one side from an optimum surface to the optimum surface and the distance from a maximum displacement of a warped surface toward the other side from the optimum surface to the optimum surface. The manufacturing method for the semiconductor device includes a step of selecting the GaN crystal substrate 10 as a substrate and growing at least one group III nitride crystal layer 20 on the crystal growth surface 10c of the GaN crystal substrate 10. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、発光素子、電子素子、半導体センサなどの半導体デバイスに用いられるGaN結晶基板およびその製造方法、ならびに基板としてこのGaN結晶基板を備える半導体デバイスおよびその製造方法に関する。   The present invention relates to a GaN crystal substrate used for a semiconductor device such as a light emitting element, an electronic element, and a semiconductor sensor, a manufacturing method thereof, a semiconductor device including the GaN crystal substrate as a substrate, and a manufacturing method thereof.

GaN結晶基板は、発光素子、電子素子、半導体センサなどの半導体デバイスの基板として非常に有用なものである。かかるGaN結晶基板は、HVPE(ハイドライド気相成長)法、MOVPE(有機金属気相成長)法などの気相成長法により成長させたGaN結晶を、所定の基板状に切り出し、その主面を研削、研磨および/またはエッチングすることにより形成される。   The GaN crystal substrate is very useful as a substrate for semiconductor devices such as light emitting elements, electronic elements, and semiconductor sensors. Such a GaN crystal substrate is obtained by cutting a GaN crystal grown by a vapor phase growth method such as HVPE (hydride vapor phase epitaxy) method or MOVPE (organic metal vapor phase epitaxy) method into a predetermined substrate shape and grinding its main surface. , Polishing and / or etching.

GaN結晶基板の一方の主面である結晶成長面上に、少なくとも1層の結晶性(結晶における原子配置の秩序性を意味する、以下同じ)のよい半導体層を成長させて特性の高い半導体デバイスを得るために、結晶成長面の反りおよび面粗さが小さいGaN結晶基板が提案されている(たとえば、特開2000−12900号公報(特許文献1)を参照)。   A semiconductor device having high characteristics by growing at least one semiconductor layer having good crystallinity (which means the order of atomic arrangement in the crystal, the same applies hereinafter) on a crystal growth surface which is one main surface of the GaN crystal substrate. In order to achieve this, a GaN crystal substrate with a small crystal growth surface warp and surface roughness has been proposed (see, for example, Japanese Patent Laid-Open No. 2000-12900 (Patent Document 1)).

しかし、GaN結晶基板の結晶成長面の反りおよび面粗さが小さくても、GaN結晶基板の裏面(他方の主面すなわち結晶成長面の反対側の面をいう、以下同じ)の反りが大きいと、基板の結晶成長面に半導体層を形成する際、基板の裏面とサセプタ(基板を配置する台をいう、以下同じ)との間に形成される空隙部が大きくなり、サセプタから基板に伝わる熱の分布が不均一となって、基板の結晶成長面上に半導体層を均一に安定して形成することができなくなる。このため、基板の結晶成長面上に結晶性のよい半導体層の形成ができず、特性のよい半導体デバイスが得られないという問題があった。また、GaN結晶基板の裏面の面粗さは、結晶成長面の面粗さより大きいのが一般的であるが、極度に大きいと上記と同様の問題が発生していた。   However, if the warpage and surface roughness of the crystal growth surface of the GaN crystal substrate are small, the back surface of the GaN crystal substrate (the other main surface, ie, the surface opposite to the crystal growth surface, hereinafter the same) warps. When a semiconductor layer is formed on the crystal growth surface of the substrate, a gap formed between the back surface of the substrate and the susceptor (hereinafter referred to as a base on which the substrate is arranged) is increased, and heat transferred from the susceptor to the substrate As a result, the semiconductor layer cannot be uniformly and stably formed on the crystal growth surface of the substrate. For this reason, there is a problem that a semiconductor layer with good crystallinity cannot be formed on the crystal growth surface of the substrate, and a semiconductor device with good characteristics cannot be obtained. Further, the surface roughness of the back surface of the GaN crystal substrate is generally larger than the surface roughness of the crystal growth surface, but if it is extremely large, the same problem as described above has occurred.

特開2000−12900号公報Japanese Patent Laid-Open No. 2000-12900

本発明は、結晶成長面上に結晶性のよい半導体層を成長させることが可能な、裏面の反りの小さいGaN結晶基板およびその製造方法、ならびにかかるGaN結晶基板を備える半導体デバイスおよびその製造方法を提供することを目的とする。   The present invention relates to a GaN crystal substrate having a small back surface warp capable of growing a semiconductor layer having good crystallinity on the crystal growth surface and a method for manufacturing the same, and a semiconductor device including the GaN crystal substrate and a method for manufacturing the semiconductor device. The purpose is to provide.

本発明は、結晶成長面の反対側の面である裏面に関して、反り曲面が最適平面に対して一方側に最も大きな変位値と最適平面との距離および他方側に最も大きな変位値と最適平面との距離の和として算出される裏面の長さ5.08cm当りの反りw(R)が、−35μm≦w(R)≦45μmであるGaN結晶基板である。 The present invention relates to the back surface, which is the surface opposite to the crystal growth surface, in which the warped curved surface has the largest displacement value on one side with respect to the optimum plane and the distance between the optimum plane and the largest displacement value on the other side and the optimum plane. This is a GaN crystal substrate in which the warp w (R) per 5.08 cm length of the back surface calculated as the sum of the distances is −35 μm ≦ w (R) ≦ 45 μm.

本発明にかかるGaN結晶基板において、裏面の面粗さRa(R)をRa(R)≦10μmとすることができる。さらに、裏面の面粗さRa(R)をRa(R)≧1μmとすることができる。また、裏面の面粗さRy(R)をRy(R)≦75μmとすることができる。さらに、裏面の面粗さRy(R)をRy(R)≧3μmとすることができる。また、光干渉方式のフラットネステスタを用いて測定される結晶成長面の長さ5.08cm当りの反りw(C)を−50μm≦w(C)≦50μmとすることができる。また、結晶成長面の面粗さRa(C)をRa(C)≦10nmとすることができる。また、結晶成長面の面粗さRy(C)をRy(C)≦60nmとすることができる。 In the GaN crystal substrate according to the present invention, the surface roughness Ra (R) of the back surface can be set to Ra (R) ≦ 10 μm. Furthermore, the surface roughness Ra (R) of the back surface can be set to Ra (R) ≧ 1 μm. Further, the surface roughness Ry (R) of the back surface can be set to Ry (R) ≦ 75 μm. Furthermore, the surface roughness Ry (R) of the back surface can be set to Ry (R) ≧ 3 μm. Further, the warp w (C) per length of 5.08 cm of the crystal growth surface measured using an optical interference type flat tester can be set to −50 μm ≦ w (C) ≦ 50 μm. Further, the surface roughness Ra (C) of the crystal growth surface can be set to Ra (C) ≦ 10 nm. Further, the surface roughness Ry (C) of the crystal growth surface can be set to Ry (C) ≦ 60 nm.

また、本発明は、上記のGaN結晶基板の製造方法であって、成長させたGaN結晶からGaN結晶基板を切り出す工程と、GaN結晶基板の裏面を処理する工程とを含み、このGaN結晶基板の裏面を処理する工程は、裏面を研削する工程、裏面を研磨する工程および裏面をエッチングする工程の少なくともいずれかの工程を含むGaN結晶基板の製造方法である。   Further, the present invention is a method for manufacturing the above GaN crystal substrate, which includes a step of cutting the GaN crystal substrate from the grown GaN crystal and a step of treating the back surface of the GaN crystal substrate. The step of processing the back surface is a method of manufacturing a GaN crystal substrate including at least one of a step of grinding the back surface, a step of polishing the back surface, and a step of etching the back surface.

また、本発明は、基板として上記のGaN結晶基板を選択し、GaN結晶基板の結晶成長面側に少なくとも1層のIII族窒化物結晶層を成長させる工程を含む半導体デバイスの製造方法である。   The present invention is also a method for manufacturing a semiconductor device, comprising the steps of selecting the GaN crystal substrate as a substrate and growing at least one group III nitride crystal layer on the crystal growth surface side of the GaN crystal substrate.

また、本発明は、上記GaN結晶基板と、上記GaN結晶基板の結晶成長面側に形成されている少なくとも1層のIII族窒化物結晶層と、を備える半導体デバイスである。   The present invention is also a semiconductor device comprising the GaN crystal substrate and at least one group III nitride crystal layer formed on the crystal growth surface side of the GaN crystal substrate.

本発明によれば、結晶成長面上に結晶性のよい半導体層を成長させることが可能な、裏面の反りの小さいGaN結晶基板およびその製造方法、ならびにかかるGaN結晶基板を備える半導体デバイスおよびその製造方法を提供することができる。   According to the present invention, it is possible to grow a semiconductor layer having good crystallinity on the crystal growth surface, a GaN crystal substrate with a small back surface warpage, and a method for manufacturing the same, and a semiconductor device including the GaN crystal substrate and the method for manufacturing the same. A method can be provided.

本発明にかかるGaN結晶基板の裏面の反りを示す模式図である。It is a schematic diagram which shows the curvature of the back surface of the GaN crystal substrate concerning this invention. 本発明にかかるGaN結晶基板の裏面の反り測定方法を示すフローチャートである。It is a flowchart which shows the curvature measurement method of the back surface of the GaN crystal substrate concerning this invention. 本発明にかかるGaN結晶基板の裏面の反り測定方法に用いられる測定装置を示す模式図である。It is a schematic diagram which shows the measuring apparatus used for the curvature measuring method of the back surface of the GaN crystal substrate concerning this invention. 本発明にかかるGaN結晶基板の裏面の反り測定方法における複数の測定点を示す模式図である。It is a schematic diagram which shows the several measurement point in the curvature measuring method of the back surface of the GaN crystal substrate concerning this invention. 複数の測定点の配列を示す模式図である。It is a schematic diagram which shows the arrangement | sequence of several measurement points. 8近傍のガウシアンフィルタのカーネルを示す模式図である。ここで、(a)は各係数となるガウス関数f(x,y)の配列される位置を示し、(b)はσ=5、規格化前の各係数の配列を示し、(c)はσ=5、規格化後の各係数の配列を示す。It is a schematic diagram which shows the kernel of the Gaussian filter of 8 vicinity. Here, (a) shows the arrangement position of the Gaussian function f (x, y) for each coefficient, (b) shows the arrangement of each coefficient before normalization, σ = 5, and (c) shows σ = 5, which shows the arrangement of coefficients after normalization. 本発明にかかるGaN結晶基板の裏面の反り測定方法における反り算出ステップを示す模式図である。It is a schematic diagram which shows the curvature calculation step in the curvature measuring method of the back surface of the GaN crystal substrate concerning this invention. 本発明にかかるGaN結晶基板の製造方法を示す模式断面図である。It is a schematic cross section which shows the manufacturing method of the GaN crystal substrate concerning this invention. 本発明にかかる半導体デバイスの製造方法を示す模式断面図である。It is a schematic cross section which shows the manufacturing method of the semiconductor device concerning this invention. GaN結晶基板の裏面の反りと半導体デバイスの歩留まりとの関係を示す図である。It is a figure which shows the relationship between the curvature of the back surface of a GaN crystal substrate, and the yield of a semiconductor device.

(実施形態1)
本発明にかかるGaN結晶基板の一実施形態は、図1を参照して、結晶成長面10cの反対側の面である裏面10rの反りw(R)が−50μm≦w(R)≦50μmである。ここで、図1(a)に示すような裏面10rが凹状となる反りを正(+の記号で示す)とし、図1(b)に示すような裏面10rが凸状となる反りを負(−の記号で示す)とする。また、反りw(R)は裏面10rにおける最凸部の変位値zPと最凹部の変位値zVとの高低差と定義される。
(Embodiment 1)
In one embodiment of the GaN crystal substrate according to the present invention, referring to FIG. 1, the warp w (R) of the back surface 10r which is the surface opposite to the crystal growth surface 10c is −50 μm ≦ w (R) ≦ 50 μm. is there. Here, a warp in which the back surface 10r is concave as shown in FIG. 1A is positive (indicated by a symbol +), and a warp in which the back surface 10r is convex in FIG. -). Further, warpage w (R) is defined as the height difference between the displacement value z V of displacement values z P and the most recessed portion of the outermost convex portion on the rear surface 10r.

図1を参照して、裏面10rの反りw(R)が、w(R)<−50μmまたはw(R)>50μmであると、GaN結晶基板10とサセプタ9の表面との間に形成される空隙部91が大きくなる。この結果、GaN結晶基板10の結晶成長面10c上に半導体層として少なくとも1つのIII族窒化物結晶層20を成長させる際に、サセプタ9からGaN結晶基板10に伝わる熱の分布が不均一となる。このため、半導体層であるIII族窒化物結晶層20を均一に安定して成長させることができなくなり、均一で高い特性を有する半導体デバイスの製造が困難となる。 Referring to FIG. 1, when w (R) of back surface 10 r is w (R) <−50 μm or w (R) > 50 μm, it is formed between GaN crystal substrate 10 and the surface of susceptor 9. The gap portion 91 becomes larger. As a result, when at least one group III nitride crystal layer 20 is grown as a semiconductor layer on the crystal growth surface 10c of the GaN crystal substrate 10, the distribution of heat transferred from the susceptor 9 to the GaN crystal substrate 10 becomes non-uniform. . For this reason, the group III nitride crystal layer 20 which is a semiconductor layer cannot be grown uniformly and stably, and it becomes difficult to manufacture a semiconductor device having uniform and high characteristics.

かかる観点から、裏面10rの反りw(R)は、−35μm≦w(R)≦45μmであることがより好ましい。ここで、図1(a)に示すように、裏面10rの反りが正(+)の場合には、裏面10rとサセプタ9の表面との間に形成される空隙部91は閉空間となる。これに対して、図1(b)に示すように、裏面10rの反りが負(−)の場合には、裏面10rとサセプタ9の表面との間に形成される空隙部91は開空間となる。したがって、基板(GaN結晶基板10)の結晶成長面10c上にIII族窒化物結晶層20を成長させるとき、反りが正(+)のときの基板の熱分布は、反りが負(−)のときの基板の熱分布に比べて小さくなる。好ましい反りの領域が−側より+側に大きくなると考えられる。 From such a viewpoint, the warp w (R) of the back surface 10r is more preferably −35 μm ≦ w (R) ≦ 45 μm. Here, as shown in FIG. 1A, when the warpage of the back surface 10r is positive (+), the gap portion 91 formed between the back surface 10r and the surface of the susceptor 9 is a closed space. On the other hand, as shown in FIG. 1B, when the warpage of the back surface 10r is negative (−), the gap portion 91 formed between the back surface 10r and the surface of the susceptor 9 is an open space. Become. Therefore, when the group III nitride crystal layer 20 is grown on the crystal growth surface 10c of the substrate (GaN crystal substrate 10), the thermal distribution of the substrate when the warp is positive (+) is that the warp is negative (-). It becomes smaller than the heat distribution of the substrate. It is considered that a preferable warp region is larger on the + side than on the-side.

ここで、基板(GaN結晶基板10)の裏面10rは一般に面粗さが大きいため、裏面10rの反りを正確に測定するため、以下の方法により基板(GaN結晶基板10)の裏面10rの反りを測定した。すなわち、図2を参照して、レーザ変位計を用いて基板の結晶成長面の反対側の面である裏面の反りを測定する方法であって、基板は基板支持台上に配置されており、レーザ変位計を用いて基板の裏面の複数の測定点にそれぞれ対応する複数の変位値を検出する基板検出ステップS1と、複数の変位値に含まれるノイズを除去するノイズ除去ステップS2と、複数の変位値から基板の外周部の測定点にそれぞれ対応する複数の変位値を除去した複数の変位値からなる複数の計算用変位値を算出する外周部除去ステップS3と、複数の計算用変位値を平滑化処理して反り曲面を算出する平滑化ステップS4と、反り曲面との距離を最小にする最適平面を算出する最適平面算出ステップS5と、反り曲面が最適平面に対して一方側に最も大きな変位値と最適平面との距離および他方側に最も大きな変位値と最適平面との距離の和を反りとして算出する反り算出ステップS6とを含む基板の裏面の反り測定方法である。かかる測定方法により、裏面の面粗さが大きな(たとえば、面粗さRaが50nm以上の)基板についても、基板の裏面の反りの測定が可能となる。なお、面粗さRaとは、粗さ曲線からその平均線の方向に基準長さだけ抜き取り、この抜き取り部分の平均線から測定曲線までの偏差の絶対値を合計してそれを基準長さで平均した値をいう。また、図2において、実線の枠で囲まれたステップは必須ステップを示し、破線の枠で囲まれたステップは任意ステップを示す。   Here, since the back surface 10r of the substrate (GaN crystal substrate 10) is generally large in surface roughness, the warp of the back surface 10r of the substrate (GaN crystal substrate 10) is measured by the following method in order to accurately measure the warpage of the back surface 10r. It was measured. That is, referring to FIG. 2, a method of measuring the warpage of the back surface, which is the surface opposite to the crystal growth surface of the substrate, using a laser displacement meter, the substrate being disposed on the substrate support, A substrate detection step S1 for detecting a plurality of displacement values respectively corresponding to a plurality of measurement points on the back surface of the substrate using a laser displacement meter, a noise removal step S2 for removing noise included in the plurality of displacement values, and a plurality of An outer peripheral portion removing step S3 for calculating a plurality of displacement values for calculation composed of a plurality of displacement values obtained by removing a plurality of displacement values respectively corresponding to measurement points on the outer peripheral portion of the substrate from the displacement values, and a plurality of displacement values for calculation. A smoothing step S4 for calculating a warped surface by smoothing, an optimum plane calculating step S5 for calculating an optimum plane that minimizes the distance from the warped surface, and the warped surface is largest on one side with respect to the optimum plane. Strange A measuring warpage of a rear surface of a method of the substrate including the warpage calculation step S6 for calculating the sum of distances between the value and the best fit plane and a distance and the other the greatest displacement value on the side and the best fit plane as warpage. With this measurement method, it is possible to measure the warpage of the back surface of the substrate even on a substrate having a large back surface roughness (for example, a surface roughness Ra of 50 nm or more). The surface roughness Ra is a reference length extracted from the roughness curve in the direction of the average line, and the absolute value of the deviation from the average line of the extracted portion to the measurement curve is summed up to obtain the reference length. The average value. In FIG. 2, steps surrounded by a solid line frame indicate essential steps, and steps surrounded by a broken line frame indicate optional steps.

ここで、図3を参照して、レーザ変位計15とは、レーザ光31を基板(GaN結晶基板10)の裏面10rに照射することにより、基板(GaN結晶基板10)の裏面10rの変位を測定する装置をいう。レーザの種類には特に制限はなく波長が670nmの赤色半導体レーザなどが用いられ、測定方式には特に制限はなくレーザフォーカス方式などが用いられる。また、レーザフォーカス方式のレーザ変位計は、光干渉方式のフラットネステスタに比べて、精度が低いが、面粗さRaが50nm以上の粗い裏面の測定が可能である。また、レーザフォーカス方式のレーザ変位計は、光干渉方式のフラットネステスタと異なり、反射光31rが得られるため、変位値の解析および処理が可能となる。   Here, referring to FIG. 3, the laser displacement meter 15 irradiates the back surface 10 r of the substrate (GaN crystal substrate 10) with a laser beam 31, thereby changing the displacement of the back surface 10 r of the substrate (GaN crystal substrate 10). A measuring device. The type of laser is not particularly limited, and a red semiconductor laser having a wavelength of 670 nm is used. The measurement method is not particularly limited, and a laser focus method is used. A laser focus type laser displacement meter is less accurate than an optical interference type flat tester, but can measure a rough back surface with a surface roughness Ra of 50 nm or more. Further, unlike the optical interference type flat tester, the laser focus type laser displacement meter can obtain the reflected light 31r, so that the displacement value can be analyzed and processed.

図3を参照して、基板(GaN結晶基板10)は基板支持台12上に配置されている。基板(GaN結晶基板10)を基板支持台12上に配置する方法には、特に制限はないが、3点の支持部12hを有する基板支持台12上に、基板(GaN結晶基板10)の結晶成長面10cが上記3点の支持部12hで支持されるように配置することが好ましい。3点の支持部12hのみで基板(GaN結晶基板10)の結晶成長面10cの外周部を支持することにより、反り測定の際の結晶成長面10cの損傷を最小限にすることができる。また、上記3点の支持によって基板(GaN結晶基板10)が傾斜しても、反り曲面(裏面の反りを示す曲面をいう、以下同じ)との距離が最も小さくなるような最適平面を算出して、その反り曲面と最適平面との距離を算出することにより、基板(GaN結晶基板10)の傾斜を相殺できる。   With reference to FIG. 3, the substrate (GaN crystal substrate 10) is disposed on a substrate support 12. The method for disposing the substrate (GaN crystal substrate 10) on the substrate support base 12 is not particularly limited, but the crystal of the substrate (GaN crystal substrate 10) is formed on the substrate support base 12 having three support portions 12h. It is preferable to arrange the growth surface 10c so as to be supported by the three support portions 12h. By supporting the outer peripheral portion of the crystal growth surface 10c of the substrate (GaN crystal substrate 10) with only the three support portions 12h, damage to the crystal growth surface 10c during warpage measurement can be minimized. Further, even when the substrate (GaN crystal substrate 10) is inclined by the support of the above three points, an optimal plane is calculated so that the distance from the curved surface (referred to as a curved surface showing the curvature of the back surface, hereinafter the same) is minimized. Thus, by calculating the distance between the warped curved surface and the optimum plane, the inclination of the substrate (GaN crystal substrate 10) can be offset.

図2〜図4を参照して、基板検出ステップS1は、特に制限はないが、基板(GaN結晶基板10)を二次元方向(図4におけるX方向およびY方向をいう、以下同じ)に段階的に移動させて、レーザ変位計15と基板(GaN結晶基板10)の裏面10rとの距離Lを測定することにより行なうことができる。ここで、基板(GaN結晶基板10)の二次元方向への段階的移動は、基板支持台12と駆動装置14とを連結している駆動部13を二次元方向に段階的に移動させることにより行なうことができる。ここで、駆動装置14は、駆動制御装置16により制御されている。   Referring to FIGS. 2 to 4, substrate detection step S <b> 1 is not particularly limited, but the substrate (GaN crystal substrate 10) is staged in a two-dimensional direction (referred to as X direction and Y direction in FIG. 4, hereinafter the same). The distance L between the laser displacement meter 15 and the back surface 10r of the substrate (GaN crystal substrate 10) can be measured. Here, the stepwise movement of the substrate (GaN crystal substrate 10) in the two-dimensional direction is performed by moving the driving unit 13 connecting the substrate support 12 and the driving device 14 stepwise in the two-dimensional direction. Can be done. Here, the drive device 14 is controlled by the drive control device 16.

このとき、基板の裏面の複数の測定点中のレーザ光31が照射されている測定点(任意に特定される測定点)100pの二次元方向の位置データ32は、駆動制御装置16を介して、データ解析装置18に集められる。   At this time, the position data 32 in the two-dimensional direction of the measurement point (arbitrarily specified measurement point) 100p irradiated with the laser light 31 among the plurality of measurement points on the back surface of the substrate is supplied via the drive control device 16. Are collected in the data analysis device 18.

距離Lの測定方法には、特に制限はないが、たとえばレーザフォーカス方式により行なうことができる。ここで、レーザフォーカス方式とは、以下の測定方式をいう。レーザ変位計15内の光源からの入射光31iは、レーザ変位計15内で音叉により高速で上下動している対物レンズ(図示せず)を介して基板(GaN結晶基板10)の裏面10rの任意に特定される測定点100pに照射される。この任意に特定される測定点100pからの反射光31rは、レーザ変位計15内のピンホール(図示せず)を通過して受光素子(図示せず)に到達する。共焦点原理により、基板(GaN結晶基板10)の裏面10rの任意に特定される測定点100pに焦点を結んだときに上記ピンホールの位置で一点に集光されて受光素子に入光する。このときの上記音叉の位置をセンサ(図示せず)で測定することにより、レーザ変位計15と基板(GaN結晶基板10)の裏面10rの任意に特定される測定点100pとの距離Lを測定できる。このようにして、基板(GaN結晶基板10)の裏面10rの任意に特定される測定点100pの変位値z(a,b)(Z方向の変位値をいう、以下同じ)を測定することができる。 The method for measuring the distance L is not particularly limited, but can be performed by, for example, a laser focus method. Here, the laser focus method refers to the following measurement method. Incident light 31i from the light source in the laser displacement meter 15 passes through an objective lens (not shown) that moves up and down at a high speed by a tuning fork in the laser displacement meter 15 on the back surface 10r of the substrate (GaN crystal substrate 10). Irradiated to an arbitrarily specified measurement point 100p. The reflected light 31r from the arbitrarily specified measurement point 100p passes through a pinhole (not shown) in the laser displacement meter 15 and reaches a light receiving element (not shown). Due to the confocal principle, when focusing on an arbitrarily specified measurement point 100p on the back surface 10r of the substrate (GaN crystal substrate 10), the light is condensed to one point at the position of the pinhole and enters the light receiving element. By measuring the position of the tuning fork at this time with a sensor (not shown), the distance L between the laser displacement meter 15 and the arbitrarily specified measurement point 100p on the back surface 10r of the substrate (GaN crystal substrate 10) is measured. it can. In this way, it is possible to measure the displacement value z (a, b) (referred to as the displacement value in the Z direction, hereinafter the same) at an arbitrarily specified measurement point 100p on the back surface 10r of the substrate (GaN crystal substrate 10). it can.

このとき、基板(GaN結晶基板10)の裏面10rの複数の測定点10p中の任意に特定される測定点100pの変位値データ33は、レーザ変位計制御装置17を介して、データ解析装置18に集められる。   At this time, the displacement value data 33 of the measurement point 100p arbitrarily specified among the plurality of measurement points 10p on the back surface 10r of the substrate (GaN crystal substrate 10) is transferred to the data analysis device 18 via the laser displacement meter control device 17. To be collected.

次に、図3および図4に示すように、基板を段階的に(たとえば、X方向またはY方向に一定のピッチPで)移動させた後、上記測定を行なうことにより、上記任意に特定される測定点100pにピッチPで隣接する測定点についての二次元方向の位置データ32および変位値データ33が得られる。かかる操作を繰り返すことにより、基板(GaN結晶基板10)の裏面10rの複数の測定点10pのそれぞれについての二次元方向(X方向およびY方向)の位置データ32およびZ方向の変位値データ33が得られる。こうして得られる二次元方向(X方向およびY方向)の位置データ32およびZ方向の変位値データ33は、データ解析装置18に集められる。   Next, as shown in FIGS. 3 and 4, the substrate is moved stepwise (for example, at a constant pitch P in the X direction or the Y direction), and then the above measurement is performed, thereby arbitrarily specifying the above. The position data 32 and the displacement value data 33 in the two-dimensional direction are obtained for the measurement points adjacent to the measurement point 100p with the pitch P. By repeating this operation, the position data 32 in the two-dimensional direction (X direction and Y direction) and the displacement value data 33 in the Z direction for each of the plurality of measurement points 10p on the back surface 10r of the substrate (GaN crystal substrate 10) are obtained. can get. The position data 32 in the two-dimensional direction (X direction and Y direction) and the displacement value data 33 in the Z direction obtained in this way are collected in the data analysis device 18.

なお、図4に示すように、円状の基板(GaN結晶基板10)を二次元方向に一定のピッチPで段階的に移動させるとき、レーザ光が基板(GaN結晶基板10)の裏面10rではなく基板支持台12上に照射される場合がある。図4に示すように、基板(GaN結晶基板10)が基板支持台12の凹部に配置されるような場合は、基板支持台12の非凹部面12aの測定点120aおよび凹部面12bの測定点120bが存在し得る。   As shown in FIG. 4, when the circular substrate (GaN crystal substrate 10) is moved stepwise in the two-dimensional direction at a constant pitch P, the laser beam is incident on the back surface 10r of the substrate (GaN crystal substrate 10). In some cases, the light is irradiated on the substrate support 12. As shown in FIG. 4, when the substrate (GaN crystal substrate 10) is disposed in the recess of the substrate support 12, the measurement point 120 a on the non-recess surface 12 a and the measurement point on the recess 12 b of the substrate support 12. 120b may be present.

かかる場合には、図3を参照して、以下のようにして測定点120aおよび120bを除去して、基板(GaN結晶基板10)の裏面10rの複数の測定点10pにそれぞれ対応する複数の変位値を検出することができる。すなわち、レーザ変位計15と基板支持台12の非凹部面12aとの距離Laおよびレーザ変位計15と基板支持台12の凹部面12bとの距離Lbに対して、レーザ変位計15との距離Lが、La<L<Lbとなるような任意に特定される測定点100pのみを検出することにより、上記測定点120aおよび120bが除去され、基板(GaN結晶基板10)の裏面10rの複数の測定点10pにそれぞれ対応する複数の変位値が得られる。   In such a case, referring to FIG. 3, the measurement points 120a and 120b are removed as follows, and a plurality of displacements respectively corresponding to the plurality of measurement points 10p on the back surface 10r of the substrate (GaN crystal substrate 10). The value can be detected. That is, the distance L between the laser displacement meter 15 and the non-recessed surface 12a of the substrate support 12 and the distance Lb between the laser displacement meter 15 and the recessed surface 12b of the substrate support 12 are L. However, by detecting only the arbitrarily specified measurement point 100p such that La <L <Lb, the measurement points 120a and 120b are removed, and a plurality of measurements on the back surface 10r of the substrate (GaN crystal substrate 10) are performed. A plurality of displacement values respectively corresponding to the point 10p are obtained.

また、ノイズ除去ステップは、複数の変位値に含まれるノイズを除去するものであれば特に制限はないが、メディアンフィルタを用いて行なうことが好ましい。ここで、図5を参照して、メディアンフィルタとは、上記複数の変位値(基板(GaN結晶基板10)の裏面10rの複数の測定点10pにそれぞれ対応する複数の変位値をいう、以下同じ)において任意に特定される変位値z(a,b)(任意に特定される測定点100pに対応する変位値をいう、以下同じ)を、変位値z(a,b)および変位値z(a,b)に近傍する複数の変位値z(a-1,b+1)、z(a-1,b)、z(a-1,b-1)、z(a,b+1)、z(a,b-1)、z(a+1,b+1)、z(a+1,b)、z(a+1、b-1)(任意に特定される測定点に近傍する複数の測定点101p,102p,103p,104p,105p,106p,107p,108pにそれぞれに対応する変位値をいう、以下同じ)を昇べきまた降べきの順に並べたときの中央値(メディアン)に置き換えるフィルタをいう。ここで、図5においては、変位値z(a,b)および変位値z(a,b)に近傍する複数の変位値z(a-1,b+1)、z(a-1,b)、z(a-1,b-1)、z(a,b+1)、z(a,b-1)、z(a+1,b+1)、z(a+1,b)、z(a+1、b-1)が2次元方向(X方向およびY方向)に一定のピッチPで配列している。 The noise removal step is not particularly limited as long as it removes noise contained in a plurality of displacement values, but is preferably performed using a median filter. Here, referring to FIG. 5, the median filter means a plurality of displacement values (a plurality of displacement values respectively corresponding to a plurality of measurement points 10p on the back surface 10r of the substrate (GaN crystal substrate 10)). ), A displacement value z (a, b) (referred to as a displacement value corresponding to an arbitrarily specified measurement point 100p, hereinafter the same), a displacement value z (a, b) and a displacement value z ( a plurality of displacement values z (a-1, b + 1) , z (a-1, b) , z (a-1, b-1) , z (a, b + 1) close to a, b) , Z (a, b-1) , z (a + 1, b + 1) , z (a + 1, b) , z (a + 1, b-1) (near an arbitrarily specified measurement point Median (median) when a plurality of measurement points 101p, 102p, 103p, 104p, 105p, 106p, 107p, and 108p are arranged in the order of ascending and descending. The filter to replace with Here, in FIG. 5, the displacement value z (a, b) and a plurality of displacement values z (a-1, b + 1) , z (a-1, b ) close to the displacement value z (a, b) are shown. ) , Z (a-1, b-1) , z (a, b + 1) , z (a, b-1) , z (a + 1, b + 1) , z (a + 1, b) , Z (a + 1, b-1) are arranged at a constant pitch P in the two-dimensional direction (X direction and Y direction).

なお、図5においては、近傍する複数の変位値として、任意に特定された変位値を取り囲んで隣接する8つの変位値z(a-1,b+1)、z(a-1,b)、z(a-1,b-1)、z(a,b+1)、z(a,b-1)、z(a+1,b+1)、z(a+1,b)およびz(a+1、b-1)を用いた(このようなメディアンフィルタを8近傍のメディアンフィルタという)が、近傍の複数の測定点は8つに限られない。たとえば、変位値の近傍の24の測定点を用いることもできる(このようなメディアンフィルタを24近傍のメディアンフィルタという)。 In FIG. 5, as a plurality of adjacent displacement values, eight adjacent displacement values z (a−1, b + 1) and z (a−1, b) surrounding an arbitrarily specified displacement value. , Z (a-1, b-1) , z (a, b + 1) , z (a, b-1) , z (a + 1, b + 1) , z (a + 1, b) and Although z (a + 1, b-1) is used (such a median filter is referred to as an 8-neighborhood median filter), the number of neighboring measurement points is not limited to eight. For example, 24 measurement points in the vicinity of the displacement value can also be used (such a median filter is called a median filter in the vicinity of 24).

また、外周部除去ステップは、複数の変位値から基板の外周部の測定点にそれぞれ対応する複数の変位値を除去した複数の変位値からなる複数の計算用変位値を算出するものであれば特に制限はないが、ノイズ除去ステップにおいて8近傍のメディアンフィルタを用いる場合には、図4を参照して、上記複数の変位値から、基板(GaN結晶基板10)の外周部の測定点にそれぞれ対応する変位値として、外周10eから少なくとも2つ内側までの測定点111p,112pのそれぞれに対応する変位値を除去することが好ましい。   Further, the outer peripheral portion removing step may calculate a plurality of displacement values for calculation composed of a plurality of displacement values obtained by removing a plurality of displacement values respectively corresponding to measurement points on the outer peripheral portion of the substrate from the plurality of displacement values. Although there is no particular limitation, when a median filter near 8 is used in the noise removal step, referring to FIG. 4, each of the plurality of displacement values is used as a measurement point on the outer peripheral portion of the substrate (GaN crystal substrate 10). As the corresponding displacement values, it is preferable to remove the displacement values corresponding to the respective measurement points 111p and 112p from the outer periphery 10e to at least two insides.

ノイズ除去ステップにおいて8近傍のメディアンフィルタを用いる場合、図4を参照して、基板(GaN結晶基板10)の外周10eから上記1つおよび2つ内側の変位値に近傍する8つの変位値の少なくとも1つの変位値は、基板支持台12の非凹部面12aまたは凹部面12bの変位値となり、上記ノイズ除去ステップによってはノイズが除去されていないからである。このようにして、複数の変位値から基板の外周部の測定点にそれぞれ対応する複数の変位値が除去されて、複数の変位値からなる複数の計算用変位値が得られる。   When using a median filter in the vicinity of 8 in the noise removal step, referring to FIG. 4, at least eight displacement values near the displacement values on the one and two inner sides from the outer periphery 10 e of the substrate (GaN crystal substrate 10) will be described. This is because one displacement value is a displacement value of the non-recessed surface 12a or the recessed surface 12b of the substrate support base 12, and noise is not removed by the noise removing step. In this way, a plurality of displacement values respectively corresponding to the measurement points on the outer peripheral portion of the substrate are removed from the plurality of displacement values, and a plurality of calculation displacement values including a plurality of displacement values are obtained.

また、平滑化ステップは、図7を参照して、上記複数の計算用変位値を平滑化処理して反り曲面40を算出するものであれば特に制限はないが、ガウシアンフィルタを用いて行なうことが好ましい。ここで、ガウシアンフィルタとは、複数の計算用変位値において任意に特定される変位値z(a,b)を、変位値z(a,b)および変位値z(a,b)に近傍する複数の変位値z(a-1,b+1)、z(a-1,b)、z(a-1,b-1)、z(a,b+1)、z(a,b-1)、z(a+1,b+1)、z(a+1,b)、z(a+1、b-1)についてのガウス関数f(x,y)を重み付けとして用いた加重平均値z'(a,b)に置き換えるフィルタをいう。かかる平滑化処理により、面粗さが大きい(たとえば、面粗さRaが50nm以上の)裏面であっても反りの測定が可能となる。 The smoothing step is not particularly limited as long as it can calculate the warped curved surface 40 by smoothing the plurality of displacement values for calculation with reference to FIG. 7, but is performed using a Gaussian filter. Is preferred. Here, the Gaussian filter refers to a displacement value z (a, b) arbitrarily specified in a plurality of displacement values for calculation close to the displacement value z (a, b) and the displacement value z (a, b) . Multiple displacement values z (a-1, b + 1) , z (a-1, b) , z (a-1, b-1) , z (a, b + 1) , z (a, b- 1) , z (a + 1, b + 1) , z (a + 1, b) , weighted average using Gaussian function f (x, y) for z (a + 1, b-1) as a weight A filter that is replaced with the value z ′ (a, b) . By this smoothing treatment, it is possible to measure warpage even on a back surface having a large surface roughness (for example, a surface roughness Ra of 50 nm or more).

二次元のガウス関数f(x,y)は、以下の式(1)で表される。ここで、aおよびbはそれぞれ任意に特定される測定点のX方向およびY方向の座標値を、σは標準偏差(σ2は分散)を、Nは規格化定数を示す。 A two-dimensional Gaussian function f (x, y) is expressed by the following equation (1). Here, a and b are coordinate values in the X direction and Y direction of arbitrarily specified measurement points, σ is a standard deviation (σ 2 is variance), and N is a normalization constant.

Figure 2009111423
Figure 2009111423

式(1)から明らかなように、測定点(x,y)と任意に特定される測定点(a,b)との距離が離れるほど、f(x,y)の値が小さくなり、重み付けが小さくなる。また、σの値が大きくなるほど、測定点(x,y)と測定点(a,b)との距離の違いによる重み付けの大小の差が小さくなる。   As is clear from the equation (1), the value of f (x, y) decreases as the distance between the measurement point (x, y) and the arbitrarily specified measurement point (a, b) increases. Becomes smaller. Further, as the value of σ increases, the difference in weight due to the difference in distance between the measurement point (x, y) and the measurement point (a, b) decreases.

上記においては、近傍する複数の変位値として、任意に特定された変位値を取り囲んで隣接する8つの変位値z(a-1,b+1)、z(a-1,b)、z(a-1,b-1)、z(a,b+1)、z(a,b-1)
(a+1,b+1)、z(a+1,b)およびz(a+1、b-1)を用いた(このようなガウシアンフィルタを8近傍のガウシアンフィルタという)が、近傍の複数の変位値は8つに限られない。たとえば、変位値の近傍の24の変位値を用いることもできる(このようなガウシアンフィルタを24近傍のガウシアンフィルタという)。
In the above, as a plurality of adjacent displacement values, eight adjacent displacement values z (a-1, b + 1) , z (a-1, b) , z ( a-1, b-1) , z (a, b + 1) , z (a, b-1) ,
z (a + 1, b + 1) , z (a + 1, b) and z (a + 1, b-1) are used (such a Gaussian filter is called an 8-neighbor Gaussian filter) The plurality of displacement values is not limited to eight. For example, 24 displacement values in the vicinity of the displacement value can also be used (such a Gaussian filter is referred to as a 24 neighborhood Gaussian filter).

8近傍のガウシアンフィルタを用いるとは、具体的には、任意に特定された変位値z(a,b)を、図5に示す複数の変位値z(a-1,b+1)、z(a-1,b)、z(a-1,b-1)、z(a,b+1)、z(a,b)、z(a,b-1)、z(a+1,b+1)、z(a+1,b)およびz(a+1、b-1)のそれぞれに対して、図6(a)のカーネル(各変位値におけるフィルタの係数をマトリックス形式で表示したもの、以下同じ)に示す各係数としてガウス関数f(x,y)(ここで、x=a−1、a、a+1;y=b−1、b、b+1)の重みをつけて加重平均したz'(a,b)に置き換えることをいう。すなわち、以下の式(2)のようにして、z'(a,b)を得ることをいう。 Specifically, the use of a Gaussian filter in the vicinity of 8 means that an arbitrarily specified displacement value z (a, b) is replaced with a plurality of displacement values z (a-1, b + 1) , z shown in FIG. (a-1, b) , z (a-1, b-1) , z (a, b + 1) , z (a, b) , z (a, b-1) , z (a + 1, For each of b + 1) , z (a + 1, b) and z (a + 1, b-1) , the kernel of FIG. 6A (filter coefficients at each displacement value are displayed in a matrix format. Weighted average with weights of Gaussian functions f (x, y) (where x = a-1, a, a + 1; y = b-1, b, b + 1) as coefficients shown in FIG. Is replaced with z ′ (a, b) . That is, z ′ (a, b) is obtained as in the following formula (2).

Figure 2009111423
Figure 2009111423

ガウシアンフィルタの各係数となるガウス関数f(x,y)は、任意に特定された変位値の測定点(a、b)からの測定点(x、y)の距離および標準偏差σによって決まる。たとえば、図6(b)はσ=5、規格化前の8近傍のガウシアンフィルタの各係数f(x,y)の値の配列を示し、図6(c)はσ=5、規格化後の8近傍のガウシアンフィルタの各係数f(x,y)の値の配列を示す。ここで、規格化とは、ガウシアンフィルタの各係数f(x,y)の比率を保持しながら、各係数f(x,y)の和が1となるように補正することをいう。   The Gaussian function f (x, y) serving as each coefficient of the Gaussian filter is determined by the distance of the measurement point (x, y) from the measurement point (a, b) of the arbitrarily specified displacement value and the standard deviation σ. For example, FIG. 6B shows an array of values of coefficients f (x, y) of 8 neighboring Gaussian filters before standardization, σ = 5, and FIG. 6C shows σ = 5, after standardization. The array of the values of the respective coefficients f (x, y) of the eight neighboring Gaussian filters is shown. Here, normalization means correcting the sum of the coefficients f (x, y) to be 1 while maintaining the ratio of the coefficients f (x, y) of the Gaussian filter.

また、最適平面算出ステップは、図7を参照して、反り曲面40との距離を最小にする最適平面50を算出するものであれば特に制限はないが、平滑化処理がされた複数の計算用変位値における各変位値と最適平面50との距離の二乗の和が最小となるように最適平面50を算出することが好ましい。かかる最小二乗法を用いることにより、3点支持されている基板(GaN結晶基板10)の裏面10r全体の平均的傾斜を示す最適平面50が得られる。   The optimum plane calculation step is not particularly limited as long as it calculates the optimum plane 50 that minimizes the distance to the warped curved surface 40 with reference to FIG. 7, but a plurality of calculations subjected to smoothing processing are performed. It is preferable to calculate the optimum plane 50 so that the sum of the squares of the distances between the respective displacement values and the optimum plane 50 in the use displacement value is minimized. By using this least square method, the optimum plane 50 showing the average inclination of the entire back surface 10r of the substrate (GaN crystal substrate 10) supported at three points is obtained.

また、反り算出ステップは、図7を参照して、反り曲面40が最適平面50に対して、一方側に最も大きな変位値zPと前記最適平面との距離D+、および、他方側に最も大きな変位値zVと前記最適平面との距離D-の和を反りとして算出する。このようにして、反り曲面40から、最適平面50で示される基板(GaN結晶基板10)の裏面10r全体の傾斜を相殺して、基板(GaN結晶基板10)の裏面10rの反りを正確に測定することができる。したがって、GaN結晶基板10の裏面10rの反りw(R)は、w(R)=D++D-により算出される。 In the warp calculation step, referring to FIG. 7, the warped curved surface 40 has the largest displacement value z P on one side with respect to the optimum plane 50 and the distance D + between the optimum plane and the most on the other side. The sum of the large displacement value z V and the distance D between the optimum plane is calculated as a warp. In this way, the warp of the back surface 10r of the substrate (GaN crystal substrate 10) is accurately measured by canceling the inclination of the entire back surface 10r of the substrate (GaN crystal substrate 10) indicated by the optimal plane 50 from the warped curved surface 40. can do. Accordingly, the warpage w (R) of the back surface 10r of the GaN crystal substrate 10 is calculated by w (R) = D + + D .

上記のGaN結晶基板の裏面の反り測定方法において、図2を参照して、上記平滑化ステップS4と、最適平面算出ステップS5と、反り算出ステップS6とを含む最適化サイクルC1を1回以上繰り返すことが好ましい。かかる最適化サイクルC1を1回以上繰り返すことにより、基板(GaN結晶基板10)の裏面10rの反り曲面をより平滑にすることにより面粗さによる影響をより少なくして、裏面10rの反りをより正確に測定することができる。ここで、最適化サイクルC1の繰り返し回数には特に制限はないが、最適サイクル前の反りの値と最適化サイクル後の反りの値の差が、好ましくは0.5μm以下、より好ましくは0.1μm以下になるまでの繰り返し回数とできる。また、最適サイクル前の反りの値に対する最適サイクル前の反りの値と最適化サイクル後の反りの値の差の比が、好ましくは0.05以下、より好ましくは0.01以下になるまでの繰り返し回数とできる。   In the above-described warpage measurement method of the GaN crystal substrate, referring to FIG. 2, the optimization cycle C1 including the smoothing step S4, the optimum plane calculation step S5, and the warpage calculation step S6 is repeated one or more times. It is preferable. By repeating this optimization cycle C1 one or more times, the warped curved surface of the back surface 10r of the substrate (GaN crystal substrate 10) is made smoother, thereby reducing the influence of surface roughness and further reducing the warpage of the back surface 10r. It can be measured accurately. Here, the number of repetitions of the optimization cycle C1 is not particularly limited, but the difference between the warp value before the optimal cycle and the warp value after the optimization cycle is preferably 0.5 μm or less, more preferably 0. It can be the number of repetitions until it becomes 1 μm or less. The ratio of the difference between the warp value before the optimal cycle and the warp value after the optimization cycle to the warp value before the optimal cycle is preferably 0.05 or less, more preferably 0.01 or less. It can be repeated.

また、図2を参照して、上記の最適化サイクルC1の繰り返しの間に、または、最適化サイクルC1中の平滑化ステップS4の後に、少なくとも1回のノイズ除去ステップS2を含むことが好ましい。かかるタイミングにおいて、少なくとも1回のノイズ除去ステップS2を含むことにより、複数の変位値に含まれるノイズのより効果的な除去が可能となり、裏面10rの反りをより正確に測定することができる。   In addition, referring to FIG. 2, it is preferable to include at least one noise removal step S2 during the repetition of the optimization cycle C1 or after the smoothing step S4 in the optimization cycle C1. By including at least one noise removal step S2 at such timing, it becomes possible to more effectively remove noise included in the plurality of displacement values, and the warpage of the back surface 10r can be measured more accurately.

本実施形態のGaN結晶基板において、裏面の面粗さRa(R)は、Ra(R)≦10μmであることが好ましい。ここで、面粗さRaとは、算術平均粗さRaとも呼ばれ、粗さ曲線からその平均線の方向に基準長さだけ抜き取り、この抜き取り部分の平均線から測定曲線までの偏差の絶対値を合計してそれを基準長さで平均した値)をいう。裏面の面粗さRa(R)がRa(R)>10μmであると、GaN結晶基板の結晶成長面側に半導体層として少なくとも1層のIII族窒化物結晶層を成長させる際に、GaN結晶基板とサセプタとの間の接触が不均一となり、サセプタからGaN結晶基板に伝わる熱の分布が不均一となる。かかるGaN結晶基板の熱分布を小さくする観点から、裏面の面粗さRa(R)はRa(R)≦6μmであることがより好ましい。 In the GaN crystal substrate of this embodiment, the surface roughness Ra (R) of the back surface is preferably Ra (R) ≦ 10 μm. Here, the surface roughness Ra is also called the arithmetic average roughness Ra, and is extracted from the roughness curve by a reference length in the direction of the average line, and the absolute value of the deviation from the average line of the extracted portion to the measurement curve. Is the value obtained by summing and averaging the values by the reference length). When the surface roughness Ra (R) on the back surface is Ra (R) > 10 μm, when growing at least one group III nitride crystal layer as a semiconductor layer on the crystal growth surface side of the GaN crystal substrate, The contact between the substrate and the susceptor becomes uneven, and the distribution of heat transferred from the susceptor to the GaN crystal substrate becomes uneven. From the viewpoint of reducing the heat distribution of the GaN crystal substrate, the surface roughness Ra (R) of the back surface is more preferably Ra (R) ≦ 6 μm.

一方、裏面の面粗さRa(R)が小さくなりすぎると、高温に加熱されたサセプタから放射される熱放射光が裏面で反射され、熱反射光の基板への吸収が低下して、基板の加熱効率が低減する。かかる観点から、裏面の面粗さRa(R)はRa(R)≧1μmであることが好ましく、Ra(R)≧2μmであることがより好ましい。 On the other hand, if the surface roughness Ra (R) on the back surface is too small, the heat radiation emitted from the susceptor heated to a high temperature is reflected on the back surface, and the absorption of the heat reflected light on the substrate is reduced. The heating efficiency is reduced. From this viewpoint, it is preferable that the rear surface has a surface roughness Ra (R) is Ra (R) ≧ 1μm, and more preferably Ra (R) ≧ 2μm.

本実施形態のGaN結晶基板において、裏面の面粗さRy(R)は、Ry(R)≦75μmであることが好ましい。ここで、面粗さRyとは、最大高さRyとも呼ばれ、粗さ曲線からその平均線の方向に基準長さだけ抜き取り、この抜き取り部分の平均面から最も高い山頂までの高さと最も低い谷底までの深さとの和をいう。裏面の面粗さRy(R)がRy(R)>75μmであると、GaN結晶基板の結晶成長面側に半導体層として少なくとも1層のIII族窒化物結晶層を成長させる際に、GaN結晶基板とサセプタとの間の接触が不均一となり、サセプタからGaN結晶基板に伝わる熱の分布が不均一となる。かかるGaN結晶基板の熱分布を小さくする観点から、裏面の面粗さRy(R)はRy(R)≦50μmであることがより好ましい。 In the GaN crystal substrate of the present embodiment, the surface roughness Ry (R) of the back surface is preferably Ry (R) ≦ 75 μm. Here, the surface roughness Ry is also called the maximum height Ry, and is extracted from the roughness curve by the reference length in the direction of the average line, and the height from the average surface of the extracted portion to the highest peak and the lowest. The sum of the depth to the bottom of the valley. When the surface roughness Ry (R) on the back surface is Ry (R) > 75 μm, when growing at least one group III nitride crystal layer as a semiconductor layer on the crystal growth surface side of the GaN crystal substrate, The contact between the substrate and the susceptor becomes uneven, and the distribution of heat transferred from the susceptor to the GaN crystal substrate becomes uneven. From the viewpoint of reducing the heat distribution of the GaN crystal substrate, the surface roughness Ry (R) of the back surface is more preferably Ry (R) ≦ 50 μm.

一方、裏面の面粗さRy(R)が小さくなりすぎると、高温に加熱されたサセプタから放射される熱放射光が裏面で反射され、熱反射光の基板への吸収が低下して、基板の加熱効率が低減する。かかる観点から、裏面の面粗さRy(R)はRy(R)≧3μmであることが好ましく、Ry(R)≧10μmであることがより好ましい。 On the other hand, if the surface roughness Ry (R) on the back surface becomes too small, the heat radiation emitted from the susceptor heated to a high temperature is reflected on the back surface, and the absorption of the heat reflected light on the substrate is reduced. The heating efficiency is reduced. From this viewpoint, the surface roughness Ry (R) on the back surface is preferably Ry (R) ≧ 3 μm, and more preferably Ry (R) ≧ 10 μm.

本実施形態のGaN結晶基板においては、基板の結晶成長面の反りw(C)の絶対値、面粗さRa(C)およびRy(C)が小さいほど、結晶成長面側に成長される半導体層であるIII属窒化物結晶層の結晶性が高くなる。かかる観点から、GaN結晶基板の結晶成長面の反りw(C)は、−50μm≦w(C)≦50μmであることが好ましく、−35μm≦w(C)≦45μmであることがより好ましい。また、結晶成長面の面粗さRa(C)は、Ra(C)≦10nmであることが好ましく、Ra(C)≦5nmであることがより好ましい。また、結晶成長面の面粗さRy(C)は、Ry(C)≦60nmであることが好ましく、Ry(C)≦30nmであることがより好ましい。なお、ここで、反りw(C)は、図1を参照して、結晶成長面10cにおける最凸部の変位値zCPと最凹部の変位値zCVとの高低差と定義される。 In the GaN crystal substrate of this embodiment, the smaller the absolute value of the warp w (C) and the surface roughness Ra (C) and Ry (C) of the crystal growth surface of the substrate, the more the semiconductor is grown on the crystal growth surface side. The crystallinity of the Group III nitride crystal layer, which is a layer, is increased. From this viewpoint, the warp w (C) of the crystal growth surface of the GaN crystal substrate is preferably −50 μm ≦ w (C) ≦ 50 μm, and more preferably −35 μm ≦ w (C) ≦ 45 μm. Further, the surface roughness Ra (C) of the crystal growth surface is preferably Ra (C) ≦ 10 nm, and more preferably Ra (C) ≦ 5 nm. The surface roughness Ry (C) of the crystal growth surface is preferably Ry (C) ≦ 60 nm, and more preferably Ry (C) ≦ 30 nm. Here, with reference to FIG. 1, the warp w (C) is defined as a difference in height between the displacement value z CP of the most convex portion and the displacement value z CV of the most concave portion in the crystal growth surface 10c.

なお、本実施形態のGaN結晶基板は、基板の加熱効率を高める観点から、熱放射光の吸収係数が高い方が好ましい。かかる観点から、本実施形態のGaN結晶基板におけるピーク波長が450nm〜550nmの光の吸収係数は、1.5cm-1以上10cm-1以下であることが好ましい。かかる光の吸収係数が1.5cm-1より低いと光が透過して吸収されず、基板の加熱効率が低下する。かかる光の吸収係数が10cm-1より高いと基板中の不純物が多く結晶性が低下する。 Note that the GaN crystal substrate of this embodiment preferably has a higher absorption coefficient of heat radiation light from the viewpoint of increasing the heating efficiency of the substrate. From this viewpoint, the absorption coefficient of light having a peak wavelength of 450 nm to 550 nm in the GaN crystal substrate of the present embodiment is preferably 1.5 cm −1 or more and 10 cm −1 or less. When the light absorption coefficient is lower than 1.5 cm −1 , the light is transmitted and not absorbed, and the heating efficiency of the substrate is lowered. If the light absorption coefficient is higher than 10 cm −1 , the impurities in the substrate are large and the crystallinity is lowered.

また、本実施形態のGaN結晶基板の熱伝導率は、基板内の熱分布を小さくする観点から、160W/mK以上であることが好ましい。また、本実施形態のGaN結晶基板熱膨張係数は、昇降温時における基板の変形を抑制する観点から、3×10-6-1以上6×10-6-1以下であることが好ましい。 In addition, the thermal conductivity of the GaN crystal substrate of this embodiment is preferably 160 W / mK or more from the viewpoint of reducing the heat distribution in the substrate. Further, the thermal expansion coefficient of the GaN crystal substrate of the present embodiment is preferably 3 × 10 −6 K −1 or more and 6 × 10 −6 K −1 or less from the viewpoint of suppressing deformation of the substrate at the time of temperature increase / decrease. .

(実施形態2)
本発明にかかるGaN結晶基板の製造方法は、図8を参照して、実施形態1のGaN結晶基板の製造方法であって、GaN結晶1からGaN結晶基板10を切り出す工程(図8(a)を参照)およびGaN結晶基板10の裏面10rを処理する工程(図8(b)を参照)とを含み、GaN結晶基板10の裏面10rを処理する工程は、裏面10rを研削する工程、裏面10rを研磨する工程および裏面10rをエッチングする工程の少なくともいずれかの工程を含む。
(Embodiment 2)
The method for manufacturing a GaN crystal substrate according to the present invention is a method for manufacturing a GaN crystal substrate according to Embodiment 1 with reference to FIG. 8, and a step of cutting the GaN crystal substrate 10 from the GaN crystal 1 (FIG. 8A). And the process of processing the back surface 10r of the GaN crystal substrate 10 (see FIG. 8B), the process of processing the back surface 10r of the GaN crystal substrate 10 includes a step of grinding the back surface 10r, and a back surface 10r. And at least one of a step of etching the back surface 10r.

図8(a)を参照して、GaN結晶1からGaN結晶基板10を切り出す工程とは、成長させたGaN結晶1から、内周刃、外周刃、ワイヤーソーなどを用いて所定形状のGaN結晶基板10を切り出す工程をいう。ここで、GaN結晶1の成長方法には、特に制限はないが、直径5.08cm(2インチ)以上の大型の結晶が比較的短時間に得られることから、HVPE法、MOVPE法などの気相成長法が好ましく用いられる。   Referring to FIG. 8A, the step of cutting the GaN crystal substrate 10 from the GaN crystal 1 is a GaN crystal having a predetermined shape by using an inner peripheral blade, an outer peripheral blade, a wire saw or the like from the grown GaN crystal 1. This refers to a process of cutting out the substrate 10. Here, the growth method of the GaN crystal 1 is not particularly limited. However, since a large crystal having a diameter of 5.08 cm (2 inches) or more can be obtained in a relatively short time, the HVPE method, the MOVPE method, etc. A phase growth method is preferably used.

図8(b)を参照して、GaN結晶基板10の裏面10rを処理する工程は、GaN結晶基板10の裏面10rを研削する工程(研削工程)、GaN結晶基板10の裏面を研磨する工程(研磨工程)およびGaN結晶基板の裏面をエッチングする工程(エッチング工程)の少なくともいずれかの工程を含む。かかる工程を含むGaN結晶基板の裏面を処理する工程を行なうことにより、結晶成長面の反対側の面である裏面の反りw(R)が−50μm≦w≦50μmであるGaN結晶基板が得られる。また、研削条件、研磨条件および/またはエッチング条件を調節することにより、裏面の面粗さRa(R)がRa(R)≦10μmおよび/または裏面の面粗さRy(R)がRy(R)≦75μmであるGaN結晶基板が得られる。 Referring to FIG. 8B, the process of processing the back surface 10r of the GaN crystal substrate 10 includes a process of grinding the back surface 10r of the GaN crystal substrate 10 (grinding process) and a process of polishing the back surface of the GaN crystal substrate 10 ( At least one of a polishing step) and a step of etching the back surface of the GaN crystal substrate (etching step). By performing the process of processing the back surface of the GaN crystal substrate including this process, a GaN crystal substrate having a back surface warp w (R) that is the surface opposite to the crystal growth surface of −50 μm ≦ w ≦ 50 μm is obtained. . Further, by adjusting grinding conditions, polishing conditions and / or etching conditions, the surface roughness Ra (R) of the back surface is Ra (R) ≦ 10 μm and / or the surface roughness Ry (R) of the back surface is Ry (R ) A GaN crystal substrate with ≦ 75 μm is obtained.

ここで、研削(グライディング)とは、砥粒をボンドで固定した固定砥粒を高速回転させながら対象物に接触させて、対象物の面を削り取ることをいう。かかる研削によって、粗い面が形成される。GaN結晶基板の裏面を研削する場合、GaN結晶より硬度の高いSiC、Al23、ダイヤモンドおよびCBN(キュービックボロンナイトライド、以下同じ)などで形成され、粒径が10μm以上100μm以下程度の砥粒を含む固定砥粒が好ましく用いられる。 Here, grinding (gliding) means that the surface of the object is scraped off by bringing the fixed abrasive grains with the abrasive grains fixed by bonding into contact with the object while rotating at high speed. A rough surface is formed by this grinding. When grinding the back surface of a GaN crystal substrate, it is formed of SiC, Al 2 O 3 , diamond and CBN (cubic boron nitride, the same shall apply hereinafter) having a hardness higher than that of a GaN crystal, and having a grain size of about 10 μm to 100 μm Fixed abrasive grains containing grains are preferably used.

また、研磨(ラッピング)とは、遊離砥粒(固定されていない砥粒をいう、以下同じ)を介して定盤と対象物とを互いに回転させながら接触させて、または固定砥粒と対象物とを互いに回転させながら接触させて、対象物の面を磨くことをいう。かかる研磨によって、研削の場合よりも面粗さが小さい面であって微研磨(ポリシング)の場合より粗い面が形成される。GaN結晶基板の裏面を研磨する場合、GaN結晶より硬度の高いSiC、Al23、ダイヤモンドおよびCBNなどで形成され、粒径が0.5μm以上15μm以下程度の砥粒が好ましく用いられる。 In addition, polishing (lapping) refers to contact between a surface plate and an object while rotating each other through loose abrasive grains (referred to as non-fixed abrasive grains hereinafter), or fixed abrasive grains and an object. The surface of the object is polished by rotating and rotating each other. By this polishing, a surface having a surface roughness smaller than that in the case of grinding and a surface rougher than that in the case of fine polishing (polishing) is formed. When the back surface of the GaN crystal substrate is polished, abrasive grains that are formed of SiC, Al 2 O 3 , diamond, CBN, and the like, which are harder than GaN crystals, and have a grain size of about 0.5 μm to 15 μm are preferably used.

また、エッチングとは、対象物の切り出し(切削)、ならびにその後の対象物の面の研削および/または研磨により生じた加工変質層および残留物(たとえば、切削くず、研削くず、研磨くず、砥粒またはワックスなど)を除去するため、その面を化学的または物理的に食刻加工することをいう(食刻部分10u)。かかるエッチングによっても面の粗さは維持される。GaN結晶基板の裏面をエッチングする場合、エッチング剤によるウェットエッチングが好ましく行なわれる。エッチング剤としては、NH3およびH22の混合溶液、KOH溶液、NaOH溶液、HCl溶液、H2SO4溶液、H3PO4溶液、H3PO4およびH2SO4の混合溶液などが好ましく用いられる。ここで、上記の溶液および混合溶液の溶媒としては水が好ましく用いられる。また、上記エッチング剤は、水などの溶媒により、適宜希釈して用いることもできる。 Etching refers to cutting (cutting) of an object, and subsequent work-affected layers and residues resulting from grinding and / or polishing of the surface of the object (for example, cutting scraps, grinding scraps, polishing scraps, abrasive grains) In order to remove wax or the like, the surface is chemically or physically etched (etched portion 10u). The roughness of the surface is maintained even by such etching. When the back surface of the GaN crystal substrate is etched, wet etching with an etchant is preferably performed. Etching agents include NH 3 and H 2 O 2 mixed solution, KOH solution, NaOH solution, HCl solution, H 2 SO 4 solution, H 3 PO 4 solution, H 3 PO 4 and H 2 SO 4 mixed solution, etc. Is preferably used. Here, water is preferably used as the solvent of the above solution and mixed solution. The etching agent can be appropriately diluted with a solvent such as water.

また、本実施形態のGaN結晶基板の製造方法においては、GaN結晶基板の結晶成長面を処理することが行なわれる。特性によい半導体デバイスを製造するためには、半導体層として結晶成長面側に結晶性のよい少なくとも1層のIII族窒化物結晶層を成長させる必要がある。このため、GaN結晶基板の結晶成長面の反りw(C)は−50μm≦w(C)≦50μm、結晶成長面の面粗さRa(C)はRa(C)≦10nm、結晶成長面の面粗さRy(C)はRy(C)≦60nmとすることが好ましい。 In the method for manufacturing a GaN crystal substrate according to this embodiment, the crystal growth surface of the GaN crystal substrate is processed. In order to manufacture a semiconductor device with good characteristics, it is necessary to grow at least one group III nitride crystal layer having good crystallinity on the crystal growth surface side as a semiconductor layer. Therefore, the warp w (C) of the crystal growth surface of the GaN crystal substrate is −50 μm ≦ w (C) ≦ 50 μm, the surface roughness Ra (C) of the crystal growth surface is Ra (C) ≦ 10 nm, and the crystal growth surface is The surface roughness Ry (C) is preferably Ry (C) ≦ 60 nm.

上記の反りw(C)、面粗さRa(C)およびRy(C)を有する結晶成長面を得るためには、GaN結晶から切り出されたGaN結晶基板の結晶成長面を処理する工程において、裏面を処理する工程における研削工程、研磨工程および/またはエッチング工程と同様の研削工程、研磨工程および/またはエッチング工程に加えて、微研磨(ポリシング)工程が行なわれる。 In order to obtain a crystal growth surface having the warp w (C) , surface roughness Ra (C) and Ry (C) , in the step of processing the crystal growth surface of the GaN crystal substrate cut out from the GaN crystal, In addition to the grinding process, polishing process and / or etching process similar to the grinding process, polishing process and / or etching process in the process of treating the back surface, a fine polishing (polishing) process is performed.

ここで、微研磨(ポリシング)とは、遊離砥粒を介して研磨パッドと対象物とを互いに回転させながら接触させて、または固定砥粒と対象物とを互いに回転させながら接触させて、対象物の面を微細に磨いて平滑化することをいう。かかる微研磨によって、研磨の場合よりも面粗さが小さい結晶成長面が形成される。   Here, the fine polishing (polishing) means that the polishing pad and the target object are brought into contact with each other through the loose abrasive grains, or the fixed abrasive grains and the target object are brought into contact with each other while being rotated. This means that the surface of an object is finely polished and smoothed. By such fine polishing, a crystal growth surface having a smaller surface roughness than that in the case of polishing is formed.

このような微研磨の方法には、とくに制限はないが、機械的ポリシングまたは化学機械的ポリシング(以下、CMPという)が好ましく用いられる。機械的ポリシングまたはCMPとは、それぞれ、砥粒を含むスラリーを介して研磨パッドと対象物とを互いに回転させながら接触させることにより、対象物の面を機械的または化学的かつ機械的に微研磨する方法をいう。砥粒としては、面粗さRaおよびRyを小さくするため、平均粒径が0.1μm以上3μm以下の微粒子であって、GaN以上に硬度が高いSiC、Si34、Al23、ダイヤモンド、CBNなどや、GaNよりも硬度の低いSiO2、CuO、TiO2、ZnO、NiO、Cr23、Fe23、CoO、MnOなどが、単独または併用で用いられる。また、化学的なポリシング効果を高めるため、スラリーは、pH≦5の酸性、または、pH≧9の塩基性とされていること、または過酸化水素(H22)、ジクロロイソシアヌル酸、硝酸、過マンガン酸カリウム、塩化銅などの酸化剤が添加されて、ORP(酸化還元電位)が高められていること(たとえば、ORP≧400mV)が好ましい。 Such a fine polishing method is not particularly limited, but mechanical polishing or chemical mechanical polishing (hereinafter referred to as CMP) is preferably used. In mechanical polishing or CMP, the surface of an object is finely polished mechanically or chemically and mechanically by bringing the polishing pad and the object into contact with each other through a slurry containing abrasive grains while rotating each other. How to do. As the abrasive grains, in order to reduce the surface roughness Ra and Ry, SiC, Si 3 N 4 , Al 2 O 3 , fine particles having an average particle diameter of 0.1 μm or more and 3 μm or less and having a hardness higher than that of GaN, Diamond, CBN, etc., and SiO 2 , CuO, TiO 2 , ZnO, NiO, Cr 2 O 3 , Fe 2 O 3 , CoO, MnO, etc., which are lower in hardness than GaN, are used alone or in combination. In order to enhance the chemical polishing effect, the slurry should be acidic with pH ≦ 5 or basic with pH ≧ 9, or hydrogen peroxide (H 2 O 2 ), dichloroisocyanuric acid, nitric acid It is preferable that an ORP (oxidation-reduction potential) is increased by adding an oxidizing agent such as potassium permanganate or copper chloride (for example, ORP ≧ 400 mV).

(実施形態3)
本発明にかかる半導体デバイスの製造方法の一実施形態は、図9を参照して、基板としてのGaN結晶基板10を選択し、GaN結晶基板10の結晶成長面10c側に少なくとも1層のIII族窒化物結晶層20を成長させる工程を含む。かかる製造方法により、GaN結晶基板10の結晶成長面10c側に、半導体層として均一なIII族窒化物結晶層20を安定して成長させることができ、特性のよい半導体デバイス99が得られる。
(Embodiment 3)
In one embodiment of the method for manufacturing a semiconductor device according to the present invention, referring to FIG. 9, a GaN crystal substrate 10 is selected as a substrate, and at least one group III is formed on the crystal growth surface 10c side of the GaN crystal substrate 10. A step of growing the nitride crystal layer 20. By such a manufacturing method, a uniform group III nitride crystal layer 20 as a semiconductor layer can be stably grown on the crystal growth surface 10c side of the GaN crystal substrate 10, and a semiconductor device 99 having good characteristics can be obtained.

本実施形態の半導体デバイスの製造方法は、より具体的には、まず、図9(a)を参照して、まず、GaN結晶基板10の結晶成長面10c上に、III族窒化物結晶層20として、n型GaN層21、In0.2Ga0.8N層22、Al0.2Ga0.8N層23、p型GaN層24を順次形成して、半導体積層ウエハ80を得る。次に、図9(b)を参照して、半導体積層ウエハ80のGaN結晶基板10の裏面10rにn側電極81を形成し、III族窒化物結晶層20の上面(すなわち、p型GaN層24の上面)にp側電極82を形成して、半導体デバイスウエハ90を得る。次に、図9(c)を参照して、半導体デバイスウエハ90をチップに分割して半導体デバイス99であるLED(発光ダイオード)を得る。 More specifically, in the semiconductor device manufacturing method of the present embodiment, first, referring to FIG. 9A, first, the group III nitride crystal layer 20 is formed on the crystal growth surface 10 c of the GaN crystal substrate 10. As a result, an n-type GaN layer 21, an In 0.2 Ga 0.8 N layer 22, an Al 0.2 Ga 0.8 N layer 23, and a p-type GaN layer 24 are sequentially formed to obtain a semiconductor laminated wafer 80. Next, referring to FIG. 9B, an n-side electrode 81 is formed on the back surface 10r of the GaN crystal substrate 10 of the semiconductor laminated wafer 80, and the upper surface of the group III nitride crystal layer 20 (that is, the p-type GaN layer). A p-side electrode 82 is formed on the upper surface of 24 to obtain a semiconductor device wafer 90. Next, referring to FIG. 9C, the semiconductor device wafer 90 is divided into chips to obtain LEDs (light emitting diodes) that are the semiconductor devices 99.

(比較例1)
1.GaN結晶基板の製造
図8(a)を参照して、HVPE法により成長させたGaN結晶1から直径5.08cm(2インチ)×厚さ550μmのGaN結晶基板10を切り出し、図8(b)を参照して、GaN結晶基板10の裏面10rおよび結晶成長面10cを以下のようにして処理した。裏面の処理は、粒径125μmのCBN砥粒をボンドで固定した固定砥粒を用いて研削し(研削工程)、粒径24μmのダイヤモンド砥粒を用いて研磨し(研磨工程)、30質量%のアンモニア水と、40質量%の過酸化水素水と純水とを体積比で1:1:2で混合させたNH3およびH22の混合水溶液を用いてエッチングすること(エッチング工程)により行なった。また、結晶成長面の処理は、平均粒径125μmのCBN砥粒をボンドで固定した固定砥粒を用いて研削し(研削工程)、平均粒径20μm、10μmおよび5μmのSiC砥粒を順次用いて研磨し(研磨工程)、30質量%のNaOH水溶液を用いてエッチングし(エッチング工程)、平均粒径1μmのTiO2砥粒を含むpH=12、ORP=450mVのスラリーを用いてCMPすること(微研磨工程)により行なった。
(Comparative Example 1)
1. Production of GaN Crystal Substrate Referring to FIG. 8A, a GaN crystal substrate 10 having a diameter of 5.08 cm (2 inches) × thickness of 550 μm is cut out from the GaN crystal 1 grown by the HVPE method, and FIG. Referring to FIG. 5, the back surface 10r and the crystal growth surface 10c of the GaN crystal substrate 10 were processed as follows. The back surface treatment is performed by grinding using fixed abrasive grains in which CBN abrasive grains having a particle diameter of 125 μm are fixed with bonds (grinding process), and polishing using diamond abrasive grains having a particle diameter of 24 μm (polishing process), and 30% by mass. Etching using a mixed aqueous solution of NH 3 and H 2 O 2 prepared by mixing 1: 1 aqueous ammonia, 40% by mass of hydrogen peroxide and pure water in a volume ratio of 1: 1: 2 (etching step) Performed. In addition, the crystal growth surface is processed by using fixed abrasive grains in which CBN abrasive grains having an average grain diameter of 125 μm are fixed with bonds (grinding process), and SiC grains having average grain diameters of 20 μm, 10 μm, and 5 μm are sequentially used. Polishing (polishing process), etching using 30% by weight NaOH aqueous solution (etching process), and CMP using a slurry of pH = 12, ORP = 450 mV containing TiO 2 abrasive grains having an average particle diameter of 1 μm (Fine polishing step).

2.GaN結晶基板の裏面および結晶成長面の反りならびに面粗さの測定 図1を参照して、上記の処理がされたGaN結晶基板10の裏面10rの反りw(R)を、レーザフォーカス方式のレーザ変位計(キーエンス社製LT−9010(レーザ出力部)およびLT−9500(レーザ制御部))、XYポジションコントローラ(コムス社製CP−500)および高速アナログ電圧データ収集装置(コムス社製CA−800)を用いて以下のように測定した。このレーザ変位計には、レーザ波長670nmの赤色半導体レーザが用いられていた。 2. Measurement of Warpage and Surface Roughness of Back Surface and Crystal Growth Surface of GaN Crystal Substrate With reference to FIG. 1, the warp w (R) of the back surface 10r of the GaN crystal substrate 10 subjected to the above-described treatment is expressed by a laser focus type laser. Displacement meter (LT-9010 (Laser output unit) and LT-9500 (Laser control unit) manufactured by Keyence), XY position controller (CP-500 manufactured by Coms), and high-speed analog voltage data acquisition device (CA-800 manufactured by Coms) ) And measured as follows. For this laser displacement meter, a red semiconductor laser having a laser wavelength of 670 nm was used.

図2〜図4を参照して、まず、GaN結晶基板10を、その結晶成長面10cの外周部が3つの支持部12hにより支持されるように、基板支持台12上に配置した。次いで、レーザ変位計15を用いてGaN結晶基板10の裏面10rの複数の測定点10pにそれぞれ対応する複数の変位値を検出した(基板検出ステップS1)。ここで、測定点10pのピッチPは700μmとして、約5000点の複数の測定点10pにそれぞれ対応する複数の変位値を測定した。次いで、8近傍のメディアンフィルタを用いて複数の変位値に含まれるノイズを除去した(ノイズ除去ステップS2)。次いで、複数の変位値からGaN結晶基板10の外周10eから3つ内側までの測定点にそれぞれ対応する複数の変位値を除去した複数の変位値からなる複数の計算用変位値を算出した(外周部除去ステップS3)。   2 to 4, first, the GaN crystal substrate 10 was placed on the substrate support 12 so that the outer peripheral portion of the crystal growth surface 10c was supported by the three support portions 12h. Next, a plurality of displacement values respectively corresponding to the plurality of measurement points 10p on the back surface 10r of the GaN crystal substrate 10 were detected using the laser displacement meter 15 (substrate detection step S1). Here, the pitch P of the measurement point 10p was 700 μm, and a plurality of displacement values respectively corresponding to the plurality of measurement points 10p of about 5000 were measured. Next, noise included in the plurality of displacement values was removed using a median filter in the vicinity of 8 (noise removal step S2). Next, a plurality of displacement values for calculation composed of a plurality of displacement values obtained by removing a plurality of displacement values respectively corresponding to the measurement points from the outer periphery 10e of the GaN crystal substrate 10 to the three inner points from the plurality of displacement values (periphery Part removal step S3).

次に、上記の複数の計算用変位値を、図6(c)に示す規格化後のσ=5の8近傍のガウシアンフィルタを用いて、平滑化処理して反り曲面を算出した(平滑化ステップS4)。次いで、平滑化処理がされた複数の計算用変位値における各変位値と最適平面との距離の二乗の和が最小となるように最適平面を算出した(最適平面算出ステップS5)。次いで、反り曲面が最適平面に対して、一方側に最も大きな変位値と最適平面との距離および他方側に最も大きな変位値と最適平面との距離の和を反りとして算出した(反り算出ステップS6)。こうして算出された反りは57.4μmであった。   Next, a warped curved surface was calculated by smoothing the plurality of calculation displacement values using a Gaussian filter in the vicinity of σ = 5 after normalization shown in FIG. Step S4). Next, the optimum plane was calculated so that the sum of the squares of the distances between the displacement values and the optimum plane in the plurality of calculation displacement values subjected to the smoothing process was minimized (optimum plane calculation step S5). Next, the sum of the distance between the largest displacement value and the optimum plane on one side and the distance between the largest displacement value and the optimum plane on the other side is calculated as a warp with respect to the optimum plane (warp calculation step S6). ). The warpage calculated in this way was 57.4 μm.

次に、再び、8近傍のメディアンフィルタを用いて複数の計算用変位値に含まれるノイズを除去した(ノイズ除去ステップS2)後、上記の平滑化ステップS4、最適平面算出ステップS5および反り算出ステップS6がこの順で行なわれる最適化サイクルを1回繰り返した。こうして算出された反りは54.9μmであった。   Next, again, noise included in a plurality of displacement values for calculation is removed using a median filter in the vicinity of 8 (noise removal step S2), and then the above-described smoothing step S4, optimal plane calculation step S5, and warp calculation step The optimization cycle in which S6 is performed in this order was repeated once. The warpage calculated in this way was 54.9 μm.

次に、上記の最適化サイクルをさらに1回繰り返した。こうして算出された反りは54.5μmであり、直前の算出反りとの差が0.5μm以下となったため、最適化サイクルを終了し、GaN結晶基板の裏面の反りw(R)を54.5μmと算出した。また、上記処理がされたGaN結晶基板10の結晶成長面10cの反りw(C)を光干渉方式のフラットネステスタを用いて測定したところ、48.2μmであった。 The above optimization cycle was then repeated once more. The warpage calculated in this way is 54.5 μm, and since the difference from the previous calculated warpage is 0.5 μm or less, the optimization cycle is finished, and the warpage w (R) of the back surface of the GaN crystal substrate is 54.5 μm. And calculated. Further, the warp w (C) of the crystal growth surface 10c of the GaN crystal substrate 10 subjected to the above-described treatment was measured using an optical interference type flatness tester and found to be 48.2 μm.

また、上記の処理がされたGaN結晶基板10の裏面10rの面粗さRa(R)および結晶成長面10cの面粗さRa(C)を、それぞれ3D−SEM(立体走査型電子顕微鏡)を用いて110μm×80μmの範囲およびレーザフォーカス方式のレーザ変位計を用いて750μm×700μmの範囲で測定し、かかる測定範囲から任意に特定した粗さ曲線からその平均線の方向に基準長さだけ抜き取り、この抜き取り部分の平均線から測定曲線までの偏差の絶対値を合計してそれを基準長さで平均することにより算出したところ、Ra(R)=11.8μm、Ra(C)=4nmであった。 Further, the surface roughness Ra (R) of the back surface 10r of the GaN crystal substrate 10 subjected to the above treatment and the surface roughness Ra (C) of the crystal growth surface 10c are respectively measured by 3D-SEM (stereoscopic scanning electron microscope). Measured in the range of 110 μm × 80 μm and in the range of 750 μm × 700 μm using a laser displacement meter of the laser focus method, and extracted from the measurement curve arbitrarily from the roughness curve by the reference length in the direction of the average line When the absolute values of deviations from the average line of the extracted part to the measurement curve are summed and averaged with the reference length, Ra (R) = 11.8 μm, Ra (C) = 4 nm there were.

また、上記の処理がされたGaN結晶基板10の裏面10rの面粗さRy(R)および結晶成長面10cの面粗さRy(C)を、レーザフォーカス方式のレーザ変位計を用いて750μm×700μmの範囲で測定し、かかる測定範囲から任意に特定した粗さ曲線からその平均線の方向に基準長さだけ抜き取り、この抜き取り部分の平均面から最も高い山頂までの高さと最も低い谷底までの深さとの和を算出したところ、Ry(R)=89.2μm、Ry(C)=38nmであった。 The above-mentioned processing has been surface roughness Ry of rear surface 10r of GaN crystal substrate 10 (R) and the surface roughness Ry of the crystal growth surface 10c (C), 750μm × using a laser displacement meter employing the laser focus technique Measured in the range of 700 μm, extracted from the roughness curve arbitrarily specified from this measurement range by the reference length in the direction of the average line, from the average surface of this extracted part to the highest peak and the lowest valley bottom When the sum with the depth was calculated, Ry (R) = 89.2 μm and Ry (C) = 38 nm.

また、上記の処理がされたGaN結晶基板10のピーク波長が450nm〜550nmの光の吸収係数は、分光測定装置により測定したところ、6.8cm-1であった。また、このGaN結晶基板10の熱伝導率は、レーザフラッフュによる二次元測定法を用いて18mm×18mmの範囲で測定したところ、165W/mKであった。また、このGaN結晶基板10の熱膨張係数は、レーザ干渉法により測定を行なったところ、4.2×10-6-1であった。 In addition, the absorption coefficient of light having a peak wavelength of 450 nm to 550 nm of the GaN crystal substrate 10 subjected to the above treatment was 6.8 cm −1 as measured by a spectroscopic measurement device. Further, the thermal conductivity of the GaN crystal substrate 10 was 165 W / mK when measured in a range of 18 mm × 18 mm using a two-dimensional measurement method using laser fluff. The thermal expansion coefficient of the GaN crystal substrate 10 was 4.2 × 10 −6 K −1 as measured by a laser interferometry.

3.半導体デバイスの製造
図9(a)を参照して、上記のGaN結晶基板10の結晶成長面10c上に、MOVPE法により、III族窒化物結晶層20として、厚さ5μmのn型GaN層21、厚さ3nmのIn0.2Ga0.8N層22、厚さ60nmのAl0.2Ga0.8N層23、厚さ150nmのp型GaN層24を順次成長させて半導体積層ウエハ80を得た。得られた半導体積層ウエハ80の発光強度の分布をフォトルミネッセンス法(以下、PL法という)により評価した。
3. Manufacturing of Semiconductor Device Referring to FIG. 9A, an n-type GaN layer 21 having a thickness of 5 μm is formed as a group III nitride crystal layer 20 on the crystal growth surface 10c of the GaN crystal substrate 10 by the MOVPE method. Then, an In 0.2 Ga 0.8 N layer 22 having a thickness of 3 nm, an Al 0.2 Ga 0.8 N layer 23 having a thickness of 60 nm, and a p-type GaN layer 24 having a thickness of 150 nm were sequentially grown to obtain a semiconductor laminated wafer 80. The distribution of light emission intensity of the obtained semiconductor laminated wafer 80 was evaluated by a photoluminescence method (hereinafter referred to as PL method).

具体的には、直径5.08cm(2インチ)の半導体積層ウエハ80のIII族窒化物結晶層20側の主面上の複数の測定点に、III族窒化物結晶層20のいずれの層の禁制帯幅より大きなエネルギーを有するレーザ光(ピーク波長が325nmのHe−Cdレーザ光)を照射し、励起された発光の強度を測定した。各測定点は、上記半導体積層ウエハ80のIII族窒化物結晶層20側の主面の全体に広がっており、この主面に平行な二次元方向に1mmのピッチで配列されている。ここで、半導体積層ウエハ80における発光強度の分布は、最も発光強度が大きい中央部の発光強度ICに対する最も発光強度が小さい外周80eから5mm以内の外周部の発光強度IEの百分率(100×IE/IC、以下、外周部の相対発光強度という)を用いて評価した。この外周部の相対発光強度の値が小さいほど発光強度の分布が大きく、外周部の相対発光強度の値が大きいほど発光強度の発光強度の分布が小さいことを示す。本比較例における外周部の相対発光強度は0.06であり、発光強度の分布が大きかった。結果を表1にまとめた。 Specifically, any layer of the group III nitride crystal layer 20 is formed at a plurality of measurement points on the main surface on the group III nitride crystal layer 20 side of the semiconductor laminated wafer 80 having a diameter of 5.08 cm (2 inches). Laser light having a larger energy than the forbidden band width (He—Cd laser light having a peak wavelength of 325 nm) was irradiated, and the intensity of the excited light emission was measured. Each measurement point extends over the entire main surface of the semiconductor laminated wafer 80 on the group III nitride crystal layer 20 side, and is arranged at a pitch of 1 mm in a two-dimensional direction parallel to the main surface. Here, the distribution of the emission intensity in the semiconductor laminated wafer 80 is the percentage of the emission intensity IE in the outer peripheral portion within 5 mm from the outer periphery 80e having the lowest emission intensity with respect to the emission intensity I C in the central portion having the highest emission intensity (100 × I E / I C, below, were evaluated using a) that the relative light emission intensity in the outer peripheral portion. The smaller the value of the relative light emission intensity at the outer peripheral part, the larger the distribution of the light emission intensity, and the larger the value of the relative light emission intensity at the outer peripheral part, the smaller the light emission intensity distribution. The relative light emission intensity at the outer peripheral portion in this comparative example was 0.06, and the light emission intensity distribution was large. The results are summarized in Table 1.

次に、図9(b)を参照して、この半導体積層ウエハ80を各チップに分離したときにGaN結晶基板10の裏面10rの中央部になる位置に直径80μm×厚さ100nmのn側電極81を形成し、p型GaN層24の上面に厚さ100nmのp側電極82を形成して、半導体デバイスウエハ90を得た。   Next, referring to FIG. 9B, an n-side electrode having a diameter of 80 μm and a thickness of 100 nm is formed at a position that becomes the center of the back surface 10r of the GaN crystal substrate 10 when the semiconductor laminated wafer 80 is separated into chips. 81 was formed, and a p-side electrode 82 having a thickness of 100 nm was formed on the upper surface of the p-type GaN layer 24 to obtain a semiconductor device wafer 90.

次に、図9(c)を参照して、この半導体デバイスウエハ90を400μm×400μmの各チップに分離して、半導体デバイス99であるLEDが得られた。得られた半導体デバイス99の歩留まり(チップ化された半導体デバイスの総数に対して一定の発光強度を有し製品として得られる半導体デバイスの数の百分率をいう、以下同じ)は、25%と低かった。結果を表1にまとめた。   Next, referring to FIG. 9C, the semiconductor device wafer 90 was separated into 400 μm × 400 μm chips, and an LED as the semiconductor device 99 was obtained. The yield of the obtained semiconductor devices 99 (referring to the percentage of the number of semiconductor devices having a constant light emission intensity with respect to the total number of semiconductor devices formed into chips and the same applies hereinafter) was as low as 25%. . The results are summarized in Table 1.

(実施例1)
GaN結晶基板の製造の際の裏面の処理において、粒径84μmのCBN砥粒をボンドで固定した固定砥粒を用いて研削し(研削工程)、粒径12μmのSiC砥粒を用いて研磨し(研磨工程)、85質量%のリン酸水溶液と90質量%の硫酸水溶液とを体積比で1:1で混合させたH3PO4およびH2SO4の混合水溶液を用いてエッチングすること(エッチング工程)により行なったこと以外は、比較例1と同様にして、GaN結晶基板を製造して、このGaN結晶基板の裏面および結晶成長面の反りならびに面粗さを測定した。得られたGaN結晶基板の裏面の反りw(R)は−22.8μm、面粗さRa(R)は10.2μm、面粗さRy(R)は78.5μmであった。なお、このGaN結晶基板の結晶成長面の反りw(C)は−17.4であり、面粗さRa(C)およびRy(C)はいずれも比較例1と同様であった。また、このGaN結晶基板のピーク波長が450nm〜550nmの光の吸収係数、熱伝導率および熱膨張係数は、いずれも比較例1と同様であった。
(Example 1)
In the processing of the back surface during the production of the GaN crystal substrate, grinding is performed using a fixed abrasive grain in which CBN abrasive grains having a grain size of 84 μm are fixed with a bond (grinding process), and polishing is performed using SiC abrasive grains having a grain size of 12 μm. (Polishing) Etching using a mixed aqueous solution of H 3 PO 4 and H 2 SO 4 in which 85% by mass phosphoric acid aqueous solution and 90% by mass sulfuric acid aqueous solution are mixed at a volume ratio of 1: 1 ( A GaN crystal substrate was manufactured in the same manner as in Comparative Example 1 except that the etching step was performed, and the warpage and surface roughness of the back surface and crystal growth surface of the GaN crystal substrate were measured. The warp w (R) of the back surface of the obtained GaN crystal substrate was −22.8 μm, the surface roughness Ra (R) was 10.2 μm, and the surface roughness Ry (R) was 78.5 μm. The warp w (C) of the crystal growth surface of this GaN crystal substrate was −17.4, and the surface roughness Ra (C) and Ry (C) were both the same as in Comparative Example 1. Further, the absorption coefficient, thermal conductivity, and thermal expansion coefficient of light having a peak wavelength of 450 nm to 550 nm of the GaN crystal substrate were all the same as those in Comparative Example 1.

次に、本実施例で得られたGaN結晶基板を用いて、比較例1と同様にして、、半導体積層ウエハおよび半導体デバイスウエハを経て、半導体デバイスを製造した。本実施例の半導体積層ウエハの外周部の相対発光強度は0.16と大きかった(すなわち、発光強度分布が小さかった)。また、半導体デバイスの歩留まりは44%と大きかった。結果を表1にまとめた。   Next, using the GaN crystal substrate obtained in this example, in the same manner as in Comparative Example 1, a semiconductor device was manufactured through a semiconductor laminated wafer and a semiconductor device wafer. The relative light emission intensity at the outer peripheral portion of the semiconductor laminated wafer of this example was as large as 0.16 (that is, the light emission intensity distribution was small). The yield of semiconductor devices was as high as 44%. The results are summarized in Table 1.

(実施例2)
GaN結晶基板の製造の際の裏面の処理において、粒径63μmのAl23砥粒をボンドで固定した固定砥粒を用いて研削し(研削工程)、粒径8μmのAl23砥粒を用いて研磨し(研磨工程)、25質量%のKOH水溶液を用いてエッチングすること(エッチング工程)により行なったこと以外は、比較例1と同様にして、GaN結晶基板を製造して、このGaN結晶基板の裏面および結晶成長面の反りならびに面粗さを測定した。得られたGaN結晶基板の裏面の反りw(R)は−19.1μm、面粗さRa(R)は6.8μm、面粗さRy(R)は55μmであった。なお、GaN結晶基板の結晶成長面の反りw(C)は−16.7μmであり、面粗さRa(C)およびRy(C)はいずれも比較例1と同様であった。また、このGaN結晶基板のピーク波長が450nm〜550nmの光の吸収係数、熱伝導率および熱膨張係数は、いずれも比較例1と同様であった。
(Example 2)
In the treatment of the back surface during the production of the GaN crystal substrate, grinding is performed using a fixed abrasive in which Al 2 O 3 abrasive grains having a particle size of 63 μm are fixed by bonding (grinding process), and Al 2 O 3 abrasive having a particle size of 8 μm. A GaN crystal substrate was produced in the same manner as in Comparative Example 1 except that polishing was performed using grains (polishing step) and etching was performed using a 25% by mass KOH aqueous solution (etching step). The warpage and surface roughness of the back surface and crystal growth surface of the GaN crystal substrate were measured. The warp w (R) of the back surface of the obtained GaN crystal substrate was −19.1 μm, the surface roughness Ra (R) was 6.8 μm, and the surface roughness Ry (R) was 55 μm. The warp w (C) of the crystal growth surface of the GaN crystal substrate was −16.7 μm, and the surface roughness Ra (C) and Ry (C) were both the same as in Comparative Example 1. Further, the absorption coefficient, thermal conductivity, and thermal expansion coefficient of light having a peak wavelength of 450 nm to 550 nm of the GaN crystal substrate were all the same as those in Comparative Example 1.

次に、本実施例で得られたGaN結晶基板を用いて、比較例1と同様にして、、半導体積層ウエハおよび半導体デバイスウエハを経て、半導体デバイスを製造した。本実施例の半導体積層ウエハの外周部の相対発光強度は0.29と大きかった(すなわち、発光強度分布が小さかった)。また、半導体デバイスの歩留まりは57%と大きかった。結果を表1にまとめた。   Next, using the GaN crystal substrate obtained in this example, in the same manner as in Comparative Example 1, a semiconductor device was manufactured through a semiconductor laminated wafer and a semiconductor device wafer. The relative light emission intensity at the outer peripheral portion of the semiconductor laminated wafer of this example was as large as 0.29 (that is, the light emission intensity distribution was small). The yield of semiconductor devices was as high as 57%. The results are summarized in Table 1.

(実施例3)
GaN結晶基板の製造の際の裏面の処理において、粒径32μmのダイヤモンド砥粒をボンドで固定した固定砥粒を用いて研削し(研削工程)、25質量%のKOHの水溶液を用いてエッチングすること(エッチング工程)により行なったこと以外は、比較例1と同様にして、GaN結晶基板を製造して、このGaN結晶基板の裏面および結晶成長面の反りならびに面粗さを測定した。得られたGaN結晶基板の裏面の反りw(R)は−3.4μm、面粗さRa(R)は4.9μm、面粗さRy(R)は31.9μmであった。なお、GaN結晶基板の結晶成長面の反りw(C)は−4.6μmであり、面粗さRa(C)およびRy(C)はいずれも比較例1と同様であった。また、このGaN結晶基板のピーク波長が450nm〜550nmの光の吸収係数、熱伝導率および熱膨張係数は、いずれも比較例1と同様であった。
(Example 3)
In the processing of the back surface during the manufacture of the GaN crystal substrate, grinding is performed using a fixed abrasive grain in which diamond abrasive grains having a particle diameter of 32 μm are fixed with a bond (grinding process), and etching is performed using an aqueous solution of 25 mass% KOH. A GaN crystal substrate was manufactured in the same manner as in Comparative Example 1 except that this was done by etching (etching step), and the warpage and surface roughness of the back surface and crystal growth surface of the GaN crystal substrate were measured. The warp w (R) of the back surface of the obtained GaN crystal substrate was −3.4 μm, the surface roughness Ra (R) was 4.9 μm, and the surface roughness Ry (R) was 31.9 μm. The warp w (C) of the crystal growth surface of the GaN crystal substrate was −4.6 μm, and the surface roughness Ra (C) and Ry (C) were both the same as in Comparative Example 1. Further, the absorption coefficient, thermal conductivity, and thermal expansion coefficient of light having a peak wavelength of 450 nm to 550 nm of the GaN crystal substrate were all the same as those in Comparative Example 1.

次に、本実施例で得られたGaN結晶基板を用いて、比較例1と同様にして、、半導体積層ウエハおよび半導体デバイスウエハを経て、半導体デバイスを製造した。本実施例の半導体積層ウエハの外周部の相対発光強度は0.41と大きかった(すなわち、発光強度分布が小さかった)。また、半導体デバイスの歩留まりは70%と大きかった。結果を表1にまとめた。   Next, using the GaN crystal substrate obtained in this example, in the same manner as in Comparative Example 1, a semiconductor device was manufactured through a semiconductor laminated wafer and a semiconductor device wafer. The relative light emission intensity at the outer peripheral portion of the semiconductor laminated wafer of this example was as large as 0.41 (that is, the light emission intensity distribution was small). The yield of semiconductor devices was as high as 70%. The results are summarized in Table 1.

(実施例4)
GaN結晶基板の製造の際の裏面の処理において、粒径30μmのSiC砥粒をボンドで固定した固定砥粒を用いて研削し(研削工程)、粒径6μmのダイヤモンド砥粒を用いて研磨し(研磨工程)、30質量%のアンモニア水と、40質量%の過酸化水素水と純水とを体積比で1:1:6で混合させたNH3およびH22の混合水溶液を用いてエッチングすること(エッチング工程)により行なったこと以外は、比較例1と同様にして、GaN結晶基板を製造して、このGaN結晶基板の裏面および結晶成長面の反りならびに面粗さを測定した。得られたGaN結晶基板の裏面の反りw(R)は4.8μm、面粗さRa(R)は3.8μm、面粗さRy(R)は23.8μmであった。なお、GaN結晶基板の結晶成長面の反りw(C)は2.8μmであり、面粗さRa(C)およびRy(C)はそれぞれ比較例1と同様であった。また、このGaN結晶基板のピーク波長が450nm〜550nmの光の吸収係数、熱伝導率および熱膨張係数は、いずれも比較例1と同様であった。
Example 4
In the processing of the back surface during the production of the GaN crystal substrate, grinding is performed using a fixed abrasive in which SiC abrasive grains having a grain size of 30 μm are fixed by bonding (grinding process), and polishing is performed using diamond abrasive grains having a grain diameter of 6 μm. (Polishing step) Using a mixed aqueous solution of NH 3 and H 2 O 2 in which 30% by mass of ammonia water, 40% by mass of hydrogen peroxide water and pure water were mixed at a volume ratio of 1: 1: 6. A GaN crystal substrate was manufactured in the same manner as in Comparative Example 1 except that the etching was performed by etching (etching process), and the warpage and surface roughness of the back surface and crystal growth surface of the GaN crystal substrate were measured. . The warp w (R) of the back surface of the obtained GaN crystal substrate was 4.8 μm, the surface roughness Ra (R) was 3.8 μm, and the surface roughness Ry (R) was 23.8 μm. The warp w (C) of the crystal growth surface of the GaN crystal substrate was 2.8 μm, and the surface roughnesses Ra (C) and Ry (C) were the same as in Comparative Example 1. Further, the absorption coefficient, thermal conductivity, and thermal expansion coefficient of light having a peak wavelength of 450 nm to 550 nm of the GaN crystal substrate were all the same as those in Comparative Example 1.

次に、本実施例で得られたGaN結晶基板を用いて、比較例1と同様にして、、半導体積層ウエハおよび半導体デバイスウエハを経て、半導体デバイスを製造した。本実施例の半導体積層ウエハの外周部の相対発光強度は0.38と大きかった(すなわち、発光強度分布が小さかった)。また、半導体デバイスの歩留まりは68%と大きかった。結果を表1にまとめた。   Next, using the GaN crystal substrate obtained in this example, in the same manner as in Comparative Example 1, a semiconductor device was manufactured through a semiconductor laminated wafer and a semiconductor device wafer. The relative light emission intensity at the outer peripheral portion of the semiconductor laminated wafer of this example was as large as 0.38 (that is, the light emission intensity distribution was small). The yield of semiconductor devices was as high as 68%. The results are summarized in Table 1.

(実施例5)
GaN結晶基板の製造の際の裏面の処理において、粒径37μmのSiC砥粒をボンドで固定した固定砥粒を用いて研削し(研削工程)、25質量%のKOH水溶液を用いてエッチングすること(エッチング工程)により行なったこと以外は、比較例1と同様にして、GaN結晶基板を製造して、このGaN結晶基板の裏面および結晶成長面の反りならびに面粗さを測定した。得られたGaN結晶基板の裏面の反りw(R)は9.9μm、面粗さRa(R)は5.5μm、面粗さRy(R)は38.7μmであった。なお、GaN結晶基板の結晶成長面の反りw(C)は10.4μmであり、面粗さRa(C)およびRy(C)はそれぞれ比較例1と同様であった。また、このGaN結晶基板のピーク波長が450nm〜550nmの光の吸収係数、熱伝導率および熱膨張係数は、いずれも比較例1と同様であった。
(Example 5)
In the processing of the back surface during the production of a GaN crystal substrate, grinding is performed using a fixed abrasive grain in which SiC abrasive grains having a grain size of 37 μm are fixed with a bond (grinding process), and etching is performed using a 25% by mass KOH aqueous solution. A GaN crystal substrate was produced in the same manner as in Comparative Example 1 except that the etching step was performed, and the warpage and surface roughness of the back surface and crystal growth surface of the GaN crystal substrate were measured. The warp w (R) of the back surface of the obtained GaN crystal substrate was 9.9 μm, the surface roughness Ra (R) was 5.5 μm, and the surface roughness Ry (R) was 38.7 μm. The warp w (C) of the crystal growth surface of the GaN crystal substrate was 10.4 μm, and the surface roughness Ra (C) and Ry (C) were the same as in Comparative Example 1. Further, the absorption coefficient, thermal conductivity, and thermal expansion coefficient of light having a peak wavelength of 450 nm to 550 nm of the GaN crystal substrate were all the same as those in Comparative Example 1.

次に、本実施例で得られたGaN結晶基板を用いて、比較例1と同様にして、、半導体積層ウエハおよび半導体デバイスウエハを経て、半導体デバイスを製造した。本実施例の半導体積層ウエハの外周部の相対発光強度は0.3と大きかった(すなわち、発光強度分布が小さかった)。また、半導体デバイスの歩留まりは65%と大きかった。結果を表1にまとめた。   Next, using the GaN crystal substrate obtained in this example, in the same manner as in Comparative Example 1, a semiconductor device was manufactured through a semiconductor laminated wafer and a semiconductor device wafer. The relative light emission intensity at the outer peripheral portion of the semiconductor laminated wafer of this example was as large as 0.3 (that is, the light emission intensity distribution was small). Moreover, the yield of semiconductor devices was as high as 65%. The results are summarized in Table 1.

(実施例6)
GaN結晶基板の製造の際の裏面の処理において、粒径74μmのダイヤモンド砥粒をボンドで固定した固定砥粒を用いて研削し(研削工程)、粒径15μmのCBN砥粒を用いて研磨し(研磨工程)、85質量%のH3PO4の水溶液を用いてエッチングすること(エッチング工程)により行なったこと以外は、比較例1と同様にして、GaN結晶基板を製造して、このGaN結晶基板の裏面および結晶成長面の反りならびに面粗さを測定した。得られたGaN結晶基板の裏面の反りw(R)は19.3μm、面粗さRa(R)は10.8μm、面粗さRy(R)は81.9μmであった。なお、GaN結晶基板の結晶成長面の反りw(C)は23.0μmであり、面粗さRa(C)およびRy(C)はそれぞれ比較例1と同様であった。また、このGaN結晶基板のピーク波長が450nm〜550nmの光の吸収係数、熱伝導率および熱膨張係数は、いずれも比較例1と同様であった。
(Example 6)
In the processing of the back surface during the production of a GaN crystal substrate, grinding is performed using a fixed abrasive grain in which diamond abrasive grains having a grain size of 74 μm are fixed with a bond (grinding process), and polishing is performed using CBN abrasive grains having a grain diameter of 15 μm. (Polishing step) A GaN crystal substrate was manufactured in the same manner as in Comparative Example 1 except that etching was performed using an aqueous solution of 85 mass% H 3 PO 4 (etching step). The warpage and surface roughness of the back surface and crystal growth surface of the crystal substrate were measured. The warp w (R) of the back surface of the obtained GaN crystal substrate was 19.3 μm, the surface roughness Ra (R) was 10.8 μm, and the surface roughness Ry (R) was 81.9 μm. The warp w (C) of the crystal growth surface of the GaN crystal substrate was 23.0 μm, and the surface roughnesses Ra (C) and Ry (C) were the same as in Comparative Example 1. Further, the absorption coefficient, thermal conductivity, and thermal expansion coefficient of light having a peak wavelength of 450 nm to 550 nm of the GaN crystal substrate were all the same as those in Comparative Example 1.

次に、本実施例で得られたGaN結晶基板を用いて、比較例1と同様にして、、半導体積層ウエハおよび半導体デバイスウエハを経て、半導体デバイスを製造した。本実施例の半導体積層ウエハの外周部の相対発光強度は0.26と大きかった(すなわち、発光強度分布が小さかった)。また、半導体デバイスの歩留まりは61%と大きかった。結果を表1にまとめた。   Next, using the GaN crystal substrate obtained in this example, in the same manner as in Comparative Example 1, a semiconductor device was manufactured through a semiconductor laminated wafer and a semiconductor device wafer. The relative light emission intensity at the outer peripheral portion of the semiconductor laminated wafer of this example was as large as 0.26 (that is, the light emission intensity distribution was small). The yield of semiconductor devices was as high as 61%. The results are summarized in Table 1.

Figure 2009111423
Figure 2009111423

表1において、比較例1と実施例1〜6とを比較すると、結晶成長面の反対側の面である裏面の反りw(R)が−50μm≦w≦50μmであるGaN結晶基板の結晶成長面側に少なくとも1層のIII族窒化物結晶層を成長させることにより、発光強度分布が小さい半導体積層ウエハが得られ、半導体デバイスの歩留まりが高くなることがわかる。 In Table 1, when Comparative Example 1 and Examples 1 to 6 are compared, the crystal growth of the GaN crystal substrate in which the warp w (R) of the back surface, which is the surface opposite to the crystal growth surface, is −50 μm ≦ w ≦ 50 μm. It can be seen that by growing at least one group III nitride crystal layer on the surface side, a semiconductor laminated wafer having a small emission intensity distribution is obtained, and the yield of semiconductor devices is increased.

また、実施例1,6と実施例2〜5とを比較すると、結晶成長面の反対側の面である裏面の反りw(R)が−50μm≦w≦50μm、裏面の面粗さRa(R)がRa(R)≦10μmおよび裏面の面粗さRy(R)がRy(R)≦75μmであるGaN結晶基板の結晶成長面側に少なくとも1層のIII族窒化物結晶層を成長させることにより、発光強度分布がより小さい半導体積層ウエハが得られ、半導体デバイスの歩留まりがさらに高くなることがわかる。 Further, when Examples 1 and 6 are compared with Examples 2 to 5, warpage w (R) of the back surface, which is the surface opposite to the crystal growth surface, is −50 μm ≦ w ≦ 50 μm, and surface roughness Ra ( At least one group III nitride crystal layer is grown on the crystal growth surface side of the GaN crystal substrate where R) is Ra (R) ≦ 10 μm and the surface roughness Ry (R) of the back surface is Ry (R) ≦ 75 μm. Thus, a semiconductor laminated wafer having a smaller emission intensity distribution is obtained, and it can be seen that the yield of semiconductor devices is further increased.

さらに、実施形態3で得られる複数の半導体デバイスについて、GaN結晶基板の裏面の反りと半導体デバイスの歩留まりとの関係を図10に示した。図10には、比較例1および実施例1〜6についての点が含まれる。図10に示すように、GaN結晶基板の裏面の反りw(R)が、−50μm≦w(R)≦50μmのとき半導体デバイスの歩留まりが高くなり、−35μm≦w(R≦45μmのとき半導体デバイスの歩留まりがより高くなった。このように、好ましい裏面の反りの領域が、負(−)側より正(+)側に大きくなるのは、既に考察したように、図1を参照して、裏面10rの反りが正(+)の場合には裏面10rとサセプタ9の表面との間に閉空間の空隙部91が形成され(図1(a)参照)、裏面10rの反りが負(−)の場合には裏面10rとサセプタ9の表面との間に開空間の空隙部91が形成され、反りが正(+)のときの基板の熱分布が反りが負(−)のときの基板の熱分布に比べて小さくなるためと考えられる。 Furthermore, regarding the plurality of semiconductor devices obtained in the third embodiment, the relationship between the warpage of the back surface of the GaN crystal substrate and the yield of the semiconductor devices is shown in FIG. FIG. 10 includes points for Comparative Example 1 and Examples 1 to 6. As shown in FIG. 10, the yield of the semiconductor device is high when the warp w (R) of the back surface of the GaN crystal substrate is −50 μm ≦ w (R) ≦ 50 μm, and the semiconductor is −35 μm ≦ w (R ≦ 45 μm). The yield of the device has become higher, and the reason why the preferred backside warp region is larger from the negative (−) side to the positive (+) side, as already discussed, is shown in FIG. When the warpage of the back surface 10r is positive (+), a gap 91 in a closed space is formed between the back surface 10r and the surface of the susceptor 9 (see FIG. 1A), and the warpage of the back surface 10r is negative ( In the case of-), an open space void 91 is formed between the back surface 10r and the surface of the susceptor 9, and the thermal distribution of the substrate when the warpage is positive (+) is negative (-). This is considered to be because it becomes smaller than the heat distribution of the substrate.

今回開示された実施の形態および実施例はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は、上記した説明でなくて特許請求の範囲によって示され、特許請求の範囲と均等の意味および範囲内のすべての変更が含まれることが意図される。   It should be understood that the embodiments and examples disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 GaN結晶、9 サセプタ、10 GaN結晶基板、10c 結晶成長面、10e,80e 外周、10p 測定点、10r 裏面、10u 食刻部分、12 基板支持台、12a 非凹部面、12b 凹部面、12h 支持部、13 駆動部、14 駆動装置、15 レーザ変位計、16 駆動制御装置、17 レーザ変位計制御装置、18 データ解析装置、20 III族窒化物結晶層、21 n型GaN層、22 In0.2Ga0.8N層、23 Al0.2Ga0.8N層、24 p型GaN層、31 レーザ光、31i 入射光、31r 反射光、32 位置データ、33 変位値データ、40 反り曲面、50 最適平面、80 半導体積層ウエハ、81 n側電極、82 p側電極、90 半導体デバイスウエハ、91 空隙部、99 半導体デバイス、100p 任意に特定される測定点、101p,102p,103p,104p,105p,106p,107p,108p 任意に特定される測定点に近傍する複数の測定点、111p 外周から1つ内側の測定点、112p 外周から2つ内側の測定点、120a 基板支持台の非凹部面の測定点、120b 基板支持台の凹部面の測定点。 1 GaN crystal, 9 susceptor, 10 GaN crystal substrate, 10c crystal growth surface, 10e, 80e outer periphery, 10p measurement point, 10r back surface, 10u etched portion, 12 substrate support base, 12a non-recessed surface, 12b recessed surface, 12h supported Unit, 13 drive unit, 14 drive unit, 15 laser displacement meter, 16 drive control unit, 17 laser displacement meter control unit, 18 data analysis unit, 20 group III nitride crystal layer, 21 n-type GaN layer, 22 In 0.2 Ga 0.8 N layer, 23 Al 0.2 Ga 0.8 N layer, 24 p-type GaN layer, 31 laser light, 31i incident light, 31r reflected light, 32 position data, 33 displacement value data, 40 warped surface, 50 optimal plane, 80 semiconductor stack Wafer, 81 n-side electrode, 82 p-side electrode, 90 semiconductor device wafer, 91 gap, 99 semiconductor device, 100p Specified arbitrarily Fixed point, 101p, 102p, 103p, 104p, 105p, 106p, 107p, 108p Multiple measurement points close to the arbitrarily specified measurement point, 111p One measurement point from the outer circumference, 112p Two measurement points from the outer circumference Point, 120a Measurement point on the non-recessed surface of the substrate support, 120b Measurement point on the recessed surface of the substrate support.

Claims (11)

結晶成長面の反対側の面である裏面に関して、反り曲面が最適平面に対して一方側に最も大きな変位値と最適平面との距離および他方側に最も大きな変位値と最適平面との距離の和として算出される前記裏面の長さ5.08cm当りの反りw(R)が、−35μm≦w(R)≦45μmであるGaN結晶基板。 With respect to the back surface, which is the surface opposite to the crystal growth surface, the sum of the distance between the largest displacement value and the optimum plane on one side and the distance between the largest displacement value and the optimum plane on the other side is the warped curved surface. The GaN crystal substrate in which the warpage w (R) per 5.08 cm length of the back surface calculated as follows is −35 μm ≦ w (R) ≦ 45 μm. 前記裏面の面粗さRa(R)が、Ra(R)≦10μmである請求項1に記載のGaN結晶基板。 2. The GaN crystal substrate according to claim 1, wherein the surface roughness Ra (R) of the back surface is Ra (R) ≦ 10 μm. 前記裏面の面粗さRa(R)が、Ra(R)≧1μmである請求項2に記載のGaN結晶基板。 The GaN crystal substrate according to claim 2, wherein the surface roughness Ra (R) of the back surface is Ra (R) ≧ 1 μm. 前記裏面の面粗さRy(R)が、Ry(R)≦75μmである請求項1から請求項3までのいずれかに記載のGaN結晶基板。 The GaN crystal substrate according to any one of claims 1 to 3, wherein a surface roughness Ry (R) of the back surface is Ry (R) ≤ 75 µm. 前記裏面の面粗さRy(R)が、Ry(R)≧3μmである請求項4に記載のGaN結晶基板。 The GaN crystal substrate according to claim 4, wherein the surface roughness Ry (R) of the back surface is Ry (R) ≧ 3 μm. 光干渉方式のフラットネステスタを用いて測定される前記結晶成長面の長さ5.08cm当りの反りw(C)が−50μm≦w(C)≦50μmである請求項1から請求項3までのいずれかに記載のGaN結晶基板。 The warp w (C) per 5.08 cm length of the crystal growth surface measured by using an optical interference type flat tester is -50 μm ≦ w (C) ≦ 50 μm. The GaN crystal substrate according to any one of the above. 前記結晶成長面の面粗さRa(C)がRa(C)≦10nmである請求項1から請求項6までのいずれかに記載のGaN結晶基板。 The GaN crystal substrate according to any one of claims 1 to 6, wherein a surface roughness Ra (C) of the crystal growth surface satisfies Ra (C) ≤ 10 nm. 前記結晶成長面の面粗さRy(C)がRy(C)≦60nmである請求項1から請求項7までのいずれかに記載のGaN結晶基板。 The GaN crystal substrate according to claim 1, wherein a surface roughness Ry (C) of the crystal growth surface is Ry (C) ≦ 60 nm. 請求項1から請求項8までのいずれかのGaN結晶基板の製造方法であって、
成長させたGaN結晶からGaN結晶基板を切り出す工程および前記GaN結晶基板の裏面を処理する工程とを含み、
前記GaN結晶基板の裏面を処理する工程は、前記裏面を研削する工程、前記裏面を研磨する工程および前記裏面をエッチングする工程の少なくともいずれかの工程を含むGaN結晶基板の製造方法。
A method for producing a GaN crystal substrate according to any one of claims 1 to 8,
Cutting the GaN crystal substrate from the grown GaN crystal and processing the back surface of the GaN crystal substrate,
The method of manufacturing a GaN crystal substrate, wherein the step of processing the back surface of the GaN crystal substrate includes at least one of a step of grinding the back surface, a step of polishing the back surface, and a step of etching the back surface.
基板として請求項1から請求項8までのいずれかのGaN結晶基板を選択し、前記GaN結晶基板の前記結晶成長面側に少なくとも1層のIII族窒化物結晶層を成長させる工程を含む半導体デバイスの製造方法。   A semiconductor device comprising: selecting the GaN crystal substrate according to any one of claims 1 to 8 as a substrate, and growing at least one group III nitride crystal layer on the crystal growth surface side of the GaN crystal substrate Manufacturing method. 請求項1から請求項8までのいずれかのGaN結晶基板と、前記GaN結晶基板の前記結晶成長面側に形成されている少なくとも1層のIII族窒化物結晶層と、を備える半導体デバイス。   A semiconductor device comprising: the GaN crystal substrate according to claim 1; and at least one group III nitride crystal layer formed on the crystal growth surface side of the GaN crystal substrate.
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