JP7406914B2 - SiC wafer and SiC wafer manufacturing method - Google Patents

Description

The present invention relates to a SiC wafer and a method for manufacturing a SiC wafer.

Silicon carbide (SiC) wafers are formed by slicing an ingot of single crystal SiC. On the surface of a sliced SiC wafer, there is a surface layer (hereinafter referred to as a process-affected layer) having crystal distortions, scratches, etc. introduced during slicing. In order not to reduce the yield in the device manufacturing process, it is necessary to remove this process-affected layer.

Conventionally, the process-affected layer introduced on the main surface and back surface of a SiC wafer has been mainly removed by surface processing using abrasive grains. In recent years, various proposals have been made regarding surface processing techniques that do not use abrasive grains. For example, Patent Document 1 describes an etching technique (hereinafter also referred to as Si vapor pressure etching) in which a SiC wafer is etched by heating it under Si vapor pressure.

Japanese Patent Application Publication No. 2011-247807

By the way, single-crystal SiC is a hard and brittle material that has a hardness second only to diamond and the like and is easily cleaved on the (0001) plane and (1-100) plane, and is classified as a material that is extremely difficult to process. What is required in the processing process of semiconductor materials is "high quality (high flatness, no damage)", "low loss (material loss, yield)", "low cost (high efficiency, inexpensive means and processes)", However, the higher the hardness and brittleness, the more there is a trade-off relationship between these, and it is difficult to achieve both.

Among these, in order to industrially produce SiC wafers, a technology for manufacturing high quality SiC wafers is particularly required. In particular, SiC wafers having a process-affected layer have problems such as an increase in the SORI value during high-temperature annealing in the subsequent device manufacturing process, and problems such as cracks (scars) and crystal distortion appearing as defects.

Therefore, it is desirable to remove the process-affected layer over the entire area of the SiC wafer. However, there has been no means for removing the process-affected layer at locations other than the main surface and back surface of the SiC wafer, such as the outer periphery, notches such as orientation flats, and the periphery of the stamped portions.

An object of the present invention is to provide a high-quality SiC wafer from which scratches and lattice distortion are removed, and a method for manufacturing the same.

In order to solve the above problems, a SiC wafer according to one embodiment of the present invention is characterized in that there is substantially no process-affected layer.
Further, an SiC wafer according to another aspect of the present invention that solves the above problem has a main surface on which a semiconductor element is formed, a back surface opposite to the main surface, and an outer peripheral portion connected to the outer edges of the main surface and the back surface. , a notch provided in a part of the outer peripheral part, and a stamped part provided in the main surface or the back surface, the main surface, the back surface, the outer peripheral part, the notch, and the The stamped portion is characterized by substantially no process-affected layer.
Further, a SiC wafer according to another aspect of the present invention that solves the above problems is characterized by substantially no lattice distortion other than lattice distortion derived from surface reconstruction.
Further, a SiC wafer according to another aspect of the present invention that solves the above problem has a main surface on which a semiconductor element is formed, a back surface opposite to the main surface, and a bulk layer adjacent to the main surface and the back surface. The bulk layer has a lattice strain amount of 0.01% or less with respect to a reference crystal lattice.

In this way, since there is substantially no lattice strain other than the lattice strain resulting from surface reconstruction, a high-quality SiC wafer suitable for subsequent device manufacturing steps can be obtained.

In this aspect, the bulk layer has a lattice strain amount of 0.01% or less with respect to a reference crystal lattice.

This embodiment is characterized in that the doping concentration is 10 ¹⁹ cm ⁻³ or more.

This embodiment is characterized in that the SORI value does not change when heated in a temperature range of 1500 to 2000°C.

Further, a method for manufacturing a SiC wafer according to another aspect of the present invention that solves the above problems includes a planarization step of planarizing the SiC wafer, and after the planarization step, heating the SiC wafer under Si vapor pressure. The method is characterized in that it includes an etching step of etching the main surface and the back surface of the wafer.

In this aspect, the processing temperature of the etching step is 1500° C. or higher.

In this aspect, the SiC wafer is characterized in that the doping concentration is 10 ¹⁹ cm ^-3 or more.

This aspect is characterized in that, subsequent to the etching step, a mirror polishing step of mirror polishing the main surface of the SiC wafer is included.

In this aspect, before the etching step, there is an ingot forming step of processing a lump of crystal-grown single crystal SiC into a cylindrical ingot, and a slicing step of slicing the ingot to obtain a thin disc-shaped SiC wafer. The method further includes: a stamp forming step of selectively removing the surface of the SiC wafer to form a stamp portion; and a chamfering step of chamfering the outer periphery of the SiC wafer.

According to the disclosed technology, it is possible to provide a high-quality SiC wafer from which scratches and lattice distortion have been removed, and a method for manufacturing the same.

Other objects, features, and advantages will become apparent from a reading of the detailed description set forth below when taken in conjunction with the drawings and claims.

It is a schematic diagram showing a manufacturing process of a SiC wafer of one embodiment. It is an explanatory view showing a process from an ingot to a wafer in the manufacturing process of a SiC wafer of one embodiment. It is an explanatory view showing a manufacturing process of a SiC wafer of one embodiment. FIG. 2 is a schematic diagram showing a high-temperature vacuum furnace used in Si vapor pressure etching. It is an image of the back surface of the SiC wafer of Example 1 observed with a white interference microscope. This is an image of the back surface of the SiC wafer of Example 2 observed with a white interference microscope. 3 is a graph showing the reflectance of the SiC wafer of Example 1. 3 is a graph showing the external transmittance of the SiC wafer of Example 1. This is an imaging image obtained by observing a cross section of the SiC wafer of Example 1 using SEM-EBSD. This is an imaging image obtained by observing a cross section of the SiC wafer of Example 2 using SEM-EBSD. 1 is an image of a cross section of the SiC wafer of Example 1 observed with a transmission electron microscope. This is an image of a cross section of the SiC wafer of Example 2 observed with a transmission electron microscope. It is a conceptual diagram when the surface of a SiC wafer subjected to general machining processing is observed from a cross section. 2 is a graph showing the relationship between the depth of a damaged layer and warpage (SORI value) of a single-crystal SiC wafer. FIG. 2 is a schematic diagram showing a conventional SiC wafer manufacturing process. FIG. 2 is an explanatory diagram showing a conventional SiC wafer manufacturing process.

Hereinafter, after a detailed description of an embodiment of the SiC wafer of the present invention, a detailed description of an embodiment of the manufacturing method of the present invention will be given.

Further, FIG. 13 shows a conceptual diagram when the surface of a wafer subjected to mechanical processing is observed from a cross section. SiC wafer 20 is formed by slicing and planarizing single-crystal SiC ingot 10 . At this time, a process-affected layer 30 is introduced onto the surface of the SiC wafer 20, including a cracked layer 31 having a large number of cracks (flaws) and a strained layer 32 in which a crystal lattice is distorted. Furthermore, the process-affected layer 30 is similarly introduced during surface processing in which the wafer surface is selectively removed by laser processing or the like to form the marking portions 25.
In order not to reduce the yield in the device manufacturing process, it is necessary to remove this process-affected layer 30. That is, it is preferable to expose the bulk layer 33 under the process-affected layer 30 in which no cracks or lattice distortions due to surface processing have been introduced.

Further, the SiC wafer 20 having the normal process-affected layer 30 has warpage caused by the process-affected layer 30 . One of the indicators for evaluating warped shape is the SORI value. This SORI value is calculated from the least squares plane calculated by the least squares method using all data on the wafer surface when the back side of the wafer is supported and the original shape is not changed. It refers to the sum of the normal distances between a point and the lowest point.

It has been newly found that the SORI value becomes more susceptible to the influence of the process-affected layer 30 as the diameter of the wafer becomes larger. FIG. 14 shows a graph showing the relationship between the depth of the process-affected layer 30 and the SORI value of a single-crystal SiC wafer. As shown in FIG. 14, it can be seen that the deeper the depth of the work-affected layer 30, the larger the SORI value. Further, when comparing a 6-inch single-crystal SiC wafer and a 4-inch single-crystal SiC wafer, it can be seen that the 6-inch single-crystal SiC wafer is more susceptible to the influence of the damaged layer 30 and has a larger SORI value. Therefore, it is important to remove the process-affected layer 30 in order to reduce warping of the SiC wafer.

In the description herein, the pear surface is a concept representing a surface on which fine irregularities are formed like the skin of a pear fruit. Examples of the satin surface include a surface in which amorphous fine spot-like irregularities are combined in a disorderly manner without any direction, and a surface in which streak-like irregularities extending in one direction are arranged.

In the description herein, the surface of the SiC wafer 20 on which semiconductor elements are formed (specifically, the surface on which an epitaxial film is deposited) is referred to as the main surface 21, and the surface opposite to this main surface 21 is referred to as the back surface 22. That's what it means. Further, the main surface 21 and the back surface 22 are collectively referred to as the front surface. Note that examples of the main surface 21 include the (0001) plane, the (000-1) plane, and a surface with an off angle of several degrees from these planes. (In this specification, in the notation of Miller index, "-" means a bar attached to the index immediately after it).

<1> SiC Wafer It is desirable that the SiC wafer 20 is substantially free of the process-affected layer 30. That is, the process-affected layer 30 is substantially not present on any of the main surface 21 on which the semiconductor element is made, the back surface 22 facing the main surface 21, the outer circumferential portion 23, the orientation flat 24, notches such as notches, and the stamped portions 25. It is desirable that there is no such thing. In other words, it is desirable that there be substantially no lattice distortion other than lattice distortion derived from surface reconstruction. In other words, it is desirable that the bulk layer 33 adjacent to the main surface 21 and the back surface 22 has substantially no lattice strain other than the lattice strain resulting from surface reconstruction.

Here, "substantially no process-affected layer" means that there is no process-affected layer that affects the device manufacturing process. For example, it means that there is no process-affected layer with a lattice strain of more than 0.01%, which will be described later.

Moreover, "there is substantially no lattice strain other than lattice strain derived from surface reconstruction" means that there is no lattice strain to the extent that it affects the device manufacturing process. For example, it means that the amount of lattice distortion of the single crystal SiC constituting the SiC wafer 20 other than the surface is 0.01% or less.

Since no lattice strain occurs throughout the SiC wafer 20 as described above, it is possible to provide the SiC wafer 20 suitable for device manufacturing processes.
Note that in the description herein, lattice distortion refers to lattice distortion excluding lattice distortion resulting from surface reconstruction.
In the description of this specification, the amount of lattice strain refers to the amount of misalignment that occurs when the crystal lattice of the bulk layer 33 in FIG. Since it is a numerical value representing , it is expressed as "%".

The lattice strain under the surface of the SiC wafer 20 can be determined by comparing it with a reference crystal lattice that serves as a reference. As a means for measuring this lattice strain, for example, the SEM-EBSD method can be used. The SEM-EBSD method is a method that can measure strain in minute areas based on the Kikuchi line diffraction pattern obtained by electron beam backscattering in a scanning electron microscope (SEM). : EBSD). In this method, the amount of lattice distortion can be determined by comparing the diffraction pattern of a reference crystal lattice serving as a reference with the diffraction pattern of a measured crystal lattice.

As the reference crystal lattice, for example, a reference point R is set in a region where no lattice distortion is considered to occur. That is, it is desirable to arrange the reference point R in the region of the bulk layer 33 in FIG. It is generally accepted that the depth of the process-affected layer 30 is about 10 μm. Therefore, the reference point R may be set at a depth of approximately 20 to 30 μm, which is considered to be sufficiently deeper than the process-affected layer 30.
Next, the diffraction pattern of the crystal lattice at this reference point R is compared with the diffraction pattern of the crystal lattice in each measurement area measured at a pitch on the order of nanometers. Thereby, the amount of lattice distortion in each measurement region with respect to the reference point R can be calculated.

In addition, although we have shown the case where the reference point R is set as the reference crystal lattice where it is considered that no lattice distortion occurs, it is also possible to set the reference point R, which is considered to be free from lattice distortion, but Of course, it is also possible to use the crystal lattice that occupies the majority (for example, more than half) as the reference.

Further, as a method for determining the amount of lattice strain under the surface of the SiC wafer 20, a general-purpose stress measurement method can be adopted, and examples thereof include Raman spectroscopy, X-ray diffraction, and electron beam diffraction. Can be done.

The crystal lattice under the surface of the SiC wafer 20 of the present invention has a lattice strain amount of preferably 0.01% or less, more preferably 0.005% or less, and still more preferably 0.001% with respect to the reference crystal lattice. It is as follows.
As described above, since the amount of lattice strain is 0.01% or less, it is possible to suppress the occurrence of defects caused by lattice strain in the subsequent device manufacturing process, thereby providing a higher quality SiC wafer 20. be able to.

It is desirable that the SiC wafer 20 of the present invention has a main surface 21 that is mirror-finished and a back surface 22 that is satin-finished.
Single crystal SiC has translucency and transmits visible light. Therefore, there is a problem in that it is difficult to detect the wafer using an optical sensor during the device manufacturing process. Since the SiC wafer 20 of the present invention has a matte surface on the back surface 22, the detection rate by an optical sensor can be improved compared to a conventional SiC wafer that has mirror surfaces on both sides.
Furthermore, since the coefficient of friction on the back surface of the wafer is large, it is difficult to slip during transportation or within the apparatus, and it is easy to peel off from an electrostatic chuck sample stage, which is advantageous in the device manufacturing process.

The arithmetic mean roughness Ra of the satin surface is preferably 50 to 300 nm, more preferably 75 to 200 nm.
Further, the maximum height Rz of the satin surface is preferably 0.5 to 5 μm, more preferably 0.75 to 2.5 μm.

By forming the roughness of the matte surface to such a value, it becomes easy to distinguish between the main surface and the back surface of the SiC wafer 20, and the coefficient of friction on the back surface of the wafer increases to prevent slipping during transportation or inside the equipment. The advantages such as being easily removed from the electrostatic chuck sample table and being easily removed from the electrostatic chuck sample table are more strongly exhibited.
Furthermore, problems such as easy adhesion of particles and deterioration of the flatness of the wafer when chucked onto a sample stage can be more strongly suppressed.

In the description herein, the arithmetic mean roughness Ra and maximum height Rz refer to the arithmetic mean roughness and maximum height conforming to Japanese Industrial Standard (JIS) B0601-2001.
Further, although it cannot be expressed numerically, it is preferable that the surface shape of the satin surface of the SiC wafer 20 of the present invention has a structure having convex portions with smooth edges, with minute burrs removed. .

It is desirable that the reflectance of the satin surface is 5% or less, more preferably 3% or less, and still more preferably 2% or less.

Note that in the description herein, the term "reflectance" refers to the rate at which the irradiated electromagnetic waves are reflected from the surface when the surface of the SiC wafer is irradiated with electromagnetic waves having a wavelength of 300 to 1500 nm. Furthermore, in the description herein, visible light refers to electromagnetic waves with a wavelength of 360 to 830 nm.

The SiC wafer 20 having a matte surface having such a reflectance has a high detection rate by an optical sensor used during the device manufacturing process. In other words, such a satin surface has high visibility, so that the wafer can be easily detected. In addition, since it is easy to distinguish from a mirror surface, during the inspection process of wafers and assemblies, you will not accidentally focus on the back side when trying to focus on the front side, and you will be able to properly inspect and diagnose. can.

Further, although it cannot be expressed numerically, it is preferable that the surface shape of the satin surface has a structure in which a plurality of gently convex portions having different diameters are arranged in a scale-like manner.
By configuring the satin surface in such a shape, advantages in the device manufacturing process can be further improved.

On the other hand, the arithmetic mean roughness Ra of the mirror surface is preferably 0.05 to 0.3 nm, more preferably 0.05 to 0.1 nm.
Further, the maximum height Rz of the mirror surface is 0.2 to 1.2 μm, more preferably 0.2 to 0.4 μm.
By forming the mirror surface in this manner, it becomes easy to identify the main surface and the back surface of the wafer.

In addition, it is desirable that the reflectance of the specular side in visible light has no variation for each wavelength, and the difference in reflectance for each wavelength is 6% or less, more preferably 5% or less, and even more preferably The difference is 4% or less.
In this way, the SiC wafer 20 with the satin surface can improve the detection rate for optical sensors of various wavelengths by reducing the difference in reflectance for each wavelength. That is, by diffusing and scattering the incident light, the satin surface can suppress interference that occurs in a specific wavelength range, and can reduce the difference in reflectance between wavelengths.

The thickness of the SiC wafer 20 (wafer thickness) is preferably 1 mm or less, more preferably 500 μm or less, and even more preferably 50 to 350 μm.
Even if the SiC wafer 20 is set to such a small thickness, the detection rate of the optical sensor can be improved because the back surface 22 is processed to have a satin finish.

The external transmittance of visible light including the interface of the SiC wafer 20 is preferably 25% or less. The SiC wafer 20 having such external transmittance has a high detection rate with an optical sensor, and can suppress detection errors in the device manufacturing process.

In the description of this specification, external transmittance refers to the rate at which electromagnetic waves with a wavelength of 300 to 1500 nm are transmitted through the SiC wafer 20 when the main surface 21 or the back surface 22 is irradiated with the electromagnetic waves. say.

Further, as the SiC wafer 20, one having a doping concentration of 10 ¹⁹ cm ^-3 or more may be used. Even in a low resistance wafer with a high doping concentration, the crack layer 31 and the strained layer 32 can be removed.

Furthermore, the SORI value of the SiC wafer according to the present invention does not change when heated in a temperature range of 1500 to 2000°C. That is, since the process-affected layer 30 has been removed over the entire area of the SiC wafer 20, warping due to the process-affected layer 30 will not occur during the subsequent device manufacturing process.
Note that "the SORI value does not change" in this specification means that there is no change in the SORI value due to the process-affected layer 30. For example, it does not include changes in the SORI value due to lattice distortion, damage, etc. introduced in the device manufacturing process after the epitaxial growth process, ion implantation process, etc.

In addition, in the SiC wafer 20 according to the present invention, the process-affected layer 30 is removed not only on the main surface 21 and the back surface 22 but also on the outer periphery 23, the orientation flat 24, notches such as notches, and the stamped portion 25, which are difficult to machine. has been done. Therefore, defects etc. that occur due to the process-affected layer 30 in the subsequent device manufacturing process can be suppressed.

Although the method for manufacturing the SiC wafer 20 of the present invention is not particularly limited, it is preferable to manufacture the SiC wafer 20 using the manufacturing method of the present invention described below. The manufacturing method of the present invention will be explained below.

<2> Method for manufacturing a SiC wafer The method for manufacturing a SiC wafer of the present invention will be described in more detail below with reference to FIGS. 1, 2, 3, and 4. Preferred embodiments are shown in the drawings. However, it can be implemented in many different forms and is not limited to the embodiments described herein.

In addition, in understanding the present invention, it is recognized that it is useful to compare with the conventional SiC wafer manufacturing process. Therefore, each step in the method for manufacturing a SiC wafer of the present invention will be described with reference to FIGS. 15 and 16 as appropriate and compared with each step in the conventional method for manufacturing a SiC wafer.

1 to 3 show the manufacturing process of a SiC wafer in one embodiment of the present invention.
The SiC wafer manufacturing method of the present invention includes an ingot forming step (step S11) in which a lump of crystal-grown single-crystal SiC is processed into a cylindrical ingot 10, and an ingot formed on the outer periphery to serve as a mark indicating the crystal orientation of the ingot 10. A crystal orientation forming step (step S12) of forming a notch in a part, a slicing step (step S13) of slicing the ingot 10 and processing it into a thin disk-shaped SiC wafer 20, and flattening the SiC wafer 20. The SiC wafer 20 is flattened by a flattening step (step S14), a marking forming step (step S15) for forming the marking portion 25, a chamfering step (step S16) for chamfering the outer peripheral portion 23, and heating under Si vapor pressure. The process includes an etching process for etching at least the back surface 22 (step S17), and a mirror processing process for making the main surface 21 of the SiC wafer 20 a mirror surface (step S18).

Hereinafter, the method for manufacturing a SiC wafer of the present invention will be explained in accordance with the process order of one embodiment shown in FIGS. 1 to 3.

<2-1> Ingot forming step The ingot forming step S11 is a step of processing a lump of crystal-grown single crystal SiC into a cylindrical ingot 10. This ingot 10 is usually processed so that the longitudinal direction of the cylinder is in the <0001> direction.

In the SiC wafer manufacturing method of the present invention, the process-affected layer 30 introduced in the ingot forming step S11 can be removed in combination with the subsequent etching step S17.

<2-2> Crystal orientation forming step The crystal orientation forming step S12 is a step of forming a notch in a part of the outer periphery of the ingot so as to serve as a mark indicating the crystal orientation of the ingot 10 formed in the ingot forming step S11. be. Examples of this notch include a plane parallel to the <11-20> direction (orientation flat 24), a groove (notch) provided at both ends in the <11-20> direction, and the like. It is formed so that the crystal orientation of single crystal SiC can be specified.

In the SiC wafer manufacturing method of the present invention, the process-affected layer 30 introduced in the crystal orientation shaping step S12 can be removed by combining it with the subsequent etching step S17.

<2-3> Slicing Step This is a step of slicing the ingot 10 to obtain a thin disk-shaped SiC wafer 20.
The slicing means in the slicing step S13 includes multi-wire saw cutting, which cuts the ingot 10 at predetermined intervals by reciprocating a plurality of wires, electric discharge machining, which cuts the ingot 10 by intermittently generating plasma discharge, and ingot cutting. Examples include cutting using a laser in which a laser is irradiated and focused during 10 to form a layer that serves as a base point for cutting.

In the SiC wafer manufacturing method of the present invention, the process-affected layer 30 introduced in this slicing step S13 can be removed by combining it with the subsequent etching step S17.

<2-4> Flattening process The flattening process S14 is a process of removing the undulations introduced into the SiC wafer 20 in the slicing process S13. The processing method, processing conditions, and properties of the abrasive grains used in the planarization step S14 will be explained below.

(1) Processing method Preferred processing methods for the flattening step S14 include fixed abrasive processing (grind grinding, etc.) in which processing is performed using a grindstone in which abrasive grains are embedded in a bond material, and fine abrasive grains are poured onto a surface plate. Free abrasive processing (such as lapping and polishing) is preferably used. Note that it is desirable that the abrasive grains be dropped as a mixed liquid (slurry) mixed with water and a dispersant. As the processing device used in this step, a general-purpose processing device used in conventional fixed abrasive processing and loose abrasive processing can be adopted. Further, a method may be used in which both sides are processed at the same time, or a method in which one side is processed.
Note that in this planarization step S14, formation of a satin surface on at least the back surface 22 of the SiC wafer 20 may be performed at the same time.

In the planarization step S14, it is preferable to process the SiC wafer 20 while crushing the abrasive grains. That is, when comparing the average abrasive grain diameter before processing in the flattening step S14 and the average abrasive grain diameter after processing, it is desirable that the abrasive grains be crushed and have a finer abrasive grain diameter after processing.

Here, the average abrasive grain diameter of the abrasive grains used in the flattening step S14 influences the processing speed. More specifically, when using large abrasive grains, a high machining speed can be achieved, and when using small abrasive grains, the machining speed becomes low.
Therefore, if the planarization step S14 is performed while crushing the abrasive grains, the surface of the SiC wafer 20 can be rapidly processed at a high processing speed at the start stage of the planarization step S14. On the other hand, as the processing progresses and the abrasive grains become smaller, the processing speed gradually decreases, and in the final stage of the process, delicate processing is realized on the surface of the SiC wafer 20, and the polishing surface introduced onto the surface of the SiC wafer is improved. It is possible to prevent roughness from becoming too large.
By performing the etching step S17 on the thus formed satin surface, a SiC wafer 20 having a matte surface suitable for a device manufacturing process can be manufactured.

Note that by using brittle abrasive grains, which will be described later, it is possible to carry out the invention in a form in which the flattening step S14 is performed while crushing the abrasive grains.
Further, under the processing conditions for the flattening step S14, which will be described later, it is possible to carry out the invention in a form in which the flattening step S14 is performed while crushing the abrasive grains.

In the embodiment in which the flattening step S14 is performed while crushing the abrasive grains, the average abrasive grain diameter of the abrasive grains before processing is preferably 20 μm or more, more preferably 40 μm or more.
By using abrasive grains having an average abrasive grain diameter in the above range in the state before processing, rapid processing at the start stage of the flattening step S14 becomes possible.

Further, in the method for manufacturing a SiC wafer of the present invention, at least at the start stage of the planarization step S14, abrasive grains having an average abrasive grain size of preferably 100 μm or less, more preferably 80 μm or less, and still more preferably 60 μm or less are used. It is preferable.
By setting the upper limit of the average abrasive grain diameter of the abrasive grains used in the above range at the start stage of the planarization step S14, the depth of the process-affected layer 30 introduced into the SiC wafer 20 by the planarization step S14 is reduced. be able to.

On the other hand, it is preferable to perform the flattening step S14 while crushing the abrasive grains so that the average abrasive grain size after processing is preferably less than 20 μm, more preferably 10 μm or less.
By performing the flattening step S14 while crushing the abrasive grains so that the average abrasive grains after processing fall within the above range, it is possible to reduce the roughness of the satin surface introduced into the SiC wafer 20, It is possible to realize a surface state of the SiC wafer 20 suitable for the etching step S17 described later.

In the SiC wafer manufacturing method of the present invention, it is preferable to use abrasive grains having an average abrasive grain size of preferably 0.5 μm or more, more preferably 1 μm or more, at least in the final stage of the planarization step S14.
At the start stage of the planarization step S14, the surface of the SiC wafer 20 can be efficiently processed by setting the lower limit of the average abrasive grain diameter of the abrasive grains to be used within the above range.

A specific example of the case where the flattening step S14 is performed while crushing the abrasive grains will be given below.
A flattening step S14 was carried out using B ₄ C abrasive grains with an average abrasive grain diameter of 40 μm under the conditions of a processing pressure of 150 g/cm ² and a processing time of 20 minutes, and an etching step S17 to be described later was performed. A pear-shaped surface equivalent to that of the wafer was formed. At this time, the average abrasive grain diameter after processing in the flattening step S14 was 10 μm or less. The average processing speed obtained by dividing the processing depth of 20 μm of the SiC wafer 20 by the processing time in this step was 1 μm/min.

(2) Properties of abrasive grains In the method for manufacturing a SiC wafer of the present invention, it is desirable to perform processing while crushing abrasive grains in the flattening step S14 under the loose abrasive method. That is, the abrasive grains used in the present invention preferably have such brittleness that they can be easily crushed by a loose abrasive method.

More specifically, it is preferable to use abrasive grains made of a material that satisfies the following brittleness conditions.
(Brittle condition) When the surface of a SiC wafer was simultaneously flattened on both sides using a free abrasive method using abrasive grains adjusted to an average abrasive grain size of 40 μm under a processing pressure of 150 g/ ^cm2 , the processing time was 20 After minutes, the average abrasive grain diameter becomes 20 μm or less.

In the flattening step S14, abrasive grains having a modified Mohs hardness of less than 15 are preferably used.
The modified Mohs hardness is a value indicating the hardness of a substance, where talc is 1 and diamond is 15. That is, in this step, abrasive grains having a hardness less than that of diamond are used. Specific examples of abrasive grain materials include boron carbide (B ₄ C), silicon carbide (SiC), alumina (Al ₂ O ₃ ), and the like. In addition to the above, any abrasive grains having a hardness of less than 15 on the modified Mohs hardness scale can of course be used.

In this way, by using abrasive grains with a hardness less than that of diamond, it is possible to suppress the roughness of the satin surface. That is, since diamond abrasive grains have extremely high hardness compared to the SiC wafer 20 to be processed, they are difficult to be crushed into small diameter pieces during the planarization step S14, and do not introduce scratches or the like deep into the surface of the SiC wafer 20. As a result, the pear surface becomes rough.

Further, it is desirable that the abrasive grains used in this step have a modified Mohs hardness of 13 or more. Specific examples of abrasive grain materials include boron carbide (B ₄ C) and silicon carbide (SiC).

In this way, by employing abrasive grains having a modified Mohs hardness of 13 or more, the SiC wafer 20 can be efficiently processed. That is, by employing a hardness equal to or higher than that of the SiC wafer 20 to be processed, efficient processing can be achieved.

Among them, it is desirable to use boron carbide (B ₄ C) abrasive grains in consideration of the cost and processing speed of the abrasive grains. That is, boron carbide (B ₄ C) abrasive grains can be obtained at low cost and can be processed at high speed and efficiently compared to silicon carbide abrasive grains.

In the description herein, the average abrasive particle diameter refers to the average particle diameter in accordance with Japanese Industrial Standards (JIS) R6001-2:2017.

(3) Processing conditions The processing pressure in free abrasive processing in the flattening step S14 is 100 to 300 g/cm ² , more preferably 150 to 200 g/cm ² .
Further, the rotation speed of the surface plate in this processing is 5 to 20 rpm, more preferably 10 to 15 rpm.
Furthermore, the processing time in this processing is 5 to 30 minutes, more preferably 5 to 15 minutes.

Further, the waviness introduced into the SiC wafer 20 in the slicing step S13 is usually 30 to 50 μm per side. In this planarization step S14, the SiC wafer 20 can be planarized at the same time, and processing is performed to a depth of 30 to 50 μm from the main surface 21 and back surface 22 of the SiC wafer 20 in order to remove waviness.

Moreover, although the case where abrasive grains with hardness less than diamond are used is shown as a preferable form of the flattening step S14, it is also possible to use diamond abrasive grains.
Furthermore, although free abrasive processing has been described as a preferable form of the flattening step S14, fixed abrasive processing may also be employed. The processing conditions are: using diamond abrasive grains with an average grain diameter of 3 to 30 μm, grinding wheel rotation speed of 1000 to 1500 rpm, cutting pitch of 1 to 3 μm, longitudinal feed of 150 to 250 m/min, and horizontal feed of 15 to 25 m/min. An example of the condition is a speed of 50 to 150 μm/hour.
Note that as the processing device, a general-purpose processing device used in conventional fixed abrasive processing can be adopted.

A preferred embodiment of the SiC wafer manufacturing method of the present invention includes a marking forming step S15 and a chamfering step S16 (FIGS. 1 and 3).

<2-5> Stamp forming process In the marking forming process S15, a laser is irradiated and focused on the back surface 22 (or main surface 21) of the SiC wafer 20, and the surface of the SiC wafer 20 is selectively removed to form a stamp. This is a step of forming the portion 25. As the marking forming means in the marking forming step S15, laser processing etc. can be exemplified. The stamp part 25 includes information (specifically, characters, symbols, barcodes, etc.) for identifying the SiC wafer 20.

<2-6> Chamfering Step The chamfering step S16 is a step in which the outer peripheral portion 23 of the SiC wafer 20 is chamfered by machining or the like. Examples of the chamfering means in the chamfering step S16 include grinding, tape polishing, and the like. This chamfer may be a round chamfer that forms a predetermined circular arc on the outer peripheral portion 23, or a chamfer that cuts diagonally at a predetermined angle.

Although the order of the flattening process S14, the stamp forming process S15, and the chamfering process S16 is not limited to that shown in FIGS. 1 and 3, the flattening process S14 can be performed before the stamp forming process S15 and the chamfering process S16. preferable.
In this way, by performing the flattening step S14 first to remove undulations on the wafer, it is possible to form the stamped portion 25 in the stamp forming step S15 and to determine the chamfering position in the chamfering step S16 with high precision. It is possible to improve the homogeneity of the wafer.

Although the order of the stamp forming step S15 and the chamfering step S16 is not particularly limited, the chamfering step S16 may be performed after the stamp forming step S15 as shown in FIGS. 1 and 3. By performing the marking forming step S15 before the chamfering step S16 in this way, the main surface 21 and the back surface 22 can be managed at an early stage, and problems in product management are less likely to occur.
Further, the marking forming step S15 may be performed after the chamfering step S16. In this case, variations in the wafer diameter can be suppressed, and the formation position of the stamped portion 25 can be determined with high accuracy.

<2-7> Etching process Etching process S17 is a process of removing the process-affected layer 30 introduced into the SiC wafer 20 in the previous process by etching the surface of the SiC wafer 20 by heating under Si vapor pressure. It is.
That is, the etching step S17 includes an ingot forming step S11 in which a lump of crystal-grown single crystal SiC is processed into a cylindrical ingot 10, and a crystal orientation step S11 in which a notch indicating the crystal orientation is formed in a part of the outer periphery of the ingot 10. A forming step S12, a slicing step S13 for slicing the ingot 10 to obtain a thin disc-shaped SiC wafer 20, a chamfering step S14 for chamfering the outer periphery 23 of the SiC wafer 20, and selecting the surface of the SiC wafer 20. It is preferable to perform this after the stamp forming step S15 in which the stamp portion 25 is formed by removing the stamp portion 25. As a result, it is possible to remove not only the main surface 21 and the back surface 22 but also the process-affected layer 30 introduced around the outer periphery 23, orientation flat 24, and engraved portion 25, contributing to higher quality of the SiC wafer 20. be able to.

On the other hand, as shown in FIGS. 15 and 16, in the rough grinding step S172 and finish grinding step S173 performed in the conventional SiC wafer manufacturing method, The processed damaged layer 30 could not be removed, which was a factor in degrading the quality of the SiC wafer 20.

The SiC wafer manufacturing method of the present invention performs an etching step S17 after the ingot forming step S11 to the marking forming step S15, thereby etching not only the main surface 21 and the back surface 22 but also the outer peripheral portion 23 and the orientation flat, which could not be processed up to now. 24. The process-affected layer 30 introduced around the engraved portion 25 can also be removed, which has a remarkable effect that can contribute to higher quality of the SiC wafer 20.

Furthermore, in the etching step S17 employed in the SiC wafer manufacturing method of the present invention, both sides can be etched at the same time, so that warping of the wafer due to the Twyman effect does not occur.

In addition, this etching step S17 heats and etches the matte surface introduced into the SiC wafer 20 in the flattening step S14 under Si vapor pressure, thereby creating a state favorable for the device manufacturing process (waviness, uneven shape, roughness, etc.). etc.).
The SiC wafer manufacturing method of the present invention combines the planarization step S14 and the etching step S17 to form a satin surface on the SiC wafer 20, which is a difficult-to-process material, without the process-affected layer 30, which is preferable for the device manufacturing process. It can have a remarkable effect.

In the etching step S17, it is desirable to etch one side of the SiC wafer 20 by preferably 0.5 μm or more, more preferably 1 μm or more.
By setting the etching amount within the above range, burrs and the like generated in the planarization step S14 are removed, thereby making it possible to form a more preferable satin surface.

Furthermore, the more the etching progresses in the etching step S17 (the greater the etching amount), the more the arithmetic mean roughness Ra and maximum height Rz of the satin surface can be reduced. That is, this etching step S17 includes a roughness adjustment step of adjusting the roughness of the satin surface by controlling the amount of etching. This has the remarkable effect of being able to form a satin surface with a desired roughness on at least the back surface 22 of the SiC wafer 20, which is a difficult-to-process material.
Specifically, in the etching step S17, one side of the SiC wafer 20 may be etched by preferably 3 μm or more, more preferably 6 μm or more, still more preferably 9 μm or more, still more preferably 10 μm or more, and even more preferably 12 μm or more.
By setting the etching amount within the above range, the arithmetic mean roughness Ra and maximum height Rz of the satin surface can be set within a preferable range.

Although the upper limit of the etching amount in the etching step S17 is not particularly limited, it can be set to preferably 100 μm or less, more preferably 80 μm or less per one side of the SiC wafer 20.

Further, from the viewpoint of reducing the amount of material loss, the etching amount in the etching step S17 is preferably 10 μm or less, more preferably 6 μm or less, and still more preferably 3 μm or less.

The etching step S17 will be explained in more detail below.
First, with reference to FIG. 4, an example of the configuration of an apparatus used in Si vapor pressure etching will be described. Next, the etching mechanism and etching conditions of Si vapor pressure etching will be explained.

(1) Apparatus Configuration In this step, as shown in FIG. 4, it is preferable to use an apparatus that includes a crucible 40 in which the SiC wafer 20 is housed, and a high-temperature vacuum furnace 50 that can heat the crucible 40.

The crucible 40 includes an upper container 41, a lower container 42 that can be fitted into the upper container 41, and a support base 43 that supports the SiC wafer 20. The wall surface (top surface, side surface) of the upper container 41 and the wall surface (side surface, bottom surface) of the lower container 42 are composed of a plurality of layers, and in order from the external side to the internal space side, a tantalum layer (Ta), a tantalum carbide layer, and a tantalum carbide layer are formed. (TaC and Ta ₂ C), and a tantalum silicide layer (such as TaSi ₂ or Ta ₅ Si ₃ ).

This tantalum silicide layer supplies Si to the internal space by heating. Further, since the crucible 40 includes a tantalum layer and a tantalum carbide layer, surrounding C vapor can be taken in. Thereby, a high-purity Si atmosphere can be created in the internal space during heating. Note that instead of providing the tantalum silicide layer, solid Si or the like may be placed in the internal space. In this case, solid Si sublimes during heating, making it possible to create a high-purity Si atmosphere in the internal space.

The support stand 43 can support the SiC wafer 20 so that both the main surface 21 and the back surface 22 are exposed.

The high-temperature vacuum furnace 50 includes a main heating chamber 51, a preheating chamber 52, and a moving stage 53 capable of moving the crucible 40 from the preheating chamber 52 to the main heating chamber 51. The main heating chamber 51 can heat the SiC wafer 20 to a temperature of 1000° C. or more and 2300° C. or less. The preheating chamber 52 is a space for preheating the SiC wafer 20 before heating it in the main heating chamber 51.

A vacuum forming valve 54, an inert gas injection valve 55, and a vacuum gauge 56 are connected to the main heating chamber 51. The vacuum forming valve 54 can adjust the degree of vacuum in the main heating chamber 51. The inert gas injection valve 55 can introduce an inert gas (for example, Ar gas) into the main heating chamber 51 and adjust the pressure thereof. The vacuum gauge 56 can measure the degree of vacuum within the main heating chamber 51.

A heater 57 is provided inside the main heating chamber 51 . Further, a heat reflecting metal plate is fixed to the side wall and ceiling of the main heating chamber 51 (not shown), and this heat reflecting metal plate directs the heat of the heater 57 toward the approximate center of the main heating chamber 51. It is designed to be reflective.
Thereby, the SiC wafer 20 can be heated strongly and evenly, and the temperature can be raised to a temperature of 1000° C. or higher and 2300° C. or lower. Note that as the heater 57, for example, a resistance heating type heater or a high frequency induction heating type heater can be used.

(2) Etching mechanism SiC wafer 20 is placed in crucible 40 and heated using high-temperature vacuum furnace 50 in a temperature range of 1500° C. to 2200° C. under high-purity Si vapor pressure. By heating the SiC wafer 20 under these conditions, the surface is etched. An outline of this etching is shown below in 1) to 4).

1) SiC(s) → Si(v) I+C(s)
2) Ta _x Si _y →Si(v)II+Ta _x' Si _y'
3) 2C(s)+Si(v)I+II→ _SiC2 (v)
4) C(s)+2Si(v)I+II→Si ₂ C(v)

Explanation of 1): When the SiC wafer 20 (SiC(s)) is heated under Si vapor pressure, Si atoms (Si(v)I) are desorbed from SiC by thermal decomposition.
Explanation of 2): Si vapor (Si(v) II) is supplied from the tantalum silicide layer (Ta _x Si _y ).
Explanation of 3) and 4): C (C(s)) remaining after Si atoms (Si(v)I) are desorbed by thermal decomposition is converted into Si vapor (Si(v)I and Si(v) II), it becomes Si ₂ C or SiC ₂ and sublimates.
The reactions 1) to 4) above are carried out continuously, and as a result, etching progresses.

(3) Etching conditions The heating temperature in Si vapor pressure etching is 1500 to 2200°C, more preferably 1800 to 2000°C.
The processing speed (etching speed) in this processing is 0.1 to 10 μm/min.
The vacuum degree of the main heating chamber 51 in the main processing is 10 ^-5 to 10 Pa, more preferably 10 ^-3 to 1 Pa.
The inert gas used in this process is Ar, and the degree of vacuum is adjusted by introducing this inert gas.
The processing time in this processing is not particularly limited, and any time that matches the desired amount of etching can be adopted.

Note that a final grinding step S173 or a final polishing step may be included before this etching step S17. By performing the final grinding step S173 and the final polishing step before the etching step S17 in this way, the flatness of the SiC wafer 20 after etching can be improved.

<2-8> Mirror polishing step The mirror polishing step S18 can be exemplified by chemical mechanical polishing (CMP) processing in which polishing is performed using both the mechanical action of a polishing pad and the chemical action of a slurry. This chemical-mechanical polishing process is a process of processing the main surface 21 of the SiC wafer 20 into a mirror surface that is a preferable surface state for the device manufacturing process (as shown by the two-dot chain line in FIG. 3).

For this processing, a general-purpose processing device used in conventional chemical mechanical polishing processing can be employed, and processing conditions can be set within the range normally performed by those skilled in the art.

<1> Manufacture of SiC wafers SiC wafers of Example 1 and Comparative Example 1 were manufactured by the following method.

<Example 1>
(slicing process)
A single crystal SiC ingot was sliced using a slurry containing diamond abrasive grains with an average abrasive grain diameter of 10 μm to obtain SiC wafers with a diameter of 6 inches.

(Flattening process)
This SiC wafer was processed using a free abrasive method using a slurry containing B ₄ C abrasive grains with an average abrasive grain diameter of 40 μm at a processing pressure of 150 g/cm ² , a surface plate rotation speed of 15 rpm, and a head rotation speed of 5 rpm. The flattening process was performed for 20 minutes and at a processing speed of approximately 1.0 μm/min.
At this time, the average abrasive grain diameter of the B ₄ C abrasive grains at the end of the flattening process was 10 μm.

(etching process)
After the planarization process, the SiC wafer was etched with an etching amount of 3 μm (processing time of about 3 min, processing speed of 1 μm/min), an etching amount of 6 μm (processing time of about 6 min, processing speed of 1 μm/min), and an etching amount of 9 μm (processing time of about 9 min). , processing speed 1 μm/min). The thickness of the SiC wafer after the etching process was 350 μm.

<Example 2>
(slicing process)
A slicing process was performed under the same conditions as in Example 1 to obtain a 6-inch diameter SiC wafer.
(Flattening process)
This SiC wafer was flattened under the following conditions using a fixed abrasive method using a grindstone (Vitriphite Bond) containing diamond abrasive grains with an average abrasive grain diameter of 30 μm.
Grinding wheel rotation speed: 1250rpm
Cutting pitch: 2μm
Front-rear feed: 190 m/min Left-right feed: 21 m/min Processing speed: 100 um/hour (etching process)
Si vapor pressure etching was performed under the same conditions as in Example 1. The thickness of the SiC wafer after the etching process was 350 μm.

<2> Observation and Evaluation <2-1> Observation and Evaluation of Satin Surface The back surfaces of the SiC wafers of Examples 1 and 2 were observed using a white interference microscope. The results are shown in FIGS. 5 and 6.
FIG. 5 is a white interference microscope image (95 μm×75 μm) of Example 1, with FIG. 5(a) showing the image before the etching process, and FIG. 5(b) showing the image after the etching process (etching amount: 3 μm).
FIG. 6 is a white interference microscope image (95 μm×75 μm) of Example 2, where FIG. 6(a) shows the image before the etching process, and FIG. 6(b) shows the image after the etching process (etching amount: 3 μm).

As shown in FIGS. 5 and 6, a satin surface is formed on the back surfaces of the SiC wafers of Examples 1 and 2. Specifically, as shown in FIG. 5, a satin surface is formed on the back surface of the SiC wafer of Example 1. Further, as shown in FIG. 6, a striped surface is formed on the back surface of the SiC wafer of Example 2. As can be seen from FIGS. 5 and 6, after etching both the matte surface and the striped surface, fine burrs are removed and the surface structure has smooth edges.

Table 1 summarizes the arithmetic mean roughness Ra and maximum height Rz with respect to the etching amount in Examples 1 and 2.

As shown in Table 1, it can be confirmed that the arithmetic mean roughness Ra and the maximum height Rz tend to decrease as the etching amount increases. Particularly in Example 1, it can be seen that the arithmetic mean roughness Ra and the maximum height Rz tend to decrease.
This result shows that by adjusting the etching amount, a remarkable effect can be obtained in that the roughness of the satin surface of the SiC wafer, which is a difficult-to-process material, can be controlled.

The satin surface of the SiC wafers of Examples 1 and 2 does not slip easily during transportation or within the apparatus, and is easy to peel off from an electrostatic chuck type sample stage. In addition, particles are less likely to adhere to the wafer, and it is possible to set the roughness of the satin surface to such a degree that problems such as deterioration of the flatness of the wafer do not occur when chucked onto the sample stage.

If the main surface of the SiC wafer of Example 1 is made into a mirror surface by a known method, it is possible to obtain a SiC wafer that can be detected by an optical sensor and is advantageous in the device manufacturing process.

<2-2> Reflectance and transmittance of SiC wafer The reflectance and external transmittance of the SiC wafer of Example 1 were measured using a spectrophotometer (U-4000 type spectrophotometer). FIG. 7 shows the results of measuring the reflectance, and FIG. 8 shows the results of measuring the external transmittance. Note that, as a comparative example, the reflectance and external transmittance of a SiC wafer whose main surface and back surface are mirror-finished are shown in FIGS. 7 and 8.

FIG. 7(a) shows the results of measuring the reflectance of an electromagnetic wave having a wavelength of 300 to 1500 nm incident on the main surface side of a SiC wafer and reflected toward the main surface side. It can be seen that the reflectance of the comparative example in which both sides are mirror surfaces varies depending on the wavelength in the visible light region, and the reflectance varies between 19% and 27%. On the other hand, the reflectance of Example 1, whose back surface is a matte surface, is lower than that of the comparative example in all wavelength regions, and the difference between wavelengths in the visible light region is small, with a reflectance of 19 to 23%. It can be seen that there is a shift between the two.

FIG. 7(b) shows the results of measuring the reflectance of an electromagnetic wave having a wavelength of 300 to 1500 nm incident on the back side of the SiC wafer and reflected back to the back side. In the results on the main surface side of Example 1 in FIG. 7(a), a reflectance of 19% or more was measured in the visible light wavelength region, whereas in the results on the back surface side in FIG. 7(b), A reflectance of 3% or less has been measured in the visible light wavelength region.
In this way, in Example 1, the main surface and the back surface have a large difference in reflectance, making it easy to identify the main surface and the back surface.

FIG. 8 shows the results of measuring the transmittance of an electromagnetic wave having a wavelength of 300 to 1500 nm incident on the main surface of the SiC wafer and passing through the SiC wafer. The transmittance of Example 1 whose back surface is a matte surface is lower than that of the SiC wafer whose both surfaces are mirror-finished in all wavelength ranges.
In particular, in the results of Example 1, a transmittance of 25% or less was measured in all wavelength regions. Therefore, in Example 1 in which the satin surface is formed on the back surface, transmission of visible light can be suppressed, and the detection rate of the optical sensor can be improved.

<2-3> Measurement of process-affected layer by SEM-EBSD The stress existing in the SiC wafers of Example 1 and Example 2 before and after the etching process was observed by SEM-EBSD. The cross sections of the SiC wafers of Examples 1 and 2 were cleaved and measured using a scanning electron microscope under the following conditions.
SEM device: Zeiss Merline
EBSD analysis: OIM crystal orientation analyzer manufactured by TSL Solutions Acceleration voltage: 15kV
Probe current: 15nA
Step size: 200nm
Reference point R depth: 20~25μm

As shown in FIGS. 7(a) and 8(a), lattice distortion was observed in the SiC wafers of Example 1 and Example 2 before the etching process. This is lattice distortion introduced by a planarization process or the like. Note that compressive stress was observed in both cases.
On the other hand, as shown in FIGS. 7(b) and 8(b), after the etching process, the lattice distortion of the subsurface crystal lattice with respect to the reference crystal lattice was 0.001% or less, and Example 1 And no lattice distortion was observed in the SiC wafer of Example 2.
This result shows that almost no stress is generated within the SiC wafer 20, and that the strained layer, which is difficult to remove, among the process-affected layers 30 has been removed. In other words, this shows that the stress introduced into the SiC wafer by the planarization process or the like can be removed by the etching process.

<2-4> Measurement of process-affected layer using TEM The cross sections of the SiC wafers of Examples 1 and 2 were observed using a transmission electron microscope (TEM). The results are shown in FIGS. 11 and 12.
FIG. 11 is a cross-sectional TEM image (50 nm x 50 nm) of Example 1, in which (a) shows the (0001) side with an etching amount of 3 μm, (b) shows the (000-1) side with an etching amount of 3 μm, (c) shows the (0001) side with an etching amount of 6 μm, and (d) shows the (000-1) side with an etching amount of 6 μm.
FIG. 12 is a cross-sectional TEM image (50 nm x 50 nm) of Example 2, in which (a) shows the (0001) side with an etching amount of 3 μm, (b) shows the (000-1) side with an etching amount of 3 μm, (c) shows the (0001) side with an etching amount of 6 μm, and (d) shows the (000-1) side with an etching amount of 6 μm.

Based on this cross-sectional TEM image, the presence or absence of an altered layer and its depth were evaluated by the following method.
[Evaluation method] Enlarge the cross-sectional TEM image to a magnification that allows confirmation of a process-affected layer of several nanometers, compare the contrast between the surface side and the bulk side, and if there is a contrast difference, evaluate it as ``there is a process-affected layer.'' If there is no contrast difference, it is evaluated that there is no process-affected layer.
If there was a "process-affected layer," the depth was measured based on a cross-sectional TEM image.

As a result, in the SiC wafer of Example 1, no process-affected layer was observed neither when the etching amount was 3 μm nor when the etching amount was 6 μm.
On the other hand, in the SiC wafer of Example 2, when the etching amount was 3 μm, a 10 nm process-affected layer was observed on the (0001) side, and a 43 nm process-affected layer was observed on the (000-1) side. However, when the etching amount was 6 μm, no process-affected layer was observed.

The above measurement of the process-affected layer by SEM-EBSD and TEM revealed that there is virtually no process-affected layer in Examples 1 and 2 by applying Si vapor pressure etching. Ta.

If chemical-mechanical polishing is applied to SiC wafers from which the process-affected layer has been removed, such as the SiC wafers of Examples 1 and 2, there will be no internal cracks (scars) or lattice distortion, and the high A high-quality SiC wafer with excellent flatness can be obtained.

10 Ingot 20 SiC wafer 30 Process-affected layer 40 Crucible 50 High-temperature vacuum furnace

Claims (5)

A planarization step of planarizing a SiC wafer;
A method for manufacturing a SiC wafer, comprising, after the planarization step, an etching step of etching the main surface and the back surface, which is a matte surface, of the SiC wafer by heating under Si vapor pressure. 2. The method of manufacturing a SiC wafer according to claim 1 , wherein the processing temperature of the etching step is 1500° C. or higher. 3. The method of manufacturing a SiC wafer according to claim 1 , wherein the SiC wafer has a doping concentration of 10 ¹⁹ cm ^-3 or more . 4. The method for manufacturing a SiC wafer according to claim 1 , further comprising a mirror polishing step of mirror polishing the main surface of the SiC wafer after the etching step. Before the etching step,
an ingot forming step of processing a lump of crystal-grown single crystal SiC into a cylindrical ingot;
a crystal orientation forming step of forming a notch indicating the crystal orientation in a part of the outer periphery of the ingot;
a slicing step of slicing the ingot to obtain a thin disk-shaped SiC wafer;
a stamp forming step of selectively removing the SiC wafer surface to form a stamp portion;
5. The method for manufacturing a SiC wafer according to claim 1 , further comprising a chamfering step of chamfering an outer peripheral portion of the SiC wafer.

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