JP2009100216A - Solid-state imaging apparatus and processing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging apparatus by which a wide dynamic range is obtained without lowering a frame rate. <P>SOLUTION: The solid-state imaging apparatus includes: a photoelectric conversion element which generates an electric charge by photoelectric conversion; a reading means for reading the signal of the generated electric charge; and a polarity imparting means for imparting polarity to the read signal so that a signal when an amount of the generated electric charge is less than a reference value and a signal when the amount is more than the reference signal have polarities reverse to each other. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and a processing method thereof.

  The following proposals have been made as methods for obtaining image information with a wide dynamic range.

  In Patent Document 1 below, the shutter speed (charge accumulation time of the photodiode) is changed, and a short time when the photodiode does not saturate and a sufficiently long time are taken, and each photographed image is synthesized. A technique for obtaining image information with a wide dynamic range is disclosed.

  Patent Document 2 below discloses a technique for storing photoelectric charge overflowing from a photodiode in a floating diffusion or a storage capacitor provided separately via the floating diffusion. In addition to reading out the signal of the photodiode, image information with a wide dynamic range is obtained by separately reading out the photoelectric charge that is saturated and overflows.

  Further, in Patent Document 3 below, a signal accumulated in a photodiode is converted into a linear photoelectric conversion signal and a logarithmic photoelectric conversion signal, a signal proportional to the light intensity and a signal proportional to the logarithm. And a technique for reading out each of them. Thereby, image information with a wide dynamic range is obtained.

  In Patent Document 2, it is determined whether the output is less than or equal to the saturation of the photodiode in the chip, and “signal accumulated in the photodiode” and “signal accumulated in the photodiode” + “overflow from the photodiode” It is also disclosed that the “output signal” is switched and output.

JP 2004-159274 A JP 2005-328493 A JP 2004-214772 A

  However, the techniques disclosed in Patent Documents 1 to 3 have a problem in that the frame rate decreases because the number of readings increases in order to obtain image information with a wide dynamic range.

  Also, when two signals are added and output by calculation within the chip, there are limits to the calculation of each gain setting, compression ratio, etc., and it is difficult to set for obtaining a good image. There was a problem.

  An object of the present invention is to provide a solid-state imaging device capable of obtaining a wide dynamic range without reducing the frame rate and a processing method thereof.

  The solid-state imaging device according to the present invention includes a photoelectric conversion element that generates a charge by photoelectric conversion, a reading unit that reads a signal of the generated charge, a signal when the generated charge amount is less than a reference value, and a reference value Polarity imparting means for imparting polarity to the read-out signal so that the signals when the number of the signals is larger than that of the signals is opposite.

  Further, the processing method of the solid-state imaging device according to the present invention is a processing method of the solid-state imaging device having a photoelectric conversion element that generates a charge by photoelectric conversion, the reading step of reading the generated charge signal, and the generation A polarity imparting step for imparting a polarity to the read signal so that a signal when the amount of charges read is less than a reference value and a signal when the charge amount is greater than a reference value are opposite to each other. And

  By giving polarity to the signal, only one signal output is required, so that the frame rate can be increased while ensuring image information with a wide dynamic range.

Embodiments of the present invention will be described below with reference to the drawings.
(First embodiment)
FIG. 1 is a waveform and timing diagram of an output terminal of the solid-state imaging device according to the first embodiment of the present invention. OUTS and OUTN in FIG. 1 are outputs of the solid-state imaging device, and are a positive output terminal and a negative output terminal for differential output.

  Both the OUTS and OUTN terminals output the reference level at the beginning of the output. In this embodiment, after the first bit is output, the reference level is output again before the second bit signal is output. . In general, the reference level is almost equal to the output level in the dark if the offset level of the sensor dark current component, circuit fixed pattern noise component, random noise component, etc. is negligibly small.

  The case where the light level voltage increases with respect to the dark level is positive, and the case where the light level voltage decreases with respect to the dark level is negative. For example, in the OUTS terminal, the first bit in the figure is positive, while the second bit shows negative polarity. A state in which the positive and negative polarities of the output are switched in this way is called an inverted output polarity.

  ADCLK is a sampling clock for A / D conversion of the outputs OUTS and OUTN, and the outputs OUTS and OUTN take in analog data at the rising timing of ADCLK and convert it into digital data.

  PFLAG is a clock for controlling the timing for determining the polarity of OUTS and OUTN, and a pulse in which the identification result is described at high level / low level is MODE.

  In the first bit, the third bit, and the fourth bit, when the light intensity increases, the voltage of the OUTS output increases (positive polarity), and the voltage of the OUTN terminal output decreases (negative polarity).

  In the second bit and the fifth bit, the polarity of the output terminal is inverted, and when the light becomes stronger, the voltage at the OUTS terminal decreases (negative polarity), and the voltage at the OUTS output increases (positive polarity).

  Depending on whether the polarity of the output terminal is OUTS or OUTN, it is possible to determine whether the type of signal readout is binary. Therefore, for example, it is possible to identify whether the luminance is within a range where the photodiode is saturated or whether the photodiode is saturated by the polarity of the output terminal.

  Therefore, in FIG. 1, since the amount of light is more than the saturation of the photodiode at the second and fifth bits, the order of the amount of light is as follows: “3rd bit <1st bit <4th bit <2nd bit < 5th bit ".

  In this way, it is determined whether the required signal information and the photodiode are saturated without reading the photodiode signal and the wide dynamic range signal when the photodiode is saturated twice. Information can be obtained. Therefore, it is possible to obtain image information with a high dynamic range while preventing a decrease in the frame rate. At this time, such a reading method may be performed on all the pixels, or an operation of outputting one of the two signals may be performed on some pixels. The effect can be obtained without applying the readout method of the present embodiment to all pixels. The same applies to other embodiments.

  A wide dynamic range is realized by changing the data processing based on the saturation and non-saturation information determined by the output polarity in this way. For example, for an inverted bit, a processing method is possible in which a gain is applied to the signal and then added to an output corresponding to the saturation level of the photodiode.

  Note that the timing for determining saturation or non-saturation in PFLAG may be any timing within an output period of 1 bit. However, as in the present embodiment, it is particularly efficient to determine the polarity before the timing of A / D conversion sampling and then perform A / D conversion.

  This is because the determination result is known in advance and the determination result is known, so that the A / D conversion can be performed after the storage destination of the digital data after the A / D conversion is already determined, and the data processing becomes smooth. is there. The polarity determination unit 130 in FIG. 2 controls A / D conversion in accordance with the polarity determination result.

  FIG. 2 is an equivalent circuit diagram of the solid-state imaging device according to the first embodiment of the present invention, and is an example of an equivalent circuit effective for realizing the output form of FIG. FIG. 3 is an operation timing chart for driving the equivalent circuit of FIG.

  Reference numeral 101 denotes a photodiode. Reference numeral 102 denotes a transfer MOSFET. Reference numeral 103 denotes a reset switch. Reference numeral 104 denotes an amplification MOSFET. Reference numeral 105 denotes a select switch. Reference numeral 108 denotes a comparator. Reference numeral 109 denotes a constant current source. Reference numeral 110 denotes a latch circuit. Reference numeral 111 denotes an AND logic circuit. Reference numeral 112 denotes an AND logic circuit. Reference numeral 113 denotes a switch MOSFET. Reference numeral 114 denotes a switch MOSFET. Reference numeral 115 denotes a storage capacitor. Reference numeral 116 denotes a storage capacitor. Reference numeral 117 denotes a switch MOSFET. Reference numeral 118 denotes a switch MOSFET. 120 is a differential amplifier.

  For pixels in which the light level in the storage period A does not exceed the saturation level, the dark level in the storage period A is stored in the storage capacitor 115 and the light level is stored in the storage capacitor 116. For pixels in which the light level in the storage period A exceeds the saturation level, the dark level and the light level in the storage period B are switched to hold the light level in the storage capacitor 115 and the dark level in the storage capacitor 116. Then, the data is read through the differential amplifier 120. A method for realizing the waveform of the output terminal shown in FIG. 1 will be described in detail with reference to the circuit diagram of FIG. 2 and the operation timing chart of FIG.

  FIG. 2 shows two pixels extracted from a plurality of pixels arranged in the solid-state imaging device. FIG. 3 is a timing chart showing the drive pulses. The MOS transistors in FIG. 2 are all N-type MOS transistors and are turned on when the gate electrode becomes high level when used as a switch.

  In FIG. 2, pix1 and pix2 are unit pixels. Pix1 and pix2 include a photodiode 101 that is a photoelectric conversion element, an amplification MOSFET 104 that is an amplification unit that amplifies a signal generated by the photodiode 101, and a reset switch 103 that resets an input of the amplification MOSFET 104 to a predetermined voltage. Further, a pixel transfer switch 102 that controls conduction between the photodiode 101 and the gate electrode of the amplification MOSFET 104 and a select switch 105 that controls conduction between the vertical common output line Vline1 and the output of the amplification MOSFET 104 are provided.

  It is assumed that a predetermined exposure time A has elapsed prior to the read operation, and photocharges are accumulated in the photodiode 101. First, the pixel reset pulse PRES changes from the high level to the low level, and the reset of the gate electrode of the amplification MOSFET 104 is released (t0).

  If the voltage of the gate electrode is in the pentode region when the pixel reset switch 103 is on, the voltage is reduced by the threshold value from the gate high level of the pixel reset switch 103. VDD voltage. When the pixel reset switch 103 is turned off, the voltage is slightly lower than these voltages. This is due to inflow of inversion layer charges formed in a state where the pixel reset switch 103 is turned on or feedthrough through a parasitic capacitance between the gate and the source of the pixel reset switch 103.

  Reading is performed with the voltage after the reset of the gate voltage is canceled as the noise level (t1). The amplification MOSFET 104 performs a source follower operation, and the output of the source follower appears on the output line Vline1 as a dark output.

  At this time, the power supply voltage VDD level is input to the + input terminal VSAT of the comparator 108, and the dark output on Vline is a voltage lower than the VDD level, so the output of the comparator 108 is at a high level. Therefore, the gate voltage of the switch MOSFET 113 is controlled at the PTN timing via the AND logic circuit 111 and the latch circuit 110.

  Therefore, at the moment when PTN becomes low level, the voltage of Vline corresponding to the dark output is sampled in the storage capacitor 115. In this embodiment, the + input terminal of the comparator is set to the VDD level. However, if the voltage is sufficiently higher than the dark output, the same effect can be obtained even if the voltage is not VDD.

  Subsequently, in the pixel, the signal PTX becomes high level, the pixel transfer switch 102 is turned on for a certain period (t2), and the photocharge accumulated in the photodiode 101 is transferred to the gate electrode of the amplification MOSFET 104. As a result, the gate potential drops from the dark voltage by Q / CFD, where Q is the transferred charge and CFD is the capacitance of the gate portion. Corresponding to this, a light-time output appears on the output line Vline.

  Similar to the sampling of the dark output, the + input terminal VSAT of the comparator 108 is at the VDD level. Since the voltage of Vline is lower than the VDD level, the output of the comparator 108 is at a high level, and the gate voltage of the switch MOSFET 114 is controlled at the timing of PTS via the AND logic circuit 112 and the latch circuit 110.

  Therefore, at the instant (t 3) when PTS becomes low level, the voltage of Vline corresponding to the light-time output including the variation of the source follower of the amplification transistor 104 and the reset variation of the reset MOS transistor 103 is sampled in the storage capacitor 116.

  Through the above operation, the storage capacitor 115 holds the dark level during the predetermined accumulation time A, and the storage capacitor 116 holds the light level during the accumulation time A.

  Here, the voltage of the VSAT terminal is changed from the VDD level to the pixel saturation level VSAT (t4). This VSAT voltage corresponds to the signal level that appears on Vline through the output of the source follower operation of the amplification transistor 104 when the photodiode reads the saturated charge. The comparator 108 outputs a high level for pixels whose Vline voltage is lower than the VSAT voltage, and outputs a low level for pixels higher than the VSAT voltage. Here, a pixel having a Vline voltage lower than the VSAT voltage is a pixel in which the photodiode is saturated, and a pixel having a voltage higher than the VSAT voltage is a pixel in which the photodiode has not reached the saturation level.

  Next, PLAT becomes high level, and the output level of the comparator 108 at this time is held at the output of the latch circuit 110. Therefore, the output level of the latch circuit 110 does not change even if the output level of Vline changes thereafter and the relationship between VSAT and Vline is reversed.

  Therefore, in the next reading, only the pixels for which the photodiode 101 has reached the saturation level are overwritten by the PTS and PTN, and the other pixels that have not reached the saturation level are held without being overwritten by the PTS and PTN pulses. (T5).

  Thereafter, the photodiode 101 performs a reset operation by setting both PRES and PTX to high level, and the next accumulation starts from the fall of PTX (t6). Thereafter, accumulation shorter than the accumulation time A (accumulation period B) is performed, and the charge accumulated in the accumulation time B is read out in the same manner as the operation and timing of the previous accumulation period A.

  However, at this time, when reading the voltage corresponding to the dark time, the PTS is held at the high level by setting the PTS to the high level (t7), and when reading the voltage corresponding to the bright time, the PTN is held at the high level. The capacity 115 is held (t8). Therefore, the timing of the gate voltage control pulses PTS and PTN of the switch MOSFETs 113 and 114 is reversed from that in the previous storage period A.

  By performing the above operation, the dark level at the storage time A is stored in the storage capacitor 115 and the bright level is stored in the storage capacitor 116 for the pixels whose light level during the storage time A does not exceed the saturation level. . For pixels exceeding the saturation level, the bright level of the accumulation time B is held in the holding capacitor 115 and the dark level is held in the holding capacitor 116. The optical response component is acquired by calculating the difference between the signals stored in the storage capacitors 115 and 116.

  As a result of performing this difference processing, pixels whose light level during the accumulation time A does not exceed the saturation level are output from the OUTS terminal with a positive polarity in which the voltage rises above the reference level when exposed to light. On the contrary, when light is applied from the OUTN terminal, the voltage is output with a negative polarity in which the voltage is lower than the reference level. On the other hand, for pixels exceeding saturation, the signal level in the accumulation period B is read from the output signal OUTS terminal with a negative polarity, and OUTN is read with a positive polarity.

  The polarity determination unit 130 can determine the polarity of the OUTS and OUTN and identify whether the output is the output of the storage period A or the output of the storage period B. Accordingly, it is not necessary to read out all the two outputs of the accumulation period A and the accumulation period B, and the number of readings does not increase twice, so that image information with a wide dynamic range can be obtained while preventing a decrease in the frame rate. .

  In the present embodiment, the timings of PTS and PTN are controlled in order to invert and output the polarity of the signals of the accumulation time A and the accumulation period B. At this time, the same effect can be obtained by replacing the vertical output lines CHS and CHN or replacing OUTS and OUTN instead of replacing PTS and PTN.

  Further, even if a signal is amplified or clamped before a signal is held in the holding capacitor by placing a clamp circuit or an amplifier circuit between the Vline and the switches 113 and 114, there is no substitute for the effect of this embodiment. .

  Further, in this embodiment, the saturation level of the photodiode is determined by comparing VSAT and Vline. At this time, it is not necessary to determine the saturation of the photodiode using this Vline. As a result, if the saturation level of the photodiode can be determined, the same effect can be obtained even if the voltages at other nodes are used for comparison.

(Second Embodiment)
FIG. 4 is a waveform and timing diagram of the output terminal of the solid-state imaging device according to the second embodiment of the present invention. OUT in FIG. 4 is an output of the solid-state imaging device, and shows an output waveform and timing diagram in which the output of the solid-state imaging device in FIG. 1 is replaced with a single-ended output.

  Whether the photodiode is saturated or not is determined by comparing the reset level and the output level, or comparing the reference level and the output level, even in a single-ended output form as shown in FIG. The same effect can be obtained. The comparison between the reset level and the output level is a comparison of the OUT level at the timings A and B in FIG. The comparison between the reference level and the output level is a comparison between the VREF level and the OUT level at the timing B.

  FIG. 5 is an example of an equivalent circuit of a solid-state imaging device effective for realizing the output form of FIG. In FIG. 5, the same parts as those in FIG. Further, the detailed description of the equivalent circuit of FIG. 5 is the same as that of the first embodiment, and thus the detailed description is omitted. 5 is the same as that shown in FIG. 3, and the drawing is the same as that shown in FIG.

  The output format of FIG. 5 includes a differential amplifier 121 that outputs a differential output signal of CHS and CHN on the basis of the reference voltage VREF. As in the first embodiment, for pixels whose light level during the storage time A does not exceed the saturation level, the dark level during the storage time A is stored in the storage capacitor 115 and the light level is stored in the storage capacitor 116. Yes. For pixels exceeding the saturation level, the bright level of the accumulation time B is held in the holding capacitor 115 and the dark level is held in the holding capacitor 116. Thereafter, the optical response component is obtained by calculating a difference between the signals stored in the storage capacitors 115 and 116.

  As a result of performing this difference processing, the pixels whose light level during the accumulation time A does not exceed the saturation level are output from the OUT terminal with a positive polarity in which the voltage rises above the reference level when exposed to light. On the contrary, for the pixel exceeding saturation, the signal level in the accumulation period B is output from the output signal OUT terminal with a negative polarity in which the voltage is lower than the reference level.

  The polarity determination unit 130 can determine the polarity of the OUT level with respect to the VREF level and identify whether the output is the output of the storage period A or the output of the storage period B. Accordingly, it is not necessary to read out all the two outputs of the accumulation period A and the accumulation period B, and the number of readings does not increase twice, so that image information with a wide dynamic range can be obtained while preventing a decrease in the frame rate. .

(Third embodiment)
FIG. 6 is an equivalent circuit diagram of the solid-state imaging device according to the third embodiment of the present invention, and is an example of an effective equivalent circuit different from the first embodiment in order to realize the output form of FIG. . It is possible to realize the same output form as in FIG. When this embodiment is used, the polarity of the low illuminance signal is changed from the signal obtained by reading the photocharge accumulated in the light receiving element and the signal obtained by reading the photocharge leaking from the light receiving element to the high illuminance signal. Can be read out.

  In the present embodiment, the description is given for realizing the differential output format of FIG. 1, but the same method can be applied to the output configuration of the equivalent circuit of the single-ended output format shown in FIG. 4, but the second embodiment. Detailed description will be omitted because it is a combination of the above and the present embodiment.

  Hereinafter, the operation for performing the reading with the polarity reversed will be described in detail with reference to the equivalent circuit diagram of FIG. 6 and the drive timing diagram of FIG.

  FIG. 6 shows two pixels extracted from a plurality of pixels. FIG. 7 is a timing chart showing the drive pulses. 6 and 7, the same parts as those in FIGS.

  The unit pixels pix1 and pix2 in FIG. 6 have a configuration in which a storage capacitor 122 and a connection switch 121 that controls conduction between the storage capacitor 122 and the gate electrode of the amplification MOSFET 104 are added to FIG. The control pulse of the connection switch 121 is PCSSEL.

  For pixels in which the light level during the accumulation period does not exceed the saturation level, the dark level during the accumulation period is held in the storage capacitor 115 and the light level is held in the storage capacitor 116. For the pixel exceeding the saturation level, the storage capacitor is replaced, the charge overflowed from the photodiode is stored in the storage capacitor 115, the dark level at that time is stored in the storage capacitor 116, and is read through the differential amplifier 120. In this way, it is possible to read out the output of the photodiode and reading out the overflowing charge from the photodiode by inverting the polarity of the output.

  It is assumed that a predetermined exposure time has passed before the reading operation, and photocharge is accumulated in the photodiode 101. At this time, the selection switch 121 is in a conductive state, and the reset switch 103 is in a non-conductive state. Therefore, the amount of charge exceeding the amount of charge that can be stored in the photodiode is stored in the sum (CFD + CS) of the gate capacitance CFD and holding capacitance 122 (hereinafter referred to as CS) of the amplification MOSFET via the transfer switch 102. (T0).

  First, PCSSEL is set to low level, the switch 121 is turned off to disconnect the capacitors CFD and CS, then PRES is set to high level for a certain period, and the reset switch 103 is turned on (t1). The subsequent operation of sampling the dark level of the photodiode in the holding capacitor 115 and the bright level in the holding capacitor 116 is the same as in the second embodiment, and thus the description thereof is omitted (t2 to t3).

  The operations of the comparator 108 and the latch circuit 110 are the same as those in the second embodiment, and the storage capacitors 115 and 116 are overwritten only for pixels exceeding the saturation level. The other pixels that have not reached the saturation level are not overwritten by the next PTS and PTN pulses and are retained.

  Thereafter, the charge overflowing the photodiode is read. First, when the reset MOSFET 103 is turned on / off, the gate electrode of the amplification MOSFET 104 is reset and the reset is released (t4). At this time, the voltage corresponding to the dark time is held in the parasitic capacitance of the pixel including the gate electrode. The amplification MOSFET 104 performs a source follower operation, and the output of the source follower appears on the output line Vline as a dark output.

  By setting the voltage corresponding to this dark time to a high level for a certain period of time, only the pixel in which the photodiode 101 reaches the saturation level is held in the holding capacitor 116 (t5).

  Subsequently, in the pixel, the conduction switch 121 between the holding capacitor 122 and the capacitor CFD is turned on for a certain period, and two capacitances, that is, the photoelectric charge overflowing from the photodiode held in the holding capacitor 122 and the capacitance CFD of the gate electrode of the amplification MOSFET 104. The capacity is divided between them (t6). As a result, the gate potential drops from the dark voltage by Qcs / (CFD + CS), where Qcs is the retained charge. The amplification MOSFET 104 performs a source follower operation, and the output of the source follower appears as a second signal component held in the holding capacitor 122 on the output line Vline.

  By setting the voltage corresponding to the second signal component to a high level for a certain period of time, only the pixel in which the photodiode 101 reaches the saturation level is held in the holding capacitor 115 (t7).

  At this time, the voltage corresponding to the dark level is held in the holding capacitor 116, and the overflow charge corresponding to the bright level is read in the holding capacitor 115. For this reason, the PTS and PTN timings are reversed from the signal components and dark level components accumulated in the photodiode, and the output polarity is reversed.

  By performing the above operation, the dark level is held in the holding capacitor 115 and the bright level is held in the holding capacitor 116 for the pixels in which the bright level accumulated in the photodiode does not exceed the saturation level. The pixel whose light level exceeds the saturation level holds the bright level using the overflow charge held in the capacitor CS as a signal in the holding capacitor 115 and the dark level in the holding capacitor 116. The optical response component is acquired by calculating the difference between the signals stored in the storage capacitors 115 and 116.

  As a result of performing this difference processing, pixels in which the light level in the photodiode does not exceed the saturation level are read from the output signal OUTS terminal with a positive polarity and from the output terminal OUTN terminal with a negative polarity. For a pixel in which the light level accumulated in the photodiode exceeds the saturation level, the overflow charge component accumulated in the storage capacitor 112 from the OUTS terminal is read with a negative polarity, and is read out with a positive polarity from the OUTN terminal.

  The polarity determination means 130 can determine the polarity of OUTS and OUTN and identify whether it is an output of a photodiode or a signal output of a charge overflowing from the photodiode. Therefore, it is not necessary to read out all the two outputs of the photodiode and the overflowed charge, and since the output of the overflowed charge is read only in the pixel in which the photodiode is saturated, the number of times of readout does not increase twice. Therefore, it is possible to obtain image information with a wide dynamic range while preventing a decrease in the frame rate.

  In this embodiment, the charge of the photodiode and the overflowed charge are read out. At this time, the same effect can be obtained by reading out the photodiode signal and then adding and reading the overflow charge held in CS by adding the switch 121 without conducting the CFD reset and the charge of the photodiode.

  In addition, the polarity is inverted by using the charge accumulated in the photodiode and the charge overflowing from the photodiode as two signals. At this time, for example, even if the polarity is inverted between the readout output obtained by linearly converting the charge stored in the photodiode and the readout output obtained by logarithmic conversion using the sub-threshold characteristic of the MOS, the effect of this embodiment is sufficiently obtained. can get.

  The first to third embodiments can be applied to an image sensor in which a wide dynamic range is desired in a CMOS image sensor mounted on a digital camera, a mobile phone with a camera, or the like. In addition, the present invention is particularly applicable to a camera system that requires a wide dynamic range and requires a high frame rate.

  According to the first to third embodiments, the signal polarities of two signals, which are different from the low illuminance signal and the high illuminance signal, read from the pixel for the purpose of expanding the dynamic range of the solid-state imaging device can be reversed. Even if only one of the signals is output, the signal can be specified by using the polarity determining means.

  Therefore, the number of signal outputs required in Patent Documents 1 to 3 can be reduced from two to one, and the frame rate can be increased while ensuring image information with a wide dynamic range.

  In addition, it is not necessary to provide an identification signal for the purpose of identifying a low illuminance signal or a high illuminance signal, and it is not necessary to route the input / output pads and wirings, thereby increasing the degree of freedom regarding the arrangement and wiring.

  As described above, in the first to third embodiments, the photoelectric conversion element corresponds to the photodiode 101 and generates electric charges by photoelectric conversion. The reading means corresponds to the select switch 105 and reads the generated charge signal. The polarity applying means corresponds to the AND logic circuits 111 and 112, the MOSFETs 113, 114, 117, and 118, the holding capacitors 115 and 116, and the differential amplifier 120 (or 121). The polarity imparting means imparts polarity to the read signal so that a signal when the generated charge amount is less than the reference value VSAT and a signal when the generated charge amount is greater than the reference value VSAT are opposite to each other. To do.

  The level detection unit corresponds to the comparator 108 and the latch circuit 110 and detects the level of the read signal. The polarity applying means provides the polarity based on a detection result by the level detecting means.

  In the first embodiment, the readout unit reads out the electric charge generated by the photoelectric conversion element during the first accumulation time A as a first signal, and the second accumulation is shorter than the first accumulation time A. At time B, the charge generated by the photoelectric conversion element is read as a second signal. The polarity applying means gives a polarity to the first signal when the generated charge amount is smaller than a reference value VSAT, and polarizes the second signal when the generated charge amount is larger than a reference value VSAT. Is output.

  In the third embodiment, the readout unit reads out the electric charge accumulated in the photoelectric conversion element as a first signal, and reads out the electric charge overflowing from the photoelectric conversion element as a second signal. The polarity applying means gives a polarity to the first signal when the generated charge amount is smaller than a reference value VSAT, and polarizes the second signal when the generated charge amount is larger than a reference value VSAT. Is output. The first signal is a signal proportional to the amount of incident light, and the second signal is a signal proportional to the logarithm of the amount of incident light.

  In the first to third embodiments, the polarity determining unit 130 determines the polarity of the signal to which the polarity is given by the polarity giving unit. The polarity determination unit 130 controls analog / digital conversion of the determined signal according to the determined polarity. For example, the storage location of digital data after analog / digital conversion is controlled in accordance with the polarity determination result.

  In the first to third embodiments, a plurality of the photoelectric conversion elements are provided, and only one of the signals switched to opposite polarities in each pixel is output.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

FIG. 2 is an output waveform diagram and a timing diagram of the solid-state imaging device according to the first embodiment of the present invention. 1 is an equivalent circuit diagram of a solid-state imaging device according to a first embodiment of the present invention. It is an operation | movement timing diagram of the solid-state imaging device by the 1st Embodiment of this invention. It is the output waveform diagram and timing diagram of the solid-state imaging device by the 2nd Embodiment of this invention. It is an equivalent circuit schematic of the solid-state imaging device by the 2nd Embodiment of this invention. It is an equivalent circuit schematic of the solid-state imaging device by the 3rd Embodiment of this invention. It is a timing diagram which shows the drive of the solid-state imaging device by the 3rd Embodiment of this invention.

Explanation of symbols

101 Photodiode 102 Transfer MOS Transistor 103 Reset Switch 104 Amplification MOSFET
105 Select switch 108 Comparator 109 Constant current source 110 Latch circuit 111 AND logic circuit 112 AND logic circuit 113 Switch MOSFET
114 switch MOSFET
115 Holding Capacitor 116 Holding Capacitor 117 Switch MOSFET
118 Switch MOSFET
120 differential amplifier 121 differential amplifier

Claims (10)

A photoelectric conversion element that generates charges by photoelectric conversion; and
Reading means for reading out the signal of the generated charge;
Polarity adding means for applying polarity to the read signal so that a signal when the generated charge amount is less than a reference value and a signal when the generated charge amount is more than a reference value have opposite polarities to each other; A solid-state imaging device. Furthermore, it has level detection means for detecting the level of the read signal,
The solid-state imaging device according to claim 1, wherein the polarity applying unit applies the polarity based on a detection result by the level detecting unit. The reading means reads the electric charge generated by the photoelectric conversion element during a first accumulation time as a first signal, and is generated by the photoelectric conversion element during a second accumulation time shorter than the first accumulation time. Read out the electric charge as a second signal,
The polarity imparting means imparts polarity to the first signal when the generated charge amount is smaller than a reference value, and imparts polarity to the second signal when the generated charge amount is larger than a reference value. The solid-state imaging device according to claim 1, wherein the solid-state imaging device outputs the output. The readout means reads out the electric charge accumulated in the photoelectric conversion element as a first signal, reads out the electric charge overflowing from the photoelectric conversion element as a second signal,
The polarity imparting means imparts polarity to the first signal when the generated charge amount is smaller than a reference value, and imparts polarity to the second signal when the generated charge amount is larger than a reference value. The solid-state imaging device according to claim 1, wherein the solid-state imaging device outputs the output. The first signal is a signal proportional to the amount of incident light,
The solid-state imaging device according to claim 4, wherein the second signal is a signal proportional to the logarithm of the amount of incident light.   The solid-state imaging device according to claim 1, further comprising a polarity determination unit that determines a polarity of the signal to which the polarity is applied by the polarity applying unit.   The solid-state imaging device according to claim 6, wherein the polarity determination unit controls analog / digital conversion of the determined signal in accordance with the determined polarity.   The solid-state imaging device according to claim 1, wherein the solid-state imaging device includes a plurality of the photoelectric conversion elements, and outputs only one of the signals switched to opposite polarities in each pixel. A processing method for a solid-state imaging device having a photoelectric conversion element that generates charges by photoelectric conversion,
A reading step of reading out the generated charge signal;
A polarity adding step of giving a polarity to the read signal so that a signal when the generated charge amount is smaller than a reference value and a signal when the generated charge amount is larger than a reference value have opposite polarities to each other. A processing method for a solid-state imaging device.   The solid-state imaging device processing method according to claim 9, wherein the solid-state imaging device includes a plurality of the photoelectric conversion elements, and outputs only one of the signals switched to opposite polarities in each pixel.

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