JP2009098799A - Electronic appliance and method for controlling electronic appliance - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data transfer control device in a serial bus whose load on the traffic is small and which performs high speed access, in the case of continuously performing a read or write instruction, and also to provide a method for controlling the data transfer control device in the serial bus. <P>SOLUTION: The data transfer control device in the serial bus transmits a plurality of addresses considering them as one data in the case of continuously performing a read or write instruction. The method for controlling the data transfer control device in the serial bus is also provided. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

The present invention relates to data transfer using a serial bus in electronic equipment.

  Conventionally, a small computer system interface (SCSI) that is a parallel interface or a USB that is a serial interface has been used for many years as an interface for connecting a personal computer and its peripheral devices.

  In recent years, with the development of digital image compression technology, there has been a demand for a function of handling digital moving image data on a personal computer and reproducing the moving image data on a personal computer while transferring the moving image data to the personal computer. However, with SCSI and USB 1.1, it is impossible to support real-time data transfer.

  In addition, data to be transferred between a personal computer and peripheral devices includes high-definition color still image data such as a digital camera and a scanner. Transfer of large amounts of data takes a long time. For this reason, a high-speed interface is required.

  A parallel interface represented by SCSI transfers data using a plurality of data lines. Therefore, the data transfer capability per clock is high, but as the operating frequency increases, noise increases, and accurate signals are caused by delays caused by interference between signal lines and differences in signal line lengths. It is difficult to communicate.

  A common clock system, which is one of parallel interface systems, uses many parallel interfaces such as PCI (Peripheral Component Interconnect). The data transmitting side and the receiving side transfer data in synchronization with a common clock. However, in order to perform transfer correctly, the delay from the transmission side to the reception side needs to be within one clock cycle, and the clock cycle cannot be made shorter than the delay time. Is difficult to shorten.

  The serial interface exchanges data on a single transmission line, and since the number of signal lines is small, the cable is thin and the number of control chip terminals is small, so interference and delay are unlikely to occur, and the operating frequency is easily increased. Can do.

  In recent years, the area of the semiconductor chip is not determined by the amount of integrated circuits, but the area of the semiconductor chip tends to depend on the number of terminals connecting the semiconductor chip and the outside. This tendency occurs because the progress of miniaturization of the semiconductor integrated circuit exceeds the progress of narrowing the distance between the semiconductor chip terminals. In other words, the amount of circuits that can be integrated on a semiconductor chip has increased due to miniaturization, but the distance between terminals on the semiconductor chip cannot be reduced so much. Determined by the number of terminals.

  In order to reduce the number of terminals, it is effective to use a serial bus instead of a parallel bus that requires many terminals.

The following invention is known as a control technique for connecting two chips via a serial bus. In other words, request processing and response processing are performed separately, each circuit in the module is transferred in a packet system, two chips are connected, parallel-serial conversion is performed between these two chips, and between modules (See, for example, Patent Document 1).
JP 2003-198356 A

  In the above prior art, when accessing a plurality of data continuously between two chips connected by a serial bus, processing to extract data from the packet occurs, and when the number increases, the traffic is concentrated accordingly, Transfer efficiency decreases.

  FIG. 10 is a block diagram showing a conventional serial transfer system SS3 for two chips connected by a serial bus. The conventional serial transfer system SS3 includes a first chip C13 and a second chip C23.

  The first chip C13 includes the first serial data transmission / reception controller 11, and is connected to the second chip C23 via the serial bus SB1. The first chip C13 is connected to each of the external CPU 31 and the external memory 32 via parallel buses PB1 and PB2.

  The second chip C23 includes a second serial data transmission / reception controller 22, a first functional circuit block 23, a second functional circuit block 24, a third functional circuit block 25, and a memory 26.

  FIG. 11 is a diagram illustrating a configuration example of a conventional packet.

  Although the packet format differs depending on the communication method, in general, a packet at the time of reading is composed of a header and an address, and a packet at the time of writing is composed of a header, an address and data. As an example, in the case of PCI Express, the sum of the number of bits of the header and the number of bits of the address is 96 to 128 bits, and the data amount can be set from 0 to 4096 bytes.

  For example, when 50 write processes are continuously performed on the register provided in the first functional circuit block 23, 50 packets are transferred through the serial bus. The headers included in these 50 packets are analyzed one by one. As the number of packets increases, the time required for header analysis increases. For this reason, there is a problem that the time for occupying the bus becomes longer in proportion to the number of packets.

The present invention provides a data transfer control device and a control method thereof in a serial bus that can be accessed at a high speed when a read or write instruction is executed a plurality of times in succession, and the load on the serial bus traffic is small. The purpose is to do.

  The present invention is an electronic apparatus comprising a first integrated circuit and a second integrated circuit connected by a serial bus, wherein the first integrated circuit is a write provided in the second integrated circuit. When writing to a register, if writing addresses are continuous, a compression means for compressing the writing address information and its data, and a packet including information related to compression by the compression means and a plurality of compressed data are generated. A packet generation means that outputs the packet data generated by the packet generation means to a serial bus, and the second integrated circuit includes an input means that inputs the packet data from the serial bus; The separating means for dividing the packet data input by the input means into address unit data, and the data separated by the separating means, An acquisition unit that expands based on information about compression and acquires address information and data corresponding to the address, and a setting unit that sets data corresponding to the address based on the address information acquired by the acquisition unit It is an electronic device characterized by being a circuit.

According to another aspect of the present invention, there is provided a method for controlling an electronic apparatus including a first integrated circuit and a second integrated circuit connected by a serial bus, wherein the first integrated circuit is connected to the second integrated circuit. When writing to the write register provided, if the write address is continuous, the compression step for compressing the write address information and its data, information relating to the compression performed in the compression step, and a plurality of compressed data A packet generating step for generating one packet consisting of: and a step of outputting the packet data generated in the packet generating step to the serial bus. The second integrated circuit transmits the packet data to the serial bus. The input process to be input, the separation process for dividing the packet data input in the input process into data in address units, and the separation in the separation process The data is expanded based on the information related to compression, the acquisition process for acquiring the address information and the data corresponding to the address, and the data corresponding to the address is set based on the address information acquired in the acquisition process. And a setting step for performing the electronic device control method.

According to the present invention, when a read or write command is continuously transmitted a plurality of times, the data amount of the header is reduced, and the bus transfer efficiency can be improved.

  The best mode for carrying out the invention is the following embodiment.

  FIG. 1 is a diagram showing a configuration of a serial transfer system SS1 that is Embodiment 1 of the present invention.

  The serial transfer system SS1 is an electronic device including a first integrated circuit and a second integrated circuit connected by a serial bus.

  The serial transfer system SS1 is an example of an electronic device, specifically, a recording apparatus (inkjet printer), and for example, drives a recording head to eject ink. In order to control this drive, there are cases where the print head control circuit is continuously accessed. Alternatively, in order to drive the motor of the printing apparatus, the motor control circuit may be continuously accessed for initialization. Access to these control circuits is performed by accessing a register provided in the circuit. Or, a memory such as a print buffer that holds recording data may be continuously accessed.

  The serial transfer system SS1 includes a first chip C11 and a second chip C21. The first chip C11 is an example of a first integrated circuit, and the second chip C21 is an example of a second integrated circuit, which are connected by a serial bus.

  The first chip C11 includes a first serial data transmission / reception controller (serial communication unit) 11 and a first data encoding / decoding circuit 12, and is connected to the second chip C21 via the serial bus SB1. . The first data encoding / decoding circuit 12 includes a compression unit that compresses address information and data and a packet generation unit that generates one packet data from a plurality of data.

  The first chip C11 is connected to an external CPU 31 via a parallel bus PB1, and the first chip C11 is connected to an external memory 32 via a parallel bus PB2.

  The second chip C21 includes a second data encode / decode circuit 21, a second serial data transmission / reception controller (serial communication unit) 22, a first functional circuit block 23, a second functional circuit block 24, and a third functional circuit. A block 25 and a memory 26 are included.

  The second serial data transmission / reception controller (serial communication unit) 22 inputs packet data from the serial bus.

  The second data encoding / decoding circuit 21 includes a separation unit that separates one packet data into a plurality of data, a decompression unit that decompresses data separated by the separation unit, and a setting unit that sets data.

  The separation unit separates the data into a plurality of data in units of addresses (in units of access). By this separation, the first chip C11 returns to the data format before generating one packet data.

  The decompression unit holds compression processing information performed by the compression unit provided in the first data encoding / decoding circuit 12, and performs decompression processing based on the compression processing information. The decompression unit performs decompression processing, whereby address information and data of a register that stores data can be acquired.

  Based on the address information, the setting unit specifies a functional circuit block for setting data, and sets (writes) the specified functional circuit block. The setting unit sets data corresponding to each address for successive addresses based on the address information.

  The memories 32 and 26 store programs, control data parameters, and the like. For example, the first functional circuit block 23 is a control block for driving the recording head. The second functional circuit block 24 is a control block for driving the motor. The first data encoding / decoding circuit 12 and the second data encoding / decoding circuit 21 have a function of encoding register access commands and the like transmitted in succession and converting them into the same packet format. The first data encode / decode circuit 12 and the second data encode / decode circuit 21 are circuits having a function of decoding a register access command and the like transmitted in the same packet format.

  The first serial data transmission / reception controller 11 is a circuit that analyzes a packet generated by the first chip C11 and transmits the packet to a predetermined circuit block included in the second chip C21. The second serial data transmission / reception controller 22 is a circuit that analyzes a packet generated by the second chip C21 and transmits the packet to a predetermined circuit block of the first chip C11.

  In the first embodiment, three functional circuit blocks and one memory are provided in the second chip C21. However, any number of functional circuit blocks and memories may be connected to the internal parallel bus.

  In the first embodiment, the first chip C11 is connected to the external CPU 31, the external memory 32, and the parallel buses PB1 and PB2. However, the CPU 31 and the memory 32 are connected to the first chip C11. It may be included in the inside.

  Next, packets generated by the data encoding / decoding circuits 12 and 21 will be described.

  In other words, the first chip C11 is an example of the first integrated circuit, and when the first integrated circuit writes to the write register provided in the second integrated circuit, the addresses to be written are consecutive. For example, it has compression means for compressing address information to be written and its data. In addition, the first integrated circuit includes a packet generation unit that generates one packet including information related to compression by the compression unit and a plurality of compressed data, and the packet data generated by the packet generation unit is transferred to the serial bus. A circuit having output means for outputting.

  Further, the second chip C21 is an example of a second integrated circuit. The second integrated circuit has an input means for inputting packet data from a serial bus, and the packet data input by the input means is an address unit. And separating means for dividing the data. The second integrated circuit further includes an acquisition unit that expands the data separated by the separation unit based on the compression-related information and acquires address information and data corresponding to the address. Further, the second integrated circuit is a circuit having setting means for setting data corresponding to the address based on the address information acquired by the acquisition means.

  FIG. 2 is a diagram illustrating the format of the packet format in the first embodiment.

  The packet generated by the data encoding / decoding circuits 12 and 21 is composed of a header, a command, and access data. This packet data is 576 bits. The header is composed of 64 bits, the command is composed of 26 bits, and the data (access data) is composed of 486 bits.

  The inside contains information necessary for passing through the serial bus and is analyzed by the first and second serial data transmission / reception controllers 11 and 22 on the transmission side. The access data is obtained by encoding a plurality of continuous access instructions from the CPU. When writing is performed, an address and data become a plurality of sets of data blocks (data blocks). When reading is performed, the data block is composed of a plurality of addresses.

  Here, the bit width of the command + access data is 512 bits. That is, the amount of commands and access data is 512 bits in terms of the number of bits. The command includes 8 bits representing the address of the data encoding / decoding circuit on the receiving side, 2 bits representing the type of access (read or write), 8 bits representing the number of access data, and 8 bits representing the bit width of one data. It is constituted by. Note that the read / write (2 bits) is data indicating the transfer direction of continuous reading or continuous writing.

  In the first embodiment, the case of header 64 bits, command 26 bits, and access data 486 bits has been described. However, the present invention is not limited to this. If the number of instructions that are continuously accessed from the CPU is small, it may be 256 bits, and if the number of instructions that are continuously accessed from the CPU is large, it may be 1024 bits.

  That is, the serial transfer system SS1 is an example of a data transfer control device, and includes a data transmission unit including a CPU, a memory, a serial data transmission / reception controller that controls transmission / reception of data, and a transmission / reception controller that controls transmission / reception of data. Have The serial transfer system SS1 is a data transfer control device in which a plurality of chips each having a means for converting a plurality of access instructions into the same packet and a means for restoring the access instructions from the packet are connected via a serial bus. .

  The packet includes a header, a command, and access data, and the command has a function of defining access data.

  In the data included in this packet, the address of the register to be accessed or the address of the memory to be accessed is continuous. This access is a write process (write process) or a read process (read process). In this case, the packet is transferred to one of the plurality of chips via the high-speed serial bus via the serial data transmission / reception controller. Then, the serial data transmission / reception controller transfers to the means for restoring the access command from the packet, analyzes a plurality of commands, and makes a register access according to the analyzed contents.

  When a read is designated from the first chip to a plurality of registers or memories of the second chip, a packet constituted by means for converting a plurality of access instructions into a packet by the serial data transmission / reception controller is transferred to the second chip. To the first chip.

  Next, transfer processing in the first embodiment will be described.

  FIG. 3 is an explanatory diagram showing an operation of writing to the first functional circuit block 23 in the serial transfer system SS1.

  When register access is continuously performed to the same circuit block in order to eject ink, 12 colors of ink are used, two ink ejection columns are provided for each color, and the number of ink ejection columns is an even number. If the odd number is configured separately, 48 register writes are continued.

  The CPU 31 receives a write request to the first functional circuit block 23 and continuously transmits an access command for register writing to the first data encode / decode circuit 12 a plurality of times. This access command is encoded by the first data encoding / decoding circuit 12 and converted into the format shown in FIG. Next, the packet formed by the first data encode / decode circuit 12 is analyzed by the first serial data transmission / reception controller 11 to specify the second data encode / decode circuit 21 stored in the packet command. Sent to address. Thereafter, the data is decoded by the second data encoding / decoding circuit 21 and written to the register of the first functional circuit block 23.

  FIG. 4 is an explanatory diagram showing a case where data of the first functional circuit block 23 is read in the serial transfer system SS1.

  The CPU 31 receives a read request from the first functional circuit block 23 and transmits an access command for performing a register read from the first functional circuit block 23 to the first data encode / decode circuit 12 continuously a plurality of times. This access command is encoded by the first data encoding / decoding circuit 12 and converted into the format shown in FIG.

  Next, for the packet formed by the first data encode / decode circuit 12, the first serial data transmission / reception controller 11 analyzes the inside of the header and specifies the second data encode / decode circuit 21 stored in the command of the packet. Send to address. Thereafter, the second data encode / decode circuit 21 decodes the data and reads it from the register of the first functional circuit block 23. The read data is encoded by the second data encoding / decoding circuit 21 and converted into the format shown in FIG. The second serial data transmission / reception controller 22 analyzes the inside of the header and transmits it to the designated address of the first data encoding / decoding circuit 12 stored in the packet command. Thereafter, the first data encode / decode circuit 12 decodes the data and writes it in the register of the CPU 31.

  In the first embodiment, the write destination and the read destination are set to be the first functional circuit block 23, but may be set to any circuit block in the second chip C21. The reading destination is the CPU 31 connected to the first chip C11 via the parallel bus PB1, but the memory 32 may be the reading destination.

  FIG. 5 is a timing chart for accessing the first data encoding / decoding circuit 12 from the CPU 31 in the serial transfer system SS1.

  FIG. 5A is a timing chart showing an operation when writing is performed in the serial transfer system SS1.

  The clock 40 is a basic clock for the CPU 31. In the case of writing, when the access command 44 becomes HIGH during the period in which the R / W signal 41 is LOW, the access address 42 and the access data 43 are transmitted to the data encoding / decoding circuit.

  FIG. 5 (2) is a timing chart showing an operation in the case of reading in the serial transfer system SS1.

  In the case of reading, when the access command 44 becomes HIGH during the period in which the R / W signal 41 is HIGH, the access address 42 is transmitted to the data encoding / decoding circuit.

  The internal counter 45 is an internal counter inside the data encode / decode circuit, counts access addresses, and determines the number of command data in the packet.

  FIG. 6 is a diagram showing an internal configuration of the encoding circuit unit 121 and the decoding circuit unit 122 of the first data encoding / decoding circuit 12 in the serial transfer system SS1.

  FIG. 6A is a diagram illustrating an internal configuration of the encoding circuit unit 121 of the first data encoding / decoding circuit 12.

  A case where the access address is transmitted in 64 bits and the access data is transmitted in 64 bits will be described. First, the encoding circuit unit 121 will be described. When an access command is received from the CPU 31 and the access address and the access data are transferred, the encoding circuit unit 121 encodes the access address + access data 128 bits to become 7-bit data. This data is stored in the register of the encoding circuit unit 121. The operation is sequentially performed.

  The first encoded data is DATA0, and in order, DATA1, DATA2,..., DATAn-1. In the example shown in FIG. 6, since 48 data are handled, DATA47 is the last. In order to collect the same packet, 48 pieces of 7-bit data are grouped as 486-bit access data. That is, 48 7-bit data are packed. If the access data is less than 486 bits, it is assumed that unassigned bit data is 0.

  Next, a packet command is created by the address of the second data encoding / decoding circuit 21, the number of data counted by the internal counter, the bit width after encoding, and the R / W signal.

  FIG. 7 is a diagram illustrating a setting example of R / W in a command.

  As shown in FIG. 7, in the case of reading, it is “10”, and in the case of writing, it is “01”.

  Next, a header including information for passing through the serial bus is generated. The header + command + access data is sent as a packet and transmitted to the serial data transmission / reception controllers 11 and 22 via the serial bus SB1.

  Next, the decoding circuit unit 122 will be described.

  FIG. 6B is a diagram illustrating an internal configuration of the decode circuit unit 122 of the first data encode / decode circuit 12.

  The decode circuit unit 122 analyzes the read data packet transmitted from the second data encode decode circuit 21. In this case, the serial data transmission / reception circuit analyzes the 64-bit header portion constituting 576 bits. The serial data transmission / reception circuit transmits 512-bit data remaining in the first data encoding / decoding circuit 12. The 26-bit command included in the packet is analyzed. By this analysis, the number of transmitted data and the bit width of one data can be known. By analyzing this command, it is divided into individual data, and each divided data is stored. In this example, 7-bit data is divided into 48 pieces and stored. Thereafter, the 7-bit data is further decoded into the original access address and access data, and transmitted to a predetermined circuit block.

In the second data encoding / decoding circuit 21, the first data encoding / decoding circuit 12, the encoding circuit unit 121, and the decoding circuit unit 122 have the same function except that an access command is received as an interrupt from the functional circuit block. .

  FIG. 8 is a diagram showing a configuration of a serial transfer system SS2 that is a system connected by a serial bus according to the second embodiment of the present invention.

  The serial transfer system SS2 is basically the same as the serial transfer system SS1. However, a first data encode / decode circuit 12 a is provided instead of the first data encode / decode circuit 12, and a second data encode / decode circuit 21 a is provided instead of the second data encode / decode circuit 21.

  The first data encode / decode circuit 12 a includes a control register 123 in the first data encode / decode circuit 12. The second data encode / decode circuit 21 a includes a control register 211 in the second data encode / decode circuit 21.

  As a result, the access data at the time of packet generation can be set to a number of bits other than 512 bits, not fixed to 512 bits.

  FIG. 9 is a diagram showing an internal configuration of the first data encode / decode circuit 12a in the serial transfer system SS2.

  The first data encoding / decoding circuit 12 a includes an encoding circuit unit 121 and a control register 123.

  The encoding circuit unit 121 is the same as that of the first embodiment. In the second embodiment shown in FIG. 9, since 48 pieces of data are handled, the last is DATA47. In order to collect the data as a packet, 48 pieces of 7-bit data are grouped as 336-bit access data.

  Next, a packet command is created by the address of the second data encoding / decoding circuit 21a, the number of data counted by the internal counter, the bit width after encoding, and the R / W signal. As shown in FIG. 7, it is assumed that “10” is used for reading and “01” is used for writing.

  Next, a header including information for passing through the serial bus SB1 is generated. Then, the header + command + access data is packetized and transmitted to the serial data transmission / reception controllers 11 and 22 via the bus SB1.

Moreover, the said Example can be grasped | ascertained as invention of a method. That is, the above embodiment is an example of a method for controlling an electronic device including a first integrated circuit and a second integrated circuit connected by a serial bus. The first integrated circuit has a compression step of compressing the address information to be written and its data if the write address is continuous when writing to the write register provided in the second integrated circuit. . Furthermore, the first integrated circuit includes a packet generation step for generating one packet including information related to compression performed in the compression step and a plurality of compressed data, and packet data generated in the packet generation step. Is output to the serial bus. In addition, the second integrated circuit performs an input process of inputting packet data from the serial bus and a separation process of dividing the packet data input in the input process into data in address units. Then, the second integrated circuit performs an acquisition step of expanding the data separated in the separation step based on the compression-related information and obtaining address information and data corresponding to the address. In addition, the second integrated circuit performs a setting step of setting data corresponding to the address based on the address information acquired in the acquisition step.

It is a figure which shows the structure of serial transfer system SS1 which is a system connected by the serial bus which is Example 1 of this invention. It is a figure explaining the format of the packet format in Example 1. FIG. FIG. 11 is an explanatory diagram showing an operation of writing to the first functional circuit block 23 in the serial transfer system SS1. FIG. 10 is an explanatory diagram showing a case where data of a first functional circuit block 23 is read in the serial transfer system SS1. FIG. 10 is a timing chart for accessing the first data encode / decode circuit 12 from the CPU 31 in the serial transfer system SS1. FIG. 2 is a diagram illustrating an internal configuration of an encoding circuit unit 121 and a decoding circuit unit 122 of a first data encoding / decoding circuit 12 in the serial transfer system SS1. It is a figure which shows the example of a setting of R / W in a command. It is a figure which shows the structure of serial transfer system SS2 which is a system connected by the serial bus which is Example 2 of this invention. FIG. 3 is a diagram showing an internal configuration of a first data encode / decode circuit 12a in the serial transfer system SS2. It is a block diagram which shows the conventional serial transfer system SS3 connected by the serial bus. It is a figure which shows the example structure of the conventional packet.

Explanation of symbols

C11 ... first chip,
C21 ... second chip,
31 ... CPU,
32 ... Memory,
SB1 ... serial bus,
11 ... 1st serial data transmission / reception controller,
12: First data encoding / decoding circuit,
21: Second data encoding / decoding circuit,
22 ... Second serial data transmission / reception controller,
23. First functional circuit block,
24 ... second functional circuit block,
25. Third functional circuit block,
26: Internal memory,
40 ... clock,
41 ... R / W signal,
42 ... Access address,
43 ... Access data,
44 ... Access command,
45. Internal counter,
121 ... Encoding circuit section,
122: Decoding circuit section.

Claims (3)

An electronic device comprising a first integrated circuit and a second integrated circuit connected by a serial bus,
The first integrated circuit includes:
When writing to the write register provided in the second integrated circuit, if there are consecutive write addresses, the compression means compresses the write address information and the data;
Packet generating means for generating one packet comprising information related to compression by the compression means and a plurality of compressed data;
Output means for outputting the packet data generated by the packet generation means to the serial bus;
A circuit having
The second integrated circuit is:
Input means for inputting packet data from the serial bus;
Separating means for dividing the packet data input by the input means into data in address units;
Obtaining means for decompressing the data separated by the separating means based on the compression-related information and obtaining address information and data corresponding to the address;
Setting means for setting data corresponding to the address based on the address information acquired by the acquisition means;
An electronic device characterized by being a circuit having In claim 1,
The second integrated circuit is a circuit including a plurality of circuit blocks, and the address information is information including information specifying a circuit block to be set among the plurality of circuit blocks. Electronics. A method for controlling an electronic device comprising a first integrated circuit and a second integrated circuit connected by a serial bus,
The first integrated circuit includes:
When writing to the write register provided in the second integrated circuit, a compression step of compressing the write address information and its data if the write addresses are continuous;
A packet generation step of generating one packet including information related to compression performed in the compression step and a plurality of compressed data;
An output step of outputting the packet data generated in the packet generation step to a serial bus;
And
The second integrated circuit is:
An input process of inputting packet data from a serial bus;
A separation step of dividing the packet data input in the input step into data in address units;
An acquisition step of decompressing the data separated in the separation step based on information related to compression to obtain address information and data corresponding to the address;
A setting step of setting data corresponding to the address based on the address information acquired in the acquisition step;
A method for controlling an electronic device, comprising:

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