JP4492362B2 - Image forming apparatus capable of improving image quality - Google Patents

Description

  The present invention relates to an image forming apparatus, and more particularly to an image forming apparatus capable of changing the number of head passes in an ink jet printer and thereby improving image quality.

  The image forming apparatus receives image forming data from a host computer, converts it to original image data through decompression processing, etc., and performs color conversion processing and binarization processing on the image data as necessary. This binarized data is image reproduction data indicating whether or not to form dots in pixels. When the image forming apparatus is an ink jet printer, for the binarized data for each pixel, a pass separation process for separating the data for each pass of the print head, and a nozzle order conversion process for rearranging the print head in the nozzle order Is done. Here, the pass means a scanning pass in which the print head moves in the recording paper scanning direction (perpendicular to the paper feed). When printing one line (one raster) by scanning the print head N times, N pass printing.

  The pass decomposition and nozzle forward conversion of the ink jet printer are described in Patent Document 1 below.

By increasing the number of passes, the resolution of the printed image can be increased and a higher quality image can be formed. On the other hand, if the number of passes is increased to improve the image quality, the number of passes increases to those that do not require high image quality, such as characters, and the printing throughput decreases. Therefore, it is desirable to be able to select the optimum number of passes corresponding to the type of image by enabling printing with a plurality of types of passes.
Japanese Patent Laid-Open No. 11-207947

  The path decomposition process is a process that decomposes binarized data (image reproduction data) arranged in raster order and line order for each pass of the print head, and is usually realized by a large-scale switching circuit network. . For example, if there are four paths, the path decomposition circuit divides the line-sequential binarized data into four groups for each path, and the divided binarized data is stored in the buffer. Thereafter, the binarized data of each pass is rearranged in the order of the nozzles of the print head, the binarized data is read at the timing when the head is scanned, and the corresponding drive signal is supplied to the head.

  However, if the number of passes is increased to enable printing with a plurality of passes, it is necessary to provide a path disassembly circuit for each different number of passes, which increases hardware and increases costs, which is not preferable.

  SUMMARY OF THE INVENTION Accordingly, the present invention provides an image forming apparatus that can perform path decomposition on image reproduction data having different numbers of passes by using a common path decomposition circuit.

  In order to achieve the above object, according to a first aspect of the present invention, in an image forming apparatus that prints one row by a plurality of scanning passes of a print head, image reproduction data arranged line-sequentially is stored. A pass separation processing unit for separating each scan pass of the print head, and image reproduction data separated for each scan pass is given to the print head according to the print head structure; A data rearrangement circuit for decomposing the image reproduction data arranged in line-sequential manner into groups of image reproduction data having a predetermined number of bits corresponding to a common scan path group, and a predetermined data decomposed by the data rearrangement circuit A path decomposing circuit for decomposing image reproduction data comprising the number of bits for each scanning pass.

  According to the first aspect described above, it is possible to decompose the image reproduction data of the different number of scanning passes for each pass by using a common pass decomposition circuit, and to reduce the cost.

  In the first aspect described above, according to a more preferred embodiment, it further comprises a time division buffer for storing the output of the data rearrangement circuit in units of 1 byte, and the number of scan passes is N (N is an integer). Each of the image reproduction data is composed of L bits (L is an integer), and the path decomposition circuit is a circuit for decomposing the image reproduction data having the predetermined number of bits every M scanning passes, The data rearrangement circuit rearranges the line-sequentially arranged image reproduction data for each of M scanning pass groups when 8 / L> M and the number of scanning passes N exceeds M, and otherwise In the case of, it is characterized by not rearranging.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the matters described in the claims and equivalents thereof.

  FIG. 1 is a configuration diagram of an image forming apparatus according to the present embodiment. As an example, this image forming apparatus is an ink jet printer that enables image formation on large-format paper. The controller 20 receives image forming data from a host computer (not shown), performs image processing on the image forming data, and outputs image reproduction data. The image reproduction signal 38 is output to the print head 10 having a large number of nozzles that generate and eject ink. The controller 20 includes a CPU (control unit) that controls image processing for generating image reproduction data, its CPU bus CBUS1, and an image processing unit 22 connected to the CPU bus CBUS1. Further, an external CPU memory CPUMEM is connected to the CPU bus CBUS1, and various parameters and control programs are stored in the external CPU memory.

  The CPU bus CBUS1 is connected to the second CPU bus CBUS2 via the CPU interface CPUIF in the image processing unit 22. Further, the image processing unit 22 includes interfaces IF1 to IF3 of various communication channels NET1 to NET3, a path control unit 24 that performs transfer control of input data, a decompression unit group 26 that performs decompression processing, and image reproduction in a raster direction. A pass separation processing unit 32 that decomposes data for each scan pass of the print head, and a nozzle order conversion processing unit 34 that changes the order of the image reproduction data decomposed for each pass in the order of the nozzles of the print head, respectively. It is provided as a block (data processing block). Further, the color conversion and binarization processing unit 12 is configured by an external dedicated processor, not the dedicated hardware in the controller 20 such as the decompression unit group 26, the pass separation processing unit 32, and the nozzle forward conversion processing unit 34. In addition, color conversion and binarization processing are realized by a program so that changes in those processing can be easily handled. This color conversion and binarization processing unit also corresponds to the data processing block.

  Further, the image processing unit 22 has a local bus LBUS for connecting the above-described pass control unit 24, decompression unit group 26, pass decomposition processing unit 32, and nozzle forward conversion processing unit 34, and this local bus LBUS has an external memory. An external large-capacity memory E-MEM is connected via the controller 28. The external memory controller 28 and the external memory E-MEM are connected via a memory bus MBUS. The external large-capacity memory E-MEM temporarily stores input image formation data and has a plurality of buffer areas for temporarily storing data after each process. The local bus LBUS is connected to the binarization interface unit 30 and is connected to the color conversion and binarization processing unit 12 via the binarization bus HTBUS. The local bus LBUS is connected to the print head 10 via the head interface unit 36.

  While the CPU buses CBUS1 and CBU2 are used for command interpretation and the like, the local bus LBUS is used for transferring a large amount of image data. 128 bits and the CPU bus is 32 bits).

  The dedicated processing units (data processing blocks) in the image processing unit 22 are controlled in operation through the CPU and the first CPU bus CBUS1 and the second CPU bus CBUS2. For example, when the CPU writes an operation start flag in the operation start register of each processing unit, each dedicated processing unit executes the corresponding processing, and the CPU receives an operation end interrupt signal when the processing of each processing unit ends. The end of the operation is detected.

  Inkjet large format printers are widely used in the printing industry and the like, but in this embodiment, they can receive three types of input formats. First, JPEG compressed data obtained by compressing RGB image data in JPEG format, and second, C (cyan), M (magenta), Y (yellow), K (black) corresponding to the nozzles of the print head 10. , Lc (light cyan), lm (light magenta), lk (light black), llk (second light black) color data of 8 colors and run-length compressed data consisting of binarized data (2 bits for each color), Third, it is RHV2 compressed data in which CMYK 8-bit image data is compared with the previous raster and the difference is obtained.

  In the case of the first JPEG compressed data, the original image data is JPEG compressed on the host computer side, and the compressed data is input to the controller 20 via the communication lines NET1 to NET3. Since the compression rate is high, the amount of communication data can be reduced, and the communication time between the host computer and the printer can be shortened. However, on the printer side, the received JPEG compressed data is decompressed and RGB image data is reproduced, and the reproduced RGB image data is converted into color conversion, binarization processing, and conversion processing (pass decomposition processing) corresponding to the head nozzle. And nozzle forward conversion processing).

  In the case of the second run-length compressed data, since color conversion and binarization processing are performed on the host computer side, decompression processing is performed on the printer side, and after conversion processing to head data, an image is applied to the print head 10. What is necessary is just to output as the reproduction signal 38, and the process in the printer side is simplified.

  Since the third RHV2 compressed data is subjected to color conversion processing on the host computer side, it is necessary to perform decompression processing on the printer side to perform binarization processing and conversion processing corresponding to the nozzles of the head. is there.

  The data input in this way includes decompression (decoding) processing corresponding to each compression format, color conversion and binarization processing as required, and conversion processing to head data, that is, two for each dot. A pass decomposition process for decomposing the digitized data for each pass, and a nozzle order conversion process for rearranging the data arranged in the raster direction decomposed for each pass in the nozzle order of the head are performed.

  Next, a data flow and processing corresponding to input image formation data will be described. The input image formation data is input in the form of a packet via various communication channels NET1 to NET1-3. Each input interface IF1-3 performs processing such as reconstructing the packet into the original data string, Restore original data before transmission. Then, the input data is stored in the first input buffer I-BUF1 constituted by the FIFO buffer in the path control unit 24, and the input buffer of the external large-capacity memory E-MEM via the local bus LBUS. Stored in the I-BUF3. The external memory E-MEM is, for example, a double data rate synchronous DRAM, and has a large capacity and a high speed. Access to the external memory E-MEM is performed via the memory controller unit E-MC and the memory bus MBUS.

  Then, the head portion of the input data stored in the external memory E-MEM is stored again in the second input buffer I-BUF2 in the path control unit 24 via the local bus LBUS. That is, all the input data is stored in the external memory E-MEM, and only a part of the top of the input data is stored in the second input buffer I-BUF2 in the path control unit 24 and stopped. The first and second input buffers I-BUF1, 2 are FIFO buffers and are controlled by a FIFO controller (not shown).

  Therefore, the CPU as the control unit accesses the second input buffer I-BUF2 via the CPU buses CBUS1 and 2, and analyzes the command at the head portion of the input data. The input data command includes compression format information (data format information) for specifying the compression format. The command describes the data amount (how many bytes) in the case of the JPEG compression format and the RHV compression format, and the subsequent data amount can be recognized. In the case of the run length compression format, there is no description of the data amount in the command.

  When the CPU analyzes the command and recognizes the format type (compression format information) and the amount of data, the CPU stores the input data stored in the third input buffer I-BUF3 of the external memory E-MEM one after another. The data is transferred to the input buffer I-BUF2, and from there, the data is transferred to the decompression units JPEGU, RLEU, and RHVU corresponding to the format type in the decompression unit group 26. This data transfer is performed via the dedicated line from the second input buffer I-BUF2 without passing through the local bus LBUS. The CPU also performs control such as initialization of necessary processing units according to the data format of the image formation data.

  In the case of the JPEG format, the image data is decompressed (decoded) by the corresponding decompression unit JPEGU, and the decompressed reproduced image data is stored in the RGB buffer RGB-BUF of the external memory E-MEM. This reproduced image data is 8-bit or 16-bit RGB gradation data corresponding to pixels of a predetermined resolution. The RGB reproduced image data stored in the RGB buffer is transferred to the color conversion & binarization processing unit 12 via the binarization interface unit 30, where it is subjected to color conversion processing, and the color space CMYK of the printer ink. Further, binarization processing is performed on the ink ejection data (2 bits) from the nozzles of the print head 10 and stored in the plane buffer PL-BUF of the external memory E-MEM. The 2-bit ink ejection data is binarized data indicating whether or not there is ejection for large dot printing and whether or not ejection for small dot printing is performed on each of the eight colors of ink described above. The binarization processing unit 12 performs resolution conversion for converting the resolution of the decompressed reproduced image data to a higher resolution as necessary. As a result, the binarization process results in binarized data indicating whether or not dots are ejected at the resolution of the pixel density printed by the print head. Since this binarized data is supplied to the print head and used for forming dots, it is image reproduction data for directly reproducing an image.

  The binarized data of CMYK stored in the plane buffer PL-BUF is decomposed into binarized data for each scanning pass of the print head 10 by the pass decomposition process 32, and the pass buffer MW- in the external memory E-MEM. Stored in BUF. The binarized data decomposed for each pass is rearranged in the nozzle order of the head by the nozzle order conversion processing unit 34, and the binarized data in the nozzle order is stored in the head buffer HD-BUF in the external memory E-MEM. Stored. Finally, the binarized binarized data rearranged in the nozzle order is transferred to the print head 10 as the image reproduction data 38 via the head control unit 36.

  When the input image formation data is in the run length compression format, it is obtained by compressing the binarized data of eight colors that have been subjected to the color conversion process and the binarization process on the host computer side. Therefore, the input image formation data is transferred from the second input buffer I-BUF2 to the run length decompression unit RLEU via a dedicated line, decompressed there, and stored in the plane buffer PL-BUF of the external memory E-MEM. . The subsequent processing is the same as the JPEG compression format.

  In the case of the RHV compression format, color conversion from RGB data to CMYK data is performed on the host computer side, and the CMYK four-color image data is RHV compressed. Therefore, the input image formation data is transferred from the second input buffer I-BUF2 to the RHV decompression unit RHVU via a dedicated line, where it is decompressed, and as CMYK image data, RGB buffer RGB- of the external memory E-MEM. Stored in BUF. Thereafter, the CMYK image data is transferred to the binarization processing unit 12, where binarization processing is performed to generate the above-described eight-color binarization data. The binarized data of the eight colors is stored in the plane buffer PL-BUF of the external memory E-MEM. The subsequent steps are the same as in the JPEG compression format.

  As described above, input data of different compression formats is saved in the third input buffer I-BUF3 in the large-capacity external memory E-MEM via the first input buffer I-BUF1. Then, the command is transferred to the second input buffer I-BUF2, and the command located at the head of the input data stored in the second input buffer I-BUF2 is analyzed by the CPU, and the compression format information is detected. . Further, the CPU transfers the compressed data from the second input buffer I-BUF2 to the decompression units JPEGU, RLEU, RHVU corresponding to the detected compression format information via a dedicated line. After decompression by each decompression unit, the color conversion and binarization processing is performed by the processing unit 12, the pass separation processing is performed by the processing unit 32, and the nozzle forward conversion processing is performed by the processing unit 34, as necessary. The binary data to be output to the print head 10 is stored in the head buffer HD-BUF. The binarized data rearranged in the order of the nozzles of the head is transmitted to the print head 10 as an image reproduction signal 38.

  FIG. 2 is a diagram for explaining the path decomposition processing in the present embodiment. FIG. 2A shows a path decomposition process when the number of passes is four, and FIG. 2B shows a path decomposition process when the number of passes is eight. In any case, in order to simplify the explanation, the image reproduction data has a 1-bit configuration per dot. First, binarized data (image reproduction data) stored in the plane buffer PL-BUF is stored in raster order and line sequential.

  In the case of 4 passes in FIG. 2A, the line-sequential image reproduction data 40 is arranged as “12341234... In the case of a stored memory, “13411234” image reproduction data is stored in each byte. Here, “1” means the pixel data formed in the first pass, and “2”, “3”, and “4” mean the pixel data formed in the second, third, and fourth passes, respectively. To do. The line-sequentially arranged image reproduction data 40 is decomposed for each scanning path by the path decomposition process and stored in the byte buffer MW-BUF of the external memory in units of 1 byte. That is, only “11111111” is stored as the image reproduction data for the first pass, and the image reproduction data for the second pass, the third pass, and the fourth pass are also grouped as illustrated.

  The print head 10 has, for example, four nozzles NZ as illustrated. Then, while the print head 10 moves in the arrow direction indicating the scanning pass direction, ink is ejected from each nozzle to form dots. One raster (row) is printed when the print head 10 is scanned four times. Accordingly, when the print head 10 is in the first pass, the image reproduction data 42 of the first pass group is given to the print head. At this time, the image reproduction data 42 is converted into the order of the nozzles of the print head 10 instead of the raster order, and is given to the print head. In the example of FIG. 1 described above, the image reproduction data converted in the nozzle order is temporarily stored in the head buffer HD-BUF, and the stored data is given to the print head 10 by the head controller unit 36.

  In the case of 8 passes in FIG. 2B, the line sequential image reproduction data 44 is arranged as “12345678...” As shown, and the plane buffer PL-BUF is in units of 1 byte (8 bits). In the case of a stored memory, “12345678” image reproduction data is stored in each byte. The image reproduction data 44 is decomposed into eight groups by path decomposition and stored in a path buffer MW-BUF of the external memory. Thereafter, in accordance with eight scanning passes of the print head 10, the image reproduction data 46 grouped for each pass is given to the print head in the order of the nozzles of the print head.

  3 and 4 are configuration diagrams of the path decomposition processing unit in the present embodiment. The path decomposition processing unit 32 inputs the image reproduction data 40 and 44 in the plane buffer PL-BUF in units of 2 bytes (16 bits), and performs data rearrangement in accordance with the print mode signal 51 or a data arrangement that is not performed. A switching circuit 50, a time division buffer 52 for sequentially storing the output of 2 bytes, a time division buffer control unit 54 for controlling the time division buffer 52, and image reproduction from the time division buffer 52 in units of 4 bytes (32 bits) A path decomposition circuit 60 for inputting data, decomposing each path, and outputting 4-byte image reproduction data. As will be described later, the circuit of the path decomposition circuit 60 is switched according to the bit number signal 61 of the image reproduction data. Then, the path decomposition circuit 60 outputs the image reproduction data by decomposing into four paths by 1 byte (8 bits), and the image reproduction data 46 decomposed into the four paths is 1 byte in the path buffer MW-BUF. Stored in units. Thereafter, as described above, the nozzle order conversion unit 34 converts the nozzle order of the print head.

  3 and 4, the line-sequential image reproduction data 40 and 44 are input to the data rearrangement circuit 50 via the 16-bit bus every two bytes, where they are rearranged as necessary. Bit-rearranged image reproduction data is stored in the time division buffer 52 in units of 1 byte and data in a common path group, in this case 1 to 4 path groups or 5 to 8 path groups, in units of 4 bytes (32 bits). Are stored separately. That is, the data of the 1-4th pass group is stored in 4 bytes, and the data of the 5-8th pass group is stored in 4 bytes. Therefore, the time division buffer control unit 54 appropriately controls the write pointer WP of the buffer, and stores the rearranged image reproduction data in the time division buffer 52 continuously or separately. Write pointers for continuous storage are WP and WP + 1, and write pointers for separate storage are WP and WP + 4. As will be described later, when the data rearranged by the data rearrangement circuit 50 is data of different path groups in consecutive bytes, they are stored separately, and in the case of data of the same path group in consecutive bytes, continuous And stored. In the example of FIGS. 3 and 4, the number of scan passes is 4 when the number of scan passes is 4, and the number of scan passes is 8 and the number of scan passes is 8 separately.

  When the 4-byte image reproduction data is stored in the time-division buffer 52, the time-division buffer control unit 54 reads the 4-byte (32-bit) image reproduction data and supplies it to the path decomposition circuit 60 all at once. . The path decomposition circuit 60 decomposes the 4-byte image reproduction data into four paths and outputs 1-byte image reproduction data respectively. That is, since the path decomposition circuit 60 is a four-path decomposition circuit, the time-division buffer 52 separates the data of the 1-4 pass group into 4 bytes and the data of the 5-8 pass group into 4 bytes. These data are each decomposed into four paths by a path decomposition circuit.

  FIG. 3 shows a data rearrangement circuit 50 for three printing modes: 1 bit per dot in 4 passes, 2 bits per dot in 4 passes, and 2 bits per dot in 8 passes. In this case, the data rearrangement circuit 50 does not perform any rearrangement. On the other hand, FIG. 4 shows a data rearrangement circuit 50 for a printing mode of 1 bit per dot in 8 passes. In this case, the data rearrangement circuit 50 exchanges the second 4 bits and the third 4 bits as indicated by the broken line. Thereby, a part of the order of the 4-bit image reproduction data is rearranged. Switching between whether the data rearrangement circuit 50 is configured as a solid line or a broken line is performed by switch means that is conductively controlled according to the print mode signal 51.

  FIG. 5 is a diagram showing a data flow in the pass decomposition processing unit when the number of scan passes is 4 and the image reproduction data is 1 bit per dot. Since the line-sequential image reproduction data 40 is printed in four passes, the data is repeatedly arranged in the first to fourth scan passes. Since one bit per dot, one byte consists of 8 dots of data. In this case, the data rearrangement circuit 50 outputs the 16-bit image reproduction data 40 as it is without rearranging. In the time division buffer 52, data of 1 byte (8 bits) is continuously stored. That is, the upper 8 bits of the 16-bit image reproduction data are stored at the address of the write pointer WP, and the lower 8 bits are stored at the address of the write pointer WP + 1. In other words, since all 16-bit data is 1-4 pass data, it is stored in the time division buffer 52 continuously. Then, the first to fourth pass image reproduction data stored in the time division buffer 52 is supplied to the 4-pass decomposition circuit 60 by 4 bytes, decomposed into four paths, and decomposed into data of each path.

  FIG. 6 is a block diagram of a 4-pass decomposition circuit. In the 4-pass decomposition circuit, 32-bit input is decomposed into data of each path (1 to 4 paths) by a conduction switch indicated by a black circle in the figure, and becomes a 32-bit output. The 4-pass decomposition circuit shown in FIG. 6 is a circuit network when the number of bits per dot of image reproduction data is 1 bit. That is, the image reproduction data of “1 to 4 passes, 1 to 4 passes, 1 to 4 passes, and 1 to 4 passes (16 bits in total) for each 1 bit” is the first pass data and the second pass data. And the data of the third pass and the data of the fourth pass are bundled by 1 byte each. The bundled image reproduction data is stored byte by byte in the pass buffer M-BUF.

  FIG. 7 is a diagram showing a data flow in the pass decomposition processing unit when the number of scan passes is 4 and the image reproduction data is 2 bits per dot. In the line sequential image reproduction data 40, the data of the first to fourth scan passes are repeatedly arranged. Since the data is 2 bits per dot, 1 byte consists of 4 dots of data. That is, 16-bit data is “1-4, 1-4”. Also in this case, the data rearrangement circuit 50 supplies the input data as it is to the time division buffer 52 without rearranging. In the time division buffer 52, data of 1 byte (8 bits) is successively stored at the addresses of the write pointers WP and WP + 1. Then, when 4 bytes (32 bits) of data is stored, they are read out, input to the 4-pass decomposition circuit 60, and decomposed every four paths.

  FIG. 8 is another configuration diagram of the 4-pass decomposition circuit. This 4-path decomposition circuit is also decomposed into data of each path (1 to 4 paths) by a conduction switch indicated by a black circle in the figure with respect to a 32-bit input, and becomes a 32-bit output. This 4-pass decomposition circuit is a circuit network when the number of bits per dot of image reproduction data is 2 bits. That is, the image reproduction data of “2 bits 1 to 4 passes and 1 to 4 passes” includes the first pass data, the second pass data, the third pass data, and the fourth pass data. Each byte is bundled 1 byte. The bundled image reproduction data is stored byte by byte in the pass buffer M-BUF.

  As is apparent from the configuration diagrams of the 4-pass decomposition circuit in FIGS. 6 and 8, the position of the conduction switch differs depending on the number of bits of the image reproduction data. Therefore, in the 4-pass decomposition circuit, a switch element such as a transistor is provided at the position of the black circle in FIGS. 6 and 8 so that one of the switch elements is turned on according to the number of bits per dot of the input data. Be controlled.

  FIG. 9 is a diagram showing a data flow in the pass decomposition processing unit when the number of scan passes is 8 and the image reproduction data is 1 bit per dot. Since the line-sequential image reproduction data 44 is printed in 8 passes, the data of the scan passes 1 to 8 are repeatedly arranged. Since one bit per dot, one byte consists of 8 dots of data. In this case, the line-sequential image reproduction data 44 is composed of 1 to 4 passes and 5 to 8 passes. On the other hand, since the same circuit shown in FIG. 6 is used for the path decomposition circuit 60 and only four path decomposition can be performed, the data rearrangement circuit 50 causes the data in the first half of “5-8 paths” to be The 1-byte “1 to 4 pass” data is rearranged and supplied to the time division buffer 52. By this data rearrangement, the time division buffer 52 has the upper 1 byte (8 bits) of “1-4 pass, 1-4 pass” data and the lower 1 byte (8 bits) of “5-8 pass, "5-8 passes" data is input. Since the number of scan passes is 8 and the number of passes 4 that can be handled by the pass decomposition circuit 60 is exceeded, the time division buffer 52 is divided into “1 to 4 pass” data and “5 to 8 pass” data. Thus, upper and lower 1-byte data are stored at the addresses of the write pointers WP and WP + 4, respectively.

  Then, the data group 32 bits in the 1st to 4th paths is read from the time division buffer 52 and decomposed every 1 to 4 paths by the 4 path decomposition circuit 60, and each path 1 byte (8 bits) data 46 is obtained. Each path is stored in the path buffer MW-BUF. Next, the data group 32 bits of the 5th to 8th passes is read from the time division buffer 52, decomposed every 5 to 8 passes by the 4-pass decomposition circuit 60, and stored in the pass buffer MW-BUF for each pass. The

  The configuration of the path decomposition circuit 60 in this case is the same as that of the circuit network including the conduction switches in FIG. 6 because the number of bits per dot of data is 1 bit. In this way, by using the 4-pass decomposition circuit 60, 8-pass, 1-bit image reproduction data can be subjected to a path decomposition process.

  FIG. 10 is a diagram showing a data flow in the pass decomposition processing unit when the number of scan passes is 8 and the image reproduction data is 2 bits per dot. Since the line-sequential image reproduction data 44 is printed in 8 passes, the data of the 1st to 8th scan passes are repeatedly arranged as in FIG. However, since there are 2 bits per dot, 1 byte consists of 4 dots of data. In this case, the line-sequential image reproduction data 44 is composed of 1 to 4 passes and 5 to 8 passes. On the other hand, the same 4-path decomposition circuit shown in FIG. 8 is used as the path decomposition circuit 60. However, since the 16-bit image reproduction data 44 is already “1 to 4 pass” data in the upper 1 byte and “5 to 8 pass” in the lower 1 byte, the data rearrangement circuit 50 has the data Data is supplied to the time division buffer 52 without rearranging. Since the number of scan passes is 8 and the number of passes 4 that can be handled by the pass decomposition circuit 60 is exceeded, the time division buffer 52 is divided into “1 to 4 pass” data and “5 to 8 pass” data. Thus, one byte of data is stored at the addresses of the write pointers WP and WP + 4.

  Then, the data group 32 bits of the 1st to 4th passes and the data group 32 bits of the 5th to 8th passes are respectively read from the time division buffer 52 and decomposed for each pass by the 4-pass decomposition circuit 60. The data is stored in the path buffer MW-BUF as path 1 byte (8 bits) data 46 for each path. The configuration of the path decomposition circuit 60 in this case is the same as that of the circuit network including the conduction switches in FIG. 8 because the number of bits per dot of data is 2 bits. As described above, by using the 4-pass decomposition circuit 60, it is possible to perform path decomposition processing on 8-pass, 2-bit image reproduction data.

  FIG. 11 shows the number L of bits per dot of data, the M path decomposition circuit, whether or not the rearrangement is performed in the rearrangement circuit, and the write pointer of the time division buffer when the scan path number N is 4, 8, and 16. It is a chart which shows. As a premise, it is assumed that data is stored in the time division buffer every 1 byte (8 bits). The number of input buses to the data rearrangement circuit indicates both 16-bit and 32-bit cases, and data input in each case is indicated by a pass number.

  The case where the number of scanning passes N is 4, 8 and the number of data bits L is 1, 2 is as described above. In these cases, data rearrangement is required when the number of scan passes N is 8 and the number of data bits L is 1. Therefore, considering the case where the number of scanning passes N is 8 and the number of bits L is 4, 1 byte (8 bits) that can be stored in the buffer contains only data for 2 passes. , 4-pass decomposition circuit and 8-pass decomposition circuit can perform path decomposition. In other words, there is no need to rearrange the data.

  Further, considering the case where the number of scan passes N is 16, when the number of bits L of data is 1, one byte that can be stored in the buffer contains data for 8 passes. In the case of a 4-pass decomposition circuit, data rearrangement is required. However, when the number of bits L is 2, data for 4 passes is included in 1 byte, and data rearrangement is necessary in the case of a 2-pass decomposition circuit. When the number of bits L is 4, only 2 paths of data are included in 1 byte, and no data rearrangement is required for all path decomposition circuits. The same applies when the number of bits L is 8.

  The write pointer is WP, WP + 1 when the data path group of the data contained in 2 bytes is the same as a result of the data rearrangement, and can be continuously stored in the buffer, but the path group is different. , WP, WP + 4, and need to be separated and stored in the buffer.

  As understood from the chart of FIG. 11, when the number N of scanning passes of the image reproduction data exceeds the number of passes M of the path decomposition circuit (N> M), data rearrangement may be necessary, and N = <If M, no sorting is necessary. Further, since the time-division buffer stores data in units of 1 byte (8 bits), the number of data paths (8 / L) that can be included in the 1 byte exceeds the number of paths M of the path decomposition circuit. In some cases (8 / L> M), it is necessary to rearrange the data. However, if N = <M, no rearrangement is necessary. Therefore, the data rearrangement is necessary when 8 / L> M and N> M. However, if the number of bits stored in the time division buffer is different, the above condition is considered to be the number of bits instead of “8”.

  The path decomposition circuit controls the conduction state of the internal switch elements so that the circuit network configuration differs according to the number of bits L of data.

  As described above, according to the present embodiment, a common 4-pass decomposition circuit is used to pass 4-pass image reproduction data and 8-pass image reproduction data, or image reproduction data having other scanning passes. It can be decomposed. Further, by using a common 8-pass decomposition circuit, 4-pass, 8-pass, and 16-pass image reproduction data can be subjected to pass decomposition processing.

1 is a configuration diagram of an image forming apparatus in the present embodiment. It is a figure explaining the path | pass decomposition | disassembly process in this Embodiment. It is a block diagram of the path | pass decomposition | disassembly processing unit in this Embodiment. It is a block diagram of the path | pass decomposition | disassembly processing unit in this Embodiment. FIG. 6 is a diagram showing a data flow in a pass decomposition processing unit when the number of scanning passes is 4 passes and the image reproduction data is 1 bit per dot. It is a block diagram of a 4-pass decomposition circuit. It is a figure which shows the data flow in the pass decomposition | disassembly processing unit in case the number of scan passes is 4 passes and image reproduction data is 2 bits per bit. It is a block diagram of a 4-pass decomposition circuit. FIG. 6 is a diagram illustrating a data flow in a pass decomposition processing unit when the number of scanning passes is 8 passes and the image reproduction data is 1 bit per dot. FIG. 6 is a diagram showing a data flow in a pass decomposition processing unit when the number of scan passes is 8 passes and image reproduction data is 2 bits per dot. FIG. 11 is a chart showing the number of data bits L, the presence / absence of rearrangement, and the write pointer of the time division buffer when the number of scan passes N is 4, 8, and 16.

Explanation of symbols

44: Image reproduction data (line sequential) 50: Data rearrangement circuit 52: Time division buffer 54: Time division buffer control means 60: Path decomposition circuit 46: Path decomposed data

Claims (5)

In an image forming apparatus that prints one line by a plurality of scanning passes of a print head,
A path decomposition processing unit that decomposes the image reproduction data arranged in a line sequential manner for each scanning pass of the print head;
The image reproduction data decomposed for each scanning pass is given to the print head according to the print head structure,
The path decomposition processing unit includes: a data rearrangement circuit that decomposes the line-sequentially arranged image reproduction data into groups of image reproduction data corresponding to a common scan path group and having a predetermined number of bits; and the data rearrangement unit A time division buffer for storing the output of the circuit in units of 1 byte, and a path decomposition for decomposing image reproduction data having a predetermined number of bits decomposed by the data rearrangement circuit for each scanning path in the common scanning path group A circuit ,
The number of scan passes is N (N is an integer),
Each of the image reproduction data is composed of L bits (L is an integer),
The path decomposition circuit is a circuit for decomposing the image reproduction data having the predetermined number of bits every M scan passes,
The data rearrangement circuit rearranges the line-sequentially arranged image reproduction data for each of M scanning pass groups when 8 / L> M and the number of scanning passes N exceeds M, and An image forming apparatus that is not rearranged in other cases . In claim 1 ,
2. An image forming apparatus according to claim 1, wherein image reproduction data having the predetermined number of bits stored in the time division buffer is input to the path decomposition circuit for each scan path group. In claim 1 ,
When the image reproduction data output from the rearrangement circuit has data of different path groups in consecutive bytes, the image reproduction data output from the rearrangement circuit is separated into different path group areas of the buffer memory. If the continuous bytes have the same path group data, the image reproduction data output from the rearrangement circuit is continuously written in the area corresponding to the same path group in the buffer memory, and the time-division buffer An image forming apparatus comprising buffer control means for outputting image reproduction data of the same path group to the path decomposition circuit. In any one of Claims 1 thru | or 3 ,
The path decomposition circuit is a switch circuit network that connects the input of the predetermined number of bits and the output of the predetermined number of bits by a switch group corresponding to the path decomposition, and according to the number of bits of the image reproduction data, An image forming apparatus having different switch groups. In any one of Claims 1 thru | or 4 ,
The image forming apparatus further comprises a head rearrangement processing unit for rearranging the image reproduction data decomposed for each scanning pass by the path decomposition circuit according to a head structure.

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