JP2009098552A - Electro-optical device, driving method, and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the irregularity of display when driving data lines by a demultiplexer system. <P>SOLUTION: The 720 columns of data lines 114 are blocked at each nine-column corresponding to a demultiplexer 50. Sub-pixels 110 are provided corresponding to intersections of scanning lines 112 and the data lines 114, have gradations corresponding to voltages applied to the data line 114 when the scan line is selected, and are arranged for each data line 114 in an order of RGB. The demultiplexer 50 selects nine data lines in a predetermined order for a period when the scan line is selected by one row and distributes them to the data line that selects data signals fed to the input end. One demultiplexer 50 selects data lines in a block in an order as follows: first, fourth, seventh, second, fifth, eighth, third, sixth and ninth column. That is, the demultiplexer 50 selects RGB in an order in the block and selects in an order in a right direction, three data lines that belongs to a color selected. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a technique for driving a data line using a demultiplexer.

For example, in electronic devices such as a mobile phone and a navigation system, display images are becoming higher definition. High definition can be achieved by increasing the number of pixels by increasing the number of rows of scanning lines and the number of columns of data lines, but connection with a display panel becomes a problem at that time. For example, in the case of performing color display with vertical 320 × horizontal 240 pixels, a total of 720 columns of data lines for 240 × 3 colors are required in the horizontal direction of the display panel, but if the display image size is small, the data The line pitch falls below the limit of COG (chip on glass) or the like, and an X driver (data line driving circuit) that supplies a data signal to each data line cannot be connected.

For this reason, in the display panel, for example, 720 columns of data lines are blocked every three columns, and three columns of data signals belonging to each block are time-divided over a period in which a selection voltage is applied to a certain row of scanning lines. And a method of selecting and supplying three columns of data lines in each block one column at a time using a demultiplexer has been proposed (see, for example, Patent Document 1).
In this method, when the elements constituting the demultiplexer are formed by a process common to the pixel switching elements in the display panel, the number of input terminals of the demultiplexer becomes 1/3 of the number of data lines, and the connection pitch is relaxed. It becomes easy to mount the driver on the display panel.
In Patent Document 1, the scanning line is divided into two blocks.
Japanese Patent Laid-Open No. 2001-343946 (see, for example, FIG. 1)

By the way, in recent years, high definition of the screen has been remarkably increased. For this reason, the number of data lines to be blocked becomes “3”, and a configuration of 4 or more, for example, “6”, “9”, “12”,. However, when the number of data lines to be blocked is 4 or more, it has been pointed out that the display quality is lowered.
The present invention has been made in view of the above-described circumstances, and one of the objects thereof is an electro-optical device that suppresses degradation in display quality when four or more data lines are driven by using a demultiplexer. An apparatus, a driving method, and an electronic apparatus are provided.

In order to achieve the above object, a driving method of an electro-optical device according to the present invention includes a plurality of scanning lines, a plurality of data lines blocked for m (m is an integer of 4 or more), and the plurality of data lines. Are provided corresponding to the intersection of the plurality of data lines and each of the plurality of data lines, and each has a gradation corresponding to a voltage applied to the data line when the scanning line is selected, and n (n is n <m satisfying n <m) corresponding to each of the sub-pixels that are one of the colors, a scanning line driving circuit that selects the plurality of scanning lines in a predetermined order, and each of the blocks Each of the demultiplexers is provided for selecting m data lines belonging to one block in a predetermined order and distributing a data signal supplied to an input terminal to the selected data lines over a period in which the scanning lines are selected. And the selected scanning line and each block And a data line driving circuit for supplying a data signal having a voltage corresponding to the gradation of the sub-pixel corresponding to the intersection with the data line of the selected column to the input terminal of the demultiplexer. A driving method, wherein the demultiplexer includes:
In the period in which the scanning line is selected, data lines corresponding to sub-pixels of the same color among the sub-pixels positioned on the selected scanning line are continuously selected. According to the present invention, since the data lines corresponding to the sub-pixels of the same color are continuously selected, the difference in leakage after selection is reduced and the display difference is suppressed.

Here, in the present invention, m is a multiple of n, and the sub-pixels positioned on the selected scanning line are repeatedly arranged in a predetermined order from the first color to the n-th color. The first color to the nth color may be selected in order, and m / n data lines belonging to the selected color may be selected in order. If comprised in this way, the display difference about each color of n color can be suppressed.
In this configuration, in the two demultiplexers adjacent to each other, when the m / n data lines belonging to the selected color are viewed at the block boundary of the two demultiplexers, the data lines corresponding to the sub-pixels of the same color are displayed. It may be selected in a symmetric relationship. If it does in this way, it will become possible to suppress the display nonuniformity when comparing between adjacent blocks.
In the present invention, two demultiplexers adjacent to each other may be configured to select data lines adjacent to each other across the block boundary of the two demultiplexers and corresponding to subpixels of the same color in the same period. . Even with such a configuration, it is possible to suppress display unevenness when compared between adjacent blocks.
The present invention can be conceptualized not only as a method for driving an electro-optical device, but also as an electro-optical device and also as an electronic apparatus having the electro-optical device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
FIG. 1 is a diagram illustrating a configuration of an electro-optical device to which the driving method according to the first embodiment of the present invention is applied.
As shown in this figure, the electro-optical device 1 is roughly divided into a control circuit 10, a scanning line driving circuit 20, a data line driving circuit 30 and a display panel 100.
Among these, in the display panel 100, although not particularly illustrated, the element substrate and the counter substrate are bonded together with a certain gap so that the electrode forming surfaces face each other, and liquid crystal is sealed in the gap. It has become. Note that a scanning line driving circuit 20 and a data line driving circuit 30 which are semiconductor chips are mounted on the element substrate by a COG (chip on glass) technique or the like. Various control signals are supplied from the control circuit 10 to the scanning line driving circuit 20, the data line driving circuit 30, and the display panel 100 via an FPC (flexible printed circuit) substrate or the like.

  The display panel 100 performs predetermined display using liquid crystal, and is divided into a region where the demultiplexer 50 is formed and a region where display is performed. In the display area, 320 rows of scanning lines 112 are provided so as to extend in the horizontal (X) direction, and 720 columns of data lines 114 are provided in the vertical direction (Y direction) in the drawing. Sub-pixels 110 are provided so as to correspond to the intersections of the scanning lines 112 and the data lines 114, respectively.

The sub-pixels 110 are repeatedly arranged in the order of R (red), G (green), and B (blue) for each column, and one sub-pixel of RGB is adjacent to each other in the X direction. Color representation of pixels. Therefore, in the present embodiment, when the sub-pixels 110 are regarded as a unit in the display panel 100, they are arranged in a matrix of 320 vertical rows × 720 horizontal columns, but when viewed as pixels that are units of color display, the vertical 320 rows × horizontal. It will be arranged in 240 columns. The present invention is not intended to be limited to this arrangement.
Further, in the present embodiment, the data lines 114 of 1 to 720 columns are divided into blocks every 9 columns adjacent to each other, that is, every output of a demultiplexer 50 described later. In this embodiment, since the number of columns of the data line 114 is “720”, the number of blocks is “80”.
For convenience, in order to generalize and describe the block, if an integer “j” of 1 to 80 is used, the j-th block from the left in FIG. 9j) Nine columns of data lines up to the column belong, and these data lines respectively correspond to RGBRGBRGB colors.

A configuration of the sub-pixel 110 will be described. FIG. 2 is a diagram showing an electrical configuration of the sub-pixel 110, and shows three RGB sub-pixels 110 in an arbitrary row.
As shown in this figure, the three sub-pixels 110 are electrically identical to each other, and each has an n-channel thin film transistor (hereinafter simply referred to as “TFT”) 116 and a liquid crystal capacitor 120. And have.
Among these, the gate electrode of the TFT 116 is connected to the scanning line 112, the source electrode thereof is connected to the data line 114, and the drain electrode thereof is connected to the pixel electrode 118. As described above, in the display panel 100, the element substrate and the counter substrate are bonded to each other with a certain gap, the pixel electrode 118 is provided on the element substrate, and the common electrode 108 is provided on the counter substrate. Yes. Since liquid crystal is sealed in the gap between the element substrate and the counter substrate, the liquid crystal capacitor 120 is configured by sandwiching the liquid crystal between the pixel electrode 118 and the common electrode 108. The common electrode 108 is common to all the sub-pixels 110, and a voltage Vcom that is constant in time is applied in the present embodiment.

  In the present embodiment, when the liquid crystal capacitor 120 is a transmissive type, a color filter (not shown) that colors transmitted light is provided. Here, the transmittance of light passing between the pixel electrode 118 and the common electrode 108 is the minimum value (darkest state) if the effective value of the voltage held in the liquid crystal capacitor 120 is zero, As the effective value increases, the normally black mode in which the transmittance gradually increases is set. For this reason, the light irradiated by the backlight unit (not shown) is emitted by being colored by the color filter at a ratio corresponding to the effective value of the voltage held in the liquid crystal capacitor 120 for each sub-pixel.

In the sub-pixel 110 having such a configuration, when the scanning line 112 becomes a voltage Vdd (selection voltage) equal to or higher than the threshold value and corresponding to the H level, the source / drain electrode of the TFT 116 is turned on. . In this ON state, a higher (positive polarity) or lower (negative polarity) voltage than the voltage Vcom applied to the common electrode 108 is supplied to the data line 114 by a voltage corresponding to the gradation (brightness). Then, since the voltage is applied to the pixel electrode 118 of the sub-pixel via the TFT 116, the voltage applied to the pixel electrode 118 and the applied voltage Vcom to the common electrode 108 are applied to the liquid crystal capacitor 120. The differential voltage will be charged.
When the scanning line 112 falls below the threshold and becomes a voltage zero (non-selection voltage) corresponding to the L level, the source / drain electrodes of the TFT 116 are turned off (off), but when the TFT 116 is turned on. The voltage charged in the liquid crystal capacitor 120 is held as it is.
Therefore, the liquid crystal capacitor 120 holds an effective value corresponding to the voltage difference between the voltage applied to the pixel electrode 118 and the applied voltage Vcom to the common electrode 108 when the TFT 116 is in an on state. The transmittance (brightness) according to the value.

Note that the voltage applied to the common electrode 108 may be switched to the higher and lower sides instead of being constant over time. The liquid crystal capacitor 120 can also be applied to an IPS (in plain switching) mode in which the direction of the electric field applied to the liquid crystal is the substrate surface direction, or an FFS (fringe field switching) mode which is a modification thereof.
Further, since the liquid crystal deteriorates when a direct current component is applied to the liquid crystal, the voltage (data signal voltage) to be applied to the pixel electrode 118 with respect to the voltage Vcom of the common electrode 108 is alternately switched between a high level and a low level. For this reason, the voltage polarity (write polarity) of the pixel electrode 118 is positive when it is higher than the voltage Vcom, and negative when it is lower. As described above, the write polarity is based on the voltage Vcom. However, unless otherwise specified, the ground potential Gnd corresponding to the L level of the logic level is used as the reference for the voltage zero.
Regarding how to change the writing polarity of the sub-pixels arranged in a matrix for one frame period, for each scanning line (row inversion), for each data line (column inversion), for each sub-pixel (dot inversion) There are various types such as for each frame (frame inversion), and any of them can be applied. However, in this embodiment, polarity inversion for each frame is used for convenience of explanation.

Returning to FIG. 1, the scanning line driving circuit 20 scans the scanning lines 112 in the first, second, third, fourth,..., 320th row in this order in the horizontal scanning period (H). A pulse-shaped scanning signal that is H level is supplied to the selected scanning line 112 over the horizontal scanning period (H). For convenience, the scanning signals supplied to the scanning lines 112 in the 1, 2, 3, 4,..., 320th row are denoted as Y1, Y2, Y3, Y4,.
In the case of general description without specifying a particular row, if Y is expressed using i, these scanning signals are as shown in FIG.

The control circuit 10 controls the scanning line driving circuit 20 and a data line driving circuit 30 described later, and outputs the following selection signal. Specifically, as shown in FIG. 3, the control circuit 10 selects the selection signals Sel-R1, Sel- over a period T obtained by dividing the horizontal scanning period (H) in which the scanning lines 112 for one row are selected into nine. R2, Sel-R3, Sel-G1, Sel-G2, Sel-G3, Sel-B1, Sel-B2, and Sel-B3 are exclusively set to H level in this order and output. Note that (1) to (9) are written in order from the start of the horizontal scanning period (H) in order to distinguish the period in which the selection signal is at the H level.

The data line driving circuit 30 outputs a data signal having a voltage corresponding to the gradation of the sub-pixel 110 corresponding to the intersection of the scanning line 112 selected by the scanning line driving circuit 20 and the nine columns of data lines 114 belonging to each block. According to the control by the control circuit 10, the time-division output is performed. For convenience, the data signals output corresponding to the 1st to 80th blocks are denoted as d1 to d80, and the data signals output corresponding to each block are generally specified without specifying the block number. In the following description, j is used to denote dj.
As shown in FIG. 4, the data line driving circuit 30 sends the data signal dj to the periods (1), (2), (in the horizontal scanning period (H) in which the i-th scanning line 112 is selected. 3) A voltage corresponding to the gray level of the R sub-pixel 110 in the i row (9j-8) column, the i row (9j-5) column, and the i row (9j-2) column in order over the period (4), A voltage corresponding to the gradation of the G sub-pixel 110 in the i row (9j-7) column, i row (9j-4) column, i row (9j-1) column in order over (5) and (6), Over the periods (7), (8), and (9), depending on the gray level of the G sub-pixel 110 in the i row (9j-6) column, i row (9j-3) column, and i row (9j) column in order. Voltage.

  Although details of the data line driving circuit 30 are omitted, for example, before the i-th scanning line is selected, data indicating the gradation of the pixel located in the i-th row for each RGB is obtained. One row is latched, and the latched data is sub-pixel color and position of the data line selected in the periods (1) to (9) in the horizontal scanning period (H) in which the i-th scanning line is selected. For example, a configuration may be considered in which output is sequentially performed in accordance with the voltage and converted into a positive or negative voltage to be supplied.

As shown in FIG. 4, the voltage of the data signal dj in the horizontal scanning period (H) is the brightest state from the voltage Vb (+) corresponding to the darkest state in the normally black mode in the case of positive writing. In the range up to the voltage Vw (+) corresponding to, in the case of negative polarity writing, in the range from the voltage Vb (−) corresponding to the darkest state to the voltage Vw (−) corresponding to the brightest state, respectively. The voltage having a difference corresponding to the gradation of the sub-pixel from the voltage Vcom of the common electrode 108. In FIG. 4, the voltage corresponding to the difference in gradation is indicated by ↑ for positive polarity and ↓ for negative polarity.
The positive voltage Vw (+) and the negative voltage Vw (-) are respectively centered on the voltage Vcom,
They are symmetrical to each other. The same applies to the positive voltage Vb (+) and the negative voltage Vb (-). The vertical scale of the voltage of the data signal dj in FIG. 4 is enlarged compared to the voltage waveform of a logic signal such as a scanning signal or a selection signal.

On the other hand, each of the 720 columns of data lines 114 is provided with a TFT 52. The TFT 52 constitutes a demultiplexer 50 that distributes the data signal output from the data line driving circuit 30 to any of the nine columns of data lines 114 belonging to the block.
Specifically, the source electrodes of the nine TFTs 52 constituting the j-th demultiplexer 50, that is, the nine TFTs 52 belonging to the j-th block, are connected in common, and this common connection portion is input to the demultiplexer. A data signal dj from the data line driving circuit 30 is supplied as an end, and each drain electrode is connected to one end of the data line 114.
Of the nine TFTs 52 belonging to the j-th block, the drain electrode is connected to the data line 114 of the (9j-8) -th column, the (9j-5) -th column, and the (9j-2) -th column. The gate electrode of the TFT 52 is connected to signal lines to which selection signals Sel-R1, Sel-R2, and Sel-R3 are supplied in order. Similarly, of the nine TFTs 52 belonging to the same block, the three TFTs 52 whose drain electrodes are connected to the data lines 114 in the (9j-7) th column, the (9j-4) th column, and the (9j-1) th column. Are sequentially connected to signal lines to which selection signals Sel-G1, Sel-G2, and Sel-G3 are supplied, and drain electrodes are in the (9j-6) th column, (9j-3) th column, ( 9j) The gate electrodes of the three TFTs 52 connected to the data line in the column are sequentially connected to the signal lines to which the selection signals Sel-G1, Sel-G2, and Sel-G3 are supplied. For example, among the nine TFTs 52 belonging to the second block, the data line 114 whose drain electrode is in the eleventh column is j = 2 and is the data line in the (9 · 2-7) column. The gate electrode is connected to a signal line to which a selection signal Sel-G1 is supplied.
In this description, regarding the column number of the data line 114, the first column to the 720th column of the display panel 100 is counted regardless of the block, and the first column is focused on only within one block. From the first column to the ninth column, there are two ways of counting from the first column to the ninth column, but unless otherwise noted, the display panel 100 is counted from the first column to the 720th column.

Next, the operation of the electro-optical device 1 will be described. 3 and 4 are timing charts for explaining the operation.
First, as shown in FIG. 3, the scanning signals Y1 to Y320 are exclusively at the H level in order for each horizontal scanning period (H) over the period of each frame. Here, the period of the frame is a period required to select the scanning lines 112 of 1 to 320 rows, and is about 16.7 milliseconds (reciprocal of 60 Hz).
In order to generalize the scanning signals Y1 to Y320 without specifying a row, the horizontal scanning period (H) in which the scanning line 112 of the i-th row is selected and the scanning signal Yi is at the H level will be described.
As shown in the figure, the control circuit 10 selects the selection signals Sel-R1 to Sel-R3, Sel-G1 to Sel-G3, Sel- in the periods (1) to (9) of the horizontal scanning period (H). B1 to Sel-B3 are set to H level exclusively in order.

Here, the data line driving circuit 30 has a horizontal scanning period (H) in which the scanning signal Yi is at the H level.
In the period (1) when the selection signal Sel-R1 is at the H level, R corresponding to the intersection of the scanning line 112 in the i-th row and the data line 114 in the 1, 10, 19,. The data signals d1, d2, d3,..., D80 having a voltage corresponding to the gradation of the sub-pixel 110 and having either a positive or negative voltage, for example, a positive voltage in this case, are output. As a result, the data signal dj output corresponding to the j-th block has the i-th scanning line 112 and the (9j-8) -th column data line as shown in FIG. 4 in the period (1). R corresponding to intersection with 114
A positive voltage (i, 9j-8) corresponding to the gray level of the sub-pixel 110 is obtained.

In the period (1), when the selection signal Sel-R1 becomes H level, the leftmost of the data lines 114 in the 1, 10, 19,..., 712 columns, that is, the R data lines in three columns in each block. Between the source and drain electrodes of the TFT 52 corresponding to the data line 114 located at is turned on. Therefore, the data signals d1 to d80 are passed through the TFTs 52 that are turned on,
In the 1st to 80th blocks, each of the 3 rows of R data lines is supplied to the R data line 114 located at the leftmost end.
When the scanning signal Yi is at the H level, the TFTs 116 are turned on in all the sub-pixels 110 located in the i-th row, so that the pixel electrode 118 is connected to the data line 114. For this reason, in each block, a positive voltage corresponding to the gradation is applied to the pixel electrode 118 of the sub-pixel 110 located at the left end among the three R sub-pixels in the i-th row. The

Next, in the horizontal scanning period (H) in which the scanning signal Yi is at the H level, the data line driving circuit 30 performs the data signals d1, d2, d3 during the period (2) in which the selection signal Sel-R2 is at the H level. ,
.., D80 is a positive voltage corresponding to the gradation of the R sub-pixel 110 corresponding to the intersection of the scanning line 112 in the i-th row and the data line 114 in the 4, 13, 22,. To do. Thus, the data signal dj output corresponding to the j-th block is R corresponding to the intersection of the i-th scanning line 112 and the (9j-5) -th data line 114 in the period (2). The positive voltage (i, 9j-5) according to the gray level of the sub-pixel 110 is obtained.
When the selection signal Sel-R2 becomes H level in the period (2), the source / drain electrodes of the TFT 52 corresponding to the data line 114 located in the center among the three R data lines in each block are turned on. become. Therefore, the data signals d1 to d80 are supplied to the R data line 114 located at the center among the R data lines in three columns in the 1st to 80th blocks via the TFTs 52 that are turned on. Therefore, in each block, a positive voltage corresponding to the gradation is applied to the pixel electrode 118 of the sub-pixel 110 located in the center among the three R sub-pixels in the i-th row.

Subsequently, in the data line driving circuit 30, the horizontal scanning period (H) in which the scanning signal Yi is at the H level.
Among these, in the period (3) when the selection signal Sel-R3 is at the H level, the data signals d1, d2, d3
,..., D80 is a positive voltage corresponding to the gradation of the R sub-pixel 110 corresponding to the intersection of the scanning line 112 in the i-th row and the data line 114 in the 7, 16, 25,. And Thus, the data signal dj output corresponding to the j-th block is R corresponding to the intersection of the i-th scanning line 112 and the (9j-2) -th column data line 114 in the period (3). The positive voltage (i, 9j-2) according to the gray level of the sub-pixel 110 is obtained.
In the period (3), when the selection signal Sel-R3 becomes H level, the source / drain electrodes of the TFT 52 corresponding to the data line 114 located on the rightmost side among the R data lines in three columns in each block are turned on. It becomes a state. For this reason, the data signals d1 to d80 are supplied to the R data line 114 positioned at the right end among the R data lines in three columns in the 1st to 80th blocks, respectively, via the TFTs 52 that are turned on. Accordingly, in each block, a positive voltage corresponding to the gradation is applied to the pixel electrode 118 of the sub-pixel 110 located at the right end among the three R sub-pixels in the i-th row. .

As described above, in the periods (1) to (3), the positive voltage corresponding to the gradation is sequentially applied to the pixel electrodes 118 in the three R sub-pixels 110 in each block.
Next, in the periods (4) to (6), the selection signals Sel-G1 to Sel-G3 sequentially become H level, and in order for the pixel electrodes 118 in the three G sub-pixels 110 in each block, A positive voltage corresponding to the gradation is applied.
In the following periods (7) to (9), the selection signals Sel-B1 to Sel-B3 become H level in order,
In each block, positive voltages corresponding to gradations are sequentially applied to the pixel electrodes 118 in the three B sub-pixels 110.

Here, the writing operation for one row of pixels located on the i-th scanning line 112 has been described. However, in practice, the scanning signals Y1 to Y320 sequentially become H level over a period of one frame. The writing operation for one pixel row is executed in the order of the first, second, third,.
In the next frame, a similar writing operation is executed in the order of the first, second, third,..., 320th rows. At this time, the writing polarity for the liquid crystal is reversed, that is, positive polarity in the previous frame. If there is, it is inverted to negative polarity in the next frame. As a result, the writing polarity with respect to the liquid crystal capacitor 120 is such that the holding voltage is inverted (AC drive) for each frame, so that deterioration of the liquid crystal due to application of a DC component is prevented.

By the way, in the horizontal scanning period (H), after the TFT 52 is turned on in each block and a data signal is supplied and then the TFT 52 is turned off, the data line 114 connected to the drain electrode of the turned off TFT 52 has a high impedance. It becomes a state. Since the data line 114 has a resistance as well as a parasitic capacitance, when the data line 114 is in a high impedance state, the voltage of the data signal, that is, a voltage corresponding to the gradation, gradually decreases to approach the ground potential Gnd due to leakage. Here, the voltage fluctuation due to leakage increases as the period of high impedance state increases.
On the other hand, when the voltage drops when the data line 114 is in a high impedance state, if the scanning signal is at the H level, the TFT 116 is turned on, so that the voltage fluctuation of the data line due to leakage is applied to the pixel electrode 118. Directly affects the voltage.
Here, the voltage applied to the pixel electrode 118 (the voltage held in the liquid crystal capacitor 120) is the timing at which the TFT 116 changes from on to off, that is, the horizontal scanning period (H ), And the voltage of the data line 114 at the timing when the scanning signal Yi changes from H to L level.
For this reason, when comparing the 9 lines of data lines in each block in the horizontal scanning period (H), the data line selected earlier in time has a larger voltage fluctuation due to leakage. It will deviate from the voltage according to the supplied gradation.

In this embodiment, the first data line selected in the horizontal scanning period (H) is the R data line 114 in the first column in each block, and the second selected data line is in each block. The R data line 114 in the fourth column, the third selected data line is the R data line 114 in the seventh column in each block, and the R data line is continuous in the horizontal scanning period (H). Are selected in order. For this reason, when the three data lines 114 corresponding to the R sub-pixel 110 are viewed from each other, the difference in the period of the high impedance state is suppressed to 1T.
The fourth, fifth, and sixth data lines selected in the horizontal scanning period (H) are the G data lines 114 in the second, fifth, and eighth columns in each block in order, and the G data lines are Selected sequentially in order. Therefore, when the three data lines 114 corresponding to the G sub-pixel 110 are viewed from each other, the difference in the period in which the high-impedance state is set is suppressed to 1T.
Similarly, the seventh, eighth, and ninth data lines selected in the horizontal scanning period (H) are the B data lines 114 in the third, sixth, and ninth columns in each block in order, and the B data lines are Selected sequentially in order. For this reason, when the three data lines 114 corresponding to the B sub-pixel 110 are viewed from each other, the difference in the period of the high impedance state is suppressed by 1T.

FIG. 6 shows the period in which the data lines in each column are in a high impedance state when 1 to 9 columns of data lines in the first block are taken in the horizontal direction and the time axis is taken in the vertical direction. It will be shown. In this figure, the square frames R1, R2, and R3 indicate that the TFT 52 is in an ON state by selection signals Sel-R1, Sel-R2, and Sel-R3, respectively.
Similarly, the square frames of G1, G2, G3, B1, B2, and B3 are selected signals Sel-G1,
Sel-G2, Sel-G3, Sel-B1, Sel-B2, and Sel-B3 indicate that the TFT 52 is on.

On the other hand, conventionally, the configuration is as shown in FIG. 11, and the selection signals Sel-R1 to Sel-R3, Sel-G1 to Sel-G3, and Sel-B1 to Sel-B3 are as shown in FIG. Had been supplied. That is, conventionally, the order of the data lines selected in the block in the horizontal scanning period (H) is 1, 2, 3, 4, 5, 6, 7, 8, 9th column, When viewed, the order was RGBRGBRGB. For this reason, as shown in FIG. 13, for example, when viewed with the R data line, the period during which the data line in the first column is in the high impedance state is 8T from (2) to (9). The period when the data lines in the 4th and 7th columns are in a high impedance state is 5T from (5) to (9), 2T from (8) and (9), respectively, and is different by 3T. Become. For this reason, as shown in FIG. 14, the voltage of the R data line in the first, fourth, and seventh columns is the end timing of the horizontal scanning period (H) even if the voltage of the data signal is the same. When viewed, they are different as indicated by a, b, and c, respectively, and the difference in voltage is visually recognized as display unevenness, thereby degrading display quality.
Here, the first, fourth, and seventh columns that are the R data lines have been described. However, as shown in FIG. 13, the second, fifth, and eighth columns that are the G data lines and the B data lines. A similar phenomenon occurs in the third, sixth, and ninth columns.

In contrast, in the present embodiment, the data lines 114 are selected in the order of the first, fourth, second, fifth, eighth, third, sixth, and ninth columns in each block in the horizontal scanning period (H). . For this reason, the order is RRRGGGBBB when viewed in color. Therefore, as shown in FIG. 5, for example, when viewed with the R data line, the period during which the first column data line is in the high impedance state in the block is 8T from (2) to (9). So far, it is the same as the conventional case, but the period when the data lines in the 4th and 7th columns are in the high impedance state is 7T from (3) to (9), and from (4) to (9), respectively. 6T, and only 1T is different.
As described above, the three R data lines in the first, fourth, and seventh columns in the same block are selected earlier in time in the horizontal scanning period (H). However, the difference in the period of the high impedance state is 1T in the first and fourth columns, and 1T in the fourth and seventh columns. For this reason, since the difference between the voltage fluctuations is small, it is difficult to visually recognize the difference in display.
The same applies to the G data lines in the second, fifth, and eighth columns and the B data lines in the third, sixth, and ninth columns in the same block, and the data lines of the same color are in a high impedance state. Since the period differences are 1T and 1T, respectively, it is difficult to visually recognize the difference in display. In this way, in this embodiment, it is possible to suppress a decrease in display quality.

In the first embodiment, one display pixel is expressed by three colors of RGB, and n is described as “3”. However, for example, emerald green (Eg) is added to add one display pixel to four.
It may be expressed in color. In other words, n may be “4”, or another color may be added or “4” or more.
In the first embodiment, the number m of data lines constituting one block has been described as “9” which is a multiple of “3” which is n. Here, when m is larger than n, there are always two or more data lines corresponding to the sub-pixels of the same color in the m columns of data lines constituting one block. If the data lines are continuously selected, display unevenness at least for the color can be suppressed.

In the first embodiment, the data lines selected in the same block have the color order RRRGGGBBB. However, the color order is not limited to this. However, when the color order is changed, the order of the data lines selected by the demultiplexer 50 is also changed, so that the data line driving circuit 30 outputs data signals in the changed order of the data lines. There is a need.

Second Embodiment
As described above, in the first embodiment, the data lines of the same color in the same block are in a relationship in which the difference in the period of the high impedance state differs by 1T as viewed in the horizontal direction.
However, in the first embodiment, when the same color data lines are viewed in different blocks, there may be a problem of a period difference in a high impedance state as shown in FIG. More specifically, since the R data line in the seventh column in the first block is selected by the selection signal Sel-R3, the period in which the high impedance state is 6T is 6T. Since the R data line of the 10th column (the first column in the second block) that belongs to the same color and is adjacent is selected by the selection signal Sel-R1, the period of high impedance state is 8T. The period difference is 2T.
While the difference in the period in which the R data lines in the same block are in the high impedance state is 1T in order, the period in which the R data line is in the high impedance state on the basis of the boundary of the different blocks The difference is, for example, 2T in the seventh and tenth rows, and this difference may be visually recognized as display unevenness. Although R has been described here, display irregularities at the block boundaries also occur in G and B in the same manner.
Therefore, a second embodiment for suppressing display unevenness that occurs at the block boundary will be described next.

FIG. 8 is a diagram illustrating a configuration of the electro-optical device 1 according to the second embodiment.
The second embodiment shown in this figure is different from the first embodiment shown in FIG. 1 in the connection destination of the gate electrode of the TFT 52 connected to the data line 114 belonging to the even-numbered block. Specifically, when j is an even number, nine TFTs 52 from the (9j-8) -th column to the (9j) -th column correspond to the even-numbered j-th block. The gate electrodes of the three TFTs 52 connected to the data line 114 in the 9j-2) th column, the (9j-5) th column, and the (9j-8) th column are in turn selected by the selection signals Sel-R1, Sel-R2, Sel. -R3 is connected to each supply signal line. Similarly, of the nine TFTs 52 belonging to the same block, the three TFTs 52 whose drain electrodes are connected to the data line 114 of the (9j-1) th column, the (9j-4) th column, and the (9j-7) th column. Are respectively connected to signal lines to which selection signals Sel-G1, Sel-G2, and Sel-G3 are supplied, and the drain electrode is in the (9j) -th column and (9j-3).
) The gate electrodes of the three TFTs 52 connected to the data line of the column and the (9j-6) column are respectively connected to the signal lines to which the selection signals Sel-G1, Sel-G2, and Sel-G3 are supplied. ing.
The connection destination of the TFT 52 in the odd-numbered block is the same as that in the first embodiment.

In the second embodiment, the selection signals Sel-R1 to Sel-R3, Sel-G1 to Sel-G3, and Sel-B1 to Sel-B3 are the same as those in the first embodiment. In the first block, the first, fourth, and seventh columns are selected, whereas in the even-numbered block, the seventh, fourth, and first columns are selected. Similarly, when viewed in G color, the odd-numbered blocks are selected in the order of the second, fifth, and eighth columns, while the even-numbered blocks are selected in the order of the eighth, fifth, and second columns. In the case of B color, the third, sixth, and ninth columns are selected in the odd-numbered block, whereas the ninth, sixth, and third columns are selected in the even-numbered block. That is, in the second embodiment, the odd-numbered and even-numbered blocks adjacent to each other have a relationship in which the selection order of the three data lines belonging to the same color is opposite to each other.
As described above, the data line driving circuit 30 needs to output data signals in the order of the data lines selected in each block.

As described above, when the selection order of the three data lines belonging to the same color is reversed, as shown in FIG. 9, the period of the period in which the R data lines in the same block are in the high impedance state is set. The difference is 1T in order, and the periods in which the R data lines are in the high impedance state are equal to each other with reference to the boundaries of different blocks, so that display unevenness due to leakage can be suppressed. Although R has been described here, display unevenness can be similarly suppressed for G and B.

  In addition, in the second embodiment, from the viewpoint of suppressing display unevenness that occurs at the boundary between adjacent blocks, adjacent to each other with the boundary between odd-numbered and even-numbered blocks adjacent to each other and the same color sub It is sufficient to select the TFT 52 of the data line corresponding to the pixel in the same period.

<Applications / Modifications>
In the above description, the reference of the writing polarity is the voltage Vcom applied to the common electrode 108. This is a case where the TFT 116 functions as an ideal switch. In practice, the gate / drain electrode of the TFT 116 is used. Due to the parasitic capacitance between them, a phenomenon that the potential of the drain electrode (pixel electrode 118) decreases when the state changes from on to off (referred to as push-down, punch-through, or field-through) occurs. In order to prevent deterioration of the liquid crystal, the liquid crystal capacitor 120 must be AC driven. However, when AC driving is performed with the applied voltage Vcom applied to the common electrode 108 as a reference for writing polarity, negative polarity writing is performed for pushdown. As a result, the effective voltage value of the liquid crystal capacitor 120 is slightly larger than the effective value due to the positive polarity writing (when the TFT 116 is n-channel). For this reason, in actuality, the reference voltage of the write polarity and the voltage Vcom of the common electrode 108 are separated, and more specifically, the reference voltage of the write polarity is set to the voltage Vcom so that the influence of pushdown is offset. Alternatively, the offset may be set to a higher position.

In the above-described embodiment, each data line 114 has a stripe arrangement corresponding to RGB. However, if the sub-pixels corresponding to the selected scanning line are arranged in RGB, the RGB arrangement for each row is changed. It can also be applied to shifted mosaic types and delta types.
Furthermore, although the liquid crystal capacitor 120 has been described as a normally black mode in the embodiment, it may be a normally white mode in which white display is performed when no voltage is applied, and is not limited to a transmissive type, a reflective type, An intermediate transflective type may be used.
In addition, the present invention can be applied to all configurations in which a data signal having a voltage corresponding to a gradation is sequentially supplied to the data line 114 that is blocked using the demultiplexer 50. For this reason, the sub-pixel is not limited to one using a liquid crystal element, and can be applied to one using an EL (Electronic Luminescence) element, an electron-emitting element, an electrophoretic element, or the like.

<Electronic equipment>
Next, an electronic apparatus having the electro-optical device 1 according to the above-described embodiment as a display device will be described. FIG. 10 is a diagram illustrating a configuration of a mobile phone 1200 using the electro-optical device 1 according to the embodiment.
As shown in this figure, a cellular phone 1200 includes the electro-optical device 1 described above, together with a plurality of operation buttons 1202, an earpiece 1204 and a mouthpiece 1206. Note that components of the electro-optical device 1 other than the portion corresponding to the display panel 100 do not appear as appearance.
As an electronic apparatus to which the electro-optical device 1 is applied, in addition to the mobile phone shown in FIG. 10, a digital still camera, a photo storage, a laptop computer, a liquid crystal television, a viewfinder type (or a monitor direct view type) ) Video recorders, car navigation devices, pagers, electronic notebooks, calculators, word processors, workstations, videophones, POS terminals, devices equipped with touch panels, and the like. Needless to say, the above-described electro-optical device 1 is applicable as a display device of these various electronic devices.

1 is a diagram illustrating a configuration of an electro-optical device according to a first embodiment of the invention. FIG. It is a figure which shows the structure of the sub pixel in the same electro-optical apparatus. It is a figure which shows operation | movement of the same electro-optical apparatus. It is a figure which shows an example of the voltage waveform of the data signal in the same electro-optical apparatus. It is a figure which shows the voltage leak in the same electro-optical apparatus. It is a figure which shows the voltage leak in the same electro-optical apparatus. It is a figure which shows the problem assumed by the same electro-optical apparatus. FIG. 6 is a diagram illustrating a configuration of an electro-optical device according to a second embodiment of the invention. It is a figure which shows the voltage leak in the same electro-optical apparatus. It is a figure which shows the structure of the mobile telephone to which the electro-optical apparatus which concerns on embodiment is applied. It is a figure which shows the structure of the electro-optical apparatus which concerns on a prior art example. It is a figure which shows operation | movement of the electro-optical apparatus which concerns on a prior art example. It is a figure which shows the voltage leak in the electro-optical apparatus which concerns on a prior art example. It is a figure which shows the voltage leak in the electro-optical apparatus which concerns on a prior art example.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Electro-optical apparatus, 10 ... Control circuit, 20 ... Scan line drive circuit, 30 ... Data line drive circuit, 52, 116 ... TFT, 100 ... Display panel, 108 ... Common electrode, 110 ... Subpixel, 112 ... Scan line , 114 ... data line, 118 ... pixel electrode, 120 ... liquid crystal capacitor, 1200 ... mobile phone

Claims (6)

A plurality of scan lines;
a plurality of data lines blocked for each m (m is an integer of 4 or more);
Provided corresponding to the intersection of the plurality of scanning lines and the plurality of data lines, each having a gradation corresponding to a voltage applied to the data line when the scanning line is selected, and n ( n is an integer of 3 or more that satisfies n <m), and a sub-pixel that is one of the colors;
A scanning line driving circuit for selecting the plurality of scanning lines in a predetermined order;
Provided corresponding to each of the blocks, each of which selects m data lines belonging to one block in a predetermined order and selects a data signal supplied to the input terminal over a period in which the scanning line is selected. A demultiplexer that distributes data to the selected data line;
A data line driving circuit for supplying a data signal having a voltage corresponding to the gradation of the sub-pixel corresponding to the intersection of the selected scanning line and the data line of the column selected in each block to the input terminal of the demultiplexer When,
An electro-optical device driving method comprising:
The demultiplexer
A driving method for an electro-optical device, wherein data lines corresponding to sub-pixels of the same color among sub-pixels positioned on the selected scanning line are continuously selected during a period in which the scanning line is selected. . m is a multiple of n,
The sub-pixels positioned on the selected scanning line are repeatedly arranged in a predetermined order from the first color to the n-th color,
2. The electro-optic according to claim 1, wherein the demultiplexer sequentially selects a first color to an nth color and sequentially selects m / n data lines belonging to the selected color. Device driving method. In two demultiplexers adjacent to each other,
The data lines corresponding to sub-pixels of the same color are selected in a symmetrical relationship when m / n data lines belonging to the selected color are viewed at the block boundary of the two demultiplexers. Item 3. A driving method of an electro-optical device according to Item 2. The two demultiplexers adjacent to each other select data lines that are adjacent to each other across the block boundary of the two demultiplexers and that correspond to sub-pixels of the same color in the same period. Driving method of the electro-optical device. A plurality of scan lines;
a plurality of data lines blocked for each m (m is an integer of 4 or more);
Provided corresponding to the intersection of the plurality of scanning lines and the plurality of data lines, each having a gradation corresponding to a voltage applied to the data line when the scanning line is selected, and n ( n is an integer of 3 or more that satisfies n <m), and a sub-pixel that is one of the colors;
A scanning line driving circuit for selecting the plurality of scanning lines in a predetermined order;
Each of the blocks is provided corresponding to each of the blocks, and each of the m data lines belonging to the block is a data line corresponding to at least one sub-pixel of the n colors over a period in which the scanning line is selected. A demultiplexer that sequentially selects the data signals supplied to the input terminals and distributes the data signals to the selected data lines;
A data line driving circuit for supplying a data signal having a voltage corresponding to the gradation of the sub-pixel corresponding to the intersection of the selected scanning line and the data line of the column selected in each block to the input terminal of the demultiplexer When,
An electro-optical device comprising:   An electronic apparatus comprising the electro-optical device according to claim 5.

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