JP2008233454A - Electrooptical device, driving method, driving circuit, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce display unevenness caused in data line units when data lines are driven by a demultiplexer system. <P>SOLUTION: Data lines 114 are grouped by three columns of R, G, and B. TFTs 52 are provided for the respective data lines 114, and have source electrodes connected in common by groups and drain electrodes connected to the data lines 114. In a horizontal scanning period wherein one row of the scan lines 112 is selected, data lines 114 of a B series are selected in order and then data lines of an R series selected firstly and data line of a G series selected secondary are selected again to turn on TFTs 51 having drain electrodes connected to the selected data lines 114. An X driver 30 outputs signals, having voltages corresponding to gradations of sub-pixels corresponding to intersections of the selected scan lines and data lines of columns selected for the respective groups, to the respective groups. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a technique for driving a data line using a demultiplexer.

In recent years, for example, in display devices such as mobile phones and navigation systems, display images have become higher definition. High definition can be achieved by increasing the number of pixels by increasing the number of rows of scanning lines and the number of columns of data lines, but connection with a display panel becomes a problem at that time. For example, when performing color display of 320 × 240 pixels, a total of 720 columns of data lines for 240 × 3 colors are required in the horizontal direction of the display panel. However, if the display image size is small, the data The line pitch falls below the limit of COG (chip on glass) or the like, and it becomes impossible to connect an X driver that supplies a data signal to each data line.
Therefore, in the display panel, 720 columns of data lines are grouped, for example, every three columns, and three columns of data signals belonging to each group are time-divided over a period in which a selection voltage is applied to a certain scanning line. A method has been proposed in which, in addition to supplying, three columns of data lines in each group are selected and supplied one by one by a demultiplexer (see, for example, Patent Document 1). In this method, when the elements constituting the demultiplexer are formed by a process common to the pixel switching elements in the display panel, the number of input terminals of the demultiplexer becomes 1/3 of the number of data lines, and the connection pitch is relaxed. It becomes easy to mount the driver on the display panel.
Note that Patent Document 1 describes an example in which the number of input terminals of a demultiplexer is ½ of the number of data lines.
Japanese Patent Laid-Open No. 6-138851 (see, for example, FIG. 1)

By the way, in this method, the data lines that have been selected in each group are in a state where they are not electrically connected to any part (high impedance state). Since the data line itself has a voltage holding property due to various parasitic capacitances, etc., the data line holds the voltage state immediately before entering the high impedance state. However, the data line itself has the wiring resistance and the adjacent data line. The held voltage fluctuates due to leakage caused by a potential difference or the like. If the data line fluctuates from the voltage corresponding to the gradation by selection during the period in which the selection voltage is applied to the scanning line, the pixel corresponding to the data line cannot be displayed at the target gradation. Inconvenience occurs.
The present invention has been made in view of the above-described circumstances, and an object of the present invention is to drive an electro-optical device that suppresses voltage fluctuation of the data line as much as possible when the data line is driven using a demultiplexer. It is to provide a method, a driving circuit, and an electronic apparatus.

In order to achieve the above object, a driving method of an electro-optical device according to the present invention includes a plurality of scanning lines, a plurality of data lines grouped for each m (m is an integer of 2 or more) columns, Provided corresponding to the intersection of the plurality of rows of scanning lines and the plurality of columns of data lines, each having a gradation corresponding to the voltage of the data lines when a selection voltage is applied to the scanning lines. Each of the plurality of columns of data lines, one end of which is connected in common to each group, and the other end of which is connected to the data line. A method for driving an optical device, wherein at least selected data lines of m columns belonging to each group are selected in a predetermined order over a period in which the selection voltage is applied to one scanning line of the plurality of rows. Transistor corresponding to the data line After making one end and the other end conductive, the first data line in the order is selected again, and one end and the other end of the transistor corresponding to the selected data line are made conductive, and the one scan is performed. A data signal having a voltage corresponding to a gray level of a pixel corresponding to an intersection of a line and a data line of a column selected in each group is supplied to one end of transistors commonly connected in each group. To do. The voltage fluctuation of the data line becomes large in the data line selected first among the m columns of data lines in each group. However, according to the present invention, after the selection of the m lines of data lines is completed. Since the data signal corresponding to the gradation is supplied again to the first selected data line, fluctuations from the voltage corresponding to the gradation can be suppressed to a minimum.

In the present invention, the first data line in the order is selected again, and one end and the other end of the transistor corresponding to the selected data line are made conductive, and then the second data line in the order is selected again. Then, one end and the other end of the transistor corresponding to the selected data line may be made conductive.
In the present invention, among the m columns of data lines belonging to each group, the first data line selected in the above order may be rotated every predetermined period.
The present invention can be conceptualized not only as a method for driving an electro-optical device, but also as a drive circuit, an electro-optical device, and an electronic apparatus having the electro-optical device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>
FIG. 1 is a diagram illustrating a configuration of an electro-optical device to which the driving method according to the first embodiment of the present invention is applied.
As shown in this figure, the electro-optical device 1 is roughly divided into a control circuit 10, a Y driver 20, an X driver 30 and a display panel 100.
Among them, in the display panel 100, although not particularly shown, the element substrate and the counter substrate are bonded together with a certain gap so that the electrode forming surfaces face each other, and liquid crystal is sealed in the gap. It has become. Note that a Y driver 20 and an X driver 30 which are semiconductor chips are mounted on the element substrate by COG technology or the like. Various control signals are supplied from the control circuit 10 to the Y driver 20, the X driver 30, and the display panel 100 via an FPC (flexible printed circuit) substrate or the like.

The display panel 100 is divided into a region where a demultiplexer or the like is formed and a region where display is performed. In the display area, in this embodiment, 320 scanning lines 112 are provided so as to extend in the row (X) direction, and 720 (= 240 × 3) columns grouped every three columns. The data lines 114 are provided so as to extend in the column (Y) direction and to be electrically insulated from each scanning line 112.
The sub-pixels (pixels) 110 are provided so as to correspond to the intersections of the scanning lines 112 in 320 rows and the data lines 114 in 720 columns. Of these, the three sub-pixels 110 corresponding to the intersections of the scanning lines 112 in the same row and the three columns of data lines 114 belonging to the same group are R (red), G (green), and B (blue), respectively. Yes, one dot is represented by these three sub-pixels 110. Therefore, in the present embodiment, the sub-pixels 110 are arranged in a matrix form of 320 rows × 720 columns. In terms of display dots, color display of 320 vertical rows × 240 horizontal columns is performed.

Here, for the sake of convenience, in order to generalize and describe the dot row (group), if an integer “j” of 1 to 240 is used, the (3j−2) -th row counting from the left in FIG. 3j-2
) And (3j) -th column data lines 114 belong to the j-th block, and are R, G, and B series.

  A configuration of the sub-pixel 110 will be described with reference to FIG. FIG. 2 is a diagram showing an electrical configuration of the sub-pixel 110, and the three sub-pixels 110 corresponding to the intersection of the i-th scanning line 112 and the three columns of data lines 114 belonging to the j-th group. The configuration of is shown. Note that “i” is a symbol for generally indicating a row in which the sub-pixels 110 are arranged (row of the scanning line 112), and is an integer of 1 to 320 in the present embodiment.

As shown in FIG. 2, the three sub-pixels 110 are electrically identical to each other, and each has an n-channel thin film transistor (hereinafter simply referred to as “TFT”) 116 and a liquid crystal capacitor 120. And a storage capacitor 130.
Among these, the gate electrode of the TFT 116 is connected to the i-th scanning line 112, the source electrode is connected to the data line 114, and the drain electrode is connected to the pixel electrode 118 that is one end of the liquid crystal capacitor 120. Yes.
The other end of the liquid crystal capacitor 120 is connected to the common electrode 108. The common electrode 108 is common to all the sub-pixels 110 in the display panel 100, and a voltage Vcom that is constant in time is applied in the present embodiment. Since the common electrode 108 is formed on the counter substrate and faces the pixel electrode 118 via the liquid crystal, the liquid crystal capacitor 120 has a configuration in which the liquid crystal 105 is sandwiched between the pixel electrode 118 and the common electrode 108.
Each sub-pixel 110 is provided with a corresponding color, that is, any one of R, G, and B color filters, and the liquid crystal capacitor 120 changes its transmittance according to the effective value of the held voltage. To do. For example, in the present embodiment, the liquid crystal capacitor 120 is set to a normally white mode in which the amount of transmitted light increases as the effective voltage value decreases.

In the sub-pixel 110 having such a configuration, when the scanning line 112 in the i-th row becomes a voltage Vdd (selection voltage) equal to or higher than the threshold value, the source / drain electrodes of the TFT 116 are turned on. In this ON state, for example, compared with the voltage Vcom applied to the common electrode 108 on the data line 114 in the (3j-2) th column, the gradation (brightness) for the R subpixel in the i-th row (3j-2) column. When a high level (positive polarity) or low level (negative polarity) voltage is supplied in accordance with the voltage corresponding to (a), the voltage is applied to the pixel electrode 118 of the sub-pixel via the TFT 116, so that the liquid crystal capacitance 120 is charged with a voltage difference between a voltage applied to the pixel electrode 118 and a voltage Vcom applied to the common electrode 108.
When the scanning line 112 in the i-th row becomes zero voltage (non-selection voltage) that is lower than the threshold value, the source / drain electrodes of the TFT 116 become non-conductive (off), but when the TFT 116 is in the on-state, the liquid crystal capacitance The voltage charged to 120 is held as it is.
Therefore, the liquid crystal capacitor 120 holds an effective value corresponding to the voltage difference between the voltage applied to the pixel electrode 118 and the applied voltage Vcom to the common electrode 108 when the TFT 116 is in an on state. The transmittance (brightness) according to the value.

Further, when the TFT 116 is turned off, the off-resistance is not ideally infinite, so that the charge accumulated in the liquid crystal capacitor 120 leaks not a little. In order to reduce the leakage in the off state, the following storage capacitor 130 is formed for each sub-pixel. That is, one end of the storage capacitor 130 is connected to the pixel electrode 118 (the drain electrode of the TFT 116), while the other end is commonly connected to the capacitor line over all subpixels. In the present embodiment, since the capacitor line is kept at the same voltage Vcom as the common electrode 108, the liquid crystal capacitor 120 and the storage capacitor 130 are eventually connected to the drain electrode of the TFT 116, as shown in FIG. This is equivalent to a configuration in which the power supply line of the voltage Vcom is connected in parallel.
The voltage of the capacitor line may be different from the voltage LCcom to the common electrode. In addition, the voltage applied to the common electrode and the voltage of the capacitor line may be switched to the higher and lower sides instead of being constant over time.
Further, as the liquid crystal capacitor 120, an IPS (in.
The present invention can also be applied to a plain switching) mode and a modified FFS (fringe field switching) mode.

Further, since a deterioration occurs when a direct current component is applied to the liquid crystal 105, the voltage (data signal voltage) to be applied to the pixel electrode 118 with respect to the voltage Vcom of the common electrode 108 is alternately switched between a high level and a low level. For this reason, the voltage polarity (write polarity) of the pixel electrode 118 is positive when it is higher than the voltage Vcom, and negative when it is lower. As described above, the write polarity is based on the voltage Vcom. However, unless otherwise specified, the ground potential Gnd corresponding to the L level of the logic level is used as the reference for the voltage zero.
Regarding how to change the writing polarity of the sub-pixels arranged in a matrix for one frame period, for each scanning line (row inversion), for each data line (column inversion), for each sub-pixel (dot inversion) There are various types such as for each frame (frame inversion), and any of them can be applied. However, in this embodiment, polarity inversion for each frame is used for convenience of explanation.

Returning to FIG. 1, the Y driver 20 scans the scanning lines 112 in the first, second, third, fourth,..., 320th row in this order for each horizontal scanning period (H) according to the control by the control circuit 10. This is a scanning line driving circuit that selects and supplies a pulsed scanning signal that becomes H level in a period narrower than the horizontal scanning period (H) to the selected scanning line 112. Here, the ground potential Gnd is zero voltage corresponding to the L level of the scanning signal, and the voltage corresponding to the H level is Vdd.
For convenience, the scanning signals supplied to the scanning lines 112 in the first, second, third, fourth,..., 320th rows are denoted as G1, G2, G3, G4,. In a general description, when i is used to represent Gi as described above, these scanning signals are as shown in FIG.

The control circuit 10 outputs selection signals Sel-R, Sel-G, and Sel-B as follows in the horizontal scanning period (H) in which one row of scanning lines 112 is selected. Specifically, as shown in FIG. 3, the control circuit 10 at a timing t1 before the scanning signal Gi becomes H level in the horizontal scanning period (H) in which the i-th scanning line 112 is selected. After the selection signals Sel-R, Sel-G, and Sel-B are set to H level, the selection signals Sel-R, Sel-G, and Sel-B are sequentially reset to L level at timings t2, t3, and t4. Then, the selection signal Sel-R is set to H level again from timing t5 to t6, and the selection signal Sel-G is set to H level again from timing t7 to timing t8 before the scanning signal Gi becomes L level. To do.

The X driver 30 uses the control circuit 10 to generate a data signal of a voltage corresponding to the gradation of the sub-pixel 110 corresponding to the intersection of the scanning line 112 selected by the Y driver 20 and the three columns of data lines 114 in each block. According to the control, it is output in the following order. For convenience, the data signals output corresponding to the 1st to 240th blocks are denoted as d1 to d240, and the data signals output corresponding to each block are generally specified without specifying the block number. In the following description, j is used to denote dj.
At this time, as shown in FIG. 3, the X driver 30 outputs the data signal dj over the period from timing t1 to t2 in the horizontal scanning period (H) in which the i-th scanning line 112 is selected. (3j-2) The voltage according to the gradation of the R subpixel in the column, and the voltage according to the gradation of the G subpixel in the i row (3j-1) column over the period from the timing t2 to t3,
The voltage corresponding to the gray level of the B subpixel in the i row (3j) column over the period from the timing t3 to t4, and the R subpixel in the i row (3j-2) column again over the period from the timing t5 to t6. The voltage is determined according to the gray level of the G sub-pixel in the i row (3j-1) column again over the period from the timing t7 to t8.

If the voltage of the data signal dj in the horizontal scanning period (H) is positive writing, the voltage Vw (+) corresponding to the brightest state from the voltage Vb (+) corresponding to the darkest state in the normally white mode. In the case of negative writing, the voltage Vb (−) corresponding to the darkest state to the voltage Vw (−) corresponding to the brightest state is subtracted from the voltage Vcom of the common electrode 108, respectively. The voltage has a difference corresponding to the gradation of the pixel.
In FIG. 3, the voltage corresponding to the difference in gradation is indicated by ↑ for positive polarity and ↓ for negative polarity. Here, (i, j-R) means the R of the line corresponding to the intersection of the i-th scanning line and the R-series data line in the j-th block, that is, the (3j-2) -th column data line. It means the difference voltage according to the gradation of the sub-pixel. Similarly, (i, j-G) means the G sub-line corresponding to the intersection of the i-th scanning line and the G-series data line in the j-th block, that is, the (3j-1) -th column data line. The difference voltage according to the gradation of the pixel means (i, j−B) is the i-th scanning line and the B-series data line in the j-th block, that is, the (3j) -th column data line. This means a difference voltage corresponding to the gradation of the B sub-pixel corresponding to the intersection.
The positive voltage Vw (+) and the negative voltage Vw (−) are centered on the voltage Vcom, respectively.
They are symmetrical to each other. The same applies to the positive voltage Vb (+) and the negative voltage Vb (-). Further, the vertical scale of the voltage of the data signal dj in FIG. 3 is enlarged as compared with the voltage waveform of the logic signal such as the scanning signal or the selection signal. The same applies to FIGS. 4 and 7 described later.

On the other hand, each of the 720 columns of data lines 114 is provided with a TFT 52.
The TFT 52 (transistor) distributes the data signal output from the X driver 30 to the three columns of data lines 114 belonging to the block, and constitutes a demultiplexer.
Specifically, the three TFTs 52 belonging to the j-th block have their source electrodes connected in common to the data signal output end of the X driver 30 and their drain electrodes connected to one end of the data line 114. In each block, the gate electrode of the R series TFT 52 is connected to a signal line for supplying a selection signal Sel-R, and the gate electrodes of the G and B series TFTs 52 supply selection signals Sel-G and Sel-B. Is connected to each signal line.
When the X driver 30 is COG-mounted on the display panel 100, the connection point between the two is a portion indicated by a circle in FIG.

Next, the operation of the electro-optical device 1 will be described. 3 and 4 are timing charts for explaining the operation.
First, as shown in FIG. 3, the scanning signals G1 to G320 are exclusively at the H level in order for each horizontal scanning period (H) over the period of each frame. Here, the period of the frame is a period required to select the scanning lines 112 of 1 to 320 rows, and is about 16.7 milliseconds (reciprocal of 60 Hz).
In order to generalize the scanning signals G1 to G320 without specifying a row, a horizontal scanning period (H) in which the i-th scanning line 112 is selected will be described. As shown in FIG. 10 changes the logic levels (voltages) of the selection signals Sel-R, Sel-G, and Sel-B as described above over the horizontal scanning period (H).

Here, in the horizontal scanning period (H) in which the i-th scanning line 112 is selected, during the period from the timing t1 to t2 when the selection signals Sel-R, Sel-G, and Sel-B are at the H level. The X driver 30 sends the data signal dj corresponding to the j-th block to the i-th scanning line 112 and j
The voltage corresponds to the gradation of the R sub-pixel 110 corresponding to the intersection with the R-series data line 114 in the second block, and is set to one of positive polarity and negative polarity. The voltage of the sex.
When the selection signals Sel-R, Sel-G, and Sel-B become H level in the period from the timing t1 to t2, the source in all the TFTs 52 corresponding to the R, G, and B series data lines 114 in each block -The drain electrode is turned on. For this reason, in the j-th block, the voltage data signal dj corresponding to the gray level of the R-series sub-pixels in the i-th row and the j-th block has three columns belonging to the j-th block. The data lines 114 are respectively supplied.
Therefore, as shown in FIG. 4, the R, G, and B series data lines 114 are in the gray level of the R sub-pixels in the i-th row and j-th block in the period from timing t1 to t2. Are respectively charged to voltages (i, j-R).
In the figure, the initial state of the data line before the timing t1 is set to the voltage Vcom for convenience. Further, after timing t1, the scanning signal Gi becomes H level.

Next, when the selection signal Sel-R changes to L bell at timing t2, the TFT 52 corresponding to the R series data line 114 is turned off, so that the R series data line 114 is electrically connected to any portion. High impedance state that is not performed.
In the period from the timing t2 to the timing t3, the X driver 30 crosses the data signal dj corresponding to the jth block with the i-th scanning line 112 and the G-series data line 114 in the jth block. And a positive voltage corresponding to the gradation of the G sub-pixel 110 corresponding to.
In the period from timing t2 to t3, the selection signals Sel-G and Sel-B are continuously at the H level, so that the TFTs 52 corresponding to the G and B series data lines 114 in each block are turned on. Therefore, in the j-th block, the voltage data signal dj corresponding to the gray level of the G-series sub-pixel in the j-th block in the i-th block is G, B belonging to the j-th block. The data lines 114 are supplied to the column data lines 114, respectively.
Therefore, as shown in FIG. 4, the R series data line 114 in the high impedance state starts to change from the charged voltage (i, j−R) starting at the timing t 2, and G , B series data lines are respectively charged to voltages (i, j−G) corresponding to the gray levels of the G sub-pixels in the i-th row and the j-th block.

When the selection signal Sel-G changes to L bell at timing t3, the G series data line 1
Since the TFT 52 corresponding to 14 is turned off, the data line 114 is in a high impedance state.
In the period from the timing t3 to t4, the X driver 30 crosses the data signal dj corresponding to the jth block with the i-th scanning line 112 and the B-series data line 114 in the jth block. A positive voltage corresponding to the gradation of the B sub-pixel 110 corresponding to.
In the period from timing t3 to t4, since the selection signal Sel-B is continuously at the H level, the TFT 52 corresponding to the B-series data line 114 in each block is turned on. Therefore, in the j-th block, the voltage data signal dj corresponding to the gray level of the B-series sub-pixel in the j-th block in the i-th block is the B column belonging to the j-th block. It is supplied only to the data line 114.
Therefore, as shown in FIG. 4, the voltage of the R-series data line 114 continues to change from the timing t2, and the G-series data line changes the timing from the charged voltage (i, j-G). The data lines of the B series are charged to voltages (i, j−B) corresponding to the gray levels of the G sub-pixels in the j-th block, respectively, starting from t3. .

When the selection signal Sel-B changes to L bell at timing t4, the B-series data line 1
Since the TFT 52 corresponding to 14 is also turned off, all the data lines 114 are in a high impedance state.
Here, the R series data line 114 is at the timing t2, and the G series data line 11
4 is already in a high-impedance state at timing t3, and thus is away from the voltage corresponding to the gradation. Since the scanning signal Gi is at the H level, the voltage fluctuation of the data line 114 affects the voltage written in the liquid crystal capacitor 120 of the R and G series sub-pixels in the i-th row.

Therefore, in the present embodiment, the control circuit 10 sets the selection signal Sel-R to the H level again during the period from the timing t5 to t6, and the X driver 30 outputs the data signal dj corresponding to the jth block. Let it be voltage (i, j-R) again. As a result, as shown in FIG. 4, the R-series data line 114 is charged to the voltage (i, j−R) again in the period from the timing t5 to t6.
Subsequently, in a period from timing t7 to t8, the control circuit 10 sets the selection signal Sel-G to the H level again, and the X driver 30 again applies the data signal dj corresponding to the jth block to the voltage (i, j-G). As a result, as shown in the figure, the G-series data line 114 is charged to the voltage (i, j-G) again in the period from the timing t7 to t8.
At timing t8, the selection signals Sel-R, Sel-G, and Sel-B become L level and all the data lines 114 are in a high impedance state, and then the scanning signal Gi becomes L level.

Here, the write operation has been described for the three sub-pixels corresponding to the j-th block. However, in the period in which the logic signal Gi is at the H level, the i-th row is 1, 2, 3,
... The same writing operation is executed in parallel for the sub-pixels 110 corresponding to the 240th block.
Although the writing operation for one row of pixels located on the i-th scanning line 112 has been described here, the scanning signals G1 to G320 sequentially become H level over a period of one frame. The writing operation for one pixel row is executed in the order of the first, second, third,..., 320th rows.
In addition, in the next frame, the same writing operation is executed in the order of the first, second, third,..., 320th row, but at this time, the writing polarity with respect to the liquid crystal is reversed, that is, in the previous frame. If it is positive, it is reversed to negative polarity in the next frame. As a result, the writing polarity for the liquid crystal capacitor 120 is such that the holding voltage is inverted (AC drive) for each frame, so that deterioration of the liquid crystal 105 due to application of a DC component is prevented.

The scanning signal Gi becomes H level after the timing t1 in the horizontal scanning period (H) in which the i-th scanning line 112 is selected, whereby all the i-th TFTs 116 are turned on, and at the timing t8. Later, it becomes L level, and this causes the TFT 11 in the i-th row.
All 6 will be turned off.

Since the voltage applied to the pixel electrode 118 (the voltage held in the liquid crystal capacitor 120) is determined by the voltage of the data line 114 immediately before the TFT 116 is turned off, the scanning signal Gi is changed from H to L.
If the voltage of the data line in the high impedance state is away from the voltage corresponding to the gradation at the timing of changing to the level, the sub-pixel cannot be displayed in the intended gradation.
If the R and G series data lines 114 are not selected again in the horizontal scanning period (H), as shown in FIG. 7, the R series data lines 114 are scanned until the scanning signal Gi becomes L level. Since the period of the high impedance state is longer than that of the B-series data line, the deviation (ΔV) from the voltage (i, j−R) corresponding to the gradation is increased. The period of the high impedance state of the B series data line 114 is also short compared to the R series data line, but is long compared to the B series data line. j-
The deviation from B) is slightly larger.
For this reason, if the R and G series data lines 114 are not selected again, it becomes impossible to display the target gradation for the R and G (particularly R) series sub-pixels.

On the other hand, in the present embodiment, at the timing when the scanning signal Gi becomes L level, R
The series data line 114 has a voltage (i, j−R) corresponding to the gradation by reselection. Similarly, the G series data line 114 has a voltage (i, j− G) is almost reached. The B-series data line 114 has a voltage (i, j-B) almost corresponding to the gradation because it is shortly after the timing t4 at which the high-impedance state is entered.
For this reason, in this embodiment, at the timing when the scanning signal Gi becomes L level, R,
The G and B series data lines 114 can be displayed at almost the intended gradation because fluctuations from the voltage corresponding to the gradation are both kept extremely small.

Second Embodiment
In the first embodiment described above, in the horizontal scanning period (H), the data lines are selected in the order of the R, G, and B series, and the selection is canceled earliest in time and the high impedance state is entered. A series data line is selected again. However, in this configuration, while the R and G sequences are reselected, the B sequence is not reselected, and the high impedance period after reselection is also between the reselected R and G sequences. The R series is longer than the G series. For this reason, the order in which the difference from the voltage corresponding to the gradation increases is fixed in the order of the B, R, and G series, which easily causes display unevenness.
Therefore, in the second embodiment, such display unevenness is intended to be eliminated by rotating this order.

The electro-optical device according to the second embodiment is structurally the same as that in FIG. 1, but the waveforms of the selection signals Sel-R, Sel-G, and Sel-B output from the control circuit 10 are the first embodiment. Changed from That is, in the second embodiment, three patterns shown in FIG. 5 are prepared as waveforms of the selection signals Sel-R, Sel-G, and Sel-B, and the control circuit 10 replaces them with a predetermined cycle. It has become.
Specifically, the control circuit 10 outputs the selection signals Sel-R, Sel-G, and Sel-B as shown in FIG. 5A in each horizontal scanning period (H) of a certain two frames. Output is performed in the same pattern as in the embodiment, and positive polarity writing and negative polarity writing are executed in these two frames. Thereafter, in each horizontal scanning period (H) of the next two frames, the selection signals Sel-R, Sel-G, and Sel-B are used as the selection signal Sel-R as shown in FIG. The selection signal Sel-B of (a) is output as the selection signal Sel-G, the selection signal Sel-R of (a) is output, and the selection signal Sel-G of (a) is output as the selection signal Sel-B, respectively. In addition, the positive polarity writing and the negative polarity writing are executed in these two frames. Thereafter, in each horizontal scanning period (H) of the following two frames, the selection signals Sel-R, Sel-G, and Sel-B are selected as the selection signal Sel-R as shown in (c) of FIG. The selection signal Sel-B of b) is output as the selection signal Sel-G, the selection signal Sel-R of (b) is output, and the selection signal Sel-G of (b) is output as the selection signal Sel-B, respectively. The positive polarity writing and the negative polarity writing are executed in these two frames.

When the selection signal is output in the pattern of FIG. 5A, the X driver 30 is selected in the periods t1 to t2, t2 to t3, t3 to t4, t5 to t6, and t7 to t8. A data signal having a voltage corresponding to the gray level of the sub-pixel corresponding to the intersection of the data lines of the series of R, G, B, R, and G is output, that is, as in the first embodiment. The data signal is output to. When the selection signal is output in the pattern of FIG. 5B, the X driver 30 is selected in the periods t1 to t2, t2 to t3, t3 to t4, t5 to t6, and t7 to t8. 5C, a data signal having a voltage corresponding to the gradation of the sub-pixel corresponding to the intersection with the data line of the series G, B, R, G, B is output. In the case where the selection signal is output in the period t1-t2, t2-t3, t3-t4, t5-t6, t7-t8, the selected scanning lines are respectively B, R, G, B , R, a voltage data signal corresponding to the gradation of the sub-pixel corresponding to the intersection with the data line of the series is output.

As a result, in the second embodiment, the patterns shown in FIGS. 5A, 5B, and 5C are executed for positive polarity and negative polarity writing, respectively. In addition, the difference in each series is leveled. For this reason, in 2nd Embodiment, it becomes possible to eliminate the display nonuniformity by the order of R, G, B series being fixed.
In the second embodiment, the patterns shown in FIGS. 5A, 5B, and 5C are switched in units of frame periods, but may be switched in units of rows or columns. When switching in units of rows or columns, when focusing on the same sub-pixel, it may be configured to sequentially switch in 6 frames.

In the first embodiment described above, the R and G series data lines are selected again. However, if there is little voltage fluctuation due to leakage when the high impedance state is entered, the first R series data lines are used. It is good also as a structure which re-selects only about. In the second embodiment, the G-series data line may be reselected for the pattern of FIG. 5B, and only the B-series data line for the pattern of FIG. 5C may be reselected.
In the first and second embodiments, the control circuit 10 outputs the selection signals Sel-R, Sel-G, and Sel-B. These selection signals are output from the data signal by the X driver 30. Therefore, the X driver 30 may include a circuit that outputs a selection signal. Further, a configuration independent of the control circuit 10 may be adopted.
Further, in the first embodiment, the selection signals Sel-R, Sel-G, and Sel-B are transmitted at the timing t1.
And then at the timings t2, t3, t4, the selection signals Sel-R, Sel-G,
Sel-B is sequentially reset to L level, but only the selection signal Sel-R is set to H level in the period from timing t1 to t2, and only the selection signal Sel-G is set to H level in the period from timing t2 to t3. In the period from timing t3 to t4, only the selection signal Sel-B may be set to H level.

In each of the above-described embodiments, the writing polarity is inverted every one frame period, because the reason is only to drive the liquid crystal capacitor 120 by alternating current, and therefore the inversion period is a period of two frames or more. There may be.
In each embodiment, the number of data line columns “m” constituting one group is “3”. However, in the present invention, “2” or more is sufficient. Further, although the liquid crystal capacitor 120 is in the normally white mode, it may be in a normally black mode in which the liquid crystal capacitor 120 becomes dark when no voltage is applied. Further, in addition to R (red), G (green), and B (blue), another color (for example, cyan (C)) is added, and these four colors of sub-pixels constitute one dot, and the color It is good also as a structure which improves reproducibility. In the case where one dot is constituted by sub-pixels of four colors, a configuration in which “m” is a multiple of 4 is preferable.
In addition, a simple black and white display may be used without providing a color filter.

In the above description, the reference of the writing polarity is the voltage Vcom applied to the common electrode 108. This is a case where the TFT 116 functions as an ideal switch. In practice, the gate / drain electrode of the TFT 116 is used. Due to the parasitic capacitance between them, a phenomenon that the potential of the drain electrode (pixel electrode 118) decreases when the state changes from on to off (referred to as push-down, punch-through, or field-through) occurs. In order to prevent deterioration of the liquid crystal, the liquid crystal capacitor 120 must be AC driven. However, when AC driving is performed with the applied voltage Vcom applied to the common electrode 108 as a reference for writing polarity, negative polarity writing is performed for pushdown. As a result, the effective voltage value of the liquid crystal capacitor 120 is slightly larger than the effective value due to the positive polarity writing (when the TFT 116 is n-channel). For this reason, in actuality, the reference voltage of the write polarity and the voltage LCcom of the common electrode 108 are separated, and in detail, the reference voltage of the write polarity is
The offset may be set higher than the voltage LCcom so that the effect of pushdown is offset.

<Electronic equipment>
Next, an electronic apparatus having the electro-optical device 1 according to the above-described embodiment as a display device will be described. FIG. 6 is a diagram illustrating a configuration of a mobile phone 1200 using the electro-optical device 1 according to any of the embodiments.
As shown in this figure, a cellular phone 1200 includes the electro-optical device 1 described above, together with a plurality of operation buttons 1202, an earpiece 1204 and a mouthpiece 1206. Note that components of the electro-optical device 1 other than the portion corresponding to the display panel 100 do not appear as appearance.
As an electronic apparatus to which the electro-optical device 1 is applied, in addition to the mobile phone shown in FIG. 6, a digital still camera, a photo storage, a laptop computer, a liquid crystal television, a viewfinder type (or a monitor direct view type) ) Video recorders, car navigation devices, pagers, electronic notebooks, calculators, word processors, workstations, videophones, POS terminals, devices equipped with touch panels, and the like. Needless to say, the above-described electro-optical device 1 is applicable as a display device of these various electronic devices.

1 is a diagram illustrating a configuration of an electro-optical device according to a first embodiment of the invention. FIG. It is a figure which shows the structure of the sub pixel in the same electro-optical apparatus. It is a figure which shows operation | movement of the same electro-optical apparatus. It is a figure which shows operation | movement of the same electro-optical apparatus. FIG. 6 is a diagram illustrating an operation of an electro-optical device according to a second embodiment of the invention. It is a figure which shows the structure of the mobile telephone to which the electro-optical apparatus which concerns on embodiment is applied. It is a figure which shows operation | movement of the comparative example with respect to embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Electro-optical apparatus, 10 ... Control circuit, 20 ... Y driver, 30 ... X driver, 52, 100 ... Display panel, 105 ... Liquid crystal, 108 ... Common electrode, 110 ... Subpixel, 112 ... Scan line, 114 ... Data 116, TFT, 118, pixel electrode, 120, liquid crystal capacity, 1200, mobile phone

Claims (6)

Multiple rows of scanning lines;
a plurality of data lines grouped by m (m is an integer of 2 or more) columns;
Provided corresponding to the intersection of the plurality of rows of scanning lines and the plurality of columns of data lines, each having a gradation corresponding to the voltage of the data lines when a selection voltage is applied to the scanning lines. Pixels,
A transistor provided in each of the plurality of columns of data lines, having one end commonly connected to each group and the other end connected to the data line;
With
An electro-optical device driving method for driving the plurality of columns of data lines, respectively.
Over a period in which the selection voltage is applied to one scanning line of the plurality of rows,
After selecting m columns of data lines belonging to each group in a predetermined order and bringing one end and the other end of the transistor corresponding to the selected data line into a conductive state, the first data line in the order is again connected. Select, and make one end and the other end of the transistor corresponding to the selected data line conductive,
A data signal of a voltage corresponding to the gray level of the pixel corresponding to the intersection of the one scanning line and the data line of the column selected in each group is supplied to one end of transistors commonly connected in each group. A driving method for an electro-optical device. After selecting the first data line in the order again and bringing one end and the other end of the transistor corresponding to the selected data line into a conductive state,
2. The method of driving an electro-optical device according to claim 1, wherein the second data line in the order is selected again, and one end and the other end of the transistor corresponding to the selected data line are made conductive. . The method of driving an electro-optical device according to claim 1, wherein among the m columns of data lines belonging to each group, the data line that is first selected in the order is rotated every predetermined period. Multiple rows of scanning lines;
a plurality of data lines grouped by m (m is an integer of 2 or more) columns;
Provided corresponding to the intersection of the plurality of rows of scanning lines and the plurality of columns of data lines, each having a gradation corresponding to the voltage of the data lines when a selection voltage is applied to the scanning lines. Pixels,
A transistor provided in each of the plurality of columns of data lines, having one end commonly connected to each group and the other end connected to the data line;
With
A drive circuit for an electro-optical device that drives each of the plurality of columns of data lines,
Over a period in which the selection voltage is applied to one scanning line of the plurality of rows, m columns of data lines belonging to each group are selected in a predetermined order, and at least one end of a transistor corresponding to the selected data line and A control circuit for selecting the first data line in the order again and bringing the one end and the other end of the transistor corresponding to the selected data line into a conductive state after bringing the other end into a conductive state;
A data signal of a voltage corresponding to the gray level of the pixel corresponding to the intersection of the one scanning line and the data line of the column selected in each group is supplied to one end of transistors commonly connected in each group. A driver,
A drive circuit for an electro-optical device, comprising: Multiple rows of scanning lines;
a plurality of data lines grouped by m (m is an integer of 2 or more) columns;
Provided corresponding to the intersection of the plurality of rows of scanning lines and the plurality of columns of data lines, each having a gradation corresponding to the voltage of the data lines when a selection voltage is applied to the scanning lines. Pixels,
A transistor provided in each of the plurality of columns of data lines, having one end commonly connected to each group and the other end connected to the data line;
A Y driver for selecting the plurality of rows of scanning lines in a predetermined order;
Over a period in which the selection voltage is applied to one scanning line of the plurality of rows, m columns of data lines belonging to each group are selected in a predetermined order, and at least one end of a transistor corresponding to the selected data line and A control circuit for selecting the first data line in the order again and bringing the one end and the other end of the transistor corresponding to the selected data line into a conductive state after bringing the other end into a conductive state;
A data signal of a voltage corresponding to the gray level of the pixel corresponding to the intersection of the one scanning line and the data line of the column selected in each group is supplied to one end of transistors commonly connected in each group. X driver,
An electro-optical device comprising:   An electronic apparatus comprising the electro-optical device according to claim 5.

Images