JP2009094280A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device incorporating a current detecting function. <P>SOLUTION: The semiconductor device has a conductor pattern 52 which is formed of a wiring layer on a surface of a semiconductor substrate (11) and has a loop shape such that it is connected to the power source of a function circuit 13 in series, a current detecting conductor pattern 54 which is a wiring layer right above the wiring layer forming the conductor pattern 52 and has a shape similar to that of the conductor pattern 52 and is disposed in parallel to the conductor pattern 52, and a bonding pad 13 connected to the current detecting conductor pattern 54. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a function of detecting current flowing through a conductor by electromagnetic induction.

  There is a demand for a current detection device that detects a current flowing through a conductor or a conductor in a semiconductor device, various electric elements, an electric circuit, or the like. A current detection device for detecting a relatively large current is built in the semiconductor module.

  On the other hand, as a current detection device that detects a relatively small change in DC current, for example, a magnetic detection coil that is minutely formed on a semiconductor substrate, and an amplification that is close to the magnetic detection coil on the same semiconductor substrate as the magnetic detection coil A magnetic sensor head comprising a circuit, a moving unit for moving the magnetic sensor head onto the integrated circuit chip to be measured, and a control unit for controlling the moving unit. A failure diagnosis device is disclosed that identifies the failure location of the integrated circuit chip under measurement by observing (see, for example, Patent Document 1).

The disclosed current detection device is a failure diagnosis device, and the semiconductor chip to be measured is, for example, a magnetic sensor head from which the sealing resin is removed and placed on the surface protective film of the semiconductor chip. The current of the semiconductor chip wiring is observed. That is, the semiconductor chip is removed from the electrical circuit of the housed application product, and the semiconductor chip package is removed. Therefore, there is a problem that it is impossible to detect a current in a semiconductor chip or a semiconductor device functioning in an electric circuit of an applied product.
Japanese Patent Laid-Open No. 10-177062 (page 4, FIG. 1)

  The present invention provides a semiconductor device incorporating a current detection function.

  A semiconductor device of one embodiment of the present invention includes a semiconductor substrate, a conductor pattern formed in a wiring layer on a surface of the semiconductor substrate, connected in series to a power supply or a ground of a functional circuit, and another wiring layer adjacent to the wiring layer. A current detection conductor pattern that is formed of a wiring layer, has substantially the same shape as the conductor pattern, is arranged in parallel with the conductor pattern, and bonding pads respectively connected to the current detection conductor pattern. It is characterized by.

  According to another aspect of the present invention, a semiconductor device includes a semiconductor substrate, a wiring layer formed on a surface of the semiconductor substrate, a conductor pattern connected in series to a power supply or ground of a functional circuit, and adjacent to the wiring layer. It is formed of another wiring layer, has a shape substantially the same as the conductor pattern, is connected to the current detection conductor pattern arranged in parallel with the conductor pattern, and the current detection conductor pattern, and the detected current is converted into a voltage. A power supply transformer circuit to be converted, and an output from the power transformer circuit and a comparator to which a reference voltage to be compared with the voltage is input.

  A semiconductor device according to another aspect of the present invention is formed of a semiconductor substrate, a wiring layer on a surface of the semiconductor substrate, a conductor pattern connected in series to a power supply or ground of a functional circuit, and the wiring layer. The current detection conductor pattern has a shape substantially the same as that of the conductor pattern, and is provided in parallel with the conductor pattern, and bonding pads respectively connected to the current detection conductor pattern.

  According to the present invention, it is possible to provide a semiconductor device incorporating a current detection function.

  Embodiments of the present invention will be described below with reference to the drawings. In each figure, the same components are denoted by the same reference numerals.

  A semiconductor device according to Embodiment 1 of the present invention will be described with reference to FIGS. 1A and 1B are diagrams schematically showing a conductor pattern of a semiconductor device. FIG. 1A is a plan view and FIG. 1B is a perspective view. FIG. 2 is a plan view schematically showing the arrangement of functional circuits and the like of the semiconductor device. FIG. 3 is a cross-sectional view schematically showing a wiring layer of the semiconductor device.

  As shown in FIG. 1, a semiconductor device (a semiconductor device 1 described later) is formed of a wiring layer on the surface of a semiconductor substrate, and has a conductor pattern 52 having a loop shape connected in series to a power source of a functional circuit 13, and a conductor pattern 52. And a bonding pad 15 connected to the current detection conductor pattern 54 and a current detection conductor pattern 54 formed in a loop shape that runs in parallel with the conductor pattern 52.

  As shown in FIG. 2, the semiconductor device 1 includes an MPU (Micro Processor Unit) having active elements and passive elements on the surface of a semiconductor substrate 11, a memory, an I / O (Input / Output), and other various control circuits. And the like, and a bonding pad 15 for connecting to the outside is disposed in the peripheral portion of the semiconductor substrate 11, and wiring such as power supply, grounding, and signal is connected to the functional circuit 13 through the bonding pad 15. Is connected. The conductor pattern shown in FIG. 1 corresponds to a part of the semiconductor device 1 shown in FIG.

  As shown in FIG. 3, the semiconductor device 1 has a structure in which wirings formed of a conductor made of aluminum, polysilicon, copper, or the like are stacked in a direction perpendicular to the surface. From the surface side of the semiconductor substrate 11, the first wiring layer 33, the outermost (also referred to as the uppermost) n-th wiring layer 36 (n is a natural number of 2 or more), and the n-1th wiring layer one inner side from the outermost side 35 and the like are arranged, and each wiring layer is separated by an interlayer insulating film 41 made of a silicon oxide film, a silicon nitride film or the like.

  For example, a well 21 is formed on the surface of a semiconductor substrate 11 made of silicon, and a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 23 composed of a diffusion layer 24, a gate electrode 28, and the like is isolated in an element isolation region 26. Has been formed. For the power supply wiring such as the Vdd wiring 51a and the Vss wiring 51b connected to the bonding pad 15, the outermost layer or the closest wiring layer is often used. For example, the contact 31 is connected from the n-1th wiring layer 35. The ground wiring is connected to the diffusion layer 24 on the source side of the MOSFET 23 similarly from the (n-1) th wiring layer 35, and the signal wiring is connected to the inner wiring layer. And is connected to the gate electrode 28 of the MOSFET 23. The outside of the nth wiring layer 36 is covered with a passivation film 43 made of a silicon nitride film or the like.

  As shown in FIG. 1, the conductor pattern 52 indicated by a thick line is a part of the Vdd wiring 51 a and is arranged in a rectangular loop between the bonding pad 15 and the selected functional circuit 13. . That is, the conductor pattern 52 is drawn out in the middle of the Vdd wiring 51a to the functional circuit 13, forms a rectangular loop, and is returned to the drawn-out vicinity. The Vdd wiring 51a can supply the Vdd voltage to the functional circuit 13 through the conductor pattern 52. The Vss wiring 51b is a ground wiring. As shown in FIGS. 1 and 3, the Vdd wiring 51 a and the Vss wiring 51 b including the conductor pattern 52 are formed in, for example, the n−1th wiring layer 35.

  The current detection conductor pattern 54 is formed in a rectangular loop adjacent to the n-1 wiring layer 35 in which the conductor pattern 52 is formed, for example, in the upper nth wiring layer 36 and substantially overlapping the conductor pattern 52. (Differences and thicknesses in the drawing are convenient displays for distinguishing them from each other), both ends are connected to the bonding pads 15. That is, the current detection conductor pattern 54 is located on the n-th wiring layer 36 on the opposite side of the conductor pattern 52 with respect to the semiconductor substrate 11 and is drawn out from the bonding pad 15 by the lead line 53a. It is formed in a loop-like rectangle similar to 52, and is connected to another bonding pad 15 by a lead line 53b. The conductor pattern 52 and the current detection conductor pattern 54 are separated by an interval between adjacent wiring layers. Note that the loop shapes of the conductor pattern 52 and the current detection conductor pattern 54 do not have to be rectangular, and may be other polygons, circles, ellipses, or the like. In addition, the positions of the wiring layers where the conductor pattern 52 and the current detection conductor pattern 54 are formed are turned upside down so that the conductor pattern 52 is the nth wiring layer 36 and the current detection conductor pattern 54 is the n−1th wiring. The layer 35 may be used.

  Next, the operation of the current detection conductor pattern 54 will be described. When a power supply voltage or the like is applied to the semiconductor device 1 to enter an operating state, a magnetic field is generated concentrically around the Vdd wiring 51a. In the Vdd wiring 51a, a change in current may occur due to charging / discharging of the functional circuit 13 or the like, which may cause a change in voltage. Inside the conductor pattern 52 in which the Vdd wiring 51a is formed in a loop shape, the magnetic flux is strengthened in the same direction. The strengthened magnetic field generated in the conductor pattern 52 penetrates the inside of the loop-shaped current detection conductor pattern 54 disposed on the upper side, and generates an electromotive force in the current detection conductor pattern 54 by electromagnetic induction. Since the current detection conductor pattern 54 also has a loop shape, a larger current is generated than when the loop is not formed.

  The current generated in the current detection conductor pattern 54 can be measured by a measuring instrument connected to the bonding pad 15. In the operation of the normal functional circuit 13 or the like, the Vdd wiring 51a undergoes a substantially constant change in charge / discharge current or the like, so that the current detection conductor pattern 54 can detect a substantially constant change and value in current.

  As described above, the semiconductor device 1 includes the loop-shaped conductor pattern 52 formed in the wiring layer, and the current detection conductor pattern 54 formed in the same loop shape as the conductor pattern 52 in the wiring layer above the conductor pattern 52. Since the bonding pad 15 connected to the current detection conductor pattern 54 is provided, it is possible to detect the current during operation flowing through the Vdd wiring 51a by electromagnetic induction. This detection can be performed outside the semiconductor device 1 through the bonding pad 15.

  As a result, it is possible to determine whether the functional circuit 13 or the like connected to the Vdd wiring 51a of the semiconductor device 1 is normal or abnormal without destroying the semiconductor device 1. Further, if the failure mode occurring in the functional circuit 13 is associated with the current generated in the current detection conductor pattern 54, the situation of the functional circuit 13 can be grasped by the current generated in the current detection conductor pattern 54. . Since the target functional circuit 13 is specified by the current generated in the current detection conductor pattern 54, it is possible to accurately and quickly determine the failure. In addition, since the conductor pattern 52 and the current detection conductor pattern 54 have a relationship of upper and lower wiring layers and are arranged close to each other, the current detection sensitivity is high.

  A semiconductor device according to Embodiment 2 of the present invention will be described with reference to FIG. FIG. 4 is a perspective view schematically showing a conductor pattern of the semiconductor device. The difference from the first embodiment is that the loops of the current detection conductor pattern are doubled. In the following, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different components will be described.

  As shown in FIG. 4, in the semiconductor device, a current detection conductor pattern 64 having a double loop shape formed in two upper and lower wiring layers is arranged. The current detection conductor pattern 64 includes a current detection conductor pattern 64a having a loop shape formed in the (n + 1) th wiring layer (not shown) increased by one layer, and a current detection conductor pattern having a loop shape formed in the nth wiring layer 36. The current detection conductor patterns 64a and 64b having 64b are connected in series by a contact 65 substantially perpendicular to the wiring layer and wound in the same direction.

  The current detection conductor pattern 64 is taken out in the (n + 1) th wiring layer and connected to the bonding pad 15. In a plan view, the conductor pattern 52 in the (n-1) th wiring layer 35 and the current detection conductor patterns 64a and 64b in the upper part thereof are almost overlapped with each other. The configuration other than the current detection conductor pattern 64 is the same as that of the semiconductor device 1 of the first embodiment, and it is possible to change the loop shape and take a relative vertical relationship as in the semiconductor device 1 of the first embodiment. It is.

  As described above, in the semiconductor device of this embodiment, since the current detection conductor pattern 64 has a double loop shape by increasing the wiring layer by one, the electromotive force generated by electromagnetic induction is implemented. It is larger than the current detection conductor pattern 54 of Example 1. As a result, a more minute change in current generated in the conductor pattern 52 can be captured more accurately, and it can be more quickly determined whether the current is normal or abnormal and how abnormal. Other effects are the same as those of the semiconductor device 1 of the first embodiment.

  A semiconductor device according to Embodiment 3 of the present invention will be described with reference to FIG. FIG. 5 is a plan view schematically showing a conductor pattern of a semiconductor device. The first embodiment is different from the first embodiment in that the conductor pattern and the current detection conductor pattern are linearly formed. In the following, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different components will be described.

  As shown in FIG. 5, the semiconductor device has a current detection conductor pattern 74 formed in a straight line on the same wiring layer as the conductor pattern 72 formed in a straight line. The conductor pattern 72 is linearly formed on the (n-1) th wiring layer 35, and has no difference in shape from the continuous Vdd wiring 51a (the drawing is shown as a thick line). On the other hand, the current detection conductor pattern 74 is linearly formed on the n−1th wiring layer 35 so as to be parallel to the conductor pattern 72. The current detection conductor pattern 74 can be disposed in the nth wiring layer 36 that is a wiring layer immediately above the conductor pattern 72.

  The current detection conductor pattern 74 is taken out by the n−1th wiring layer 35 and connected to the bonding pad 15. The configuration other than the conductor pattern 72 and the current detection conductor pattern 74 is the same as that of the semiconductor device 1 of the first embodiment. The conductor pattern 72 and the current detection conductor pattern 74 are straight portions that run in parallel, but may be straight lines that run in parallel with a certain angle, for example, 90 degrees, Or the curve etc. which run in parallel may be sufficient.

  As described above, since the conductor pattern 72 and the current detection conductor pattern 74 are straight in the semiconductor device of this embodiment, the electromotive force generated by electromagnetic induction is compared with the current detection conductor pattern 54 of the first embodiment. And small. As a result, although it is difficult to detect a minute change in current generated in the conductor pattern 72, the conductor pattern 72 and the current detection conductor pattern 74 can be formed on the same wiring layer, so that the wiring layer can be reduced by one layer, Therefore, since the occupied area can be reduced as compared with the loop shape, the semiconductor device manufacturing process can be shortened and the cost can be reduced as compared with the semiconductor device 1 of the first embodiment. Other effects are the same as those of the semiconductor device 1 of the first embodiment.

  A semiconductor device according to Embodiment 4 of the present invention will be described with reference to FIGS. FIG. 6 is a plan view schematically showing a conductor pattern of the semiconductor device. FIG. 7 is a plan view schematically showing the conductor pattern shown in FIG. 6 of the semiconductor device, in which a plurality of conductor patterns shown in FIG. 6 are arranged. Example 1 is different from Example 1 in that a voltage based on the output of the current detection conductor pattern is output by comparing with a reference voltage. In the following, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different components will be described.

  As shown in FIG. 6, the semiconductor device is formed in the same wiring layer as the current detection conductor pattern 64 of the first embodiment, has the same shape, and has the same positional relationship with respect to the lower conductor pattern 52. A conductor pattern 84 is provided. The current detection conductor pattern 84 is connected to the voltage conversion circuit 81 without being connected to the bonding pad 15. The current detected by the current detection conductor pattern 84 is converted into a voltage by the voltage conversion circuit 81 and output to the comparator 83.

  A reference voltage 82 is connected to the comparator 83, and the magnitude of the voltage of the voltage conversion circuit 81 compared with the reference voltage 82 is output, for example, via a circuit outside the semiconductor device. For example, the reference voltage 82 is supplied by dividing the Vdd voltage. A voltage value that is expected to be detected and converted by the current detection conductor pattern 84 when the functional circuit 13 or the like fails is set as the reference voltage 82 as an abnormal value. In addition, other voltage values that require detection can be set as the reference voltage 82.

  In addition, as shown in FIG. 7, a circuit including the current detection conductor pattern 84, the voltage conversion circuit 81, the reference voltage 82, the comparator 83, and the like shown in FIG. They are arranged in parallel. The functional circuits 13a, 13b, and 13c connected separately from the Vdd wiring 51a are detected by the current detection conductor patterns 84a, 84b, and 84c, respectively, and in accordance with the voltage that determines the failure of the functional circuits 13a, 13b, and 13c. Reference voltages 82a, 82b, and 82c are set, and compared and output by comparators 83a, 83b, and 83c, respectively.

  As described above, the semiconductor device of this embodiment includes the current detection conductor patterns 84, 84a, 84b, 84c, the voltage conversion circuits 81, 81a, 81b, 81c, the reference voltages 82, 82a, 82b, 82c, and the comparator. By having one or a plurality of circuits composed of 83, 83a, 83b, 83c, etc., voltage values based on the currents detected by the current detection conductor patterns 84, 84a, 84b, 84c are compared with the comparators 83, 83a, 83b. , 83c can be output as comparison values with reference voltages 82, 82a, 82b, 82c. As a result, it is possible to know whether the circuit to which the conductor patterns 52, 52a, 52b, 52c are connected is normal or abnormal.

  Further, it is possible to connect the output of the comparator 83 to the MPU and execute a response at the time of abnormality by a program prepared in advance. As a result, it is possible to minimize the influence on the semiconductor device itself and the connected peripheral circuits.

  A semiconductor device according to Embodiment 5 of the present invention will be described with reference to FIG. FIG. 8 is a plan view schematically showing a conductor pattern of a semiconductor device. The fourth embodiment is different from the fourth embodiment in that a functional circuit is connected to an external circuit of the semiconductor device, and an operation state of the external circuit greatly changes depending on a power supply voltage. Hereinafter, the same components as those in the first embodiment and the fourth embodiment are denoted by the same reference numerals, description thereof will be omitted, and different components will be described.

  As shown in FIG. 8, the semiconductor device 2 has a circuit including a current detection conductor pattern 84, a voltage conversion circuit 81, a reference voltage 92, a comparator 83, and the like, similar to the semiconductor device of the fourth embodiment. A functional circuit 93 connected to the Vdd wiring 51 a is connected to an external oscillation circuit 91 outside the semiconductor device 2.

  When the external oscillation circuit 91 causes abnormal oscillation, a voltage value that is expected to be detected and converted by the current detection conductor pattern 84 is set to the reference voltage 92 as an abnormal value. In addition, other voltage values that require detection can be set as the reference voltage 92.

  As described above, the semiconductor device 2 according to the present embodiment includes the circuit including the current detection conductor pattern 84, the voltage conversion circuit 81, the reference voltage 92, the comparator 83, and the like, so that the current detection conductor pattern 84 detects the current detection conductor pattern 84. The comparator 83 can output a voltage value based on the generated current as a comparison value with the reference voltage 92. As a result, it is possible to know whether the functional circuit 93 connected to the external oscillation circuit 91 to which the conductor pattern 52 is connected is normal or abnormal, that is, abnormal oscillation of the oscillation circuit 91 or the like. In addition, since it has the same effect as the semiconductor device of the fourth embodiment, it is possible to minimize the influence on the peripheral circuit caused by abnormal oscillation.

  The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

  For example, in the embodiment, the conductor pattern is formed in series with the Vdd wiring between the bonding pad and the functional circuit. However, the conductor pattern is formed in series with the Vss wiring between the bonding pad and the functional circuit. It is possible.

The present invention can be configured as described in the following supplementary notes.
(Appendix 1) A semiconductor substrate, a wiring layer formed on the surface of the semiconductor substrate, a conductor pattern connected in series with a power supply or ground of a functional circuit, and another wiring layer adjacent to the wiring layer, A semiconductor device comprising a current detection conductor pattern having a shape substantially the same as the conductor pattern and disposed in parallel with the conductor pattern, and bonding pads respectively connected to the current detection conductor pattern.

(Supplementary Note 2) The current detection conductor pattern is formed such that a plurality of loops respectively formed in the wiring layer and the separate wiring layer are connected in series, and current flows in the same direction through the loops. The semiconductor device according to appendix 1.

(Additional remark 3) The said conductor pattern is a semiconductor device of Additional remark 1 connected to the specific functional circuit.

(Supplementary note 4) The semiconductor device according to supplementary note 1, wherein the conductor pattern and the current detection conductor pattern are straight lines.

FIGS. 1A and 1B are diagrams schematically illustrating a conductor pattern of a semiconductor device according to a first embodiment of the present invention, in which FIG. 1A is a plan view, and FIG. 1 is a plan view schematically showing the arrangement of functional circuits and the like of a semiconductor device according to Example 1 of the present invention. Sectional drawing which shows typically the wiring layer of the semiconductor device which concerns on Example 1 of this invention. The perspective view which shows typically the conductor pattern of the semiconductor device which concerns on Example 2 of this invention. FIG. 9 is a plan view schematically showing a conductor pattern of a semiconductor device according to Example 3 of the invention. FIG. 9 is a plan view schematically showing a conductor pattern of a semiconductor device according to Example 4 of the invention. FIG. 9 is a plan view schematically showing a plurality of conductor patterns of a semiconductor device according to Embodiment 4 of the present invention. FIG. 9 is a plan view schematically showing a conductor pattern of a semiconductor device according to Example 5 of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 2 Semiconductor device 11 Semiconductor substrate 13, 13a, 13b, 13c, 93 Functional circuit 15 Bonding pad 21 Well 23 MOSFET
24 Diffusion region 26 Element isolation region 28 Gate electrode 31, 65 Contact 33 First wiring layer 35 n-1 wiring layer 36 nth wiring layer 38 Via plug 41 Interlayer insulating film 43 Passivation film 51a Vdd wiring 51b Vss wiring 52, 52a, 52b, 52c, 72 Conductor patterns 53a, 53b Lead-out lines 54, 64, 64a, 64b, 74, 84, 84a, 84b, 84c Current detection conductor pattern 81 Voltage conversion circuit 82 Reference voltage 83, 83a, 83b, 83c Comparator 91 Oscillator circuit

Claims (5)

A semiconductor substrate;
A conductor pattern formed of a wiring layer on the surface of the semiconductor substrate and connected in series to the power supply or ground of the functional circuit;
Formed of another wiring layer adjacent to the wiring layer, substantially the same shape as the conductor pattern, and a current detection conductor pattern arranged in parallel with the conductor pattern;
Bonding pads respectively connected to the current detection conductor patterns;
A semiconductor device comprising: A semiconductor substrate;
A conductor pattern formed of a wiring layer on the surface of the semiconductor substrate and connected in series to the power supply or ground of the functional circuit;
Formed of another wiring layer adjacent to the wiring layer, substantially the same shape as the conductor pattern, and a current detection conductor pattern arranged in parallel with the conductor pattern;
A power transformer circuit that is connected to the current detection conductor pattern and converts a detected current into a voltage;
A comparator to which an output from the power transformer circuit and a reference voltage to be compared with the voltage are input;
A semiconductor device comprising:   The semiconductor device according to claim 2, wherein the functional circuit is connected to an external oscillation circuit.   4. The semiconductor device according to claim 1, wherein the conductor pattern and the current detection conductor pattern have a rectangular portion. 5. A semiconductor substrate;
A conductor pattern formed of a wiring layer on the surface of the semiconductor substrate and connected in series to the power supply or ground of the functional circuit;
A current detection conductor pattern formed of the wiring layer, having a shape substantially similar to the conductor pattern, and arranged in parallel with the conductor pattern;
Bonding pads respectively connected to the current detection conductor patterns;
A semiconductor device comprising:

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