JP2009088421A - Semiconductor device manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method for preventing the abnormal growth of a metal silicide layer. <P>SOLUTION: A gate insulating film 5, gate electrodes 6a, 6b, a source/drain n<SP>+</SP>-type semiconductor region 7b, and a p<SP>+</SP>-type semiconductor region 8b are formed on a semiconductor substrate 1. Then, the metal silicide layer 13 is formed on the gate electrodes 6a, 6b and the source/drain region with salicide technology. After plasma treatment is applied to the surface of the metal silicide layer 13 with reducing gas, an insulating film 21 formed of silicon nitride is accumulated on the semiconductor substrate 1 including the metal silicide layer 13 in a plasma CVD method without exposing the semiconductor substrate 1 to the atmosphere. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique effective when applied to the manufacture of a semiconductor element in which a silicon nitride film is formed on a metal silicide layer.

  As semiconductor devices become more highly integrated, field effect transistors (MISFETs) are miniaturized according to scaling rules, but the resistance of gates, sources and drains increases, and field effect transistors are miniaturized. However, there arises a problem that high-speed operation cannot be obtained. Therefore, by forming a low-resistance metal silicide layer such as a nickel silicide layer or a cobalt silicide layer by self-alignment on the surface of the conductive film constituting the gate and the semiconductor region constituting the source / drain, the gate, source / drain, etc. The salicide technology to reduce the resistance is being studied.

Japanese Patent Laying-Open No. 2003-86569 (Patent Document 1) describes a technique related to a plasma processing method for removing a natural oxide film on the surface of a CoSi ₂ film.

Japanese Patent Laid-Open No. 10-112446 (Patent Document 2) describes a technique for forming a TiN layer after removing a TiO _x layer on a Ti silicide layer.

Japanese Patent Application Laid-Open No. 2001-284284 (Patent Document 3) describes a technique for growing a TiN layer after removing a natural oxide film on the surface of a CoSi ₂ layer.

International Publication WO2007 / 020684 pamphlet (Patent Document 4) describes a technique of forming a silicon nitride film for preventing Cu diffusion on a Cu wiring formed by using a damascene method.
JP 2003-86569 A JP-A-10-112446 JP 2001-284284 A International Publication WO2007 / 020684 Pamphlet

  According to the study of the present inventor, the following has been found.

  After forming a metal silicide layer by a salicide process on the surface of the conductive film constituting the gate and the semiconductor region constituting the source / drain, after forming a silicon nitride film on the semiconductor substrate including the surface of the metal silicide layer, A thick silicon oxide interlayer insulating film is formed on the silicon nitride film, and contact holes are opened in the interlayer insulating film. When opening the contact hole, first, the silicon nitride film functions as an etching stopper to dry-etch the interlayer insulating film, and then the silicon nitride film is dry-etched at the bottom of the contact hole. After the contact hole is formed, a plug is embedded in the contact hole.

  However, when the silicon nitride film is formed in a state where the natural oxide film is formed on the surface of the metal silicide layer, the natural oxide film remains at the interface between the metal silicide layer and the silicon nitride film. If a natural oxide film remains at the interface between the metal silicide layer and the silicon nitride film, various heating processes after the formation of the silicon nitride film (for example, various insulating films and conductive film deposition processes) The inventors have found that the metal silicide layer partially grows abnormally due to the oxygen in the natural oxide film on the surface of the metal silicide layer in the process involving heating of the metal silicide layer. Such abnormal growth of the metal silicide layer causes an increase in resistance of the metal silicide layer, and if the metal silicide layer abnormally grows in the channel portion, an increase in leakage current between the source and drain of the field effect transistor. May be incurred. This degrades the performance of the semiconductor device.

  An object of the present invention is to provide a technique capable of improving the performance of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The present invention forms a metal silicide layer on the surface of a semiconductor region formed on a semiconductor substrate, treats the surface of the metal silicide layer with plasma of a reducing gas, and then exposes the semiconductor substrate to the atmosphere without exposing it to the atmosphere. A silicon nitride film is formed on the semiconductor substrate including the silicide layer by a plasma CVD method.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  The performance of the semiconductor device can be improved.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

(Embodiment 1)
A manufacturing process of a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 to FIG. 10 are cross-sectional views of a main part during a manufacturing process of a semiconductor device according to an embodiment of the present invention, for example, a semiconductor device having a CMISFET (Complementary Metal Insulator Semiconductor Field Effect Transistor).

  First, as shown in FIG. 1, a semiconductor substrate (semiconductor wafer) 1 made of, for example, p-type single crystal silicon having a specific resistance of about 1 to 10 Ωcm is prepared. Then, the element isolation region 2 is formed on the main surface of the semiconductor substrate 1. The element isolation region 2 is made of an insulator such as silicon oxide, and is formed by, for example, an STI (Shallow Trench Isolation) method or a LOCOS (Local Oxidization of Silicon) method. For example, the element isolation region 2 can be formed by an insulating film embedded in a groove (element isolation groove) 2 a formed in the semiconductor substrate 1.

  Next, as shown in FIG. 2, a p-type well 3 and an n-type well 4 are formed from the main surface of the semiconductor substrate 1 to a predetermined depth. The p-type well 3 is formed on the semiconductor substrate 1 in the n-channel type MISFET formation region by using a photoresist film (not shown) covering the p-channel type MISFET formation region as a mask for ion implantation. It can be formed by ion implantation of a type impurity. The n-type well 4 is formed on the semiconductor substrate 1 in the p-channel type MISFET formation region with, for example, phosphorus (P) using another photoresist film (not shown) covering the n-channel type MISFET formation region as an ion implantation blocking mask. ) Or n-type impurities such as arsenic (As).

  Next, the surface of the semiconductor substrate 1 is cleaned (washed) by wet etching using a hydrofluoric acid (HF) aqueous solution, for example, and then the surface of the semiconductor substrate 1 (that is, the surface of the p-type well 3 and the n-type well 4). A gate insulating film 5 is formed thereon. The gate insulating film 5 is made of, for example, a thin silicon oxide film, and can be formed by, for example, a thermal oxidation method.

  Next, a silicon film (conductor film) 6 such as a polycrystalline silicon film is formed on the semiconductor substrate 1 (that is, on the gate insulating film 5 of the p-type well 3 and the n-type well 4) as a conductor film for forming a gate electrode. Form. An n channel MISFET formation planned region (a region to be a gate electrode 6a described later) in the silicon film 6 is made of n (such as phosphorus (P) or arsenic (As)) using a photoresist film (not shown) as a mask. A low-resistance n-type semiconductor film (doped polysilicon film) is formed by ion implantation of a type impurity. Further, a p-channel type MISFET formation scheduled region (a region to be a gate electrode 6b described later) in the silicon film 6 is a p-type such as boron (B) using another photoresist film (not shown) as a mask. As a result, a low-resistance p-type semiconductor film (doped polysilicon film) is obtained. Further, the silicon film 6 can be changed from an amorphous silicon film at the time of film formation to a polycrystalline silicon film by heat treatment after film formation (after ion implantation).

  Next, as shown in FIG. 3, the gate electrodes 6a and 6b are formed by patterning the silicon film 6 using a photolithography method and a dry etching method.

  The gate electrode 6a serving as the gate electrode of the n-channel type MISFET is made of polycrystalline silicon (n-type semiconductor film, doped polysilicon film) into which an n-type impurity is introduced, and the gate insulating film 5 is formed on the p-type well 3. Formed through. That is, the gate electrode 6 a is formed on the gate insulating film 5 of the p-type well 3. The gate electrode 6b serving as the gate electrode of the p-channel type MISFET is made of polycrystalline silicon (p-type semiconductor film, doped polysilicon film) into which p-type impurities are introduced, and a gate insulating film is formed on the n-type well 4. 5 is formed. That is, the gate electrode 6 b is formed on the gate insulating film 5 of the n-type well 4. The gate lengths of the gate electrodes 6a and 6b can be changed as necessary, but can be, for example, about 50 nm.

Next, as shown in FIG. 4, n-type impurities such as phosphorus (P) or arsenic (As) are ion-implanted into the regions on both sides of the gate electrode 6a of the p-type well 3 (a pair). An n ⁻ type semiconductor region 7 a is formed and a p type impurity such as boron (B) is ion-implanted into regions on both sides of the gate electrode 6 b of the n type well 4, thereby (a pair of) p ⁻ type semiconductor regions 8 a. Form. The depth (junction depth) of the n ⁻ type semiconductor region 7a and the p ⁻ type semiconductor region 8a can be set to, for example, about 30 nm.

  Next, sidewall spacers or sidewalls (sidewall insulating films) 9 made of, for example, silicon oxide or silicon nitride or a laminated film of these insulating films are formed on the sidewalls of the gate electrodes 6a and 6b. For example, the sidewall 9 is formed by depositing a silicon oxide film or a silicon nitride film or a laminated film thereof on the semiconductor substrate 1 and depositing the silicon oxide film or the silicon nitride film or the laminated film on the RIE (Reactive Ion Etching) method or the like. Can be formed by anisotropic etching.

After the formation of the sidewalls 9, the (pair) n ⁺ type semiconductor regions 7 b (source and drain) are formed, for example, on the gate electrode 6 a of the p-type well 3 and the regions on both sides of the sidewalls 9 with phosphorus (P) or arsenic ( An n-type impurity such as (As) is ion-implanted. Further, (a pair of) p ⁺ -type semiconductor regions 8b (source and drain) are ionized with p-type impurities such as boron (B) in the regions on both sides of the gate electrode 6b and sidewalls 9 of the n-type well 4, for example. It is formed by injection. The n ⁺ type semiconductor region 7b may be formed first, or the p ⁺ type semiconductor region 8b may be formed first. After the ion implantation, an annealing process for activating the introduced impurities can be performed. The depth (junction depth) of the n ⁺ type semiconductor region 7b and the p ⁺ type semiconductor region 8b can be set to, for example, about 80 nm.

The n ⁺ type semiconductor region 7b has a higher impurity concentration than the n ⁻ type semiconductor region 7a, and the p ⁺ type semiconductor region 8b has a higher impurity concentration than the p ⁻ type semiconductor region 8a. Thus, an n-type semiconductor region (impurity diffusion layer) functioning as a source or drain of the n-channel MISFET is formed by the n ⁺ -type semiconductor region (impurity diffusion layer) 7b and the n ⁻ -type semiconductor region 7a, and the p-channel A p-type semiconductor region (impurity diffusion layer) functioning as a source or drain of the type MISFET is formed by the p ⁺ -type semiconductor region (impurity diffusion layer) 8b and the p ⁻ -type semiconductor region 8a. Therefore, the source / drain regions of the n-channel MISFET and the p-channel MISFET have an LDD (Lightly doped Drain) structure. The n ⁻ type semiconductor region 7a is formed in a self-aligned manner with respect to the gate electrode 6a, and the n ⁺ type semiconductor region 7b is formed in a self-aligned manner with respect to the sidewall 9 formed on the side wall of the gate electrode 6a. The p ⁻ type semiconductor region 8a is formed in a self-aligned manner with respect to the gate electrode 6b, and the p ⁺ type semiconductor region 8b is formed in a self-aligned manner with respect to the sidewall 9 formed on the side wall of the gate electrode 6b. Formed.

In this way, an n-channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) Qn is formed in the p-type well 3, and a p-channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) Qp is formed in the n-type well 4. A structure of 4 is obtained. The n ⁺ type semiconductor region 7b (first semiconductor region) can be regarded as a semiconductor region for the source or drain of the n channel MISFET Qn, and the p ⁺ type semiconductor region 8b (first semiconductor region) is a p channel. It can be regarded as a semiconductor region for the source or drain of the type MISFET Qp.

Next, by the salicide (Salicide: Self Aligned Silicide) technique, the surface of the gate electrode 6a and the source / drain region (here, n ⁺ -type semiconductor region 7b) of the n-channel type MISFET Qn, the gate electrode 6b of the p-channel type MISFET Qp, and A low-resistance metal silicide layer (corresponding to a metal silicide layer 13 described later) is formed on the surface of the source / drain region (here, the p ⁺ -type semiconductor region 8b). Below, the formation process of this metal silicide layer is demonstrated.

After the structure of FIG. 4 is obtained as described above, as shown in FIG. 5, after exposing the surfaces of the gate electrodes 6a and 6b, the n ⁺ type semiconductor region 7b and the p ⁺ type semiconductor region 8b, On the main surface (entire surface) of the semiconductor substrate 1 including the gate electrodes 6a and 6b, the n ⁺ type semiconductor region 7b and the p ⁺ type semiconductor region 8b, a metal film 11 is sputtered so as to cover the gate electrodes 6a and 6b, for example. It is formed (deposited) using a method. Then, a barrier film 12 is formed (deposited) on the metal film 11.

Further, before the metal film 11 is deposited on the semiconductor substrate 1, a dry cleaning process using at least one of HF gas, NF ₃ gas, NH ₃ gas, and H ₂ gas is performed to obtain the gate electrode 6a. , 6b, the n ⁺ type semiconductor region 7b and the p ⁺ type semiconductor region 8b after removing the natural oxide film on the surface thereof, the formation process of the metal film 11 without exposing the semiconductor substrate 1 to the atmosphere (in an oxygen-containing atmosphere). It is more preferable to perform the step of forming the barrier film 12.

  The metal film 11 is made of, for example, a nickel (Ni) film, and the thickness (deposited film thickness) can be set to, for example, about 9 nm. In addition to Ni (nickel) film, for example, Ni-Pt alloy film (Ni and Pt alloy film), Ni-V alloy film (Ni and V alloy film), Ni-Pd alloy film (Ni and Pd alloy film) ), A nickel alloy film such as a Ni—Yb alloy film (Ni—Yb alloy film) or a Ni—Er alloy film (Ni—Er alloy film) can be used as the metal film 11. The barrier film 12 is made of, for example, a titanium nitride (TiN) film or a titanium (Ti) film, and the thickness (deposited film thickness) can be set to, for example, about 15 nm. The barrier film 12 is provided on the metal film 11 in order to prevent oxidation of the metal film 11 and control stress acting on the semiconductor substrate 1.

After the metal film 11 and the barrier film 12 are formed, the semiconductor substrate 1 is subjected to a first heat treatment (annealing process), whereby the polycrystalline silicon film and the metal film 11 constituting the gate electrodes 6a and 6b, and the n ⁺ type are formed. The single crystal silicon constituting the semiconductor region 7b and the p ⁺ type semiconductor region 8b and the metal film 11 are selectively reacted to form a metal silicide layer 13 which is a metal / semiconductor reaction layer. Since the metal silicide layer 13 is formed by the reaction between the upper portions (upper layer portions) of the gate electrodes 6a and 6b, the n ⁺ type semiconductor region 7b and the p ⁺ type semiconductor region 8b and the metal film 11, the metal silicide layer 13 is formed. Are formed on the respective surfaces (upper layer portions) of the gate electrodes 6a and 6b, the n ⁺ type semiconductor region 7b and the p ⁺ type semiconductor region 8b. The first heat treatment for forming the metal silicide layer 13 is performed under normal pressure filled with an inert gas (eg, argon (Ar) gas, helium (He) gas, or nitrogen (N ₂ ) gas) atmosphere. preferable.

Next, by performing a wet cleaning process, the barrier film 12 and the metal film 11 that has not reacted with the unreacted metal film 11 (that is, the gate electrodes 6a and 6b, the n ⁺ type semiconductor region 7b, or the p ⁺ type semiconductor region 8b). And 11). At this time, the metal silicide layer 13 is left on the surfaces of the gate electrodes 6a and 6b, the n ⁺ type semiconductor region 7b and the p ⁺ type semiconductor region 8b. This wet cleaning treatment can be performed by wet cleaning using sulfuric acid or wet cleaning using sulfuric acid and hydrogen peroxide. In this way, the structure of FIG. 6 is obtained.

Next, the semiconductor substrate 1 is subjected to a second heat treatment (annealing process). This second heat treatment is performed at a heat treatment temperature higher than the heat treatment temperature of the first heat treatment. The second heat treatment is preferably performed under normal pressure filled with an inert gas (eg, argon (Ar) gas, helium (He) gas, or nitrogen (N ₂ ) gas) atmosphere.

As described above, the metal electrode 11 is selectively reacted with the gate electrode 6a, 6b, the n ⁺ type semiconductor region 7b and the p ⁺ type semiconductor region 8b (which constitutes the silicon) and the metal film 11 by the first heat treatment. 13 is formed, but the metal silicide layer 13 is changed to the MSi (metal monosilicide) phase at the stage of the first heat treatment, and not the M ₂ Si (dimetal silicide) phase or the MSi ₂ (metal disilicide) phase. It is preferable. By performing the second heat treatment, the MSi phase metal silicide layer 13 can be stabilized.

That is, the MSi-phase metal silicide layer 13 is formed by the first heat treatment, and this metal silicide layer 13 remains in the MSi phase even when the second heat treatment is performed, but the second heat treatment is performed. As a result, the composition in the metal silicide layer 13 is made more uniform, the composition ratio between the metal element M and Si in the metal silicide layer 13 becomes closer to the stoichiometric ratio of 1: 1, and the metal silicide layer 13 is stabilized. Can be When the M ₂ Si phase portion is formed in the metal silicide layer 13 by the first heat treatment, the M ₂ Si phase portion can be changed to the MSi phase by the second heat treatment. Note that the MSi phase has a lower resistivity than the M ₂ Si phase and the MSi ₂ phase, and the metal silicide layer 13 is maintained as the low resistance MSi phase even after the second heat treatment (until the end of manufacturing the semiconductor device). In the manufactured semiconductor device (for example, even when the semiconductor substrate 1 is separated into a semiconductor chip), the metal silicide layer 13 has a low resistance MSi phase.

In the present embodiment, the metal element constituting the metal film 11 is expressed as M in the chemical formula and “metal” in the katakana notation. For example, when the metal film 11 is a nickel (Ni) film, the M (metal element M constituting the metal film 11) is Ni, and the MSi (metal monosilicide) is NiSi (nickel monosilicide). The M ₂ Si (die metal silicide) is Ni ₂ Si (die nickel silicide), and the MSi ₂ (metal disilicide) is NiSi ₂ (nickel disilicide). In the case where the metal film 11 is a Ni-Pt alloy film (Ni _0.98 Pt _0.02 alloy film) in which Ni is 98 atomic% and Pt is 2 atomic%, the above M (metal element M constituting the metal film 11) Is Ni and Pt (where M is Ni _0.98 Pt _0.02 considering the composition ratio of Ni and Pt), the MSi is Ni _0.98 Pt _0.02 Si, and the M ₂ Si is (Ni _0.98 Pt _0.02 ) ₂ Si, and the MSi ₂ is Ni _0.98 Pt _0.02 Si ₂ . When the metal film 11 is a Ni—Pd alloy film (Ni _0.99 Pt _0.01 alloy film) with 99 atomic% Ni and 1 atomic% Pd, the above M (metal element M constituting the metal film 11) Is Ni and Pd (where M is Ni _0.99 Pd _0.01 considering the composition ratio of Ni and Pd), the MSi is Ni _0.99 Pd _0.01 Si, and the M ₂ Si is (Ni _0.99 Pd _0.01 ) ₂ Si, and the MSi ₂ is Ni _0.99 Pd _0.01 Si ₂ . The same can be considered when the metal film 11 is an alloy film having another composition.

In this way, the surface (upper layer part) of the gate electrode 6a and the source / drain region (n ⁺ type semiconductor region 7b) of the n channel MISFET Qn, and the gate electrode 6b and the source / drain region (p ^{+ of the} p channel type MISFET Qp). A metal silicide layer 13 made of MSi (metal monosilicide) is formed on the surface (upper layer portion) of the type semiconductor region 8b). Further, depending on the thickness of the metal film 11, when the thickness of the metal film 11 is, for example, about 9 nm, the thickness of the metal silicide layer 13 is, for example, about 19 nm.

  Next, as shown in FIG. 7, an insulating film 21 (first insulating film) is formed on the main surface of the semiconductor substrate 1. That is, the insulating film 21 is formed on the semiconductor substrate 1 including the metal silicide layer 13 so as to cover the gate electrodes 6a and 6b. The insulating film 21 is made of a silicon nitride film and is formed using a plasma CVD method. The step of forming the insulating film 21 will be described in detail later.

  Next, as shown in FIG. 8, an insulating film 22 thicker than the insulating film 21 is formed on the insulating film 21. The insulating film 22 is made of, for example, a silicon oxide film, and can be formed by a plasma CVD method using TEOS (Tetraethoxysilane: also called Tetra Ethyl Ortho Silicate). Thereby, an interlayer insulating film composed of the insulating films 21 and 22 is formed. Thereafter, the upper surface of the insulating film 22 is planarized by polishing the surface of the insulating film 22 by CMP or the like. Even if unevenness is formed on the surface of the insulating film 21 due to the base step, by polishing the surface of the insulating film 22 by the CMP method, an interlayer insulating film having a flattened surface can be obtained. .

  Next, as shown in FIG. 9, by using the photoresist pattern (not shown) formed on the insulating film 22 as an etching mask, the insulating films 22 and 21 are dry-etched, thereby insulating films 21 and 22. A contact hole (through-hole, hole) 23 is formed.

At this time, first, the insulating film 22 is dry-etched under the condition that the insulating film 22 is more easily etched than the insulating film 21 (that is, the etching condition that the etching speed of the insulating film 22 is higher than the etching speed of the insulating film 21). By making the insulating film 21 function as an etching stopper film, a contact hole 23 is formed in the insulating film 22. At this stage, the contact hole 23 penetrates the insulating film 22 but does not penetrate the insulating film 21, etching is stopped at the insulating film 21, and at least a part of the insulating film 21 remains at the bottom of the contact hole 23. Like that. Then, the insulating film 21 at the bottom of the contact hole 23 is formed under conditions where the insulating film 21 is more easily etched than the insulating film 22 (that is, an etching condition in which the etching rate of the insulating film 21 is higher than the etching rate of the insulating film 22) Remove by dry etching. Thereby, the insulating film 21 is completely removed at the bottom of the contact hole 23, the contact hole 23 penetrates the insulating films 22, 21, and a part of the main surface of the semiconductor substrate 1 at the bottom of the contact hole 23, for example, n ⁺ A part of metal silicide layer 13 on the surface of type semiconductor region 7b and p ⁺ type semiconductor region 8b, a part of metal silicide layer 13 on the surface of gate electrodes 6a and 6b, and the like are exposed.

Next, plugs (connecting conductor portions, embedded plugs, embedded conductor portions) 24 made of tungsten (W) or the like are formed in the contact holes 23. In order to form the plug 24, for example, a barrier conductor film 24a (for example, a titanium film, a titanium nitride film, or the like) is formed on the insulating film 22 including the inside (on the bottom and side walls) of the contact hole 23 by a plasma CVD method or the like. A laminated film) is formed. Then, a main conductor film 24b made of a tungsten film or the like is formed so as to fill the contact hole 23 on the barrier conductor film 24a by CVD or the like, and the unnecessary main conductor film 24b and barrier conductor film 24a on the insulating film 22 are CMPed. By removing by the method or the etch back method, the plug 24 composed of the main conductor film 24b and the barrier conductor film 24a remaining in the contact hole 23 can be formed. The plug 24 formed on the gate electrodes 6a, 6b, the n ⁺ type semiconductor region 7b or the p ⁺ type semiconductor region 8b has a gate electrode 6a, 6b, an n ⁺ type semiconductor region 7b or a p ⁺ type semiconductor region 8b at the bottom. The metal silicide layer 13 on the surface of the metal is in contact with and electrically connected.

  Next, as shown in FIG. 10, a stopper insulating film 31 and a wiring forming insulating film 32 are sequentially formed on the insulating film 22 in which the plugs 24 are embedded. The stopper insulating film 31 is a film that becomes an etching stopper when a groove is formed in the insulating film 32, and a material having an etching selectivity with respect to the insulating film 32 is used. The stopper insulating film 31 can be, for example, a silicon nitride film formed by a plasma CVD method, and the insulating film 32 can be, for example, a silicon oxide film formed by a plasma CVD method. The stopper insulating film 31 and the insulating film 32 are formed with the first layer wiring described below.

Next, a first layer wiring is formed by a single damascene method. First, after forming a wiring groove 33 in a predetermined region of the insulating film 32 and the stopper insulating film 31 by dry etching using a resist pattern (not shown) as a mask, the wiring groove 33 is formed on the main surface of the semiconductor substrate 1 (that is, the wiring groove 33). A barrier conductor film (barrier metal film) 34 is formed on the insulating film 32 including the bottom and side walls. As the barrier conductor film 34, for example, a titanium nitride film, a tantalum film, a tantalum nitride film, or the like can be used. Subsequently, a copper seed layer is formed on the barrier conductor film 34 by CVD or sputtering, and further a copper plating film is formed on the seed layer by electrolytic plating or the like. The inside of 33 is embedded. Then, the copper plating film, the seed layer, and the barrier metal film 34 in a region other than the wiring trench 33 are removed by CMP to form a first-layer wiring 35 embedded in the wiring trench 33 and using copper as a main conductive material. To do. The wiring 35 is electrically connected to the n ⁺ type semiconductor region 7b and p ⁺ type semiconductor region 8b for the source or drain of the n channel MISFET Qn and p channel MISFET Qp, the gate electrodes 6a and 6b, and the like through the plug 24. ing. Thereafter, a second layer wiring is formed by a dual damascene method, but illustration and description thereof are omitted here.

  Next, the formation process of the insulating film 21 will be described in more detail.

  FIG. 11 is a schematic plan view showing an example of a film forming apparatus 41 that can be used for forming the insulating film 21. The film formation apparatus 41 in FIG. 11 can be used for forming the insulating film 21.

  As shown in FIG. 11, the film forming apparatus 41 includes a transfer chamber 42, load lock chambers 44 a and 44 b arranged around the transfer chamber 42 through a gate valve 43 serving as an opening / closing means, and chambers (processing chambers, Reaction chamber) 46a, 46b, 47a, 47b, 48a, 48b. In the film forming apparatus 41, a wafer loading / unloading chamber 51 is provided on the opposite side of the load lock chambers 44a and 44b from the transfer chamber 42, and the wafer loading / unloading chamber 51 is opposite to the load lock chambers 44a and 44b. Are provided with ports 53 for attaching FOUPs (Front Open Unified Pods) 52a and 52b for storing the semiconductor wafer SW.

  The transfer chamber 42 is maintained at a predetermined degree of vacuum by an exhaust mechanism or the like, and a transfer robot 42a for transferring the semiconductor wafer SW is provided at the center thereof. The chambers 46a and 46b provided in the transfer chamber 42 are film forming chambers for forming the insulating film 21 by plasma CVD.

  The film forming apparatus 41 is a multi-chamber type apparatus including a plurality of chambers 46a, 46b, 47a, 47b, 48a, and 48b, but the number of chambers included in the film forming apparatus 41 can be variously changed. Although an apparatus of a type having only a chamber can be used, at least one of the chambers 46a and 46b is necessary.

  Further, in the film forming apparatus 41, the chamber 46a and the chamber 46b have the same configuration as the twin chamber, the chamber 47a and the chamber 47b have the same configuration as the twin chamber, and the chamber 48a and the chamber 48b have the same configuration. The chamber is a twin chamber so that the same processing can be performed on two semiconductor wafers at a time. As another form, one of the chambers 46a and 46b, one of the chambers 47a and 47b, and one of the chambers 48a and 48b can be omitted.

  Next, the configuration of the chambers 46a and 46b of the film forming apparatus 41 will be described. Since the chamber 46a and the chamber 46b have the same configuration, the chambers 46a and 46b will be described as the chamber 46 here. FIG. 12 is a schematic cross-sectional view of a film forming chamber 46 (that is, chambers 46 a and 46 b) provided in the film forming apparatus 41.

  The chamber 46 is a chamber (processing chamber, reaction chamber) used for forming the insulating film 21 on the semiconductor wafer SW (that is, the semiconductor substrate 1) by the CVD method. For example, the chamber 46 is a chamber of a parallel plate type plasma CVD apparatus. is there.

  As shown in FIG. 12, the chamber 46 is a processing chamber capable of vacuum-tightness. In the chamber 46, a lower electrode (substrate electrode) 61 and an upper electrode (high-frequency electrode) 62 facing each other are arranged. Yes. The lower electrode 61 is configured such that the semiconductor wafer SW (that is, the semiconductor substrate 1) can be disposed thereon, and incorporates a heating mechanism such as a heater (not shown) therein. Further, a high-frequency power or a high-frequency voltage can be supplied (applied) between the lower electrode 61 and the upper electrode 62 by a high-frequency power source 63 provided outside the chamber 46.

Further, the chamber 46 is configured so that a desired gas can be introduced into the chamber 46 at a desired flow rate from a gas introduction port 62 a provided in the upper electrode 62. For example, the gas introduction port 62a is connected to a mass flow controller (gas flow rate) in an introduction path of gases (here, SiH ₄ gas, NH ₃ gas, H ₂ gas, N ₂ gas and Ar gas) required in steps S2 and S3 described later. A control device) 64, whereby a desired type of gas (a gas selected from SiH ₄ , NH ₃ , H ₂ , N ₂ and Ar) is supplied from the gas inlet 62a at a desired flow rate. It can be introduced into the chamber 46.

  The chamber 46 is connected to a gas exhaust means (for example, a vacuum pump) (not shown) via a gas exhaust port 65 so that the chamber 46 can be exhausted from the gas exhaust port 65 at a desired exhaust speed. Yes. Further, a pressure control unit (not shown) can adjust the exhaust speed from the gas exhaust port 65 according to the pressure in the chamber 46 detected by the pressure sensor or the like, and can maintain the inside of the chamber 46 at a desired pressure. It is configured as follows.

  FIG. 13 is a manufacturing process flow chart showing the step of forming the insulating film 21. The formation process of the insulating film 21 is performed as follows using the film forming apparatus 41.

  First, the semiconductor wafer SW is taken out from the FOUP 52a or FOUP 52b by the transfer robot 51a or the transfer robot 51b installed in the wafer carry-in / out chamber 51, and is loaded into the load lock chambers 44a and 44b. At this time, the transfer of the semiconductor wafer SW between the transfer robots 51 a and 51 b is performed via the wafer transfer station 54. The semiconductor wafer SW corresponds to the semiconductor substrate 1. The FOUPs 52a and 52b are hermetically sealed containers for batch transfer of the semiconductor wafers SW, and normally store the semiconductor wafers SW in batch units such as 25, 12, and 6 sheets. The container outer walls of the hoops 52a and 52b have a secret structure except for a fine ventilation filter portion, and dust is almost completely eliminated. Therefore, even if transported in a class 1000 atmosphere, the inside can maintain a class 1 cleanliness. Docking with the film forming apparatus 41 is performed in a state in which cleanliness is maintained by attaching the doors of the FOUPs 52 a and 52 b to the port 53 and pulling them into the wafer carry-in / out chamber 51. Subsequently, after the inside of the load lock chambers 44a and 44b is evacuated, the semiconductor robot SW is vacuum transferred from the load lock chambers 44a and 44b to the film forming chambers 46a and 46b via the transfer chamber 42 by the transfer robot 42a. In this manner, the semiconductor wafer SW, that is, the semiconductor substrate 1 is transferred to the chamber 46 (that is, the chambers 46a and 46b) and is disposed in the chamber 46 (step S1). At this time, the semiconductor substrate 1 (semiconductor wafer SW) is disposed on the lower electrode 61 in the chamber 46 with the main surface (upper surface, surface) on the side where the insulating film 21 is formed facing the upper electrode 62. The semiconductor substrate 1 (semiconductor wafer SW) disposed on the lower electrode 61 is heated by a heater built in the lower electrode 61. The semiconductor substrate 1 (semiconductor wafer SW) can also be disposed on the already heated lower electrode 61.

  Next, the semiconductor substrate 1 (semiconductor wafer SW) disposed in the chamber 46 is treated with reducing gas plasma (step S2). Since the metal silicide layer 13 is formed on the semiconductor substrate 1, in step S2, the surface of the metal silicide layer 13 formed on the semiconductor substrate 1 is treated with reducing gas plasma. The natural oxide film (corresponding to an oxide film 72 described later) on the surface of the metal silicide layer 13 is reduced and removed by the plasma treatment of the reducing gas in step S2.

  The reducing gas plasma in step S2 is preferably hydrogen gas plasma (hydrogen plasma), ammonia gas plasma (ammonia plasma), or a mixed gas plasma of hydrogen gas and ammonia gas. As a result, the natural oxide film on the surface of the metal silicide layer 13 can be accurately removed.

That is, in step S2, a reducing gas (preferably hydrogen (H ₂ ) gas, ammonia (NH ₃ ) gas, or a mixed gas thereof) is introduced into the chamber 46 from the gas inlet port 62a, and the gas exhaust port 65 The pressure in the chamber 46 is controlled to a predetermined pressure by adjusting the exhaust speed, and high frequency power (high frequency voltage) is supplied (applied) between the lower electrode 61 and the upper electrode 62 by the high frequency power source 63. Thereby, plasma is generated between the lower electrode 61 and the upper electrode 62 by high-frequency glow discharge. In this way, the plasma of the reducing gas (preferably hydrogen (H ₂ ) gas, ammonia (NH ₃ ) gas, or a mixed gas thereof) introduced from the gas inlet 62 a is generated in the chamber 46 (the lower electrode 61 and the upper electrode). 62), the surface of the metal silicide layer 13 is treated (plasma treatment) by this plasma, and the natural oxide film on the surface of the metal silicide layer 13 is removed. The plasma treatment of the reducing gas performed in step S2 is preferably performed for about 10 to 60 seconds, whereby the natural oxide film on the surface of the metal silicide layer 13 can be removed, and the manufacturing time is increased and the throughput is reduced. Can be prevented.

In step S2, in addition to the reducing gas (preferably hydrogen (H ₂ ) gas, ammonia (NH ₃ ) gas, or a mixed gas thereof), an inert gas such as nitrogen (N ₂ ) is used as a dilution gas or a carrier gas. ) Gas, single or plural gases selected from argon (Ar) gas and helium (He) gas may be introduced into the chamber 46 from the gas inlet 62a. In this case, in step S2, a reducing gas (preferably hydrogen (H ₂ ) gas or ammonia (NH ₃ ) gas or a mixed gas thereof) and an inert gas (for example, nitrogen gas, argon gas and helium gas) are selected. The natural oxide film is removed by treating the surface of the metal silicide layer 13 with a mixed gas plasma with a single gas or a plurality of gases.

Further, since step S2 is intended to reduce the surface of the metal silicide layer 13 (reduction treatment or removal of the natural oxide film), in step S2, a silicon source gas such as silane (SiH ₄ ) gas (Si is used. Gas contained as a constituent element) is not introduced into the chamber 46.

  After the plasma treatment of the reducing gas in step S2, an insulating film 21 made of silicon nitride is deposited on the semiconductor substrate 1 (that is, the semiconductor wafer SW) by the plasma CVD method (step S3). After the plasma treatment of the reducing gas in step S2, it is important to perform the step of depositing the insulating film 21 in step S3 without exposing the semiconductor substrate 1 (semiconductor wafer SW) to the atmosphere (in an oxygen-containing atmosphere). . Thereby, the insulating film 21 can be formed on the semiconductor substrate 1 including the surface of the metal silicide layer 13 without re-forming the natural oxide film on the surface of the metal silicide layer 13. For this reason, it is preferable that the reducing gas plasma treatment process in step S2 and the insulating film 21 deposition process in step S3 are continuously performed in the same chamber 46. Further, it is preferable to start the deposition process of step S3 in the same chamber 46 without taking out the semiconductor substrate 1 from the chamber 46 after performing the reducing gas plasma processing process of step S2 in the chamber 46. The oxygen-containing gas is not introduced into the chamber 46 after the plasma treatment of the reducing gas in step S2 until the insulating film 21 (silicon nitride film) is deposited in step S3. As a result, after the plasma treatment of the reducing gas in step S2, the step of depositing the insulating film 21 in step S3 can be performed without exposing the semiconductor substrate 1 (semiconductor wafer SW) to an oxygen-containing atmosphere. Reoxidation of the surface of the layer 13 can be prevented.

That is, after step S2, high-frequency power (high-frequency voltage) supplied (applied) between the lower electrode 61 and the upper electrode 62 is temporarily stopped. Then, in step S3, a reaction gas (source gas, source gas, film forming gas), for example, silane (SiH ₄ ) gas, ammonia (NH ₃ ) gas, and nitrogen (N ₂ ) is introduced into the chamber 46 from the gas inlet 62a. Gas is introduced, the exhaust speed from the gas exhaust port 65 is adjusted, and the pressure in the chamber 46 is controlled to a predetermined pressure. Is supplied (applied). Thereby, plasma is generated between the lower electrode 61 and the upper electrode 62 by high frequency glow discharge, the reaction gas is decomposed, and a silicon nitride film is formed on the semiconductor substrate 1 (semiconductor wafer SW) disposed on the lower electrode 61. An insulating film 21 made of (plasma silicon nitride film) is deposited. Hereinafter, a silicon nitride film formed by plasma CVD may be referred to as a plasma silicon nitride film.

In step S3, a first gas containing silicon (Si) element as a constituent element, preferably a silane-based material such as silane (SiH ₄ ) gas, is used as a silicon source gas of silicon nitride from the gas inlet 62a into the chamber 46. A gas and a second gas containing nitrogen as a constituent element, preferably ammonia (NH ₃ ) gas, are introduced as a nitrogen source gas of silicon nitride, and plasma of these gases is generated to deposit the insulating film 21. Let In step S3, an inert gas such as a diluent gas or a carrier gas, for example, a single gas or a plurality of gases selected from nitrogen (N ₂ ) gas, argon (Ar) gas, and helium (He) gas is used. The gas can be introduced into the chamber 46 from the gas inlet 62a.

  In this embodiment, before the step of depositing the insulating film 21 (silicon nitride film) in step S3, a natural oxide film (corresponding to an oxide film 72 described later) on the surface of the metal silicide layer 13 is formed by in-situ processing. Since it is reduced and removed by the reducing gas plasma treatment in step S2, the insulating film 21 is deposited on the metal silicide layer 13 from which the oxide film on the surface has been removed.

  After the step of forming the insulating film 21 in step S3, the semiconductor substrate 1 (semiconductor wafer SW) is taken out of the chamber 46 (step S4) and sent to the next step (step of forming the insulating film 22). For example, the semiconductor wafer SW is vacuum-transferred from the deposition chambers 46a and 46b (that is, the chamber 46) to the load lock chambers 44a and 44b by the transfer robot 42a, and then transferred to the load robots 51a and 51b. Thus, the semiconductor wafer SW is returned from the load lock chambers 44a and 44b to the original FOUP 52a or FOUP 52b via the wafer loading / unloading chamber 51. At this time, the transfer of the semiconductor wafer SW between the transfer robots 51 a and 51 b is performed via the wafer transfer station 54.

  As described above, in this embodiment, after the surface of the metal silicide layer 13 is treated with plasma of a reducing gas (preferably ammonia gas, hydrogen gas, or a mixed gas thereof) in step S2, the semiconductor substrate 1 is exposed to the atmosphere. In step S3, an insulating film 21 (silicon nitride film) is formed on the semiconductor substrate 1 including the metal silicide layer 13 by plasma CVD without being exposed to the inside. More preferably, after the surface of the metal silicide layer 13 is treated with reducing gas plasma in step S2, the semiconductor substrate 1 including the metal silicide layer 13 is exposed in step S3 without exposing the semiconductor substrate 1 to an oxygen-containing atmosphere. An insulating film 21 is formed. The natural oxide film (corresponding to an oxide film 72 described later) on the surface of the metal silicide layer 13 is removed by the plasma treatment of the reducing gas in step S2, and then the semiconductor substrate 1 is exposed to the atmosphere (in an oxygen-containing atmosphere). Therefore, since the insulating film 21 is deposited in step S3, an oxide film is not formed at the interface between the formed insulating film 21 and the metal silicide layer 13. For this reason, even if various heating processes after the formation of the insulating film 21 (for example, processes involving heating of the semiconductor substrate 1 as in the process of forming various insulating films and conductor films) are performed, the metal silicide layer 13 is formed. It is possible to prevent the metal silicide layer 13 from partially growing abnormally due to oxygen in the oxide film at the interface between the insulating film 21 and the insulating film 21. Thereby, an increase in resistance of the metal silicide layer 13 due to abnormal growth can be prevented. Further, it is possible to prevent the metal silicide layer 13 formed on the source / drain regions from abnormally growing in the channel portion and increasing the leakage current between the source and drain of the field effect transistor. Therefore, the performance of the semiconductor device can be improved. In addition, the reliability of the semiconductor device can be improved.

  The insulating film 21 functions as an etching stopper film when the insulating film 22 is etched to form the contact hole 23, but can also be regarded as an insulating film for SAC (Self Align Contact). If the insulating film 21 formed on the main surface of the semiconductor substrate 1 is a film that generates a tensile stress in the semiconductor substrate 1, the n-channel MISFET Qn has improved mobility and increased drive current. improves. Further, if the insulating film 21 formed on the main surface of the semiconductor substrate 1 is a film that generates compressive stress in the semiconductor substrate 1, the p-channel type MISFET Qp has improved mobility and increased drive current. Improved characteristics. For this reason, the insulating film 21 formed on the main surface of the semiconductor substrate 1 may be a film that generates a tensile stress in the semiconductor substrate 1 or a film that generates a compressive stress. Selected.

  Therefore, the insulating film 21 formed in step S3 is used as a film that generates tensile stress in the semiconductor substrate 1, and the insulating film 21 formed in step S3 is used as a film that generates compressive stress in the semiconductor substrate 1. The preferable deposition method of the insulating film 21 will be described in more detail by dividing the plasma treatment of the reducing gas in step S2 into ammonia plasma and hydrogen plasma.

  First, referring to FIG. 14, a case where the insulating film 21 formed in step S3 is a film that causes tensile stress in the semiconductor substrate 1 and the plasma treatment of the reducing gas in step S2 is performed with ammonia plasma. I will explain.

  FIG. 14 is an explanatory diagram (table) showing process steps of the first film forming method in the film forming process of the insulating film 21 (silicon nitride film), and after the semiconductor substrate 1 is placed in the chamber 46 in step S1. The state of the chamber 46 until the semiconductor substrate 1 is taken out from the chamber 46 in step S4 is shown. In the first film forming method of FIG. 14, the reducing gas plasma treatment in step S2 is performed with ammonia plasma, and the insulating film 21 formed in step S3 is a film that causes tensile stress on the semiconductor substrate 1. This corresponds to a preferable example (embodiment, specific example).

14 and FIGS. 15 to 17 to be described later, the time required for each step (unit: second) is described in the “time” column, and the semiconductor substrate 1 at each step is described in the “temperature” column. The heating temperature (unit: ° C.) is described, and the pressure (unit: Pa) in the chamber 46 at each step is described in the “pressure” column. In FIG. 14 and FIGS. 15 to 17 to be described later, the flow rate (unit: sccm) of silane (SiH ₄ ) gas introduced into the chamber 46 from the gas introduction port 62a in each step in the column of “SiH ₄ flow rate”. In the “NH ₃ flow rate” column, the flow rate (unit: sccm) of ammonia (NH ₃ ) gas introduced into the chamber 46 from the gas introduction port 62a in each step is described. In FIG. 14 and FIGS. 15 to 17 to be described later, the flow rate of hydrogen (H ₂ ) gas introduced into the chamber 46 from the gas inlet 62a in each step is indicated in the “H ₂ flow rate” column (unit is sccm). In the “N ₂ flow rate” column, the flow rate (unit: sccm) of nitrogen (N ₂ ) gas introduced into the chamber 46 from the gas inlet 62a in each step is described. In FIG. 14 and FIGS. 15 to 17 described later, the flow rate of argon (Ar) gas introduced into the chamber 46 from the gas inlet 62a in each step is described in the “Ar flow rate” column (unit is sccm). is doing. Further, in FIG. 14 and FIGS. 15 to 17 to be described later, high-frequency power (unit: W) supplied (applied) between the lower electrode 61 and the upper electrode 62 in each step is entered in the column of “high-frequency RF power”. The frequency to be described and applied is 13.56 MHz. In FIG. 16 and FIG. 17 to be described later, in the “low frequency RF power” column, a frequency lower than “high frequency RF power” supplied (applied) between the lower electrode 61 and the upper electrode 62 in each step. The high frequency power (unit: W) is described, and the applied frequency is 350 kHz. 14 and FIG. 15 to FIG. 17 described later, when “full open” is described, the chamber 46 is evacuated (vacuum) with the exhaust speed from the gas exhaust port 65 maximized. This corresponds to the case of exhaust. In each of FIG. 14 and FIGS. 15 to 17 described below, the steps shown are performed continuously.

  In step S <b> 1, the semiconductor substrate 1 (semiconductor wafer SW) is placed on the lower electrode 61 in the chamber 46 and heated by a heater built in the lower electrode 61. The semiconductor substrate 1 (semiconductor wafer SW) may be disposed on the already heated lower electrode 61. During steps S11a to S21a in FIG. 14, the heating temperature of the semiconductor substrate 1 (the temperature of the lower electrode 61 on which the semiconductor substrate 1 is disposed) is preferably maintained at 250 to 500 ° C., for example, about 480 ° C.

Then, in step S11a of FIG. 14, nitrogen (N ₂ ) gas is introduced into the chamber 46 from the gas inlet 62a at a predetermined flow rate (for example, 18000 sccm), and the pressure in the chamber 46 is set to a predetermined pressure (for example, 560 Pa). Control. This pressure is maintained in steps S11a and S12a in FIG. Step S11a is a step of stabilizing the pressure in the chamber 46.

Next, in step S12a of FIG. 14, in addition to nitrogen (N ₂ ) gas similar to that in step S11a, ammonia (NH ₃ ) gas is further introduced into the chamber 46 from the gas inlet 62a into the chamber 46 at a predetermined flow rate (for example, 160 sccm). Then, plasma is generated by supplying (applying) high frequency power (high frequency voltage) of, for example, 13.56 MHz at a predetermined power (preferably 30 to 1000 W, for example, 300 W) between the lower electrode 61 and the upper electrode 62. As a result, ammonia (NH ₃ ) gas and nitrogen (N ₂ ) gas in the chamber 46 (between the lower electrode 61 and the upper electrode 62) are turned into plasma, and the surface of the metal silicide layer 13 is treated with ammonia plasma. Therefore, step S12a is a step of treating the surface of the metal silicide layer 13 with ammonia plasma, and corresponds to the above step S2 (step of treating the surface of the metal silicide layer 13 with plasma of reducing gas). The natural oxide film on the surface of the metal silicide layer 13 is reduced and removed by the ammonia plasma treatment in step S12a. Step S12a is preferably performed for about 10 to 60 seconds, whereby it is possible to reduce and remove the natural oxide film on the surface of the metal silicide layer 13, and it is possible to prevent the manufacturing time from increasing and the throughput from decreasing. The reason why not only ammonia (NH ₃ ) gas but also nitrogen (N ₂ ) gas is introduced into the chamber 46 from the gas inlet 62a in step S12a is to stabilize the pressure and plasma.

  Next, in step S13a of FIG. 14, the supply (application) of high-frequency power (high-frequency voltage) between the lower electrode 61 and the upper electrode 62 and the introduction of gas into the chamber 46 from the gas inlet 62a are stopped. The chamber 46 is evacuated (evacuated) from the exhaust port 65. Step S13a is a step of evacuating (evacuating) the chamber 46.

Next, in step S17a of FIG. 14, silane (SiH ₄ ) gas, ammonia (NH ₃ ) gas, and nitrogen (N ₂ ) gas are supplied from the gas inlet 62a into the chamber 46 at predetermined flow rates (for example, 25 sccm and 50 sccm, respectively). And 20000 sccm), and the pressure in the chamber 46 is controlled to a predetermined pressure (for example, 800 Pa). This pressure is maintained in steps S17a to S20a in FIG. Further, the introduction of nitrogen (N ₂ ) gas into the chamber 46 is maintained in steps S17a to S20a in FIG. Step S17a is a step of stabilizing the gas (gas ratio, pressure, etc.) in the chamber 46.

In step S17a, the flow rate of one or both of silane (SiH ₄ ) gas and ammonia (NH ₃ ) gas is set to zero (that is, one or both of silane gas and ammonia gas are not introduced into chamber 46). it can. However, in step S17a, it is preferable to introduce both silane (SiH ₄ ) gas and ammonia (NH ₃ ) gas into the chamber 46 as in step S18a, and thereby the silicon nitride film semiconductor deposited in step S18a. The uniformity (for example, the uniformity of the film thickness distribution) within the main surface of the wafer SW can be improved.

Next, in step S18a of FIG. 14 (and step S18b of FIG. 15 described later), which is a silicon nitride film deposition (film formation) step, for example, a high-frequency power (high-frequency) of 13.56 MHz is provided between the lower electrode 61 and the upper electrode 62. A voltage is supplied (applied) at a predetermined power (preferably 30 to 150 W, for example, 45 W) to generate plasma. As a result, silane (SiH ₄ ) gas, ammonia (NH ₃ ) gas, and nitrogen (N ₂ ) gas in the chamber 46 (between the lower electrode 61 and the upper electrode 62) are turned into plasma, and the semiconductor disposed on the lower electrode 61. A silicon nitride film (plasma silicon nitride film) is deposited on the substrate 1. Step S18a (and step S18b described later) is a step of depositing a silicon nitride film on the semiconductor substrate 1 by a plasma CVD method. Supply (application) of the high-frequency power (for example, 13.56 MHz) between the lower electrode 61 and the upper electrode 62 is maintained in steps S18a and S19a in FIG. 14 (and steps S18b and S19b in FIG. 15 described later).

In step S18a of FIG. 14 and step S18b of FIG. 15 described later, the flow rate ratio of ammonia (NH ₃ ) gas and silane (SiH ₄ ) gas introduced into the chamber 46 from the gas inlet 62a is “ammonia (NH ₃ ) Gas flow rate "/" Silane (SiH ₄ ) gas flow rate "is preferably 2/1 or more and 500/1 or less. In step S18a in FIG. 14 and step S18b in FIG. 15 described later, the flow rate of the silane (SiH ₄ ) gas is preferably 10 to 150 sccm. Thereby, the silicon nitride film can be deposited accurately.

In step S18a (and step S18b described later), silane (SiH ₄ ) gas, which is a silicon source gas of silicon nitride, and ammonia (NH _3), which is a nitrogen source gas of silicon nitride, enter the chamber 46 from the gas inlet 62a. ) The reason for introducing not only gas but also nitrogen (N ₂ ) gas is to stabilize the pressure and plasma.

Next, in order to further increase the stress (tensile stress) of the tensile stress film (silicon nitride film) obtained in step S18a in FIG. 14, step S19a in FIG. 14 may be added after step S18a. In step S19a of FIG. 14, the introduction of silane (SiH ₄ ) gas and ammonia (NH ₃ ) gas from the gas inlet 62a into the chamber 46 is stopped, and the introduction of nitrogen (N ₂ ) gas is continued. Thereby, the surface of the semiconductor substrate 1, that is, the surface of the silicon nitride film (plasma silicon nitride film) deposited in step S18a is treated with nitrogen plasma. By treating the surface of the silicon nitride film (plasma silicon nitride film) deposited in step S18a with nitrogen plasma in step S19a, hydrogen (H) in the silicon nitride film (plasma silicon nitride film) is reduced, There are many unbound hands. Step S19a is a step of performing nitrogen plasma treatment on the surface of the silicon nitride film deposited in step S18a.

  Thereafter, steps S17a, S18a, and S19a in FIG. 14 are repeated one or more cycles until the total thickness of the silicon nitride films deposited in step S18a reaches a desired thickness. That is, after step S17a, step S18a, and step S19a are performed in order, the process returns to step S17a and step S17a, step S18a, and step S19a are performed again in order, and this is repeated until the deposited thickness of the silicon nitride film reaches a desired thickness. . Accordingly, the step S17a, S18a, S19a repeated one or more times a predetermined number of times corresponds to the step S3 (deposition step of the insulating film 21). When steps S17a, S18a, and S19a are repeated, the high-frequency power (for example, 13.56 MHz) is supplied (applied) between the lower electrode 61 and the upper electrode 62 in steps S18a and S19a, and in step S17a, the lower electrode 61 and High frequency power is not supplied (applied) between the upper electrodes 62.

After steps S17a, S18a, and S19a in FIG. 14 are repeated to form a silicon nitride film having a desired film thickness on the semiconductor substrate 1, a high frequency between the lower electrode 61 and the upper electrode 62 is obtained in step S20a in FIG. Stop supplying (applying) power (high-frequency voltage). In step S20a, only nitrogen (N ₂ ) gas is introduced into the chamber 46 from the gas inlet 62a, and the inside of the chamber 46 is purged with nitrogen (N ₂ ) gas.

  Next, in step S21a of FIG. 14, the introduction of gas from the gas inlet 62a into the chamber 46 is stopped, and the inside of the chamber 46 is exhausted (vacuum exhausted) from the gas exhaust port 65. Step S21a is a step of evacuating (evacuating) the chamber 46.

  Thereafter, in step S4, the semiconductor substrate 1 (semiconductor wafer SW) is taken out of the chamber 46 and sent to the next process (film formation process of the insulating film 22).

A silicon nitride film formed by plasma CVD on the main surface of the semiconductor substrate 1 becomes a film that causes tensile stress in the semiconductor substrate 1 when there are a large number of dangling bonds in the film, thereby reducing dangling bonds in the film. As a result, the semiconductor substrate 1 becomes a film that generates compressive stress. In step S18a, a silicon nitride film in which hydrogen (a hydrogen element in SiH ₄ and NH ₃ in this case) contained as a constituent element of the film-forming gas is taken into the film is deposited, but the hydrogen in the silicon nitride film ( H) is reduced by the nitrogen plasma treatment in step S19a, and the number of dangling bonds in the silicon nitride film can be increased. Therefore, the insulating film 21 made of a silicon nitride film deposited to a desired thickness by repeating steps S17a, S18a, and S19a (which corresponds to an insulating film 21a described later) has more dangling bonds in the film. It becomes a film, and thereby a film that causes a larger tensile stress on the semiconductor substrate 1. By making the insulating film 21 a film that generates a tensile stress in the semiconductor substrate 1, the n-channel type MISFET Qn has improved mobility and increased driving current, so that switching characteristics can be improved.

  Further, if the insulating film 21 is formed by repeating steps S17a, S18a, and S19a for a plurality of cycles, the thickness of the silicon nitride film deposited in step S18a of each cycle is reduced, and it is subjected to nitrogen plasma treatment in step S19a. Therefore, the effect of reducing hydrogen by nitrogen plasma is greater than when a silicon nitride film having a final thickness is deposited in a single step and then subjected to nitrogen plasma treatment. For this reason, the number of dangling bonds in the finally formed insulating film 21 is increased, and the tensile stress generated by the insulating film 21 on the semiconductor substrate 1 can be further increased.

  Next, refer to FIG. 15 for the case where the insulating film 21 formed in step S3 is a film that generates tensile stress in the semiconductor substrate 1 and the plasma treatment of the reducing gas in step S2 is performed with hydrogen plasma. To explain.

  FIG. 15 is an explanatory diagram (table) showing process steps of the second film formation method in the film formation process of the insulating film 21 (silicon nitride film), and after the semiconductor substrate 1 is placed in the chamber 46 in step S1. The state of the chamber 46 until the semiconductor substrate 1 is taken out from the chamber 46 in step S4 is shown. In the second film forming method of FIG. 15, the reducing gas plasma treatment in step S2 is performed with hydrogen plasma, and the insulating film 21 formed in step S3 is a film that generates a tensile stress on the semiconductor substrate 1. This corresponds to a preferable example (embodiment, specific example).

  In step S <b> 1, the semiconductor substrate 1 (semiconductor wafer SW) is placed on the lower electrode 61 in the chamber 46 and heated by a heater built in the lower electrode 61. The semiconductor substrate 1 (semiconductor wafer SW) may be disposed on the already heated lower electrode 61. During steps S11b to S21b in FIG. 15, the heating temperature of the semiconductor substrate 1 (the temperature of the lower electrode 61 on which the semiconductor substrate 1 is disposed) is preferably maintained at 250 to 500 ° C., for example, about 480 ° C.

Then, in step S11b of FIG. 15, hydrogen (H ₂ ) gas and argon (Ar) gas are introduced into the chamber 46 from the gas inlet 62a at a predetermined flow rate (for example, 4000 sccm and 800 sccm, respectively), and the pressure in the chamber 46 is increased. Is controlled to a predetermined pressure (for example, 560 Pa). This flow rate and pressure are maintained in steps S11b to S12b. Step S11b is a step of stabilizing the pressure in the chamber 46.

Next, in step S12b of FIG. 15, high frequency power (high frequency voltage) of, for example, 13.56 MHz is supplied (applied) between the lower electrode 61 and the upper electrode 62 at a predetermined power (preferably 30 to 1000 W, for example, 300 W). To generate plasma. As a result, the hydrogen (H ₂ ) gas and the argon (Ar) gas in the chamber 46 (between the lower electrode 61 and the upper electrode 62) are turned into plasma, and the surface of the metal silicide layer 13 is treated with hydrogen plasma. Therefore, step S12b is a step of treating the surface of the metal silicide layer 13 with hydrogen plasma, and corresponds to the above step S2 (step of treating the surface of the metal silicide layer 13 with plasma of reducing gas). The natural oxide film on the surface of the metal silicide layer 13 is reduced and removed by the hydrogen plasma treatment in step S12b. Step S12b is preferably performed for about 10 to 60 seconds, whereby it is possible to reduce and remove the natural oxide film on the surface of the metal silicide layer 13, and it is possible to prevent the manufacturing time from increasing and the throughput from decreasing.

The reason why not only hydrogen (H ₂ ) but also argon (Ar) gas is introduced into the chamber 46 from the gas inlet 62a in step S12b is to stabilize the plasma as an inert gas.

  Next, in step S13b of FIG. 15, the supply (application) of high-frequency power (high-frequency voltage) between the lower electrode 61 and the upper electrode 62 and the introduction of gas from the gas inlet 62a into the chamber 46 are stopped, The chamber 46 is evacuated (evacuated) from the exhaust port 65. Step S13b is a step of evacuating (evacuating) the chamber 46.

Next, in step S14b of FIG. 15, ammonia (NH ₃ ) gas and nitrogen (N ₂ ) gas are introduced into the chamber 46 from the gas inlet 62a at predetermined flow rates (for example, 100 sccm and 20000 sccm, respectively). The pressure is controlled to a predetermined pressure (for example, 800 Pa). This pressure is maintained in steps S14b to S20b in FIG. Further, the introduction of nitrogen (N ₂ ) gas into the chamber 46 is maintained in steps S14b to S20b in FIG. Step S14b is a step of stabilizing the pressure in the chamber 46, but may be omitted if unnecessary. However, in the case where the flow rate of ammonia (NH ₃ ) gas is sufficiently larger than the flow rate of silane (SiH ₄ ) gas in step S 15 b described later, it is more preferable to provide step S 14 b and to stabilize the gas in the chamber 46. Can increase the sex.

Next, in step S15b in FIG. 15, in addition to ammonia (NH ₃ ) gas and nitrogen (N ₂ ) gas similar to step S14b, silane (SiH ₄ ) gas is further introduced at a predetermined flow rate (for example, 75 sccm). The gas is introduced into the chamber 46 from the port 62a. This step S15b is a step for forming a thin nitride film (corresponding to a nitride film 73b described later) on the metal silicide layer 13 of the semiconductor substrate 1 by the catalytic action of the metal silicide. In step S15b, the state of introducing silane (SiH ₄ ) gas, ammonia (NH ₃ ) gas, and nitrogen (N ₂ ) gas into the chamber 46 from the gas inlet 62a is preferably continued for about 3 to 30 seconds. By setting step S15b to 3 to 30 seconds, a nitride film 73b described later can be formed, and an increase in manufacturing time can be prevented.

Next, in step S16b of FIG. 15, introduction of silane (SiH ₄ ) gas and ammonia (NH ₃ ) gas into the chamber 46 from the gas introduction port 62a is stopped, and introduction into the chamber 46 from the gas introduction port 62a. The gas is only nitrogen (N ₂ ) gas. Step S <b> 16 b is a step of exhausting silane (SiH ₄ ) gas and ammonia (NH ₃ ) gas from the chamber 46. Step S16b can be omitted if unnecessary. However, if the flow rate ratio of silane (SiH ₄ ) gas and ammonia (NH ₃ ) gas introduced into the chamber 46 is different between step S15b and steps S17b and S18b described later, step S16b is provided. Preferably, this makes it possible to make the gas in the chamber 46 more stable in steps S17b and S18b described later.

  Thereafter, steps S17b, S18b, S19b, S20b, and S21b similar to steps S17a, S18a, S19a, S20a, and S21a are performed.

That is, in step S17b of FIG. 15, in addition to the same nitrogen (N ₂ ) gas as in step S14b, silane (SiH ₄ ) gas and ammonia (NH ₃ ) gas are further supplied into the chamber 46 from the gas inlet 62a. At a flow rate of, for example, 25 sccm and 50 sccm, respectively. Step S17b is a step of stabilizing the gas (gas ratio, pressure, etc.) in the chamber 46.

Next, in step S18b of FIG. 15, high frequency power (high frequency voltage) of, for example, 13.56 MHz is supplied (applied) between the lower electrode 61 and the upper electrode 62 at a predetermined power (preferably 30 to 150 W, for example, 45 W). To generate plasma. As a result, silane (SiH ₄ ) gas, ammonia (NH ₃ ) gas, and nitrogen (N ₂ ) gas in the chamber 46 (between the lower electrode 61 and the upper electrode 62) are turned into plasma, and the semiconductor disposed on the lower electrode 61. A silicon nitride film (plasma silicon nitride film) is deposited on the substrate 1. Step S18b is a step of depositing silicon nitride on the semiconductor substrate 1 by a plasma CVD method. The supply (application) of the high-frequency power (for example, 13.56 MHz) between the lower electrode 61 and the upper electrode 62 is maintained in steps S18b to S19b.

Next, in order to further increase the stress (tensile stress) of the tensile stress film (silicon nitride film) obtained in step S18b of FIG. 15, step S19b of FIG. 15 may be added after step S18b. In step S19b of FIG. 15, the introduction of silane (SiH ₄ ) gas and ammonia (NH ₃ ) gas from the gas inlet 62a into the chamber 46 is stopped, and the introduction of nitrogen (N ₂ ) gas is continued. Thus, the surface of the semiconductor substrate 1, that is, the surface of the silicon nitride film (plasma silicon nitride film) deposited in step S18b is treated with nitrogen plasma. By treating the surface of the silicon nitride film (plasma silicon nitride film) deposited in step S18b with nitrogen plasma in step S19b, hydrogen (H) in the silicon nitride film (plasma silicon nitride film) is reduced, There are many unbound hands. Step S19b is a step of performing nitrogen plasma treatment on the surface of the silicon nitride film deposited in step S18b.

  Thereafter, steps S17b, S18b, and S19b are repeated one or more cycles until the total thickness of the silicon nitride films deposited in step S18b reaches a desired thickness. That is, after step S17b, step S18b, and step S19b are performed in order, the process returns to step S17b and step S17b, step S18b, and step S19b are performed again in order, and this is repeated until the deposition thickness of the silicon nitride film reaches a desired thickness. . Accordingly, the step S17b, S18b, S19b repeated one or more times a predetermined number of times corresponds to the step S3 (deposition step of the insulating film 21). When steps S17b, S18b, and S19b are repeated, the high-frequency power (for example, 13.56 MHz) is supplied (applied) between the lower electrode 61 and the upper electrode 62 in steps S18b to S19b, and in step S17b, the lower electrode 61 and High frequency power is not supplied (applied) between the upper electrodes 62.

After steps S17b, S18b, and S19b are repeated to form a silicon nitride film having a desired film thickness on the semiconductor substrate 1, in step S20b of FIG. (Voltage) supply (application) is stopped. In step S20b, only nitrogen (N ₂ ) gas is introduced into the chamber 46 from the gas inlet 62a, and the inside of the chamber 46 is purged with nitrogen (N ₂ ) gas.

  Next, in step S21b of FIG. 15, the introduction of gas from the gas inlet 62a into the chamber 46 is stopped, and the inside of the chamber 46 is exhausted (vacuum exhausted) from the gas outlet 65. Step S21b is a step of evacuating (evacuating) the chamber 46.

  Thereafter, in step S4, the semiconductor substrate 1 (semiconductor wafer SW) is taken out of the chamber 46 and sent to the next process (film formation process of the insulating film 22).

  The insulating film 21 made of a silicon nitride film deposited to a desired thickness by repeating steps S17b, S18b, and S19b similar to steps S17a, s18a, and S19a described above corresponds to the insulating film 21a described later. As described above, the film has a larger number of dangling bonds in the film, and as a result, a film that causes a greater tensile stress on the semiconductor substrate 1 is obtained. By making the insulating film 21 a film that generates a tensile stress in the semiconductor substrate 1, the n-channel type MISFET Qn has improved mobility and increased driving current, so that switching characteristics can be improved.

  Further, for the purpose of increasing the number of dangling bonds in the silicon nitride film (plasma silicon nitride film) deposited in steps S18a and S18b, instead of steps S19a and 19b (nitrogen plasma treatment), the semiconductor substrate 1 (semiconductor The wafer SW can be subjected to UV (ultraviolet) irradiation treatment. In this case, for example, after depositing a silicon nitride film in step S18a or step S18b, the semiconductor wafer SW (semiconductor substrate 1) is taken out from the chamber 46 and moved to a UV irradiation processing chamber (for example, the chambers 47a and 47b). After the semiconductor wafer SW is subjected to UV irradiation treatment in the chamber, the semiconductor wafer SW is returned to the chamber 46, and the silicon nitride film is deposited again in step S18a or step S18b. In other words, the deposition of the plasma silicon nitride film in the chamber 46 in step S18a or step S18b and the UV irradiation process in the other chamber, the total film thickness of the silicon nitride film deposited in step S18a or step S18b is desired. By repeating until the film thickness is reached, the insulating film 21 having a desired thickness is formed. In steps S18a and S18b, a silicon nitride film containing hydrogen is deposited, but hydrogen (H) in the silicon nitride film is further reduced by the UV irradiation treatment, and more dangling bonds in the silicon nitride film can be obtained. . For this reason, the insulating film 21 made of a silicon nitride film deposited to a desired thickness by repeating the step S18a or step S18b and the UV irradiation process becomes a film with more dangling bonds in the film, thereby making the semiconductor It can be set as the film | membrane which produces the bigger tensile stress on the board | substrate 1. FIG.

  Next, refer to FIG. 16 for the case where the insulating film 21 formed in step S3 is a film that generates compressive stress in the semiconductor substrate 1 and the plasma treatment of the reducing gas in step S2 is performed with ammonia plasma. To explain.

  FIG. 16 is an explanatory diagram (table) showing process steps of the third film forming method in the film forming process of the insulating film 21 (silicon nitride film), and after the semiconductor substrate 1 is placed in the chamber 46 in step S1. The state of the chamber 46 until the semiconductor substrate 1 is taken out from the chamber 46 in step S4 is shown. In the third film forming method of FIG. 16, the plasma treatment of the reducing gas in step S2 is performed with ammonia plasma, and the insulating film 21 formed in step S3 is a film that generates compressive stress on the semiconductor substrate 1. This corresponds to a preferable example (embodiment, specific example).

  In step S <b> 1, the semiconductor substrate 1 (semiconductor wafer SW) is placed on the lower electrode 61 in the chamber 46 and heated by a heater built in the lower electrode 61. The semiconductor substrate 1 (semiconductor wafer SW) may be disposed on the already heated lower electrode 61. During steps S31a to S41a in FIG. 16, the heating temperature of the semiconductor substrate 1 (the temperature of the lower electrode 61 on which the semiconductor substrate 1 is disposed) is preferably maintained at 250 to 500 ° C., for example, about 480 ° C.

  Next, in step S31a in FIG. 16, the same operation (process) as in step S11a in FIG. 14 is performed. Then, in step S32a in FIG. 16, the same operation (process) as in step S12a in FIG. In step S33a in FIG. 16, the same operation (process) as in step S13a in FIG. 14 is performed. That is, steps S31a, 32a, and 33a in FIG. 16 are the same operations and processes as steps S11a, 12a, and 13a in FIG.

Next, in step S35a of FIG. 16, silane (SiH ₄ ) gas, ammonia (NH ₃ ) gas, and nitrogen (N ₂ ) gas are supplied from the gas inlet 62a into the chamber 46 at predetermined flow rates (for example, 60 sccm and 130 sccm, respectively). And 4000 sccm), and the pressure in the chamber 46 is controlled to a predetermined pressure (for example, 267 Pa). This pressure is maintained in steps S35a to S40a in FIG. Further, introduction of silane (SiH ₄ ) gas and ammonia (NH ₃ ) gas into the chamber 46 is maintained in steps S35a to S39a in FIG. Introducing nitrogen (N ₂ ) gas into the chamber 46 reduces the flow rate in order in steps S35a and S36a, step S37a, step S38a, and steps S39a and 40a. Step S35a is a step of stabilizing the gas (gas ratio, pressure, etc.) in the chamber 46.

In step S35a, the flow rate of one or both of silane (SiH ₄ ) gas and ammonia (NH ₃ ) gas is set to zero (that is, one or both of silane gas and ammonia gas are not introduced into chamber 46). it can. However, also in step S35a, it is preferable to introduce both silane (SiH ₄ ) gas and ammonia (NH ₃ ) gas into the chamber 46, so that the silicon nitride film to be deposited later on the main surface of the semiconductor wafer SW (For example, the uniformity of the film thickness distribution) can be improved.

Next, in step S36a of FIG. 16, in addition to the silane (SiH ₄ ) gas, ammonia (NH ₃ ) gas, and nitrogen (N ₂ ) gas similar to step S35a, argon (Ar) gas is further added at a predetermined flow rate ( For example, 1000 sccm) is introduced into the chamber 46 from the gas inlet 62 a, and a high frequency power (high frequency voltage) of 350 kHz, for example, is supplied (applied) between the lower electrode 61 and the upper electrode 62 at a predetermined power (for example, 75 W). The supply (application) of the 350 kHz high frequency power between the lower electrode 61 and the upper electrode 62 is maintained in steps S36a to S39b in FIG. The introduction of argon (Ar) gas into the chamber 46 increases the flow rate in order in steps S36a and S37a, step S38a, and steps S39a and 40a.

Next, in step S37a of FIG. 16, the flow rate of the nitrogen (N ₂ ) gas introduced into the chamber 46 from the gas inlet 62a is reduced to a predetermined flow rate (eg, 3000 sccm), and the lower electrode 61 and the upper electrode 62 In the meantime, in addition to the high frequency power of, for example, 350 kHz, a higher frequency, for example, high frequency power of 13.56 MHz (high frequency voltage) is supplied (applied) at a predetermined power (preferably 50 to 1000 W, for example, 100 W). . The supply (application) of the 13.56 MHz high-frequency power between the lower electrode 61 and the upper electrode 62 is maintained in steps S37a to S39b in FIG.

Next, in step S38a of FIG. 16, the flow rate of nitrogen (N ₂ ) gas introduced into the chamber 46 from the gas introduction port 62a is reduced to a predetermined flow rate (for example, 2000 sccm) and nitrogen (N ₂ ) gas. The flow rate of argon (Ar) gas introduced into the chamber 46 from the gas introduction port 62a is increased by a flow rate corresponding to a reduction amount (for example, 1000 sccm).

Next, in step S39a of FIG. 16, the flow rate of the nitrogen (N ₂ ) gas introduced into the chamber 46 from the gas inlet 62a is reduced to a predetermined flow rate (for example, 1000 sccm) and the nitrogen (N ₂ ) gas. The flow rate of argon (Ar) gas introduced into the chamber 46 from the gas introduction port 62a is increased by a flow rate corresponding to a reduction amount (for example, 1000 sccm).

In steps S37a to S39a, by supplying (applying) high-frequency power between the lower electrode 61 and the upper electrode 62, silane (SiH ₄ ) gas, ammonia (NH) in the chamber 46 (between the lower electrode 61 and the upper electrode 62). ₃ ) Gas, nitrogen (N ₂ ) gas, and argon (Ar) gas are turned into plasma, and a silicon nitride film (plasma silicon nitride film) is deposited on the semiconductor substrate 1 disposed on the lower electrode 61. Therefore, steps S37a to S39a are steps for depositing silicon nitride. However, since steps S37a and S38a are short time (for example, about 1 second each) and step S39a is long time (for example, 230 seconds), the silicon nitride film is mainly deposited in step S39a.

Further, in steps S37a to S39a of FIG. 16 and steps S37b to S39b of FIG. 17 to be described later, which are silicon nitride film deposition (film formation) steps, ammonia (NH ₃ ) gas introduced into the chamber 46 from the gas inlet 62a. silane (SiH ₄₎ flow rate ratio of the gas is the "ammonia (NH ₃₎ flow rate of gas" / "silane (SiH ₄₎ flow rate of gas" is preferably 2/1 or more 500/1 or less. Further, in steps S37a to S39a of FIG. 16 and steps S37b to S39b of FIG. 17 described later, the flow rate of the silane (SiH ₄ ) gas is preferably 10 to 150 sccm. Thereby, the silicon nitride film can be deposited accurately.

Further, in steps S37a to S39a of FIG. 16, which is a silicon nitride film deposition (film formation) step, silane (SiH ₄ ) gas, which is a silicon source gas of silicon nitride, and silicon nitride enter the chamber 46 from the gas inlet 62a. The reason for introducing nitrogen (N ₂ ) gas as well as ammonia (NH ₃ ) gas, which is the nitrogen source gas, is to stabilize the pressure and plasma.

  In addition, in steps S37a to S39a of FIG. 16, which is a silicon nitride film deposition (film formation) step, argon (Ar) gas, which is not a silicon nitride source gas, is also introduced into the chamber 46 from the gas inlet 62a. This is because the deposited silicon nitride film is formed into a denser film by bombardment (impact) of argon (Ar) ions. Argon (Ar) gas is introduced to reduce the number of dangling bonds in the silicon nitride film, thereby forming a denser film, thereby further increasing the compressive stress generated in the semiconductor substrate 1 by the silicon nitride film (insulating film 21). can do.

Further, in steps S37a to S39a of FIG. 16 which is a silicon nitride film deposition (film formation) step, hydrogen (H ₂ ) gas can be further introduced into the chamber 46 from the gas inlet 62a. By introducing hydrogen (H ₂ ) gas, decomposition of ammonia (NH ₃ ) gas, silane (SiH ₄ ) gas, and nitrogen (N ₂ ) can be promoted, whereby the deposited silicon nitride film is bonded to the unbonded hand. Less denser film can be obtained. By making the silicon nitride film a denser film with less dangling bonds, the compressive stress generated in the semiconductor substrate 1 by the silicon nitride film (insulating film 21) can be further increased.

  Further, in steps S37a to S39a of FIG. 16 which is a silicon nitride film deposition (film formation) step, not only the high frequency power (high frequency voltage) of, for example, 13.56 MHz is provided between the lower electrode 61 and the upper electrode 62, but also from that. The reason why high frequency power (high frequency voltage) of 350 kHz, for example, is also supplied (applied) is to accelerate the decomposition of the gas and make the deposited silicon nitride film a denser film with fewer unbonded hands. . By making the silicon nitride film a denser film with less dangling bonds, the compressive stress generated in the semiconductor substrate 1 by the silicon nitride film (insulating film 21) can be further increased.

Step S39a is continued for a predetermined time (for example, 230 seconds), and after a silicon nitride film having a desired film thickness is formed on the semiconductor substrate 1, between step S40a in FIG. 16 and between the lower electrode 61 and the upper electrode 62. The supply (application) of the above-described 350 kHz and 13.56 MHz high-frequency power (high-frequency voltage) is stopped, and introduction of silane (SiH ₄ ) gas and ammonia (NH ₃ ) gas from the gas inlet 62 a into the chamber 46 is stopped. Stop. In step S40a, only nitrogen (N ₂ ) gas and argon (Ar) gas are introduced into the chamber 46 from the gas inlet 62a, and the inside of the chamber 46 is purged with nitrogen (N ₂ ) gas and argon (Ar) gas. .

  Next, in step S41a of FIG. 16, the introduction of gas from the gas inlet 62a into the chamber 46 is stopped, and the inside of the chamber 46 is exhausted (vacuum exhausted) from the gas outlet 65. Step S41a is a step of exhausting (evacuating) the inside of the chamber 46.

  Thereafter, in step S4, the semiconductor substrate 1 (semiconductor wafer SW) is taken out of the chamber 46 and sent to the next process (film formation process of the insulating film 22).

A silicon nitride film formed by plasma CVD on the main surface of the semiconductor substrate 1 becomes a film that causes tensile stress in the semiconductor substrate 1 when there are a large number of dangling bonds in the film, thereby reducing dangling bonds in the film. As a result, the semiconductor substrate 1 becomes a film that generates compressive stress. A silicon nitride film is deposited in steps S37a to S39a. Two types of high-frequency power (high-frequency voltage) supplied (applied) during film formation, argon (Ar), hydrogen (H ₂ ), etc., which are additive introduction gases, etc. Thus, a denser silicon nitride film with fewer dangling bonds is deposited in steps S37a to S39a. For this reason, the insulating film 21 made of the silicon nitride film deposited to a desired thickness in steps S37a to S39a (this corresponds to an insulating film 21b described later) becomes a dense film with few dangling bonds. It becomes a film that generates compressive stress on the substrate 1. By using the insulating film 21 as a film that generates compressive stress in the semiconductor substrate 1, the p-channel type MISFET Qp has improved mobility and increased drive current, so that switching characteristics can be improved.

  Next, refer to FIG. 17 for the case where the insulating film 21 formed in step S3 is a film that generates compressive stress on the semiconductor substrate 1 and the reducing gas plasma treatment in step S2 is performed with hydrogen plasma. To explain.

  FIG. 17 is an explanatory view (table) showing process steps of the fourth film forming method in the film forming process of the insulating film 21 (silicon nitride film), and after the semiconductor substrate 1 is placed in the chamber 46 in step S1. The state of the chamber 46 until the semiconductor substrate 1 is taken out from the chamber 46 in step S4 is shown. In the fourth film forming method of FIG. 17, the plasma treatment of the reducing gas in step S2 is performed with hydrogen plasma, and the insulating film 21 formed in step S3 is a film that generates compressive stress on the semiconductor substrate 1. This corresponds to a preferable example (embodiment, specific example).

  In step S <b> 1, the semiconductor substrate 1 (semiconductor wafer SW) is placed on the lower electrode 61 in the chamber 46 and heated by a heater built in the lower electrode 61. The semiconductor substrate 1 (semiconductor wafer SW) may be disposed on the already heated lower electrode 61. During steps S31b to S41b in FIG. 17, the heating temperature of the semiconductor substrate 1 (the temperature of the lower electrode 61 on which the semiconductor substrate 1 is disposed) is preferably maintained at 250 to 500 ° C., for example, about 480 ° C.

  Next, in step S31b in FIG. 17, the same operation (process) as in step S11b in FIG. 15 is performed. Then, in step S32b in FIG. 17, the same operation (process) as in step S12b in FIG. 15 is performed. In step S33b in FIG. 17, the same operation (process) as in step S13b in FIG. 15 is performed. That is, steps S31b, 32b, and 33b in FIG. 17 are the same operations and processes as steps S11b, 12b, and 13b in FIG.

Next, in step S34b of FIG. 17, silane (SiH ₄ ) gas, ammonia (NH ₃ ) gas, and nitrogen (N ₂ ) gas are supplied from the gas inlet 62a into the chamber 46 at predetermined flow rates (for example, 60 sccm, 130 sccm, and 4000 sccm) and the pressure in the chamber 46 is controlled to a predetermined pressure (for example, 267 Pa). This pressure is maintained in steps S34b to S40b. Further, introduction of silane (SiH ₄ ) gas and ammonia (NH ₃ ) gas into the chamber 46 is maintained in steps S34b to S39b. Further, the introduction of nitrogen (N ₂ ) gas into the chamber 46 reduces the flow rate in order in steps S34b, S35b, S36b, step S37b, step S38b, and steps S39b, 40b.

When the flow rate of ammonia (NH ₃ ) gas is sufficiently larger than the flow rate of silane (SiH ₄ ) gas in step S34b, a step (chamber similar to step S14b described above) is provided between step S33b and step S34b. It is more preferable to provide a step in which ammonia gas and nitrogen gas are introduced into 46 but silane gas is not introduced, whereby the stability of the gas in the chamber 46 can be improved.

This step S34b is a step for forming a thin nitride film (corresponding to a nitride film 73b described later) on the metal silicide layer 13 of the semiconductor substrate 1 as in step S15b of FIG. In step S34b, the state of introducing silane (SiH ₄ ) gas, ammonia (NH ₃ ) gas, and nitrogen (N ₂ ) gas from the gas inlet 62a into the chamber 46 is preferably continued for about 3 to 30 seconds. By setting step S34b to 3 to 30 seconds, a nitride film 73b described later can be formed, and an increase in manufacturing time can be prevented.

Further, when the flow rate ratio of silane (SiH ₄ ) gas and ammonia (NH ₃ ) gas introduced into the chamber 46 is different between step S34b and later-described steps S35b, S36b, S37b, S38b, and S39b, the above steps are performed. A step similar to S16b (a step of exhausting the chamber 46 without introducing gas into the chamber 46) may be provided between step S34b and step S35b described later. Thereby, the gas in the chamber 46 after step S35b mentioned later can be made more stable.

  Thereafter, in steps S35b, S36b, 37b, 38b, 39b, 40b, and 41b in FIG. 17, the same operations (processes) as in steps S35a, S36a, 37b, 38b, 39b, 40b, and 41b in FIG. That is, steps S35b, S36b, 37b, 38b, 39b, 40b, and 41b in FIG. 17 are the same operations and processes as steps S35a, S36a, 37b, 38b, 39b, 40b, and 41b in FIG. The description is omitted here.

  After performing Steps S35b, S36b, 37b, 38b, 39b, 40b, and 41b in FIG. 17, the semiconductor substrate 1 (semiconductor wafer SW) is taken out from the chamber 46 in Step S4, and the next step (insulating film 22) is performed. Sent to the film forming step).

A silicon nitride film formed by plasma CVD on the main surface of the semiconductor substrate 1 becomes a film that causes tensile stress in the semiconductor substrate 1 when there are a large number of dangling bonds in the film, thereby reducing dangling bonds in the film. As a result, the semiconductor substrate 1 becomes a film that generates compressive stress. A silicon nitride film is deposited in steps S37b to S39b. Two types of high-frequency power (high-frequency voltage) supplied (applied) during film formation, argon (Ar), hydrogen (H ₂ ), etc., which are additive introduction gases, etc. Thus, in steps S37b to S39b, a denser silicon nitride film with fewer dangling bonds is deposited. For this reason, the insulating film 21 made of the silicon nitride film deposited to a desired thickness in steps S37b to S39b (which corresponds to an insulating film 21b described later) becomes a dense film with few dangling bonds. It becomes a film that generates compressive stress on the substrate 1. By using the insulating film 21 as a film that generates compressive stress in the semiconductor substrate 1, the p-channel type MISFET Qp has improved mobility and increased drive current, so that switching characteristics can be improved.

  Next, the effect of this embodiment will be described in more detail.

18 is a fragmentary cross-sectional view (partially enlarged cross-sectional view) showing a state before the insulating film 21 is formed as shown in FIG. 7 after the metal silicide layer 13 is formed by the salicide process as shown in FIG. In this state, the metal silicide layer 13 is formed on the semiconductor region (silicon region) 71 made of silicon (Si). The semiconductor region 71 corresponds to the gate electrode 6a, the gate electrode 6b, the n ⁺ type semiconductor region 7b, or the p ⁺ type semiconductor region 8b. Therefore, when the semiconductor region 71 is the gate electrode 6a or the gate electrode 6b, the semiconductor region 71 is a polycrystalline silicon film constituting the gate electrode, and the semiconductor region 71 is the n ⁺ type semiconductor region 7b or the p ⁺ type semiconductor. The region 8b is a single crystal silicon region (single crystal silicon substrate region) constituting the source / drain region.

  According to the study of the present inventor, as shown in FIG. 18 after the metal silicide layer 13 is formed as described with reference to FIGS. 5 and 6 until the insulating film 21 is formed. Further, it was found that the surface of the metal silicide layer 13 was oxidized, and an oxide film 72, which is a natural oxide film, was formed on the surface of the metal silicide layer 13. The oxide film 72 is mainly formed of silicon oxide. In order to completely prevent the formation of the oxide film 72, it is necessary to strictly control from the formation of the metal silicide layer 13 to the formation of the insulating film 21, which complicates the manufacturing equipment of the semiconductor device, etc. Increase the manufacturing cost of the semiconductor device. For this reason, it is desirable to allow the oxide film 72 to be formed on the surface of the metal silicide layer 13 between the formation of the metal silicide layer 13 and the formation of the insulating film 21.

  FIG. 19 is a fragmentary cross-sectional view of the semiconductor device of the comparative example during the manufacturing process, and the region corresponding to FIG. 18 is shown. FIG. 19 illustrates the present embodiment after the state of FIG. Unlike the embodiment, the state in which the insulating film 21 is deposited by the plasma CVD method without performing the plasma treatment of the reducing gas in step S2 is shown. That is, the comparative example in FIG. 19 corresponds to the case where steps S3 and S4 are performed after step S1 in FIG.

  After the metal silicide layer 13 is formed, unlike the present embodiment, when the insulating film 21 is deposited by the plasma CVD method without performing the reducing gas plasma processing in the above step S2, FIG. 19 shows. As described above, the oxide film 72 is formed (remaining) at the interface between the metal silicide layer 13 and the insulating film 21.

When the oxide film 72 is formed (remains) at the interface between the metal silicide layer 13 and the insulating film 21 as shown in FIG. 19, various heating processes (for example, various insulating films and conductor films) after the formation of the insulating film 21 are performed. In the process involving heating of the semiconductor substrate 1 as in the film formation process of FIG. 5, the metal silicide layer 13 may partially grow abnormally due to oxygen in the oxide film 72 on the surface of the metal silicide layer 13. It was found by the study of the present inventors. This is because, when the oxide film 72 exists at the interface between the metal silicide layer 13 and the insulating film 21, oxygen (O) in the oxide film 72 diffuses and defects due to oxygen increase. This is considered to be because the metal element (for example, Ni) of the metal silicide layer 13 is likely to diffuse through the defect and promote the abnormal growth of the metal silicide layer 13. This abnormal growth is particularly noticeable when the metal silicide layer 13 is in the MSi (eg, NiSi) phase, and the metal element (eg, Ni) in the MSi phase metal silicide layer 13 is diffused to cause MSi ₂ (eg, NiSi ₂ ). The part of grows abnormally.

  Such abnormal growth of the metal silicide layer 13 causes an increase in resistance of the metal silicide layer 13, and if the metal silicide layer 13 formed on the source / drain regions is abnormally grown in the channel portion, the electric field effect There is a possibility of increasing the leakage current between the source and drain of the transistor. This degrades the performance of the semiconductor device.

  Although it is conceivable that the oxide film 72 is removed by wet etching after the metal silicide layer 13 is formed and before the insulating film 21 is formed, in this case, the oxide film 72 may be re-formed after the wet etching. is there. In order to completely prevent the oxide film 72 from being re-formed after the oxide film 72 is removed by wet etching, it is necessary to strictly control the process after the wet etching until the insulating film 21 is formed. And the manufacturing cost of the semiconductor device is increased.

  20 to 23 are cross-sectional views of the main part during the manufacturing process of the semiconductor device according to the present embodiment, and the region corresponding to FIG. 19 is shown. FIGS. After the state 18, the state in which the insulating film 21 is formed according to the manufacturing process of the present embodiment (process step corresponding to FIG. 7) is shown. That is, FIGS. 20 to 23 correspond to the case where Step S2 and Step S3 are performed after Step S1 of FIG. However, FIG. 20 corresponds to the case where the insulating film 21 is formed by the first film forming method of FIG. 14, that is, the case where steps S1 to S4 are performed as shown in FIG. 14 (steps S11a to S21a). To do. FIG. 21 corresponds to the case where the insulating film 21 is formed by the second film forming method of FIG. 15, that is, the steps S1 to S4 are performed as shown in FIG. 15 (steps S11b to S21b). To do. FIG. 22 corresponds to the case where the insulating film 21 is formed by the third film forming method of FIG. 16, that is, the case where steps S1 to S4 are performed as shown in FIG. 16 (steps S31a to S41a). To do. FIG. 23 corresponds to the case where the insulating film 21 is formed by the fourth film forming method of FIG. 17, that is, the case where steps S1 to S4 are performed as shown in FIG. 17 (steps S31b to S41b). To do. Note that the case where the insulating film 21 is a film that generates a tensile stress in the semiconductor substrate 1 is shown as an insulating film 21 a in FIGS. 20 and 21, and the case where the insulating film 21 is a film that generates a compressive stress in the semiconductor substrate 1. An insulating film 21b is shown in FIGS.

  In this embodiment, after the metal silicide layer 13 is formed, the insulating gas 21 is deposited by the plasma CVD method after performing the plasma treatment of the reducing gas in step S2. Therefore, the insulating film 21 is deposited after the oxide film 72 on the surface of the metal silicide layer 13 is reduced and removed by the plasma treatment of the reducing gas in step S2. Further, the semiconductor substrate 1 is subjected to the period from when the oxide film 72 on the surface of the metal silicide layer 13 is reduced and removed by the plasma treatment of the reducing gas in step S2 until the insulating film 21 is deposited on the metal silicide layer 13. Is not exposed to the oxygen-containing atmosphere, the surface of the metal silicide layer 13 is not re-oxidized. For this reason, the oxide film 72 does not remain at the interface between the metal silicide layer 13 and the insulating film 21 when the insulating film 21 is formed. Instead, as shown in FIGS. 20 to 23, a nitride film 73 (nitride film 73 a or nitride film 73 b) is formed at the interface between the metal silicide layer 13 and the insulating film 21. The reason is as follows.

When the plasma treatment of the reducing gas in step S2 (that is, step S12a or step S32a) is performed with ammonia (NH ₃ ) gas plasma, that is, ammonia plasma, as shown in FIGS. Although the oxide film 72 on the surface of the layer 13 is reduced and removed, a nitride film 73a is formed on the surface of the metal silicide layer 13 due to nitrogen of ammonia. After that, since the insulating film 21 is deposited in step S3 (that is, step S18a or steps S37a to S39a), the metal silicide layer 13 and the insulating film 21 (insulating film 21a or insulating film 21b) are formed as shown in FIGS. A nitride film 73a is formed at the interface between the two.

In the plasma treatment of ammonia (NH ₃ ) gas in step S12a or step S32a, mainly,
SiO ₂ +2 (N ^* + 3H ^* ) → Si + 2H ₂ O + 2N ^* + 2H ^* Formula (1)
3SiO ₂ +4 (N ^* + 3H ^* ) → Si ₃ N ₄ + 6H ₂ O Formula (2)
It is thought that this reaction occurs. The reactions of the above formulas (1) and (2) are exothermic reactions and tend to occur thermodynamically. In step S12a and step S32a (ammonia plasma treatment), the oxide film 72 is reduced by the reaction of formula (1) (reduction reaction) and Si ₃ by the reaction of formula (2) (production reaction of silicon nitride). N ₄ is generated, whereby the oxide film 72 is removed and a nitride film 73a is generated (formed).

On the other hand, unlike this embodiment, when plasma is not generated in step S12a or step S32a,
SiO ₂ + 2NH ₃ → Si + 2H ₂ O + N ₂ + H ₂ formula (3)
3SiO ₂ + 4NH ₃ → Si ₃ N ₄ + 6H ₂ O Formula (4)
This reaction is considered. However, since the reactions of the above formulas (3) and (4) are endothermic reactions and hardly occur thermodynamically, unlike the present embodiment, when plasma is not generated in step S12a or step S32a, The oxide film 72 cannot be reduced, and the oxide film 72 is formed (remaining) at the interface between the metal silicide layer 13 and the insulating film 21 as shown in FIG. End up.

15 and 17, when the plasma treatment of the reducing gas in step S2 (ie, steps S12b and S32b) is performed with hydrogen (H ₂ ) gas plasma, ie, hydrogen plasma, The oxide film 72 on the surface of the silicide layer 13 is reduced and removed. During the hydrogen plasma treatment in steps S12b and S32b, no nitride film is formed on the surface of the metal silicide layer 13. However, after the oxide film 72 is reduced and removed by hydrogen plasma treatment of S12b and S32b to expose the surface of the metal silicide layer 13, silane (SiH ₄ ) gas and ammonia (NH ₃ ) gas are used in steps S15b and S34b. It is introduced into the chamber 46. As a result, the surface of the metal silicide layer 13 is exposed to silane (SiH ₄ ) gas and ammonia (NH ₃ ) gas that have not been converted into plasma, and a nitride film 73 b is formed on the surface of the metal silicide layer 13. Thereafter, since the insulating film 21 is deposited in Step S18a or Steps S37a to S39a, as shown in FIG. 21 and FIG. 23, the interface between the metal silicide layer 13 and the insulating film 21 (the insulating film 21a or the insulating film 21b) The nitride film 73b is formed.

That is, in step S3 (steps S18b, S37b to S39b), a first gas (preferably silane (SiH ₄ ) gas containing silicon (Si) element as a constituent element as a silicon source gas of silicon nitride in the chamber 46. And a second gas containing nitrogen as a constituent element (preferably ammonia (NH ₃ ) gas) as a nitrogen source gas of silicon nitride, and these gases are converted into plasma. Silicon nitride is deposited. In steps S15b and S34b prior to step S3 (steps S18b, S37b to S39b), the first gas and the second gas are introduced into the chamber 46, and the first gas that has not been converted to plasma and The nitride film 73b is formed on the surface of the metal silicide layer 13 by exposing the surface of the metal silicide layer 13 to the second gas. Since the semiconductor substrate 1 is heated in all the steps of FIGS. 14 to 17, the semiconductor substrate 1 is also heated in steps S15b and S34b, which also contributes to the formation of the nitride film 73b.

In the plasma treatment of hydrogen (H ₂ ) gas in step S12b or step S32b, mainly,
SiO ₂ + 4H ^* → Si + 2H ₂ O Formula (5)
It is thought that this reaction occurs. The reaction of the above formula (5) is an exothermic reaction and easily occurs thermodynamically. In step S12b and step S32b, the oxide film 72 is reduced and removed by the reaction (reduction reaction) of the above formula (5), and silicon nitride is not generated.

On the other hand, unlike this embodiment, when plasma is not generated in step S12b or step S32b,
SiO ₂ + 2H ₂ → Si + 2H ₂ O Formula (6)
This reaction is considered. However, since the reaction of the above formula (6) is an endothermic reaction and hardly occurs thermodynamically, unlike the present embodiment, when plasma is not generated in step S12b or step S32b, the oxide film 72 Therefore, the oxide film 72 is formed (remaining) at the interface between the metal silicide layer 13 and the insulating film 21 as shown in FIG.

In step S15b and step S34b, mainly,
3SiH ₄ + 4NH ₃ → 3Si ₃ N ₄ + 12H ₂ formula (7)
It is thought that this reaction occurs. The reaction of the above formula (7) is an exothermic reaction and easily occurs thermodynamically. Furthermore, since the steps S15b and S34b are performed in a state where the oxide film 72 is removed by the plasma treatment of hydrogen (H ₂ ) gas in steps S12b and S32b, the surface of the metal silicide layer 13 is exposed in steps S15b and S34b. ing. For this reason, decomposition of ammonia (NH ₃ ) gas and silane (SiH ₄ ) gas is promoted by the metal catalytic action of the metal silicide layer 13, and the reaction of the above formula (7) easily occurs. For this reason, in step S15b and step S34b, Si ₃ N ₄ is generated by the reaction of formula (7) (a generation reaction of silicon nitride), thereby generating (forming) a nitride film 73b.

When ammonia (NH ₃ ) gas and silane (SiH ₄ ) gas are sufficiently decomposed by the metal catalytic action of the metal silicide layer 13, the gas is introduced in step S 15 b of FIG. 15 and step S 34 b of FIG. 17. The flow rate ratio of ammonia (NH ₃ ) gas and silane (SiH ₄ ) gas introduced into the chamber 46 through the port 62 a is ₄ as “flow rate of ammonia (NH ₃ ) gas” / “flow rate of silane (SiH ₄ ) gas”. / 3 is sufficient. In general, ammonia (NH ₃ ) gas tends to be more difficult to be decomposed than silane (SiH ₄ ) gas at a high temperature. Therefore, decomposition of ammonia (NH ₃ ) gas due to metal catalysis of the metal silicide layer 13 is difficult. If it is not sufficient, the flow rate of ammonia (NH ₃ ) gas may be increased. Therefore, the flow ratio of ammonia (NH ₃ ) gas and silane (SiH ₄ ) gas introduced into the chamber 46 from the gas inlet 62a in step S15b in FIG. 15 and step S34b in FIG. 17 is “ammonia (NH ₃ ) Gas flow rate "/" Silane (SiH ₄ ) gas flow rate "is preferably 4/3 or more and 500/1 or less, which facilitates formation of the nitride film 73b.

Thus, since the formation of the nitride film 73 (nitride film 73a or nitride film 73b) is mainly caused by the reaction as described above, the nitride film 73 (nitride film 73a or nitride film 73b) is mainly made of silicon nitride. the atomic ratio of silicon (Si) and nitrogen (N) is in the composition close to the stoichiometric ratio (i.e. film having a composition close to the Si ₃ N _4).

15 and 17, when the plasma treatment of the reducing gas in step S2 (that is, steps S12b and S32b) is performed with plasma of hydrogen (H ₂ ) gas, that is, hydrogen plasma, the nitride film 73b is not formed. For this purpose, step S15b (or steps S14b and S15b) in FIG. 15 and step 34b in FIG. 17 are omitted. In this case, the oxide film 72 on the surface of the metal silicide layer 13 is reduced and removed by the hydrogen plasma treatment in steps S12b and S32b. Thereafter, the surface of the metal silicide layer 13 is silane (SiH ₄ ) gas and ammonia (NH _3). ) Since the exposure time to the gas is short, the formation of the nitride film 73b on the surface of the metal silicide layer 13 can be prevented. In this state, since the insulating film 21 is deposited in step S18a or steps S37a to S39a, the metal silicide layer 13 and the insulating film 21 (insulating film 21a or insulating film 21b) are interposed as shown in FIGS. Neither the oxide film 72 nor the nitride film 73b is formed at the interface, and the metal silicide layer 13 and the insulating film 21 are in direct contact with each other. 24 is a fragmentary cross-sectional view of the same semiconductor device as that of FIG. 21 during the manufacturing process. Steps S1 to S4 are performed as shown in FIG. 15 (steps S11b to S21b). Unlike this, it corresponds to the case where step S15b (or steps S14b and S15b) in FIG. 15 is omitted. FIG. 25 is a fragmentary cross-sectional view of the same semiconductor device as that of FIG. 23 during the manufacturing process. Steps S1 to S4 are performed as shown in FIG. 17 (steps S31b to S41b). Unlike this, it corresponds to the case where step S34b in FIG. 17 is omitted.

Further, in step S12a in FIG. 15 and step S32a in FIG. 17, hydrogen (H ₂ ) gas can be further introduced into the chamber 46 from the gas inlet 62a, which is the same as the reducing gas plasma in step S2. This corresponds to the case of plasma of a mixed gas of ammonia (NH ₃ ) gas and hydrogen (H ₂ ) gas. In this case, in step S12a or step 32a, the surface of the metal silicide layer 13 is treated (plasma treatment) by plasma of a mixed gas of ammonia (NH ₃ ) gas and hydrogen (H ₂ ) gas, and thereby the metal silicide layer 13 The oxide film 72 on the surface is reduced and removed, and a nitride film 73a is formed on the surface of the metal silicide layer 13 by ammonia plasma. Therefore, the state shown in FIGS. 20 and 22 is obtained after the insulating film 21a and the insulating film 21b are formed.

  20 to 25, no oxide film is formed at the interface between the metal silicide layer 13 and the insulating film 21. For this reason, even if various heating processes after the formation of the insulating film 21 (for example, processes involving heating of the semiconductor substrate 1 as in the process of forming various insulating films and conductor films) are performed, the metal silicide layer 13 is formed. It is possible to prevent the metal silicide layer 13 from partially growing abnormally due to oxygen in the oxide film at the interface between the insulating film 21 and the insulating film 21. For this reason, an increase in resistance of the metal silicide layer 13 due to abnormal growth can be prevented. Further, it is possible to prevent the metal silicide layer 13 formed on the source / drain regions from abnormally growing in the channel portion and increasing the leakage current between the source and drain of the field effect transistor. Therefore, the performance of the semiconductor device can be improved. In addition, the reliability of the semiconductor device can be improved.

  In addition, since no oxide film is formed at the interface between the metal silicide layer 13 and the insulating film 21, the tensile stress or compressive stress that the insulating film 21 should act on the semiconductor substrate 1 (the insulating film 21 is the insulating film 21a). In this case, the tensile stress, and the compressive stress in the case where the insulating film 21 is the insulating film 21b) are not disturbed by the oxide film and are sufficiently transmitted to the semiconductor substrate 1. Therefore, the characteristics of the n-channel MISFET Qn (in the case of tensile stress) or the p-channel MISFET Qp (in the case of compressive stress) can be improved accurately.

FIG. 26 is a graph (an explanatory diagram) showing a spectrum obtained by measuring a silicon nitride film formed on the semiconductor wafer SW by an XPS (X-ray Photoelectron spectroscopy) method. The horizontal axis of the graph of FIG. 26 corresponds to binding energy. The vertical axis of the graph of FIG. 26 corresponds to the intensity of the spectrum (arbitrary unit: arbitrary unit) and is normalized (normalized) with the peak intensity in the vicinity of 397.1 to 397.2 eV being 1. In the graph of FIG. 26, the first spectrum, which is the spectrum of a silicon nitride film (corresponding to the insulating film 21) formed by the plasma CVD method, is indicated by a dotted line, and the second spectrum and the third spectrum described later are solid lines. However, since the second spectrum and the third spectrum are almost the same spectrum, they are overlapped and shown by the same solid line in the graph of FIG. The second spectrum shows a silicon nitride film (corresponding to the nitride film 73a) formed by treating the surface of a nickel-containing metal silicide layer (corresponding to the metal silicide layer 13) with ammonia plasma. It is a spectrum. The third spectrum shows that after the surface of a metal silicide layer containing nickel (corresponding to the metal silicide layer 13) is treated with hydrogen plasma, silane (SiH ₄ ) gas and ammonia (NH ₃ ) that have not been converted to plasma. It is a spectrum of a silicon nitride film (corresponding to the nitride film 73b) formed by exposure to gas.

In the graph of FIG. 26, the peak shown in the vicinity of 397.1 to 397.2 eV is a spectrum corresponding to silicon nitride. In the graph of FIG. 26, the peak positions of the second spectrum and the third spectrum indicated by the solid line are shifted to the higher energy side than the first spectrum indicated by the dotted line. This is because the silicon nitride film (corresponding to the nitride film 73a) in which the second spectrum was measured and the third spectrum were measured rather than the silicon nitride film (corresponding to the insulating film 21) in which the first spectrum was measured. This suggests that the formed silicon nitride film (corresponding to the nitride film 73b) has a composition close to the stoichiometric ratio (that is, Si ₃ N ₄ ). Therefore, the nitride films 73a and 73b and the insulating film 21 are both made of silicon nitride, but the nitride films 73a and 73b have a composition closer to the stoichiometric ratio (Si ₃ N ₄ ) than the insulating film 21. I understand.

  As in this embodiment, the natural oxide film on the surface of the metal silicide layer 13 is removed, and the insulating film which is a plasma silicon nitride film directly or in a state where the nitride film 73 (nitride film 73a or nitride film 73b) is formed. If 21 is deposited, the natural oxide film (72) does not intervene at the interface, so that the adhesion between the insulating film 21 and the metal silicide layer 13 can be improved. The reason is that if a natural oxide film is interposed between the metal silicide layer 13 and the insulating film 21, the stress of the insulating film 21 is applied to the natural oxide film, so that the interface between the natural oxide film and the insulating film 21 is applied. This is because there is a possibility of starting peeling.

The nitride film 73 a is made of silicon nitride having a composition close to the stoichiometric ratio (Si ₃ N ₄ ) formed by the plasma reaction, and becomes a film that generates a tensile stress in the semiconductor substrate 1. The nitride film 73b is made of silicon nitride having a composition close to the stoichiometric ratio (Si ₃ N ₄ ) formed by the thermal reaction by the catalytic action on the surface of the metal silicide, and is a film that generates tensile stress on the semiconductor substrate 1. Become. Therefore, as shown in FIGS. 20 and 21, tensile stress is generated in the semiconductor substrate 1 as the insulating film 21 in a state where the nitride film 73 (nitride film 73 a or nitride film 73 b) is formed on the surface of the metal silicide layer 13. If the insulating film 21a to be formed is formed, the tensile stress of the nitride film 73 (nitride film 73a or nitride film 73b) acts on the semiconductor substrate 1 in addition to the tensile stress of the insulating film 21a. Thereby, the tensile stress generated in the semiconductor substrate 1 can be further increased, and the n-channel type MISFET Qn can further improve the switching characteristics since the mobility is further improved and the drive current is further increased.

  Further, when the insulating film 21b that generates a compressive stress on the semiconductor substrate 1 is formed as the insulating film 21, in order to further improve the compressive stress generated on the semiconductor substrate 1, a metal silicide is used as shown in FIGS. It is also effective to deposit the insulating film 21b without forming the nitride film 73 (nitride film 73b) after removing the oxide film 72 on the surface of the layer 13 by hydrogen plasma treatment. In this way, the insulating film 21b generates a compressive stress in the semiconductor substrate 1 and no tensile stress is generated by the nitride film 73, so that the compressive stress generated in the semiconductor substrate 1 can be further increased. As a result, the p-channel type MISFET Qp further improves the mobility and further increases the drive current, so that the switching characteristics can be further improved.

Further, since the metal silicide layer 13 preferably has a low resistivity, the metal silicide layer 13 has an M ₂ Si (dimetal silicide) phase, an MSi (metal monosilicide) phase, and an MSi ₂ (metal disilicide) phase. Of these, it is necessary to make the phase with the lowest resistivity, but depending on the type of metal element constituting the metal silicide layer 13, the MSi phase has the lowest resistivity and the MSi ₂ phase has the lowest resistivity. There is. On the other hand, as described above, when the oxide film 72 is formed (remaining) at the interface between the metal silicide layer 13 and the insulating film 21 as shown in FIG. 19, various heating processes after the formation of the insulating film 21 are performed. The metal silicide layer 13 partially grows abnormally due to oxygen in the oxide film 72. This abnormal growth becomes particularly noticeable when the metal silicide layer 13 is in the MSi phase. This is because the MSi ₂ phase is a phase that is less likely to react with Si (silicon), whereas the M ₂ Si phase and the MSi phase are phases that are more likely to react with Si (silicon). When the metal silicide layer 13 is in the MSi phase, oxygen (O) in the oxide film 72 is diffused and defects due to oxygen increase, and the metal elements in the MSi phase metal silicide layer 13 are diffused through the generated defects. ,
MSi + Si → MSi ₂
This occurs, and the MSi ₂ portion grows abnormally.

Therefore, when the MSi phase has a lower resistivity than the M ₂ Si phase and the MSi ₂ phase, in order to apply the MSi phase in which the portion of MSi ₂ tends to abnormally grow to the metal silicide layer 13, the metal silicide It is extremely important to prevent abnormal growth of the metal silicide layer 13 due to the oxide film 72 at the interface between the layer 13 and the insulating film 21.

In this embodiment, since the oxide film 72 is reduced and removed in step S2, and the insulating film 21 is formed in step S3, no oxide film is formed at the interface between the metal silicide layer 13 and the insulating film 21. In various heating steps after the formation of the insulating film 21, it is possible to prevent the metal silicide layer 13 from partially growing abnormally. For this reason, even if the MSi phase in which the MSi ₂ portion is likely to grow abnormally is applied to the metal silicide layer 13, it is possible to prevent the MSi ₂ portion from growing abnormally. Therefore, in the present embodiment, as a first condition, the MSi (metal monosilicide) phase has a lower resistivity than the MSi ₂ (metal disilicide) phase and the M ₂ Si (dimetal silicide) phase. If the present invention is applied to the case where the metal silicide layer 13 is formed by a certain metal silicide, the effect is great. Further, in this case, the metal silicide layer 13 remains in the MSi phase until the end of manufacturing the semiconductor device (for example, a stage in which the semiconductor substrate 1 is diced to form a semiconductor chip). This is because, in the manufactured semiconductor device, the metal silicide layer 13 is an MSi phase having a lower resistivity than the MSi ₂ phase and the M ₂ Si phase, so that the metal silicide layer 13 has a low resistance, contact resistance, This is because the diffusion resistance of the source / drain can be reduced and the performance of the semiconductor device in which the MISFET is formed can be improved.

Further, in the present embodiment, even if the MSi phase metal silicide layer 13 is formed, abnormal growth of MSi ₂ can be prevented. Therefore, as a _second condition, a silicide in which an MSi ₂ (metal disilicide) phase can exist is present. Therefore, if applied to the formation of the metal silicide layer 13, the effect is great.

In the present embodiment, the metal element M of the metal silicide layer 13 is diffused due to the oxide film 72 at the interface between the metal silicide layer 13 and the insulating film 21 in various heating processes after the formation of the insulating film 21. Then, since the portion of MSi ₂ can be prevented from growing abnormally, if the present embodiment is applied when the metal element M becomes a diffusion species instead of Si (silicon) as the third condition, the effect can be obtained. large.

Considering these first to third conditions, if this embodiment is applied when the metal film 11 is a Ni (nickel) film or a Ni (nickel) alloy film, the effect is great. That is, if the present embodiment is applied when the metal silicide layer 13 is a nickel silicide layer (nickel silicide layer) or a nickel alloy silicide layer (nickel alloy silicide layer), the effect is great. Examples of Ni (nickel) alloy films that can be used for the metal film 11 include Ni—Pt (nickel-platinum) alloy films, Ni—V (nickel-vanadium) alloy films, Ni—Pd (nickel-palladium) alloy films, There is a Ni—Yb (nickel-ytterbium) alloy film or a Ni—Er (nickel-erbium) alloy film. If the metal film 11 is a Ni film, a Ni—Pt alloy film, a Ni—V alloy film, a Ni—Pd alloy film, a Ni—Yb alloy film, or a Ni—Er alloy film, a metal element instead of Si (silicon) M becomes a diffusing species, an MSi ₂ phase exists, and the MSi phase has a lower resistivity than the MSi ₂ phase and the M ₂ Si phase. However, the problem of abnormal growth of MSi ₂ from the metal silicide layer 13 to the channel portion and the problem of increased resistance variation due to formation of the MSi ₂ portion in the metal silicide layer are that the metal film 11 is a Ni film, a Ni-Pt alloy film. This occurs in any case of Ni-V alloy film, Ni-Pd alloy film, Ni-Yb alloy film or Ni-Er alloy film, but it appears most prominent particularly when the metal film 11 is a Ni (nickel) film. . For this reason, if this embodiment is applied when the metal film 11 is a Ni (nickel) film, the effect is the greatest.

In the present embodiment, the case where the metal silicide layer 13 is formed on the source or drain semiconductor regions (7b, 8b) and the gate electrodes (6a, 6b) has been described. Without forming the metal silicide layer 13 on the gate electrodes 6a and 6b, the metal silicide layer 13 is formed on the source or drain semiconductor region (here, the n ⁺ type semiconductor region 7b and the p ⁺ type semiconductor region 8b). You can also

In the present embodiment, as the best mode, the metal silicide layer 13 is formed on the source or drain semiconductor region (here, the n ⁺ type semiconductor region 7 b and the p ⁺ type semiconductor region 8 b) formed in the semiconductor substrate 1. Although the case where it is formed has been described, as another embodiment, the metal silicide layer 13 can be formed on the semiconductor region other than the source or drain formed on the semiconductor substrate 1. Even in that case, by using the method of forming the insulating film 21 as in the present embodiment, abnormal growth of the metal silicide layer 13 can be prevented, and variation in resistance of the metal silicide layer 13 can be reduced. However, as in the present embodiment, the metal silicide layer 13 may be formed on the source or drain semiconductor region (n ⁺ type semiconductor region 7b, p ⁺ type semiconductor region 8b) formed on the semiconductor substrate 1. For example, in addition to the effect of reducing the variation in resistance of the metal silicide layer 13, the effect of preventing the metal silicide layer 13 from abnormally growing in the channel portion and increasing the leakage current between the source and drain of the field effect transistor can be prevented. Since it is obtained, the effect is extremely large.

(Embodiment 2)
27 to 32 are main-portion cross-sectional views during the manufacturing process of the semiconductor device according to another embodiment of the present invention.

  In the first embodiment, the common insulating film 21 is formed in the region where the n-channel type MISFET Qn is formed and the region where the p-channel type MISFET Qp is formed. The common insulating film 21 is either the insulating film 21 a that generates a tensile stress in the semiconductor substrate 1 or the insulating film 21 b that generates a compressive stress in the semiconductor substrate 1.

  On the other hand, in the present embodiment, in the region where the n-channel type MISFET Qn is formed, the insulating film 21a that generates tensile stress is formed in the semiconductor substrate 1, and in the region where the p-channel type MISFET Qp is formed, the semiconductor substrate An insulating film 21b that generates compressive stress in 1 is formed.

  The manufacturing process of the semiconductor device of the present embodiment is the same as that of the first embodiment up to the process of FIG. 7 (process for forming the insulating film 21). However, in the present embodiment, the insulating film 21 is made to be a film that causes tensile stress in the semiconductor substrate 1, that is, the insulating film 21a. That is, by forming the insulating film 21 by the first film forming method of FIG. 14 or the second film forming method of FIG. 15, the structure corresponding to the structure in which the insulating film 21 is the insulating film 21a in FIG. The following structure is obtained.

  After the structure of FIG. 27 corresponding to FIG. 7 is obtained, a photoresist film (not shown) that covers the region where the n-channel MISFET Qn is formed and exposes the region where the p-channel MISFET Qp is formed is formed. The insulating film 21a is formed on the insulating film 21a, and the insulating film 21a is dry-etched using the photoresist film as an etching mask. Thus, the insulating film 21a in the region where the p-channel type MISFET Qp is formed is removed, and the insulating film 21a in the region where the n-channel type MISFET Qn is formed is left. Thereafter, the photoresist film is removed. In this way, the structure of FIG. 28 is obtained. At this stage, the surface of the metal silicide layer 13 in the region where the p-channel type MISFET Qp is formed is exposed.

  Next, as shown in FIG. 29, the insulating film 21a and the gate electrode 6b are covered over the entire main surface of the semiconductor substrate 1 including the metal silicide layer 13 in the region where the p-channel type MISFET Qp is formed. An insulating film 21b is formed.

  The step of forming the insulating film 21b is performed in the same manner as the step of forming the insulating film 21 in the first embodiment, but the insulating film 21b is a film that generates compressive stress on the semiconductor substrate 1. Therefore, the insulating film 21b is formed by the third film formation method in FIG. 16 or the fourth film formation method in FIG. Therefore, when forming the insulating film 21b in the present embodiment, as described in the first embodiment, the surface of the metal silicide layer 13 is reduced to a reducing gas (preferably in step S2 (step S32a or step S32b)). Is treated with plasma of ammonia gas, hydrogen gas, or a mixed gas thereof, and then the insulating film 21b is deposited by plasma CVD in step S3 (steps S37a to S39a or steps S37b to S39b).

  Next, a photoresist film (not shown) is formed on the insulating film 21b so as to cover the region where the p-channel type MISFET Qp is formed and to expose the region where the n-channel type MISFET Qn is formed. The insulating film 21b is dry-etched using the etching mask. Thereby, the insulating film 21b in the region where the n-channel type MISFET Qn is formed is removed, and the insulating film 21b in the region where the p-channel type MISFET Qp is formed is left. In this dry etching process, the insulating film 21a in the region where the n-channel type MISFET Qn is formed is left without being removed. Thereafter, the photoresist film is removed. In this way, the structure of FIG. 30 is obtained.

  Subsequent steps are substantially the same as those in the first embodiment. That is, as in the first embodiment, the insulating film 22 is formed on the insulating films 21a and 21b as shown in FIG. Then, as in the first embodiment, as shown in FIG. 32, a contact hole 23 is formed in the insulating films 21a, 21b, and 22, and a plug 24 is formed in the contact hole 23. Thereafter, the stopper insulating film 31, the insulating film 32, the wiring groove 33, and the wiring 35 are formed in the same manner as in the first embodiment, but the illustration thereof is omitted here.

  As described in the first embodiment, the insulating film 21 a is a silicon nitride film formed by a plasma CVD method, and is a film that applies compressive stress to the semiconductor substrate 1. In addition, the insulating film 21 b is a silicon nitride film formed by a plasma CVD method, and applies compressive stress to the semiconductor substrate 1.

In the semiconductor device of the present embodiment formed as described above, in the region where the n-channel type MISFET Qn is formed, the insulating film 21a, which is a film that generates tensile stress on the semiconductor substrate 1, is formed on the semiconductor substrate 1. The channel type MISFET Qn (that is, the gate electrode 6a and the n ⁺ type semiconductor region 7b) is formed to be covered. In the region where the p-channel type MISFET Qp is formed, the insulating film 21b, which is a film that generates compressive stress on the semiconductor substrate 1, is formed on the semiconductor substrate 1 with the p-channel type MISFET Qp (that is, the gate electrode 6b and the p ⁺ -type semiconductor region 8b). ).

  For this reason, in the region where the n-channel type MISFET Qn is formed, the insulating film 21a, which is a film that generates a tensile stress, is formed on the semiconductor substrate 1, so that the n-channel type MISFET Qn moves due to the tensile stress caused by the insulating film 21a. Thus, the driving current is increased and the switching characteristics can be improved. On the other hand, in the region where the p-channel type MISFET Qp is formed, the insulating film 21b, which is a film that generates compressive stress, is formed on the semiconductor substrate 1, so that the p-channel type MISFET Qp has a mobility due to the compressive stress caused by the insulating film 21b. As a result, the drive current increases and the switching characteristics can be improved. As a result, in a semiconductor device including the n-channel MISFET Qn and the p-channel MISFET Qp, that is, a semiconductor device including the CMISFET, the mobility is improved and the drive current is increased in both the n-channel MISFET Qn and the p-channel MISFET Qp. And the overall characteristics can be further improved.

  Also in the present embodiment, the insulating films 21a and 21b are formed in the same manner as in the first embodiment. For this reason, the surface of the metal silicide layer 13 is treated with plasma of a reducing gas (preferably ammonia gas, hydrogen gas, or a mixed gas thereof) and then exposed to the atmosphere (in an oxygen-containing atmosphere) without being exposed to the metal. An insulating film 21a (silicon nitride film) is formed on the semiconductor substrate 1 including the silicide layer 13 by a plasma CVD method. Also, an oxide film (corresponding to the oxide film 72) is generated on the surface of the metal silicide layer 13 exposed in the region where the p-channel type MISFET Qp is formed in the step of FIG. Is reduced by plasma treatment of the reducing gas in step S2 (step S32a or step S32b), and then the insulating film 21b (silicon nitride film) is subjected to plasma CVD without being exposed to the atmosphere (in an oxygen-containing atmosphere). It is deposited by the method. For this reason, in the region where the n-channel type MISFET Qn is formed, the state of FIG. 20, FIG. 21 or FIG. 24 is obtained, and in the region where the p-channel type MISFET Qp is formed, the state of FIG. Become. Thereby, the same effect as the first embodiment can be obtained.

  That is, also in this embodiment, no oxide film is formed at the interface between the metal silicide layer 13 and the insulating films 21a and 21b. For this reason, even if various heating processes after the formation of the insulating films 21a and 21b (for example, processes involving heating of the semiconductor substrate 1 as in the process of forming various insulating films and conductor films) are performed, the metal silicide It is possible to prevent the metal silicide layer 13 from partially growing abnormally due to oxygen in the oxide film at the interface between the layer 13 and the insulating films 21a and 21b. Accordingly, an increase in resistance of the metal silicide layer 13 due to abnormal growth can be prevented. Further, it is possible to prevent the metal silicide layer 13 formed on the source / drain regions from abnormally growing in the channel portion and increasing the leakage current between the source and drain of the field effect transistor. For this reason, the performance of the semiconductor device can be improved. In addition, the reliability of the semiconductor device can be improved.

  In this embodiment, the case where the insulating film 21a is formed first among the insulating films 21a and 21b has been described. However, the insulating film 21b may be formed first. In this case, in FIG. 27, an insulating film 21b is formed instead of the insulating film 21a, and the insulating film 21b is removed in the region where the n-channel type MISFET Qn is formed in the stage of FIG. 28 and the p-channel type MISFET Qp is formed. Leave in the area. Then, an insulating film 21a is formed in place of the insulating film 21b in the stage of FIG. 29, and the insulating film 21a is removed in the region where the p-channel type MISFET Qp is formed in the stage of FIG. 30 and an n-channel type MISFET Qn is formed. It is sufficient to leave it in the reserved area.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is effective when applied to a manufacturing technique of a semiconductor device including a semiconductor element in which a silicon nitride film is formed on a metal silicide layer.

It is principal part sectional drawing in the manufacturing process of the semiconductor device which is one embodiment of this invention. FIG. 2 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 1; FIG. 3 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 2; FIG. 4 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 3; FIG. 5 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4; 6 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5; FIG. FIG. 7 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 6; FIG. 8 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 7; FIG. 9 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 8; FIG. 10 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 9; 1 is a schematic plan view showing a silicon nitride film forming apparatus used in a semiconductor device manufacturing process according to an embodiment of the present invention; FIG. 12 is a schematic cross-sectional view of a film forming chamber provided in the film forming apparatus of FIG. 11. It is a manufacturing process flowchart which shows the formation process of the silicon nitride film in the manufacturing process of the semiconductor device which is one embodiment of this invention. It is explanatory drawing which shows the process step of the 1st film-forming method in the film-forming process of a silicon nitride film. It is explanatory drawing which shows the process step of the 2nd film-forming method in the film-forming process of a silicon nitride film. It is explanatory drawing which shows the process step of the 3rd film-forming method in the film-forming process of a silicon nitride film. It is explanatory drawing which shows the process step of the 4th film-forming method in the film-forming process of a silicon nitride film. It is principal part sectional drawing which shows the state before forming a silicon nitride film on a metal silicide layer after forming a metal silicide layer by a salicide process. It is principal part sectional drawing in the manufacturing process of the semiconductor device of a comparative example. It is principal part sectional drawing in the manufacturing process of the semiconductor device which is one embodiment of this invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device which is other embodiment of this invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device which is other embodiment of this invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device which is other embodiment of this invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device which is other embodiment of this invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device which is other embodiment of this invention. It is a graph which shows the spectrum which measured the silicon nitride film formed on the semiconductor wafer by XPS method. It is principal part sectional drawing in the manufacturing process of the semiconductor device which is other embodiment of this invention. FIG. 28 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 27; FIG. 29 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 28; FIG. 30 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 29; FIG. 31 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 30; FIG. 32 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 31;

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation region 3 P-type well 4 N-type well 5 Gate insulating film 6 Silicon film 6a, 6b Gate electrode 7a n ⁻ type semiconductor region 7b n ⁺ type semiconductor region 8a p ⁻ type semiconductor region 8b p ⁺ type semiconductor Region 9 Side wall 11 Metal film 12 Barrier film 13 Metal silicide layers 21, 21a, 21b Insulating film 22 Insulating film 23 Contact hole 24 Plug 24a Barrier conductor film 24b Main conductor film 31 Stopper insulating film 32 Insulating film 33 Wiring groove 34 Barrier metal Film 35 Wiring 41 Film forming apparatus 42 Transfer chamber 42a Transfer robot 43 Gate valves 44a, 44b Load lock chambers 46, 46a, 46b, 47a, 47b, 48a, 48b Chamber 51 Wafer loading / unloading chambers 51a, 51b Transfer robot 52a, 52b Hoop 53 Port 54 Wafer holder Delivery station 61 Lower electrode 62 Upper electrode 62a Gas introduction port 63 High frequency power supply 64 Mass flow controller 65 Gas exhaust port Qn n channel type MISFET
Qp p-channel MISFET
SW semiconductor wafer

Claims (19)

(A) a step of preparing a semiconductor substrate;
(B) forming a first semiconductor region of a first conductivity type on the semiconductor substrate;
(C) forming a metal silicide layer on the surface of the first semiconductor region;
(D) treating the surface of the metal silicide layer with plasma of a reducing gas;
(E) forming a first insulating film made of silicon nitride on the semiconductor substrate including the metal silicide layer by a plasma CVD method;
Have
The method of manufacturing a semiconductor device, wherein the step (e) is performed after the step (d) without exposing the semiconductor substrate to the atmosphere. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the reducing gas plasma is plasma of ammonia gas, hydrogen gas, or a mixed gas thereof. The method of manufacturing a semiconductor device according to claim 2.
A method of manufacturing a semiconductor device, wherein a natural oxide film on a surface of the metal silicide layer is removed by plasma treatment of the reducing gas in the step (d). In the manufacturing method of the semiconductor device according to claim 3,
The semiconductor device manufacturing method, wherein the first semiconductor region is a source or drain semiconductor region. In the manufacturing method of the semiconductor device according to claim 4,
The step (c)
(C1) forming a metal film on the semiconductor substrate including the first semiconductor region;
(C2) performing a heat treatment to react the metal film and the first semiconductor region to form the metal silicide layer on the surface of the first semiconductor region;
(C3) removing the unreacted metal film after the step (c2), leaving the metal silicide layer on the first semiconductor region;
Have
The step (d) is performed after the step (c3). In the manufacturing method of the semiconductor device according to claim 5,
The method of manufacturing a semiconductor device, wherein the metal film is a nickel film or a nickel alloy film. The method of manufacturing a semiconductor device according to claim 6.
The method of manufacturing a semiconductor device, wherein the metal film is a Ni film, a Ni-Pt alloy film, a Ni-V alloy film, a Ni-Pd alloy film, a Ni-Yb alloy film, or a Ni-Er alloy film. The method of manufacturing a semiconductor device according to claim 7.
The method of manufacturing a semiconductor device, wherein the steps (d) and (e) are performed in the same chamber. In the manufacturing method of the semiconductor device according to claim 1,
After the step (d), the method (e) is performed without exposing the semiconductor substrate to an oxygen-containing atmosphere. In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein an oxide film is not formed at an interface between the first insulating film and the metal silicide layer formed in the step (e). In the manufacturing method of the semiconductor device according to claim 1,
The reducing gas plasma is ammonia gas plasma,
The semiconductor device, wherein the natural oxide film on the surface of the metal silicide layer is removed by the plasma treatment of the ammonia gas in the step (d), and a first nitride film is formed on the surface of the metal silicide layer. Manufacturing method. The method of manufacturing a semiconductor device according to claim 11.
The method of manufacturing a semiconductor device, wherein the first nitride film is a silicon nitride film having a stoichiometric ratio closer to that of the first insulating film formed in the step (e). In the manufacturing method of the semiconductor device according to claim 1,
The step (d)
(D1) placing the semiconductor substrate in the first chamber;
(D2) generating a plasma of the reducing gas in the first chamber and treating the surface of the metal silicide layer with the plasma of the reducing gas;
Have
In the step (e), plasma of a first gas containing silicon element as a constituent element and a second gas containing nitrogen element as a constituent element is generated in the first chamber, and the plasma is formed on the metal silicide layer. A method of manufacturing a semiconductor device, comprising depositing the first insulating film on the semiconductor substrate. 14. The method of manufacturing a semiconductor device according to claim 13,
The method of manufacturing a semiconductor device, wherein the first gas is silane gas and the second gas is ammonia gas. 14. The method of manufacturing a semiconductor device according to claim 13,
The reducing gas plasma is a hydrogen gas plasma,
A natural oxide film on the surface of the metal silicide layer is removed by the plasma treatment of the hydrogen gas in the step (d2),
After the step (d2) and before the step (e),
(D3) The first gas and the second gas are introduced into the first chamber, and the surface of the metal silicide layer is formed on the first gas and the second gas that have not been converted to plasma. Forming a second nitride film on the surface of the metal silicide layer by exposing;
A method for manufacturing a semiconductor device, further comprising: In the manufacturing method of the semiconductor device according to claim 15,
The method of manufacturing a semiconductor device, wherein the second nitride film is a silicon nitride film having a stoichiometric ratio closer to that of the first insulating film formed in the step (e). In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the first insulating film formed in the step (e) is a film that generates a tensile stress on the semiconductor substrate. The method of manufacturing a semiconductor device according to claim 17.
The step (e)
(E1) depositing a silicon nitride film on the semiconductor substrate by a plasma CVD method;
(E2) treating the surface of the silicon nitride film deposited in the step (e1) with nitrogen plasma;
Have
The method of manufacturing a semiconductor device, wherein the steps (e1) and (e2) are repeated one or more times to form the first insulating film. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the first insulating film formed in the step (e) is a film that generates compressive stress on the semiconductor substrate.

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