JP5507654B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a manufacturing technique of a semiconductor device, and more particularly to a technique effective when applied to a manufacturing process of a semiconductor device in which a metal film is embedded in a connection hole opened in an insulating film.

  Japanese Patent Publication No. 2003-324108 (corresponding US is USP 6864183) includes a group consisting of nitrogen trifluoride gas, hydrogen fluoride gas, hexafluorocarbon gas, carbon tetrafluoride gas and sulfur hexafluoride gas. A method of removing a natural oxide film present on the surface of a silicon substrate and a gate electrode by performing plasma etching using a mixed gas of at least one selected fluorinated gas and argon gas is disclosed. (See Patent Document 1).

  JP-A-2-256235 (corresponding US is USP 5030319) discloses that a halogen salt is generated by a gas containing a halogen element and a basic gas, and this is reacted with an oxide film of an object to be treated. A method is disclosed in which a halogen salt gas is directly reacted with an oxide film to selectively etch and remove the oxide film without damaging the underlying layer (see Patent Document 2).

  Japanese Patent Publication No. 3-116727 discloses that a semiconductor substrate having an oxide film formed on the surface thereof is exposed to a gas containing fluorine atoms and then annealed in a reducing gas, an inert gas, or in a vacuum. Thus, a cleaning method for removing the oxide film is disclosed (see Patent Document 3).

JP 2003-324108 A JP-A-2-256235 Japanese Patent Laid-Open No. 3-116727

  As semiconductor devices become more highly integrated, field effect transistors are miniaturized according to the scaling law and connect gates, sources / drains, and wirings, so that connection holes formed in interlayer insulating films have a diameter of 0.1 μm or less. Is required. However, on the surface of the conductive material exposed at the bottom of the connection hole (for example, the surface of the conductive film constituting the gate, the semiconductor region constituting the source / drain, or the silicide layer formed on the conductive film or the semiconductor region). Is easy to form a natural oxide film, and when the metal film is embedded in the connection hole, it is necessary to remove the natural oxide film for good conduction. In particular, with a fine connection hole having a diameter of 0.1 μm or less, it is difficult to remove the natural oxide film at the bottom of the connection hole, and various cleaning methods and processing apparatuses have been proposed.

By the way, the thickness of the natural oxide film formed at the bottom of the connection hole varies. For this reason, as a method for completely removing the natural oxide film and impurities at the bottom of the connection hole without over-etching, the present inventors have formed, for example, HF gas and NH ₃ gas or NF ₃ gas after forming the connection hole. and NH ₃ dry cleaning treatment with a reducing gas such as gas, or a dry cleaning process using a reactive plasma of Ar gas containing NF ₃ gas and NH ₃ gas or NF ₃ gas and the reducing gas of the H ₂ gas, etc. Is going.

  However, the dry cleaning process has various technical problems described below.

Ammonium silicofluoride ((NH ₄ ) ₂ SiF ₆ ) is generated at the bottom and side surfaces of the connection hole subjected to the dry cleaning treatment. Generally, a metal film as a main conductive material is embedded in the connection hole through a barrier metal film (for example, a laminated film in which a titanium nitride film is stacked on a titanium film), but the product remains The contact resistance between the barrier metal film and the underlying conductive material varies on the bottom surface of the connection hole, and the barrier metal film peels off on the side surface of the connection hole.

Then, the examination which removes a product from the bottom face and side surface of a connection hole was performed by heating the connection hole part which performed the dry cleaning process at about 100 degreeC which is the sublimation temperature of the said product. However, it has been clarified that the product cannot be sublimated completely even when the connecting hole portion is heated at a temperature of about 100 ° C., and the above problem cannot be avoided. This connecting hole bottom and composition of the product produced in the side all _{(NH 4)} rather than _{2 SiF 6, (NH 4)} 2 composition slightly deviates from SiF ₆ (non-stoichiometric compound composition When these are not confused, for the sake of convenience, ammonium silicofluoride or ((NH ₄ ) ₂ SiF ₆ ) is also included, and a product with a slightly deviated composition is about 100 ° C. This is considered to be due to remaining on the bottom and side surfaces of the connection hole without sublimation.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, before forming the barrier metal film inside the connection hole opened in the insulating film, placing the semiconductor wafer on the wafer stage provided in the first chamber, and installing the semiconductor wafer above the wafer stage A step of supplying a reducing gas through the showerhead and dry-cleaning the inside of the connection hole; and a step of heat-treating the semiconductor wafer at a first temperature of 100 to 150 ° C. using the heating temperature of the showerhead; A step of transporting the semiconductor wafer from the first chamber to the second chamber and a step of heat-treating the semiconductor wafer at a second temperature of 150 to 400 ° C. in the second chamber.

  According to one embodiment, since variation in electrical characteristics in the connection hole portion can be reduced, the reliability and manufacturing yield of the semiconductor device can be improved.

FIG. 6 is a main-portion cross-sectional view of the semiconductor substrate showing the manufacturing process of the CMOS device according to the first embodiment; FIG. 2 is a fragmentary cross-sectional view of the same portion as that in FIG. 1 of the CMOS device during the manufacturing step following that of FIG. 1; FIG. 3 is a fragmentary cross-sectional view of the same portion as that in FIG. 1 of the CMOS device during the manufacturing step following that of FIG. 2; FIG. 4 is a fragmentary cross-sectional view of the same portion as that in FIG. 1 of the CMOS device during the manufacturing step following that of FIG. 3; (A) is principal part sectional drawing of the same location in FIG. 1 in the manufacturing process of the CMOS device following FIG. 4, (b) is the same as FIG. 1 in the manufacturing process of the CMOS device following the same figure (a). It is principal part sectional drawing of a location. 1 is a schematic plan view of a barrier metal film forming apparatus according to a first embodiment. FIG. 4 is a film formation process diagram of a barrier metal film according to the first embodiment. 2 is a schematic cross-sectional view of a dry cleaning processing chamber provided in the barrier metal film forming apparatus according to Embodiment 1. FIG. (A), (b) and (c) are schematic sectional views of a chamber for explaining a semiconductor wafer processing step in a dry cleaning processing chamber provided in the barrier metal film forming apparatus according to the first embodiment. is there. It is a graph which shows the relationship between the electric current which flows between a gate electrode and a semiconductor substrate at the time of giving a dry cleaning process and heat processing to a semiconductor substrate after forming nMIS, and a heat processing temperature. FIG. 6 is a fragmentary cross-sectional view of the same portion as that in FIG. 1 of the CMOS device during a manufacturing step following that of FIG. 5; FIG. 12 is a fragmentary cross-sectional view of the same portion as that of FIG. 1 during a manufacturing step of the CMOS device following that of FIG. 11; FIG. 13 is a fragmentary cross-sectional view of the same portion as that of FIG. 1 during a manufacturing step of the CMOS device following that of FIG. 12; FIG. 14 is an essential part cross-sectional view of the same portion as that of FIG. 1 of the CMOS device during a manufacturing step following that of FIG. 13; FIG. 6 is a film forming process diagram of a barrier metal film according to a second embodiment. (A), (b), and (c) are schematic sectional views of a chamber for explaining a semiconductor wafer processing step in a dry cleaning processing chamber provided in the barrier metal film forming apparatus according to the second embodiment. is there. (A), (b), and (c) are schematic sectional views of a dry cleaning processing chamber provided in the barrier metal film forming apparatus according to Embodiment 3, respectively.

  In this embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Some or all of the modifications, details, supplementary explanations, and the like are related. Further, in this embodiment, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), unless otherwise specified, or in principle limited to a specific number in principle. It is not limited to the specific number, and may be a specific number or more. Further, in the present embodiment, the constituent elements (including element steps and the like) are not necessarily essential unless particularly specified and apparently essential in principle. Yes. Similarly, in this embodiment, when referring to the shape, positional relationship, etc. of the component, etc., the shape, etc. substantially, unless otherwise specified, or otherwise considered in principle. It shall include those that are approximate or similar to. The same applies to the above numerical values and ranges.

  In the present embodiment, a MIS • FET (Metal Insulator Semiconductor Field Effect Transistor) representing a field effect transistor is abbreviated as MIS, a p-channel type MIS • FET is abbreviated as pMIS, and an n-channel type MIS • FET. Is abbreviated as nMIS. In addition, the description of MOS for convenience does not exclude a non-oxide film. In this embodiment, the term “wafer” mainly refers to a Si (Silicon) single crystal wafer, but not only to this, but also to form an SOI (Silicon On Insulator) wafer and an integrated circuit thereon. It shall refer broadly to an insulating film substrate or the like. The shape includes not only a circle or a substantially circle but also a square, a rectangle and the like. In addition, when referring to a silicon film, a silicon portion, a silicon member, etc., it is not only pure silicon but a substance containing impurities, silicon such as SiGe or SiGeC, unless clearly stated otherwise or otherwise. Needless to say, alloys containing one of the main components (including strained silicon) include additives. In addition, when it is called polycrystalline silicon or the like, it is needless to say that amorphous silicon or the like is included as well as typical ones, unless it is clearly not or is clearly stated otherwise.

  In all the drawings for explaining the embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. Hereinafter, the present embodiment will be described in detail with reference to the drawings.

  Regarding dry cleaning technology, Japanese Patent Application No. 2006-3704 (2006.1.11 application), Japanese Patent Application No. 2006-12355 (application for 2006.1.20), Japanese Patent by Ichinose et al. Since it is disclosed in Japanese Patent Application No. 2006-107780 (2006. 4.10 application), the overlapping part will not be repeated in principle.

(Embodiment 1)
A method of manufacturing a complementary metal oxide semiconductor (CMOS) device according to the first embodiment will be described with reference to FIGS. 1 to 5 and FIGS. 11 to 14 are cross-sectional views of the main part of the CMOS device, FIG. 6 is a schematic plan view of a barrier metal film forming apparatus, FIG. 7 is a film forming process diagram of a barrier metal film, and FIG. FIGS. 9A, 9B, and 9C are schematic cross-sectional views of a dry cleaning processing chamber provided in the film forming apparatus, respectively. FIGS. 9A, 9B, and 9C illustrate a semiconductor wafer processing process in the dry cleaning processing chamber provided in the barrier metal film forming apparatus. FIG. 10 is a schematic cross-sectional view of a chamber for forming the nMIS, and FIG. 10 shows the relationship between the current flowing between the gate electrode and the semiconductor substrate and the heat treatment temperature when dry cleaning treatment and heat treatment are performed on the semiconductor substrate after forming the nMIS. FIG.

  First, as shown in FIG. 1, a semiconductor substrate (semiconductor plate having a substantially planar shape called a semiconductor wafer) 1 made of, for example, p-type single crystal silicon is prepared. Next, the element isolation region 4 is formed on the main surface of the semiconductor substrate 1. In the element isolation region 4, a groove having a depth of 0.35 μm is formed by etching the semiconductor substrate 1, and then an insulating film such as a silicon oxide film is formed on the main surface of the semiconductor substrate 1 by a CVD (Chemical Vapor Deposition) method. After the deposition, the silicon oxide film outside the trench is formed by removing by a CMP (Chemical Mechanical Polishing) method.

  Next, a p-type impurity such as boron (B) is ion-implanted into the nMIS formation region of the semiconductor substrate 1 to form a p-type well 6, and an n-type impurity such as phosphorus (P) is formed in the pMIS formation region of the semiconductor substrate 1. Are implanted to form an n-type well 8. Thereafter, an impurity for controlling the threshold value of nMIS or pMIS may be ion-implanted into the p-type well 6 or the n-type well 8.

  Next, after cleaning the surface of the semiconductor substrate 1 by, for example, wet etching using a hydrofluoric acid aqueous solution, the semiconductor substrate 1 is thermally oxidized, and the gate insulating film 9 having a thickness of, for example, 5 nm is formed on the surface of the semiconductor substrate 1 (p-type). Each surface is formed on the well 6 and the n-type well 8.

  Next, as shown in FIG. 2, a gate electrode conductor film having a thickness of, for example, 0.2 μm is formed on the gate insulating film 9, and then the gate electrode conductor film is formed by dry etching using the resist pattern as a mask. Are processed to form gate electrodes 10n and 10p made of a conductor film. The conductive film for the gate electrode is made of, for example, a polycrystalline silicon film formed by a CVD method, the gate electrode 10n is made of a polycrystalline silicon film into which an n-type impurity is introduced in the nMIS formation region, and p is formed in the pMIS formation region. A gate electrode 10p made of a polycrystalline silicon film doped with type impurities is formed.

Next, an n-type impurity such as arsenic (As) is ion-implanted into the p-type well 6 to form a relatively low concentration source / drain extension region 11 in a self-aligned manner with respect to the gate electrode 10n of the nMIS. Similarly, a p-type impurity, for example, boron fluoride (BF ₂ ) is ion-implanted into the n-type well 8 to form a relatively low concentration source / drain extension region 12 in a self-aligned manner with respect to the gate electrode 10p of the pMIS. Form. The depth of the source / drain extension regions 11 and 12 is, for example, 30 nm.

  Next, as shown in FIG. 3, after a silicon oxide film 13 having a thickness of, for example, 10 nm is deposited on the main surface of the semiconductor substrate 1 by a CVD method, a silicon nitride film is further formed on the silicon oxide film 13 by a CVD method. accumulate. Subsequently, the silicon nitride film is anisotropically etched by RIE (Reactive Ion Etching) to form sidewalls 15 on the respective sidewalls of the nMIS gate electrode 10n and the pMIS gate electrode 10p. Thereafter, an n-type impurity, for example, arsenic is ion-implanted into the p-type well 6 to form a relatively high concentration source / drain diffusion region 16 in a self-aligned manner with respect to the gate electrode 10 n and the sidewall 15 of the nMIS. Similarly, a p-type impurity such as boron fluoride is ion-implanted into the n-type well 8 to form a source / drain diffusion region 17 having a relatively high concentration in a self-aligned manner with respect to the gate electrode 10p and the side wall 15 of the pMIS. Form. The depth of the source / drain diffusion regions 16 and 17 is, for example, 50 nm.

  Next, a low resistance nickel silicide (NiSi) layer 18 is formed on the surface of the nMIS gate electrode 10n and the source / drain diffusion region 16 and the surface of the pMIS gate electrode 10p and the source / drain diffusion region 17 by the salicide technique. Although the nickel silicide layer is illustrated here, other silicide layers such as a titanium silicide layer or a cobalt silicide layer may be formed. The nickel silicide layer 18 is formed, for example, by the method described below.

  First, a nickel film and a titanium nitride film are sequentially deposited on the main surface of the semiconductor substrate 1 by sputtering. The nickel film has a thickness of 10 nm, for example, and the titanium nitride film has a thickness of 15 nm, for example. The titanium nitride film is provided on the nickel film to prevent oxidation of the nickel film, and a titanium film may be used instead of the titanium nitride film. Subsequently, the semiconductor substrate 1 is subjected to, for example, a heat treatment at a temperature of 320 ° C. for 30 seconds using an RTA (Rapid Thermal Anneal) method, whereby an n-type polycrystalline silicon film and a nickel film constituting the nMIS gate electrode 10n are formed. The nickel silicide layer 18 is formed by selectively reacting the single crystal silicon constituting the semiconductor substrate 1 on which the source / drain diffusion regions 16 of nMIS are formed. Similarly, the nickel film and the p-type polycrystalline silicon film constituting the pMIS gate electrode 10p and the nickel film and the single crystal silicon constituting the semiconductor substrate 1 on which the pMIS source / drain diffusion regions 17 are formed are selectively used. A nickel silicide layer 18 is formed by reaction. Subsequently, after removing the unreacted nickel film and titanium nitride film by wet cleaning using sulfuric acid or wet cleaning using sulfuric acid and hydrogen peroxide solution, the RTA method is applied to the semiconductor substrate 1, for example, By applying a heat treatment at a temperature of 550 ° C. for 30 seconds, the resistance of the nickel silicide layer 18 is reduced.

  Next, as shown in FIG. 4, a silicon nitride film is deposited on the main surface of the semiconductor substrate 1 by a CVD method to form a first insulating film 19a. Subsequently, a TEOS (Tetra Ethyl Ortho Silicate) film is deposited on the first insulating film 19a by plasma CVD to form a second insulating film 19b, and an interlayer insulating film made up of the first and second insulating films 19a and 19b is formed. Form. Thereafter, the surface of the second insulating film 19b is polished by a CMP method. Even if an uneven shape is formed on the surface of the first insulating film 19a due to the base step, by polishing the surface of the second insulating film 19b by the CMP method, an interlayer insulating film whose surface is flattened is formed. can get.

  Next, the first and second insulating films 19a and 19b are etched using the resist pattern as a mask, and the connection holes 20 are formed at predetermined positions, for example, the nMIS gate electrode 10n and the source / drain diffusion region 16, and the pMIS gate electrode 10p. And formed on the first and second insulating films 19a and 19b located above the source / drain diffusion region 17. The diameter of the connection hole 20 is 0.1 μm or less, for example, 0.08 μm.

  Next, as shown in FIG. 5A, a titanium film 21 is deposited on the main surface of the semiconductor substrate 1 including the inside of the connection hole 20, and further, on the titanium film 21 as shown in FIG. Then, a titanium nitride film 22 is deposited. Since the titanium film 21 can dissolve oxygen atoms up to 25 at%, it is used as a reducing material on the surface of the nickel silicide layer 18 and has a function of reducing contact resistance with the nickel silicide layer 18. The titanium nitride film 22 has a function of suppressing or preventing diffusion of constituent atoms of a metal film embedded in the connection hole 20 in a later process. In the following description, a laminated film in which the titanium nitride film 22 is stacked on the titanium film 21 is referred to as a barrier metal film, and is distinguished from a metal film embedded in the connection hole 20 and serving as a main conductive material.

  A film forming apparatus 50 shown in FIG. 6 is used for forming the titanium film 21 and the titanium nitride film 22. Hereinafter, a method for forming the titanium film 21 and the titanium nitride film 22 will be described in detail with reference to FIGS.

  The film forming apparatus 50 includes two transfer chambers, a first transfer chamber 51a and a second transfer chamber 51b. Around the first transfer chamber 51a, a loader 53, an unloader 54, This is a multi-chamber type in which three chambers 55, 56 and 57 are provided, and two chambers 58 and 59 are provided around the second transfer chamber 51b via a gate valve 52 which is an opening / closing means. Further, two transfer chambers 60 and 61 are provided between the first transfer chamber 51a and the second transfer chamber 51b. The first transfer chamber 51a is maintained at a predetermined degree of vacuum by an exhaust mechanism or the like, and a transfer robot 62a having an articulated arm structure for transferring the semiconductor wafer SW is provided at the center thereof. Similarly, the second transfer chamber 51b is maintained at a predetermined degree of vacuum by an exhaust mechanism or the like, and a transfer robot 62b having an articulated arm structure for transferring the semiconductor wafer SW is provided at the center thereof.

  The chambers 55 and 56 provided in the first transfer chamber 51a are heat treatment chambers for performing heat treatment at a high temperature of, for example, 150 ° C. or higher, and the chamber 57 is a dry cleaning treatment chamber. The chamber 58 provided in the second transfer chamber 51b is a titanium film forming chamber for depositing the titanium film 21 by a highly directional sputtering method or a plasma CVD method, and the chamber 59 is nitrided by a MOCVD (Metal Organic Chemical Vapor Deposition) method or a plasma CVD method. This is a titanium nitride film forming chamber in which the titanium film 22 is deposited. The chambers 60 and 61 provided between the first transfer chamber 51a and the second transfer chamber 51b are transfer chambers for transferring the semiconductor wafer SW between the first transfer chamber 51a and the second transfer chamber 51b. The cooling chamber is also used for cooling the semiconductor wafer SW. In the film forming apparatus 50, three chambers are provided only in the first transfer chamber 51a and two chambers are provided only in the second transfer chamber 51b. However, the present invention is not limited to this, and chambers for the same purpose are used. It is also possible to add chambers for other applications.

  First, after placing a hoop (Front Open Unified Pod) on which a plurality of semiconductor wafers SW are mounted on the loader 53 (step P1 in FIG. 7), one semiconductor wafer SW is taken out from the hoop by the transfer robot 62a. Vacuum transfer into the transfer chamber 51a. The FOUP is a sealed storage container for batch transfer of semiconductor wafers SW, and normally stores the semiconductor wafers SW in batch units of 25 sheets, 12 sheets, 6 sheets, and the like. The outer wall of the container of the hoop has a secret structure except for a fine ventilation filter portion, and dust is almost completely eliminated. Therefore, even if transported in a class 1000 atmosphere, the inside can maintain a class 1 cleanliness. Docking with the film forming apparatus 50 is performed in a state in which cleanliness is maintained by drawing the door of the hoop into the film forming apparatus 50.

  Next, the semiconductor wafer SW is vacuum-transferred from the first transfer chamber 51a to the dry cleaning processing chamber 57 by the transfer robot 62a (step P2 in FIG. 7). FIG. 8 shows a schematic cross-sectional view of the chamber 57. The chamber 57 is mainly composed of a wafer stage 57a, wafer lift pins 57b, a shower head 57c, and a remote plasma generator 57d. The wafer stage 57a and the wafer lift pin 57b have independent lifting mechanisms and can arbitrarily control the distance between the shower head 57c and the semiconductor wafer SW and the distance between the semiconductor wafer SW and the wafer stage 57a. The shower head 57c installed above the wafer stage 57a is always maintained at a constant temperature, and the temperature is, for example, 180 ° C.

  When the semiconductor wafer SW is carried into the chamber 57, as shown in FIG. 9A, the wafer stage 57a is lowered, the wafer lift pins 57b are raised, and the semiconductor wafer SW is placed on the wafer lift pins 57b. The distance between the shower head 57c and the semiconductor wafer SW is set to, for example, 16.5 ± 12.7 mm, and the distance between the semiconductor wafer SW and the wafer stage 57a is set to, for example, 25.4 ± 17.8 mm.

  Subsequently, when dry-cleaning the main surface of the semiconductor wafer SW, as shown in FIG. 9B, the wafer stage 57a is raised, the wafer lift pins 57b are lowered, and the semiconductor wafer SW is placed on the wafer stage 57a. Put on. The distance between the shower head 57c and the semiconductor wafer SW is set to 17.8 ± 5.1 mm, for example.

During the dry cleaning process, plasma is generated by exciting a reducing gas such as Ar gas added with NF ₃ gas and NH ₃ gas or Ar gas added with NF ₃ gas and H ₂ gas in the remote plasma generator 57d. Plasma is introduced into the chamber 57. By supplying the plasma introduced into the chamber 57 onto the main surface of the semiconductor wafer SW via the shower head 57c, it occurs between the plasma and a natural oxide film formed on the surface of the nickel silicide layer 18, for example. The natural oxide film is removed by the reduction reaction shown in Formula (1). The process conditions during the dry cleaning process are, for example, a shower head temperature of 180 ° C., an NF ₃ gas flow rate of 14 sccm, an NH ₃ gas flow rate of 70 sccm, a pressure of 400 Pa, and a plasma power of 30 W.

SiO ₂ + NF ₃ + NH ₃ → (NH ₄ ) ₂ SiF ₆ + O ₂ Formula (1)
At this time, the product ((NH ₄ ) ₂ SiF ₆ ) generated by the reduction reaction remains on the main surface of the semiconductor wafer SW including the inside of the connection hole 20. Furthermore, the semiconductor wafer SW is only placed on the wafer stage 57a, and the product remains on part of the side surface and the back surface of the semiconductor wafer SW. The product remaining on a part of the side surface and the back surface of the semiconductor wafer SW is peeled off when the semiconductor wafer SW is transported to another chamber or the like, causing contamination and dust generation. Therefore, by subjecting the semiconductor wafer SW to a heat treatment in the chamber 57 following the dry cleaning treatment, products remaining on the main surface of the semiconductor wafer SW are removed, and at the same time, part of the side and back surfaces of the semiconductor wafer SW. The product remaining in is removed.

  Subsequently, when the semiconductor wafer SW is heat-treated, as shown in FIG. 9C, the wafer stage 57a is lowered, the wafer lift pins 57b are raised, and the shower head 57c in which the temperature of the semiconductor wafer SW is set to 180 ° C. Move closer. The distance between the shower head 57c and the semiconductor wafer SW is set to, for example, 3.8 ± 2.6 mm, and the distance between the semiconductor wafer SW and the wafer stage 57a is set to, for example, 5.9 mm or more.

During the heat treatment, the semiconductor wafer SW is heated using the heating temperature (180 ° C.) of the shower head 57c. The temperature of the semiconductor wafer SW becomes 100 to 150 ° C., and the product ((NH ₄ ) ₂ SiF ₆ ) formed on the main surface of the semiconductor wafer SW during the dry cleaning treatment is caused, for example, by the reaction shown in the formula (2). Sublimated and removed. Furthermore, the side surface and the back surface of the semiconductor wafer SW are also heated by this heat treatment, and the product remaining on a part of the side surface and the back surface is also removed.

(NH ₄ ) ₂ SiF ₆ → SiF ₄ + 2NH ₃ + 2HF Formula (2)
However, if the composition of the product formed on the semiconductor wafer SW during the dry cleaning process is slightly deviated from (NH ₄ ) ₂ SiF ₆ , the reaction of formula (2) occurs in the heat treatment at a temperature of 100 to 150 ° C. It is difficult to completely remove the product, and a very small amount of product remains on the main surface of the semiconductor wafer SW. As described above, even if a small amount of product remains in the connection hole 20, problems such as variations in contact resistance between the titanium film 21 and the nickel silicide layer 18 formed in the connection hole 20 after that occur. Arise. Therefore, in the next step, the semiconductor wafer SW is subjected to a heat treatment at a temperature higher than 150 ° C. to remove minute products remaining on the main surface of the semiconductor wafer SW.

  Next, the semiconductor wafer SW is vacuum-transferred from the dry cleaning processing chamber 57 to the heat processing chamber 55 (or chamber 56) via the first transfer chamber 51a by the transfer robot 62a, and the chamber 55 (or chamber 56) is transferred. ) (Step P3 in FIG. 7). By placing the semiconductor wafer SW on the stage of the chamber 55 (or the chamber 56), the semiconductor wafer SW is heated at a predetermined temperature and remains on the main surface of the semiconductor wafer SW without being sublimated at a temperature of 100 to 150 ° C. The product is removed by sublimation. The temperature on the main surface of the semiconductor wafer SW is considered to be an appropriate range of, for example, 150 to 400 ° C. (not to be limited to this range depending on other conditions). Further, a range suitable for mass production is 165 to 350 ° C., but a range having a central value of 200 ° C. such as 180 to 220 ° C. is considered most suitable.

  FIG. 10 shows the current (leakage current) flowing between the gate electrode and the semiconductor substrate and the heat treatment temperature when dry cleaning treatment and heat treatment are performed on the semiconductor substrate after forming the nMIS (inset of FIG. 10). It is a graph which shows a relationship.

The gate current of normal nMIS is about 1 × 10 ⁻¹³ A / μm ² , but if the product generated by the dry cleaning process remains on the surface of nMIS, 5 × 10 ⁻¹¹ A / μm ² is passed through the product. The above surface leakage current flows. However, when heat treatment is performed at a temperature higher than 150 ° C., the surface leakage current decreases as the temperature increases. For example, when heat treatment is performed at a temperature of about 160 ° C., the leakage current is about 1 × 10 ⁻¹² A / μm ² . When heat treatment is further performed at a temperature of about 180 ° C., the leakage current is reduced to about 1 × 10 ⁻¹³ A / μm ² . From this, it is considered that the product can be removed by performing the heat treatment at a temperature higher than 180 ° C. until no leakage current flows on the surface of the nMIS.

  Next, the semiconductor wafer SW is vacuum-transferred from the heat treatment chamber 55 (or the chamber 56) to the cooling / delivery chamber 60 (or the chamber 61) via the first transfer chamber 51a by the transfer robot 62a. 60 (or chamber 61) is placed on a stage (step P4 in FIG. 7). By placing the semiconductor wafer SW on the stage of the chamber 60 (or the chamber 61), the semiconductor wafer SW is cooled.

Next, the semiconductor wafer SW is vacuum-transferred from the cooling / delivery chamber 60 (or chamber 61) to the titanium film-forming chamber 58 via the second transfer chamber 51b by the transfer robot 62b (process P5 in FIG. 7). ). After the inside of the chamber 58 is set to a predetermined degree of vacuum by an exhaust mechanism, for example, 1.33 × 10 ⁻⁶ Pa, the semiconductor wafer SW is heated to a predetermined temperature, and Ar gas is introduced into the chamber 58 at a predetermined flow rate. A titanium film 21 is deposited on the main surface of the semiconductor wafer SW by a highly directional sputtering method. The thickness of the titanium film 21 is 20 nm, for example. The titanium film 21 can be deposited by a plasma CVD method in addition to the high directivity sputtering method.

  Next, the semiconductor wafer SW is vacuum-transferred from the titanium film forming chamber 58 to the titanium nitride film forming chamber 59 through the second transfer chamber 51b by the transfer robot 62b (step P6 in FIG. 7). After the chamber 59 is evacuated to a predetermined degree by an exhaust mechanism, the semiconductor wafer SW is heated to a predetermined temperature, a predetermined gas is introduced into the chamber 59 at a predetermined flow rate, and the semiconductor wafer is formed by MOCVD or plasma CVD. A titanium nitride film 22 is deposited on the main surface of the SW. The thickness of the titanium nitride film 22 is, for example, 5 nm.

  Next, the semiconductor wafer SW is vacuum-transferred from the titanium nitride film forming chamber 59 to the cooling / delivery chamber 60 (or the chamber 61) via the second transfer chamber 51b by the transfer robot 62b (step of FIG. 7). P7).

  Next, the semiconductor wafer SW is transferred from the cooling / delivery chamber 60 (or the chamber 61) to the unloader 54 by the transfer robot 62a (step P8 in FIG. 7), and placed on the hoop placed on the unloader 54.

  As described above, the semiconductor substrate 1 is subjected to heat treatment at 150 to 400 ° C. between the dry cleaning process (process P2 in FIG. 7) and the process of depositing the titanium film 21 (process P5 in FIG. 7) ( Step P3 in FIG. 7, since the product generated during the dry cleaning treatment is removed from the bottom and side surfaces of the connection hole 20, variation in contact resistance between the titanium film 21 and the nickel silicide layer 18 on the bottom surface of the connection hole 20. Can be reduced. Furthermore, peeling of the titanium film 21 on the side surface of the connection hole 20 can be prevented.

  Thereafter, as shown in FIG. 11, a tungsten film 23 is deposited on the main surface of the semiconductor substrate 1 including the inside of the connection hole 20 by a CVD method, and the surface of the tungsten film 23 is flattened by, for example, a CMP method to be connected. A tungsten film 23 is embedded in the hole 20 to form a plug using the tungsten film 23 as a main conductive material.

  In the step of forming the plug inside the connection hole 20 described above, the main conductive material of the plug is the tungsten film 23, and the barrier metal film is a laminated film in which the titanium nitride film 22 is stacked on the titanium film 21, The present invention is not limited to this, and various changes can be made. For example, (1) the main conductive material of the plug is a tungsten film, and the barrier metal film is a tungsten nitride film. Since a tungsten nitride film and a tungsten film can be sequentially formed using one tungsten film forming apparatus, throughput can be improved and cost can be reduced. (2) The main conductive material of the plug is a copper film, and the barrier metal film is a titanium nitride film. (3) The main conductive material of the plug is a copper film, and the barrier metal film is a tantalum nitride film. By using a tantalum nitride film, it is possible to suppress or prevent copper atoms from diffusing more than when a titanium nitride film is used as the barrier metal film. (4) The main conductive material of the plug is a copper film, and the barrier metal film is a laminated film in which a tantalum film is stacked on a tantalum nitride film. By inserting the tantalum film between the copper film and the tantalum nitride film, the adhesion between the copper film and the tantalum nitride film can be improved. (5) The main conductive material of the plug is a copper film, and the barrier metal film is a laminated film in which a ruthenium film is stacked on a tantalum nitride film. By inserting a ruthenium film between the copper film and the tantalum nitride film, the adhesion between the copper film and the tantalum nitride film can be improved. (6) The main conductive material of the plug is an aluminum film, and the barrier metal film is a laminated film in which a titanium nitride film is stacked on a titanium film, or a tungsten nitride film.

  Next, as shown in FIG. 12, a stopper insulating film 24 and a wiring forming insulating film 25 are sequentially formed on the main surface of the semiconductor substrate 1. The stopper insulating film 24 is a film that becomes an etching stopper when a groove is formed in the insulating film 25, and a material having an etching selectivity with respect to the insulating film 25 is used. The stopper insulating film 24 can be a silicon nitride film formed by, for example, plasma CVD, and the insulating film 25 can be, for example, a silicon oxide film formed by plasma CVD. The stopper insulating film 24 and the insulating film 25 are formed with the first layer wiring described below.

  Next, a first layer wiring is formed by a single damascene method. First, after forming a wiring groove 26 in a predetermined region of the stopper insulating film 24 and the insulating film 25 by dry etching using a resist pattern as a mask, a barrier metal film 27 is formed on the main surface of the semiconductor substrate 1. The barrier metal film 27 is, for example, a titanium nitride film, a tantalum nitride film, a stacked film in which a tantalum film is stacked on a tantalum nitride film, or a stacked film in which a ruthenium film is stacked on a tantalum nitride film. Subsequently, a copper seed layer is formed on the barrier metal film 27 by CVD or sputtering, and a copper plating film is further formed on the seed layer by electrolytic plating. The inside of the wiring groove 26 is filled with a copper plating film. Subsequently, the copper plating film, the seed layer, and the barrier metal film 27 in a region other than the wiring groove 26 are removed by CMP to form a first layer wiring M1 using the copper film as a main conductive material.

  Next, a second layer wiring is formed by a dual damascene method. First, as shown in FIG. 13, a cap insulating film 28, an interlayer insulating film 29, and a wiring forming stopper insulating film 30 are sequentially formed on the main surface of the semiconductor substrate 1. As will be described later, connection holes are formed in the cap insulating film 28 and the interlayer insulating film 29. The cap insulating film 28 is made of a material having an etching selectivity with respect to the interlayer insulating film 29, and can be a silicon nitride film formed by, for example, a plasma CVD method. Further, the cap insulating film 28 has a function as a protective film for preventing diffusion of copper constituting the first layer wiring M1. The interlayer insulating film 29 can be a TEOS film formed by, for example, a plasma CVD method. The stopper insulating film 30 is made of an insulating material having an etching selectivity with respect to the interlayer insulating film 29 and an insulating film for wiring formation deposited later on the stopper insulating film 30, and is formed by, for example, a plasma CVD method. A silicon nitride film can be formed.

  Next, after the stopper insulating film 30 is processed by dry etching using a resist pattern for hole formation as a mask, an insulating film 31 for wiring formation is formed on the stopper insulating film 30. The insulating film 31 can be a TEOS film, for example.

  Next, the insulating film 31 is processed by dry etching using a resist pattern for wiring trench formation as a mask. At this time, the stopper insulating film 30 functions as an etching stopper. Subsequently, the interlayer insulating film 29 is processed by dry etching using the stopper insulating film 30 and the resist pattern for forming the wiring trench as a mask. At this time, the cap insulating film 28 functions as an etching stopper. Subsequently, the exposed cap insulating film 28 is removed by dry etching, whereby a connection hole 32 is formed in the cap insulating film 28 and the interlayer insulating film 29, and a wiring groove 33 is formed in the stopper insulating film 30 and the insulating film 31. .

  Next, a second layer wiring is formed inside the connection hole 32 and the wiring groove 33. The second layer wiring is made of a barrier metal layer and a copper film that is a main conductive material, and a connecting member that connects this wiring and the first layer wiring M1 that is a lower layer wiring is the second layer wiring. It is integrally formed. First, the barrier metal film 34 is formed on the main surface of the semiconductor substrate 1 including the insides of the connection holes 32 and the wiring grooves 33. The barrier metal film 34 is, for example, a titanium nitride film, a tantalum nitride film, a stacked film in which a tantalum film is stacked on a tantalum nitride film, or a stacked film in which a ruthenium film is stacked on a tantalum nitride film. The dry cleaning process described above is performed before the barrier metal film 34 is formed. In this dry cleaning process, the heating at a temperature of 100 to 150 ° C. and the heating at a temperature higher than 150 ° C. are performed thereafter. The product formed on the bottom surface of the connection hole 32 and the side walls of the connection hole 32 and the wiring groove 33 may be removed. As a result, variation in contact resistance between the barrier metal film 34 and the first-layer wiring M1 can be reduced, and from the cap insulating film 28, the interlayer insulating film 29, the stopper insulating film 30, and the insulating film 31. The barrier metal film 34 can be prevented from peeling off. Subsequently, a copper seed layer is formed on the barrier metal film 34 by a CVD method or a sputtering method, and a copper plating film is further formed on the seed layer by an electrolytic plating method. The inside of the connection hole 32 and the wiring groove 33 is embedded with a copper plating film. Subsequently, the copper plating film, the seed layer, and the barrier metal film 34 in regions other than the connection hole 32 and the wiring groove 33 are removed by CMP to form a second-layer wiring M2 using the copper film as a main conductive material. .

  After that, as shown in FIG. 14, for example, an upper layer wiring is formed by the same method as the above-described second layer wiring M2. FIG. 14 illustrates a CMOS device in which wirings M3, M4, M5, and M6 from the third layer to the sixth layer are formed. Subsequently, a silicon nitride film 35 is formed on the sixth-layer wiring M 6, and a silicon oxide film 36 is formed on the silicon nitride film 35. The silicon nitride film 35 and the silicon oxide film 36 function as a passivation film that prevents moisture and impurities from entering from the outside and suppresses the transmission of α rays.

  Next, the silicon nitride film 35 and the silicon oxide film 36 are processed by etching using a resist pattern as a mask to expose a part of the sixth layer wiring M6 (bonding pad portion). Subsequently, a bump base electrode 37 made of a laminated film such as a gold film and a nickel film is formed on the exposed sixth layer wiring M6, and a bump electrode 38 made of gold, solder, or the like is formed on the bump base electrode 37. As a result, the CMOS device according to the first embodiment is almost completed. The bump electrode 38 serves as an external connection electrode. Thereafter, the semiconductor wafer SW is cut into individual semiconductor chips and mounted on a package substrate or the like to complete the semiconductor device, but the description thereof is omitted.

In the dry cleaning process of the first embodiment, the remote plasma generator 57d uses Ar gas to which a reducing gas, for example, NF ₃ gas and NH ₃ gas is added (Ar gas is often used as the plasma excitation gas, Other rare gases or mixed gases thereof may be excited to generate plasma, and this plasma is introduced into the chamber 57 to remove the natural oxide film by a reduction reaction. However, HF gas is used without using plasma. A reducing gas such as NH ₃ gas or NF ₃ gas and NH ₃ gas may be introduced into the chamber 57 to remove the natural oxide film by a reduction reaction.

  Further, the present invention is not limited to the remote plasma apparatus, and if there is no problem in other characteristics, there is no problem even if a normal plasma apparatus is used. Remote plasma has the advantage of not damaging the substrate.

  In the case of processing using plasma, this process is not limited to the combination of the above gases, as long as it generates each radical or reactive species of nitrogen, hydrogen, and fluorine (including these complex radicals). Other gas combinations may be used as long as they are not harmful. That is, a mixed gas atmosphere of nitrogen, hydrogen, and fluorine radical generating gas (including mixed gas), plasma excitation gas, and other additive gases may be used as appropriate.

  Further, the reactive gas such as the reducing gas is not limited to the above gas, and any reactive gas that reacts with the oxide film at a relatively low temperature to generate vaporized species may be used.

  As described above, according to the first embodiment, the connection hole is formed by the dry cleaning treatment performed before the barrier metal film (the laminated film in which the titanium nitride film 22 is stacked on the titanium film 21) is formed in the connection hole 20. A product slightly deviating from the stoichiometric composition remains on the bottom surface and the side surface of 20 but this product is removed by a heat treatment at a temperature higher than 150 ° C. performed after the dry cleaning treatment. Variation in contact resistance between the barrier metal film and the nickel silicide layer 18 on the bottom surface of the contact hole 20 can be reduced, and peeling of the barrier metal film on the side surface of the connection hole 20 can be prevented. Variations in characteristics can be reduced. The first embodiment can also be applied to connection hole portions connecting upper and lower layer wirings, and the same effect can be obtained. For example, in the formation process of the dual damascene wiring exemplified in the first embodiment, the first embodiment is performed after the dry cleaning process performed before forming the barrier metal film 34 in the connection hole 32 and the wiring groove 33. The variation in electrical characteristics in the connection hole 32 portion can be reduced.

(Embodiment 2)
As described in the first embodiment, in the dry cleaning process performed in the barrier metal film forming process, the product remains on the main surface, side surface, and part of the back surface of the semiconductor wafer SW. For this reason, the semiconductor wafer SW is heated at a temperature of 100 to 150 ° C. by the shower head 57 c set at 180 ° C. provided in the chamber 57 for the dry cleaning process to remove the product of the composition of (NH ₄ ) ₂ SiF _6. Further, the semiconductor wafer is heated at a temperature higher than 150 ° C. by the heat treatment chambers 55 and 56 to remove the product slightly deviated from the composition of (NH ₄ ) ₂ SiF ₆ .

In the second embodiment, the temperature of the shower head 57CH provided in the dry cleaning process chamber 57 is set to a temperature higher than 180 ° C., for example, 250 ° C., and immediately after the dry cleaning process, the semiconductor wafer SW is loaded by the shower head 57CH. 180 is heated at a temperature of 220 ° C. to remove the _{(NH 4)} the product of the composition of 2 SiF ₆ and _{(NH 4)} shifted product slightly composition from 2 SiF _6.

  A barrier metal film forming method according to the second embodiment will be described with reference to FIGS. FIG. 15 illustrates a barrier metal film deposition process, and FIGS. 16A, 16B, and 16C illustrate a semiconductor wafer processing process in a dry cleaning processing chamber provided in the barrier metal film deposition apparatus, respectively. It is a schematic sectional drawing of the chamber for. The barrier metal film forming apparatus uses the film forming apparatus 50 of the first embodiment described above.

  First, as in the first embodiment, the semiconductor wafer SW is vacuum-transferred from the loader 53 to the dry cleaning processing chamber 57 (steps P1 and P2 in FIG. 15). The shower head 57CH provided in the chamber 57 is always maintained at a constant temperature, and the temperature is, for example, 250 ° C.

  When the semiconductor wafer SW is carried into the chamber 57, as shown in FIG. 16A, the wafer stage 57a is lowered, the wafer lift pins 57b are raised, and the semiconductor wafer SW is placed on the wafer lift pins 57b. The distance between the shower head 57CH and the semiconductor wafer SW is set to, for example, 16.5 ± 12.7 mm, and the distance between the semiconductor wafer SW and the wafer stage 57a is set to, for example, 25.4 ± 17.8 mm.

Subsequently, when the dry cleaning process is performed on the main surface of the semiconductor wafer SW, as shown in FIG. 16B, the wafer stage 57a is raised and the wafer lift pins 57b are lowered to place the semiconductor wafer SW on the wafer stage 57a. Put on. The distance between the shower head 57CH and the semiconductor wafer SW is set to 17.8 ± 5.1 mm, for example. A product ((NH ₄ ) ₂ SiF ₆ ) generated by the reduction reaction remains on the main surface, the side surface, and a part of the back surface of the semiconductor wafer SW subjected to the dry cleaning process.

  Subsequently, when the semiconductor wafer SW is heat-treated, as shown in FIG. 16C, the wafer stage 57a is lowered, the wafer lift pins 57b are raised, and the semiconductor wafer SW is set at a temperature of 250 ° C. Move closer. The distance between the shower head 57CH and the semiconductor wafer SW is set to, for example, 3.8 ± 2.6 mm, and the distance between the semiconductor wafer SW and the wafer stage 57a is set to, for example, 5.9 mm or more.

At the time of heat treatment, the semiconductor wafer SW is heated using the heating temperature (250 ° C.) of the shower head 57CH, so that the temperature of the semiconductor wafer SW becomes higher than 150 ° C., and the main surface of the semiconductor wafer SW is subjected to the dry cleaning treatment. A product having a composition of (NH ₄ ) ₂ SiF ₆ remaining on a part of the upper surface, the side surface and the back surface is removed, and a product slightly deviated from the composition of (NH ₄ ) ₂ SiF ₆ is also removed.

  Next, the semiconductor wafer SW is vacuum-transferred from the dry cleaning processing chamber 57 to the cooling / delivery chamber 60 (or chamber 61) via the first transfer chamber 51a by the transfer robot 62a, and the chamber 60 (or chamber) 61) (step P3 in FIG. 15). By placing the semiconductor wafer SW on the stage of the chamber 60 (or the chamber 61), the semiconductor wafer SW is cooled.

  Thereafter, as in the first embodiment described above, a titanium film is deposited in the titanium film forming chamber 58 by the transfer robot 62b (step P4 in FIG. 15), and the titanium film is deposited on the titanium film in the titanium nitride film forming chamber 59. After depositing a titanium nitride film (process P5 in FIG. 15), the semiconductor wafer SW is vacuum transferred to the cooling / delivery chamber 60 (or chamber 61) (process P6 in FIG. 15). Further, the semiconductor wafer SW is unloaded to the unloader 54 by the transfer robot 62a (step P7 in FIG. 15) and placed on the hoop placed on the unloader 54.

  As described above, according to the second embodiment, unnecessary products generated on part of the side surface and the back surface of the semiconductor wafer SW in the dry cleaning process are heat-treated at 180 to 220 ° C. by the shower head 57CH following the dry cleaning process. Therefore, the heat treatment process in the heat treatment chambers 55 and 56 performed in the first embodiment described above becomes unnecessary, and the number of manufacturing steps can be reduced as compared with the first embodiment described above.

(Embodiment 3)
As described in the first embodiment, in the dry cleaning process performed in the barrier metal film forming process, the semiconductor wafer SW is generally simply placed on the wafer stage 57a. The product of the composition of (NH ₄ ) ₂ SiF ₆ remains not only on the top but also on a part of the side surface and the back surface of the semiconductor wafer SW. The product remaining on a part of the side surface and the back surface of the semiconductor wafer SW is peeled off when the semiconductor wafer SW is transported to another chamber or the like, causing contamination and dust generation. Therefore, in the first and second embodiments described above, by performing heat treatment on the semiconductor wafer SW in the same chamber 57 following the dry cleaning treatment, the product remaining on the main surface of the semiconductor wafer SW is removed at the same time. The product remaining on a part of the side surface and the back surface of the semiconductor wafer SW is removed.

  In the third embodiment, during the dry cleaning process, the generation of products on the side surface and part of the back surface of the semiconductor wafer SW is prevented by preventing the dry cleaning gas from flowing into the back surface of the semiconductor wafer SW. Accordingly, the heat treatment of the semiconductor wafer SW by the shower head 57c performed after the dry cleaning process in the first embodiment described above, that is, the wafer stage 57a provided in the chamber 57 is lowered and the wafer lift pins 57b are raised to raise the semiconductor wafer SW. The heat treatment (FIG. 9C) by bringing the temperature close to the shower head 57 c set at a temperature of 180 ° C. becomes unnecessary. The product remaining on the main surface of the semiconductor wafer SW by the dry cleaning process can be removed by a heat treatment at a temperature higher than 150 ° C. in the heat treatment chambers 55 and 56.

  A dry cleaning method according to the third embodiment will be described with reference to FIG. FIGS. 17A, 17B, and 17C are schematic cross-sectional views of a dry cleaning processing chamber provided in the barrier metal film forming apparatus, respectively.

  FIG. 17A is a view for explaining a first dry cleaning processing method for preventing the generation of products on part of the side surface and the back surface of the semiconductor wafer SW. The semiconductor wafer SW is placed on the wafer stage 57a, and a sealing 57e having an elevating mechanism is held in contact with the periphery on the main surface of the semiconductor wafer SW to press dry cleaning gas to the periphery and the back surface of the semiconductor wafer SW. Is prevented.

  FIG. 17B is a diagram for explaining a second dry cleaning processing method for preventing generation of a product on part of the side surface and the back surface of the semiconductor wafer SW. The semiconductor wafer SW is placed on a wafer stage 57a having an electrostatic chuck function, and a dry cleaning process can be performed without forming a gap between the back surface of the semiconductor wafer SW and the wafer stage 57a. The electrostatic chuck is a mechanism in which a dielectric layer is provided on the wafer stage 57a, a voltage is applied between the wafer stage 57a and the semiconductor wafer SW, and the semiconductor wafer SW is attracted by the force generated therebetween. Depending on the adsorption method, it is classified into a Coulomb force type that uses an insulating material as a dielectric and a Johnson Labek force type. The Johnson Labek force type that has a strong adsorption force at low voltage is a ceramic static type such as alumina. It is popular for electric chucks and is popular because it is advantageous in terms of heat resistance and plasma resistance. Since the electrostatic chuck does not use a mechanical holder, the entire surface of the semiconductor wafer SW can be processed uniformly.

  Further, a shadow ring 57f having a lifting mechanism is provided on the periphery of the main surface of the semiconductor wafer SW. The periphery of the semiconductor wafer SW is covered with the shadow ring 57f without contacting the semiconductor wafer SW, and from the periphery of the wafer stage 57a. An inert gas such as He gas is allowed to flow upward. This prevents the dry cleaning gas from entering the periphery and back surface of the semiconductor wafer SW.

  FIG. 17C is a diagram for explaining a third dry cleaning processing method for preventing generation of a product on part of the side surface and the back surface of the semiconductor wafer SW. The semiconductor wafer SW is placed on the wafer stage 57a, and a sealing 57e having an elevating mechanism is held in contact with the periphery on the main surface of the semiconductor wafer SW to press dry cleaning gas to the periphery and the back surface of the semiconductor wafer SW. Is prevented.

  Further, an exhaust chamber 57g connected to the ceiling 57e is provided below the ceiling 57e, and the wafer stage 57a is placed in the exhaust chamber 57g. The exhaust chamber 57g is provided with a pipe for introducing an inert gas such as He gas into the exhaust chamber 57g and a pipe for exhausting from the exhaust chamber 57g so that the inert gas can flow into and around the semiconductor wafer SW. It has become.

  As described above, according to the third embodiment, unnecessary products are not generated on the side surface and the back surface of the semiconductor wafer SW in the dry cleaning process, and the heat treatment of the semiconductor wafer SW by the shower head 57c following the dry cleaning process. Therefore, the number of manufacturing steps can be reduced as compared with the first embodiment described above.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

The outline of the invention disclosed in the present application will be briefly described below.
1. A method of manufacturing a semiconductor device in which a metal film is embedded in a connection hole opened in an insulating film via a barrier metal film, and the barrier metal is formed in the connection hole after the connection hole is formed in the insulating film. A semiconductor device manufacturing method including the following steps before depositing a film:
(A) placing a semiconductor wafer on a wafer stage provided in the first chamber;
(B) a step of supplying a reducing gas via a shower head installed above the wafer stage and performing a dry cleaning process on the inside of the connection hole;
(C) a step of performing a first heat treatment on the semiconductor wafer at a first temperature using a heating temperature of the shower head (such as radiation of the shower head);
(D) transporting the semiconductor wafer from the first chamber to a second chamber;
(E) performing a second heat treatment on the semiconductor wafer at a second temperature higher than the first temperature in the second chamber;

  In this application, the cleaning process in the connection hole before the formation of the barrier metal has been mainly described. However, the process of each sub-paragraph of this item 1, 8, or 11 is performed as a pre-process (dry cleaning) of other wafer processing. Needless to say, it can be applied.

  That is, dry cleaning as cleaning before wafer processing such as heat treatment or formation of various films (for example, processing for converting a natural oxide film on a silicon surface into a substance that sublimes, evaporates or vaporizes at a relatively low temperature (for example, 400 degrees Celsius or lower) When cleaning is performed, cleaning residues (including cleaning processing products) that are generated as a result of dry cleaning and deposited, condensed or condensed on the wafer surface (including top, side, and back) are cleaned in the same room as the dry cleaning chamber. A part or all of the mechanism is used to heat and remove a part of the cleaning residue by heat treatment at a first temperature (wafer upper surface temperature), and then the wafer is moved to another processing chamber. Residual residues are vaporized by heat treatment at a second temperature (wafer upper surface temperature) higher than the first temperature.

Since the first heat treatment can be performed at a relatively low temperature, there is an advantage that the apparatus structure can be made relatively simple or the throughput can be secured. In addition, this process has an advantage that residues on the back and side surfaces necessary for handling can be removed relatively completely (to the extent that propagation of contamination due to handling is avoided). The second heat treatment is necessary because the vaporization temperature may increase if the product contains a non-stoichiometric composition, and the actual wafer top surface with a complex structure depends on topographical features. This is because the effective vaporization temperature may increase.
2. In the method of manufacturing a semiconductor device according to the item 1, the first temperature is not less than 100 and less than 150 ° C.
3. In the method of manufacturing a semiconductor device according to Item 1, the second temperature is 150 to 400 ° C.
4). In the method of manufacturing a semiconductor device according to Item 1, the second temperature is 165 to 350 ° C.
5. In the method of manufacturing a semiconductor device according to Item 1, the second temperature is 180 to 220 ° C.
6). In the method of manufacturing a semiconductor device according to Item 1, the second temperature is 200 ° C.
7). In the method for manufacturing a semiconductor device according to the item 1, the transfer of the semiconductor wafer between the first chamber and the second chamber is performed by vacuum transfer.
8). A method of manufacturing a semiconductor device in which a metal film is embedded in a connection hole opened in an insulating film via a barrier metal film, and the barrier metal is formed in the connection hole after the connection hole is formed in the insulating film. A semiconductor device manufacturing method including the following steps before depositing a film:
(A) placing a semiconductor wafer on a wafer stage provided in the first chamber;
(B) a step of supplying a reducing gas through a shower head installed above the wafer stage to dry-clean the silicon surface on the main surface of the semiconductor wafer;
(C) performing a first heat treatment on the semiconductor wafer at a first temperature using a heating temperature of the showerhead;
Here, the shower head is maintained at a temperature higher than 180 ° C.

  That is, dry cleaning as cleaning before wafer processing such as heat treatment or formation of various films (for example, processing for converting a natural oxide film on a silicon surface into a substance that sublimes, evaporates or vaporizes at a relatively low temperature (for example, 400 degrees centigrade or less)). When cleaning is performed, cleaning residues (including cleaning processing products) that are generated as a result of dry cleaning and deposited, condensed or condensed on the wafer surface (including top, side, and back) are cleaned in the same room as the dry cleaning chamber. By using a part or all of the mechanism and performing heat treatment at a sufficiently high temperature (wafer upper surface temperature), almost all of the cleaning residue is vaporized and removed.

In this case, since it can be performed in a single heat treatment and in the same chamber, there is an advantage that the processing chamber of the apparatus can be used effectively.
9. 9. The method for manufacturing a semiconductor device according to Item 8, wherein the first temperature is 180 to 220 ° C.
10. 9. The method for manufacturing a semiconductor device according to Item 8, wherein the first temperature is 200.degree.
11. A method of manufacturing a semiconductor device in which a metal film is embedded in a connection hole opened in an insulating film via a barrier metal film, and the barrier metal is formed in the connection hole after the connection hole is formed in the insulating film. A semiconductor device manufacturing method including the following steps before depositing a film:
(A) placing a semiconductor wafer on a wafer stage provided in the first chamber;
(B) a step of supplying a reducing gas via a shower head installed above the wafer stage and performing a dry cleaning process on the inside of the connection hole;
(C) transferring the semiconductor wafer from the first chamber to a second chamber;
(D) a step of heat-treating the semiconductor wafer at a second temperature in the second chamber (corresponding to the second heat-treatment according to item 1);
Here, in the step (b), the reducing gas is not supplied to the side surface and the back surface of the semiconductor wafer.

That is, dry cleaning as cleaning before wafer processing such as heat treatment or formation of various films (for example, processing for converting a natural oxide film on a silicon surface into a substance that sublimes, evaporates or vaporizes at a relatively low temperature (for example, 400 degrees centigrade or less)). Is generated as a result of dry cleaning, and is deposited and condensed on the wafer surface (at this time, it is necessary to execute dry cleaning so that deposits do not adhere to the periphery, side and back of the upper surface). Alternatively, the condensed cleaning residue (including the cleaning processing product) is heat-treated at a sufficiently high temperature (wafer upper surface temperature) in a separate chamber from the dry cleaning chamber to vaporize and remove almost all of the cleaning residue. .
12 12. The method for manufacturing a semiconductor device according to Item 11, wherein the second temperature is 150 to 400 ° C.
13. 12. The method for manufacturing a semiconductor device according to Item 11, wherein the second temperature is 165 to 350 ° C.
14 12. The method for manufacturing a semiconductor device according to Item 11, wherein the second temperature is 180 to 220 ° C.
15. 12. The method for manufacturing a semiconductor device according to Item 11, wherein the second temperature is 200.degree.
16. 12. The method for manufacturing a semiconductor device according to Item 11, wherein the step (b) includes the following steps:
(B1) A step of pressing a peripheral portion of the semiconductor wafer placed on the wafer stage by sealing.
17. 12. The method for manufacturing a semiconductor device according to Item 11, wherein the step (b) includes the following steps:
(B1) adsorbing the semiconductor wafer onto the wafer stage by an electrostatic chuck;
(B2) A step of covering the peripheral portion of the semiconductor wafer with a shadow ring without contacting the semiconductor wafer and allowing an inert gas to flow from the peripheral portion of the wafer stage.
18. 12. The method for manufacturing a semiconductor device according to Item 11, wherein the step (b) includes the following steps:
(B1) a step of pressing a peripheral portion of the semiconductor wafer placed on the wafer stage by sealing;
(B2) A step of flowing an inert gas from the back side of the wafer stage.
19. 12. The manufacturing method of a semiconductor device according to Item 11, wherein the semiconductor wafer is transferred between the first chamber and the second chamber by vacuum.
20. 12. In the method for manufacturing a semiconductor device according to Item 1, 8 or 11, the metal film is a tungsten film, and the barrier metal film is a laminated film in which a titanium nitride film is stacked on a titanium film, or a tungsten nitride film.
21. 12. The manufacturing method of a semiconductor device according to Item 1, 8 or 11, wherein the metal film is a copper film, and the barrier metal film is a titanium nitride film, a tantalum nitride film, and a laminated film in which a tantalum film is stacked on the tantalum nitride film. Or a laminated film in which ruthenium films are stacked on a tantalum nitride film.
22. 12. In the method for manufacturing a semiconductor device according to Item 1, 8 or 11, the metal film is an aluminum film, and the barrier metal film is a laminated film in which a titanium nitride film is stacked on a titanium film, or a tungsten nitride film.

1 semiconductor substrate 4 element isolation region 6 p-type well 8 n-type well 9 gate insulating film 10 n gate electrode 10 p gate electrode 11 source / drain extension region 12 source / drain extension region 13 silicon oxide film 15 sidewall 16 source / drain diffusion region 17 Source / drain diffusion region 18 Nickel silicide layer 19a First insulating film 19b Second insulating film 20 Connection hole 21 Titanium film 22 Titanium nitride film 23 Tungsten film 24 Stopper insulating film 25 Insulating film 26 Wiring groove 27 Barrier metal film 28 Cap insulation Film 29 Interlayer insulating film 30 Stopper insulating film 31 Insulating film 32 Connection hole 33 Wiring groove 34 Barrier metal film 35 Silicon nitride film 36 Silicon oxide film 37 Bump base electrode 38 Bump electrode 50 Film forming apparatus 51a First transfer chamber 51b Second transfer Chamber 52 Gate valve 53 Loader 54 Unloader 55, 56, 57 Chamber 57a Wafer stage 57b Wafer lift pin 57c, 57CH Shower head 57d Remote plasma generator 57e Sealing 57f Shadow ring 57g Exhaust chamber 58, 59, 60, 61 Chamber 62a, 62b Transport robot M1, M2, M3, M4, M5, M6 Wiring SW Semiconductor wafer

Claims (5)

A method of manufacturing a semiconductor device in which a metal film is embedded in a connection hole opened in an insulating film via a barrier metal film, and the barrier metal is formed in the connection hole after the connection hole is formed in the insulating film. A semiconductor device manufacturing method including the following steps before depositing a film:
(A) placing a semiconductor wafer on a wafer stage provided in the first chamber;
(B) Supplying a plasma-excited reducing gas through a shower head installed above the wafer stage, and performing a dry cleaning process on the inside of the connection hole, thereby forming a natural oxide film inside the connection hole. Removing by reduction reaction;
(C-1) After the step (b), the step of raising the semiconductor wafer from the wafer stage to bring the main surface of the semiconductor wafer close to the shower head;
(C-2) After the step (c-1), the semiconductor wafer is heat-treated at a first temperature using the heating temperature of the shower head, and the reduction reaction between the reducing gas and the natural oxide film Removing a product of stoichiometric composition produced by the method and remaining in the connection hole;
(D) a step of transferring the semiconductor wafer from the first chamber to the second chamber after the step (c-2);
(E) After the step (d), in the second chamber, the semiconductor wafer is heat-treated at a second temperature higher than the first temperature, and the reducing gas and the natural oxide film are heated. Removing a non-stoichiometric product produced by a reduction reaction and remaining inside the connection hole;
The reducing gas is NF ₃ gas and NH ₃ gas, or NF ₃ gas and H ₂ gas,
The first temperature is from 100 to 150 ° C .;
The second temperature is Ri 400 ° C. der 150,
The metal film is a copper film;
The barrier metal film is a tantalum nitride film, a stacked film in which a tantalum film is stacked on a tantalum nitride film, or a stacked film in which a ruthenium film is stacked on a tantalum nitride film.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the second temperature is 165 to 350.degree.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the second temperature is 180 to 220.degree.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the second temperature is 200.degree.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor wafer is transferred between the first chamber and the second chamber by vacuum.

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