JP2009088344A - Chip resistor - Google Patents

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JP2009088344A
JP2009088344A JP2007257658A JP2007257658A JP2009088344A JP 2009088344 A JP2009088344 A JP 2009088344A JP 2007257658 A JP2007257658 A JP 2007257658A JP 2007257658 A JP2007257658 A JP 2007257658A JP 2009088344 A JP2009088344 A JP 2009088344A
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electrode
resistor
terminal electrodes
chip resistor
heat dissipation
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Hidekazu Karasawa
秀和 唐澤
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Koa Corp
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Koa Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a chip resistor having an excellent heat dissipating capacity in which plating defects of a heat dissipating electrode can be easily avoided. <P>SOLUTION: The chip resistor 1 includes: a rectangular solid shaped ceramic board 2; a pair of terminal electrodes 3 disposed at both ends of longitudinal direction of the ceramic board 2; a resistor 4 bridging the pair of terminal electrodes 3 on the one face of the ceramic board 2; an insulating protective layer 5, 6 disposed in the area covering the resistor 4; a heat dissipating electrode 7 which is disposed on the other face (or on the surface of protective layer 6) of the ceramic board 2, and is electrically isolated from the pair of the terminal electrodes 3; and a plating layer 8 coating the heat dissipating electrode 7 and the terminal electrodes 3, wherein the terminal electrodes 3 and the heat dissipating electrode 7 are configured so as to be soldered to a plurality of mutually separated lands 51, 52 on a print board 50. This chip resistor 1 is designed so that the planar shape of the heat dissipating electrode 7 is almost an elliptic shape without angularity in the periphery. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、直方体形状のセラミック基板の片面に抵抗体が設けられているチップ抵抗器に係り、特に、電力印加時に抵抗体が発生する熱を逃がすために放熱用の電極を付設しているチップ抵抗器に関する。   The present invention relates to a chip resistor in which a resistor is provided on one side of a rectangular parallelepiped ceramic substrate, and in particular, a chip provided with a heat radiation electrode to release heat generated by the resistor when power is applied. Related to resistors.

従来の一般的な角形のチップ抵抗器は、直方体形状のセラミック基板の片面に抵抗体と該抵抗体を覆う絶縁性の保護層とが設けられていると共に、Niめっき層やSnめっき層等が被着された一対の端子電極が該セラミック基板の長手方向の両端部に設けられ、これら一対の端子電極が抵抗体によって橋絡されるという構成になっている。この種のチップ抵抗器は、通常、抵抗体の存する側を上に向けた姿勢でプリント基板等の実装基板上に面実装され、この実装基板に配設されているランドに各端子電極が半田付けされるようになっているが、チップ抵抗器の小型化が促進されると、電力印加時の抵抗体の発熱によって抵抗値が変化したり半田接合部が溶融する等の不具合が発生しやすくなる。   A conventional general rectangular chip resistor is provided with a resistor and an insulating protective layer covering the resistor on one side of a rectangular parallelepiped ceramic substrate, and a Ni plating layer, a Sn plating layer, or the like. A pair of attached terminal electrodes are provided at both ends in the longitudinal direction of the ceramic substrate, and the pair of terminal electrodes are bridged by a resistor. This type of chip resistor is usually surface-mounted on a mounting board such as a printed circuit board with the resistor side facing up, and each terminal electrode is soldered to a land disposed on the mounting board. However, if miniaturization of chip resistors is promoted, problems such as resistance changes due to the heat generated by the resistors when power is applied and solder joints are likely to melt. Become.

そこで従来、セラミック基板の抵抗体の存する側とは逆側の面(実装基板と対向する側の面)に、一対の端子電極の間で電気的に孤立した平面視矩形状の放熱電極を設け、この放熱電極を実装基板の電気的に孤立したランドに半田付けすることによって、電力印加時に抵抗体の発生する熱が実装基板を介して放出されるようにし、もって放熱性を向上させて温度上昇を抑制できるようにしたチップ抵抗器が知られている(例えば、特許文献1参照)。かかる従来のチップ抵抗器においては、放熱電極用のランドをサーマルビアやヒートシンク等に導通させて効率良く放熱させることが可能となり、また、実装基板上に端子電極用のランドとは別に放熱電極用のランドが配設されるため、実装基板に対するチップ抵抗器の取付強度も向上する。
特開平2−309602号公報
Therefore, conventionally, a heat radiation electrode having a rectangular shape in plan view, which is electrically isolated between a pair of terminal electrodes, is provided on the surface of the ceramic substrate opposite to the side where the resistor exists (surface facing the mounting substrate). By soldering this heat dissipation electrode to an electrically isolated land on the mounting board, heat generated by the resistor is released through the mounting board when power is applied, thereby improving heat dissipation and increasing the temperature. A chip resistor capable of suppressing the rise is known (for example, see Patent Document 1). In such a conventional chip resistor, it is possible to efficiently dissipate heat by connecting the land for the heat dissipation electrode to a thermal via, a heat sink or the like, and for the heat dissipation electrode separately from the land for the terminal electrode on the mounting substrate. Therefore, the mounting strength of the chip resistor to the mounting substrate is also improved.
JP-A-2-309602

ところで、前述した従来のチップ抵抗器のように、セラミック基板の一面に平面視矩形状の放熱電極を設けたものにおいては、端子電極と同様に放熱電極にもNiやSn等のめっき層を被着させる必要があるが、チップ抵抗器の製造工程最終段階で一般的に行われるバレルめっき時に、放熱電極に均一な厚みのめっき層を被着させることは容易でなかった。すなわち、セラミック基板の一面で電気的に孤立している放熱電極はバレルめっき時の通電量が少ないため、放熱電極のめっき層が端子電極のめっき層に比べて膜厚が薄くなることは当然であるが、バレルめっき時には放熱電極が非通電状態で端子電極が通電状態となることが多いため、平面視矩形状の放熱電極の四隅に電荷が集中、つまり、端子電極とは逆のプラス電荷が集中して該四隅のめっき層が溶出し易くなる。特に、Snめっき層の溶出が顕著なため、めっき工程後の放熱電極の四隅に下地のNiめっき層が露出してしまい、こうしためっき不良の放熱電極はNiめっき層が酸化されてしまうため、半田付け不良を起こし易いチップ抵抗器が製造されてしまうという問題があった。   By the way, in the case where a rectangular heat radiation electrode is provided on one surface of the ceramic substrate as in the conventional chip resistor described above, a plating layer such as Ni or Sn is coated on the heat radiation electrode as well as the terminal electrode. Although it is necessary to deposit, it is not easy to deposit a plating layer having a uniform thickness on the heat dissipation electrode during barrel plating, which is generally performed at the final stage of the manufacturing process of the chip resistor. In other words, since the heat dissipation electrode that is electrically isolated on one surface of the ceramic substrate has a small amount of energization during barrel plating, the plating layer of the heat dissipation electrode is naturally thinner than the plating layer of the terminal electrode. However, at the time of barrel plating, the terminal electrode is often energized while the radiation electrode is not energized.Therefore, charges are concentrated at the four corners of the radiation electrode that is rectangular in plan view, that is, positive charges opposite to the terminal electrode are present. It concentrates and the plating layers at the four corners are easily eluted. In particular, since the elution of the Sn plating layer is remarkable, the underlying Ni plating layer is exposed at the four corners of the heat dissipation electrode after the plating process, and the Ni plating layer is oxidized in the heat dissipation electrode having such poor plating, so that the solder There has been a problem that a chip resistor that is prone to attachment failure is produced.

本発明は、このような従来技術の実情に鑑みてなされたものであり、その目的は、放熱性が良好で放熱電極のめっき不良も回避しやすいチップ抵抗器を提供することにある。   The present invention has been made in view of the actual situation of the prior art, and an object of the present invention is to provide a chip resistor that has good heat dissipation and can easily avoid defective plating of the heat dissipation electrode.

上記の目的を達成するため、本発明は、直方体形状のセラミック基板と、このセラミック基板の長手方向の両端部に設けられた一対の端子電極と、前記セラミック基板の片面に設けられて前記両端子電極を橋絡する抵抗体と、この抵抗体を覆う領域に設けられた絶縁性の保護層と、この保護層の表面または前記セラミック基板の他面に設けられて前記両端子電極の間で電気的に孤立している放熱電極と、この放熱電極および前記端子電極に被着されためっき層とを備え、前記放熱電極と前記端子電極が実装基板上の互いに離隔した複数のランドに半田付けされるチップ抵抗器において、前記放熱電極の平面形状が外周部に角部を有さない略楕円形に設定されている構成とした。   In order to achieve the above object, the present invention provides a rectangular parallelepiped ceramic substrate, a pair of terminal electrodes provided at both ends in the longitudinal direction of the ceramic substrate, and the both terminals provided on one surface of the ceramic substrate. A resistor for bridging the electrodes, an insulating protective layer provided in a region covering the resistor, and an electric circuit between the two terminal electrodes provided on the surface of the protective layer or the other surface of the ceramic substrate. A heat dissipating electrode and a plating layer deposited on the heat dissipating electrode and the terminal electrode, and the heat dissipating electrode and the terminal electrode are soldered to a plurality of lands separated from each other on the mounting substrate. The chip resistor has a configuration in which the planar shape of the heat dissipation electrode is set to an approximately elliptical shape having no corners on the outer periphery.

このように構成されたチップ抵抗器では、一対の端子電極の間で電気的に孤立している放熱電極が平面視略楕円形に形成されているため、製造工程の最終段階で行われるバレルめっき時に、放熱電極の特定部位にプラス電荷が集中してめっき層が溶出するという現象が起こりにくくなる。また、平面視略楕円形の放熱電極は一対の端子電極の間に比較的大きく形成することができるため、平面視矩形状の放熱電極とほぼ同様の放熱効果が期待できる。   In the chip resistor configured in this way, since the heat radiation electrode that is electrically isolated between the pair of terminal electrodes is formed in a substantially elliptical shape in plan view, barrel plating performed at the final stage of the manufacturing process Sometimes, the phenomenon that the positive charge concentrates on a specific portion of the heat dissipation electrode and the plating layer is eluted is less likely to occur. Further, since the heat dissipation electrode having a substantially elliptical shape in plan view can be formed relatively large between the pair of terminal electrodes, a heat dissipation effect substantially the same as that of the heat dissipation electrode having a rectangular shape in plan view can be expected.

なお、抵抗体を覆う絶縁性の保護層の表面に放熱電極を設けた場合には、端子電極用ランドと放熱電極用ランドとが配設されている実装基板上にチップ抵抗器がフェイスダウンで面実装されるため、電力印加時に抵抗体の発生する熱を放熱電極や実装基板の放熱電極用ランドに効率良く伝えることができ、放熱性を大幅に向上させることが可能となる。また、セラミック基板の抵抗体の存する側とは逆側の面に放熱電極を設けた場合にも、抵抗体の熱がセラミック基板を介して放熱電極に伝わるため、放熱電極を実装基板の放熱電極用ランドに半田付けすることによって放熱性を向上させることができる。   When a heat dissipation electrode is provided on the surface of the insulating protective layer covering the resistor, the chip resistor is face-down on the mounting substrate on which the terminal electrode land and the heat dissipation electrode land are arranged. Since it is surface-mounted, the heat generated by the resistor when power is applied can be efficiently transmitted to the heat radiation electrode or the heat radiation electrode land of the mounting substrate, and the heat dissipation can be greatly improved. In addition, even when a heat dissipation electrode is provided on the surface of the ceramic substrate opposite to the side where the resistor exists, the heat of the resistor is transferred to the heat dissipation electrode via the ceramic substrate. The heat dissipation can be improved by soldering to the land.

本発明のチップ抵抗器によれば、一対の端子電極の間で電気的に孤立している放熱電極が外周部に角部を有さない平面視略楕円形に形成されているため、製造段階のバレルめっき工程時に放熱電極の特定部位にプラス電荷が集中してめっき層が溶出するという現象が起こりにくくなり、よってめっき不良に起因する放熱電極の半田付け不良を回避することができる。また、一対の端子電極の間に比較的大きな放熱電極を設けることができるため、チップ抵抗器の温度上昇を大幅に抑制することも可能である。   According to the chip resistor of the present invention, the heat dissipating electrode that is electrically isolated between the pair of terminal electrodes is formed in a substantially elliptical shape in a plan view having no corners on the outer peripheral portion. In this barrel plating process, the phenomenon that the positive charge concentrates on a specific portion of the heat dissipation electrode and the plating layer is eluted is less likely to occur, and thus the soldering failure of the heat dissipation electrode due to the plating failure can be avoided. Further, since a relatively large heat dissipation electrode can be provided between the pair of terminal electrodes, it is possible to significantly suppress the temperature rise of the chip resistor.

発明の実施の形態を図面を参照して説明すると、図1は本発明の第1実施形態例に係るチップ抵抗器の実装状態を示す断面図、図2は該チップ抵抗器の下面形状をめっき層を省略して示す説明図である。   BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing a mounted state of a chip resistor according to a first embodiment of the present invention, and FIG. 2 is a plan view of the lower surface of the chip resistor. It is explanatory drawing which abbreviate | omits a layer and shows.

これらの図に示すチップ抵抗器1は、直方体形状のセラミック基板2と、セラミック基板2の長手方向の両端部に設けられた一対の端子電極3と、セラミック基板2の上面に設けられて一対の端子電極3を橋絡する抵抗体4と、抵抗体4を覆う領域に設けられた絶縁性の第1保護層5および第2保護層6と、セラミック基板2の下面に設けられて一対の端子電極3の間で電気的に孤立している放熱電極7と、放熱電極7および端子電極3に被着された2層構造のめっき層8とによって主に構成されている。図1に示すように、このチップ抵抗器1は実装基板であるプリント基板50上に搭載され、端子電極3と放熱電極7をそれぞれ対応するランド51,52に半田付けすることによって面実装される。すなわち、プリント基板50上には、一対の端子電極3を半田付けするための一対のランド51と、放熱電極7を半田付けするためのランド52とが互いに離隔した位置に配設されており、放熱電極7用のランド52はサーマルビア53や放熱用シリコン54を介してヒートシンク55へ効率良く熱が伝えられるように設計されている。なお、図1中の符号40は半田を示している。   The chip resistor 1 shown in these drawings includes a rectangular parallelepiped ceramic substrate 2, a pair of terminal electrodes 3 provided at both ends in the longitudinal direction of the ceramic substrate 2, and a pair of terminal electrodes 3 provided on the upper surface of the ceramic substrate 2. A resistor 4 bridging the terminal electrode 3, an insulating first protective layer 5 and a second protective layer 6 provided in a region covering the resistor 4, and a pair of terminals provided on the lower surface of the ceramic substrate 2 The heat radiation electrode 7 is electrically isolated between the electrodes 3 and the two-layered plating layer 8 attached to the heat radiation electrode 7 and the terminal electrode 3 is mainly configured. As shown in FIG. 1, this chip resistor 1 is mounted on a printed circuit board 50, which is a mounting board, and surface-mounted by soldering the terminal electrode 3 and the heat radiation electrode 7 to the corresponding lands 51 and 52, respectively. . That is, on the printed circuit board 50, a pair of lands 51 for soldering the pair of terminal electrodes 3 and a land 52 for soldering the heat dissipation electrode 7 are disposed at positions separated from each other. The land 52 for the heat radiation electrode 7 is designed so that heat can be efficiently transmitted to the heat sink 55 via the thermal via 53 and the heat radiation silicon 54. In addition, the code | symbol 40 in FIG. 1 has shown the solder.

セラミック基板2はアルミナ基板であり、図示せぬ大判基板を縦横に分割して多数個取りされたものである。各端子電極3は、セラミック基板2の上面に形成された表面電極31と、セラミック基板2の下面に形成された裏面電極32とがセラミック基板2の側端面に形成された端面電極33を介して接続されたものであり、表面電極31と裏面電極32はAg/Pdからなり、端面電極33はニッケルクロム(Ni/Cr)からなる。抵抗体4は酸化ルテニウム等からなり、この抵抗体4の長手方向の両端部が一対の表面電極31に接続されている。なお、抵抗体4には抵抗値を調整するための図示せぬトリミング溝が形成されている。第1保護層5は抵抗体4を覆うプリガラスコートであり、第2保護層6は第1保護層5を覆う樹脂やガラスからなるオーバーコートである。放熱電極7はAgからなり、この放熱電極7の平面形状は図2に示すように小判形状である。2層構造のめっき層8は、電極くわれの防止や半田付けの信頼性向上を図るためのものであり、下地のNiめっき層9と、このNiめっき層9上に被着されたSnめっき層10とからなる。   The ceramic substrate 2 is an alumina substrate, which is obtained by dividing a large substrate (not shown) vertically and horizontally. Each terminal electrode 3 includes a surface electrode 31 formed on the upper surface of the ceramic substrate 2 and a back electrode 32 formed on the lower surface of the ceramic substrate 2 via an end surface electrode 33 formed on the side end surface of the ceramic substrate 2. The front surface electrode 31 and the back surface electrode 32 are made of Ag / Pd, and the end surface electrode 33 is made of nickel chromium (Ni / Cr). The resistor 4 is made of ruthenium oxide or the like, and both ends in the longitudinal direction of the resistor 4 are connected to a pair of surface electrodes 31. The resistor 4 has a trimming groove (not shown) for adjusting the resistance value. The first protective layer 5 is a pre-glass coat that covers the resistor 4, and the second protective layer 6 is an overcoat made of resin or glass that covers the first protective layer 5. The heat radiation electrode 7 is made of Ag, and the planar shape of the heat radiation electrode 7 is an oval shape as shown in FIG. The plating layer 8 having a two-layer structure is for preventing electrode cracking and improving the reliability of soldering. The underlying Ni plating layer 9 and the Sn plating deposited on the Ni plating layer 9 are used. Layer 10.

このように構成されたチップ抵抗器1を製造する際には、まず各チップ領域を区切るように格子状の分割溝が形成された大判基板を準備し、この大判基板に個々のチップ抵抗器1に対応する多数の表面電極31と裏面電極32を印刷形成すると共に、隣接する表面電極31間にそれぞれ抵抗体4を印刷形成する。そして、大判基板の各抵抗体4上に第1保護層(プリガラスコート)5を印刷形成した後、各抵抗体4にレーザトリミング等を行って抵抗値調整用のトリミング溝を形成し、さらに、これらトリミング溝と共に第1保護層5を覆うように第2保護層(オーバーコート)6を印刷形成する。しかる後、大判基板の裏面電極32が形成されている側の面に、裏面電極32とは離隔して位置する平面視略楕円形(小判形状)の放熱電極7を印刷形成する。次に、この大判基板を一方の分割溝に沿って分割(一次分割)して多数の短冊状分割片を得た後、この短冊状分割片の分割面にスパッタリング等を施して端面電極33を形成する。そして、各短冊状分割片を他方の分割溝に沿ってチップサイズの個片に分割(二次分割)した後、これら個片にバレルめっきを施してNiめっき層9とSnめっき層10を順次形成する。つまり、まずNiめっき用バレル内で電解めっきを行い、次いでSnめっき用バレル内で電解めっきを行うことにより、端子電極3と放熱電極7の表面に2層構造のめっき層8を被着させる。こうして図1に示すようなチップ抵抗器1が多数個取りされる。   When manufacturing the chip resistor 1 configured as described above, first, a large substrate having a grid-like dividing groove formed so as to divide each chip region is prepared, and each chip resistor 1 is formed on the large substrate. A large number of front surface electrodes 31 and back surface electrodes 32 corresponding to the above are printed and formed, and the resistor 4 is printed between adjacent front surface electrodes 31. Then, after printing and forming a first protective layer (pre-glass coat) 5 on each resistor 4 of the large substrate, laser trimming or the like is performed on each resistor 4 to form a trimming groove for adjusting a resistance value. Then, a second protective layer (overcoat) 6 is formed by printing so as to cover the first protective layer 5 together with the trimming grooves. Thereafter, the heat radiation electrode 7 having a substantially elliptical shape (oval shape) in plan view, which is located away from the back electrode 32, is printed on the surface of the large substrate where the back electrode 32 is formed. Next, after dividing the large substrate along one dividing groove (primary division) to obtain a large number of strip-shaped segment pieces, sputtering or the like is applied to the segmented surfaces of the strip-shaped segment pieces to form the end face electrodes 33. Form. And after dividing each strip-shaped division | segmentation piece into the chip-sized piece along the other division | segmentation groove | channel (secondary division), these metal pieces are barrel-plated and the Ni plating layer 9 and the Sn plating layer 10 are sequentially carried out. Form. That is, first, electrolytic plating is performed in a Ni plating barrel, and then electrolytic plating is performed in a Sn plating barrel, thereby depositing a plating layer 8 having a two-layer structure on the surfaces of the terminal electrode 3 and the heat dissipation electrode 7. Thus, a large number of chip resistors 1 as shown in FIG.

以上説明したように、本実施形態例に係るチップ抵抗器1は、一対の端子電極3の間に電気的に孤立した放熱電極7を設け、プリント基板50上の複数のランド51,52にそれぞれ端子電極3と放熱電極7を半田付けすることによって面実装されるというものであり、電力印加時に抵抗体4で発生する熱を放熱電極7からランド52やサーマルビア53等を介してヒートシンク55へ伝えて効率良く放熱させることができるため、放熱性に優れており、プリント基板50に対する取付強度も高い。また、このチップ抵抗器1の放熱電極7は外周部に角部を有さない略楕円形(小判形状)に形成されているため、製造段階のバレルめっき工程で放熱電極7の特定部位にプラス電荷が集中してSn等のめっき層が溶出するという現象が起こりにくくなっている。すなわち、放熱電極7の外周部にはバレルめっき時にめっき層の溶出を助長する角部が存しないため、2層構造のめっき層8(Niめっき層9とSnめっき層10)を放熱電極7に安定かつ均一に被着させることができ、めっき不良に起因する放熱電極7の半田付け不良が回避できるようになっている。   As described above, in the chip resistor 1 according to this embodiment, the electrically isolated heat radiation electrode 7 is provided between the pair of terminal electrodes 3, and the plurality of lands 51 and 52 on the printed circuit board 50 are respectively provided. Surface mounting is performed by soldering the terminal electrode 3 and the heat radiation electrode 7, and heat generated in the resistor 4 when power is applied is transferred from the heat radiation electrode 7 to the heat sink 55 via the land 52, the thermal via 53, and the like. Since it can be transmitted and efficiently dissipated, the heat dissipation is excellent and the mounting strength to the printed circuit board 50 is also high. Further, since the heat radiation electrode 7 of the chip resistor 1 is formed in a substantially oval shape (oval shape) having no corners on the outer peripheral portion, it is added to a specific part of the heat radiation electrode 7 in the barrel plating process at the manufacturing stage. The phenomenon that the electric charge concentrates and the plating layer of Sn or the like elutes hardly occurs. That is, since there is no corner portion that promotes elution of the plating layer during barrel plating in the outer peripheral portion of the heat dissipation electrode 7, the two-layered plating layer 8 (Ni plating layer 9 and Sn plating layer 10) is used as the heat dissipation electrode 7. It can be deposited stably and uniformly, and the soldering failure of the heat radiation electrode 7 due to the plating failure can be avoided.

なお、図2に示すように、放熱電極7が矩形の四隅を円弧状に面取りしたような小判形状に設定されていれば、一対の端子電極3の間に比較的大きな放熱電極7を設けることができるため、この放熱電極7を介して効果的に放熱させることは容易であり、バレルめっき時に放熱電極7の通電量が極端に不足する虞もない。   In addition, as shown in FIG. 2, if the heat radiation electrode 7 is set to an oval shape in which four corners of a rectangle are chamfered in an arc shape, a relatively large heat radiation electrode 7 is provided between the pair of terminal electrodes 3. Therefore, it is easy to effectively dissipate heat through the heat radiating electrode 7, and there is no possibility that the energization amount of the heat radiating electrode 7 becomes extremely short during barrel plating.

図3は本発明の第2実施形態例に係るチップ抵抗器の実装状態を示す断面図、図4は該チップ抵抗器の下面形状をめっき層を省略して示す説明図であって、図1および図2と対応する部分には同一符号が付してあるため重複する説明は省略する。   FIG. 3 is a sectional view showing a mounted state of the chip resistor according to the second embodiment of the present invention, and FIG. 4 is an explanatory view showing the shape of the lower surface of the chip resistor with the plating layer omitted. 2 and the parts corresponding to those in FIG.

図3および図4に示すチップ抵抗器20は、抵抗体4を覆う第2保護層6の表面に放熱電極7を設け、プリント基板50上にフェイスダウンで面実装されるようにした点が、前述した第1実施形態例と大きく異なっている。したがって、このチップ抵抗器20の場合、電力印加時に抵抗体4の発生する熱を放熱電極7やプリント基板50のランド52に効率良く伝えることができ、放熱性が大幅に向上する。なお、この第2実施形態例では、放熱電極7が楕円形状に形成されているが、第1実施形態例と同様に放熱電極7が小判形状であっても良く、あるいは放熱電極7が真円に近い楕円形状であっても良い。   The chip resistor 20 shown in FIG. 3 and FIG. 4 is provided with the heat radiation electrode 7 on the surface of the second protective layer 6 covering the resistor 4 and is surface-mounted on the printed board 50 face down. This is significantly different from the first embodiment described above. Therefore, in the case of this chip resistor 20, the heat generated by the resistor 4 when power is applied can be efficiently transmitted to the heat radiation electrode 7 and the land 52 of the printed circuit board 50, and the heat dissipation is greatly improved. In the second embodiment, the heat radiation electrode 7 is formed in an elliptical shape. However, the heat radiation electrode 7 may have an oval shape as in the first embodiment, or the heat radiation electrode 7 is a perfect circle. An elliptical shape close to

本発明の第1実施形態例に係るチップ抵抗器の実装状態を示す断面図である。It is sectional drawing which shows the mounting state of the chip resistor which concerns on the example of 1st Embodiment of this invention. 第1実施形態例に係るチップ抵抗器の下面形状をめっき層を省略して示す説明図である。It is explanatory drawing which abbreviate | omits a plating layer and shows the lower surface shape of the chip resistor which concerns on the example of 1st Embodiment. 本発明の第2実施形態例に係るチップ抵抗器の実装状態を示す断面図である。It is sectional drawing which shows the mounting state of the chip resistor which concerns on the example of 2nd Embodiment of this invention. 第2実施形態例に係るチップ抵抗器の下面形状をめっき層を省略して示す説明図である。It is explanatory drawing which abbreviate | omits a plating layer and shows the lower surface shape of the chip resistor which concerns on the example of 2nd Embodiment.

符号の説明Explanation of symbols

1,20 チップ抵抗器
2 セラミック基板
3 端子電極
4 抵抗体
5 第1保護層(プリガラスコート)
6 第2保護層(オーバーコート)
7 放熱電極
8 めっき層
9 Niめっき層
10 Snめっき層
50 プリント基板(実装基板)
51 (端子電極用の)ランド
52 (放熱電極用の)ランド
53 サーマルビア
55 ヒートシンク
1,20 Chip resistor 2 Ceramic substrate 3 Terminal electrode 4 Resistor 5 First protective layer (pre-glass coating)
6 Second protective layer (overcoat)
7 Heat Dissipation Electrode 8 Plating Layer 9 Ni Plating Layer 10 Sn Plating Layer 50 Printed Circuit Board (Mounting Board)
51 Land (for terminal electrode) 52 Land (for heat radiation electrode) 53 Thermal via 55 Heat sink

Claims (1)

直方体形状のセラミック基板と、このセラミック基板の長手方向の両端部に設けられた一対の端子電極と、前記セラミック基板の片面に設けられて前記両端子電極を橋絡する抵抗体と、この抵抗体を覆う領域に設けられた絶縁性の保護層と、この保護層の表面または前記セラミック基板の他面に設けられて前記両端子電極の間で電気的に孤立している放熱電極と、この放熱電極および前記端子電極に被着されためっき層とを備え、前記放熱電極と前記端子電極が実装基板上の互いに離隔した複数のランドに半田付けされるチップ抵抗器において、前記放熱電極の平面形状が外周部に角部を有さない略楕円形に設定されていることを特徴とするチップ抵抗器。   A rectangular parallelepiped ceramic substrate, a pair of terminal electrodes provided at both ends in the longitudinal direction of the ceramic substrate, a resistor provided on one side of the ceramic substrate to bridge the terminal electrodes, and the resistor An insulating protective layer provided in a region covering the heat sink, a heat dissipating electrode provided on the surface of the protective layer or the other surface of the ceramic substrate and electrically isolated between the two terminal electrodes, and the heat dissipation In a chip resistor comprising an electrode and a plating layer deposited on the terminal electrode, wherein the heat dissipation electrode and the terminal electrode are soldered to a plurality of lands separated from each other on a mounting substrate, the planar shape of the heat dissipation electrode Is set to be a substantially oval shape having no corners on the outer periphery.
JP2007257658A 2007-10-01 2007-10-01 Chip resistor Pending JP2009088344A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021261504A1 (en) * 2020-06-26 2021-12-30 パナソニックIpマネジメント株式会社 Resistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021261504A1 (en) * 2020-06-26 2021-12-30 パナソニックIpマネジメント株式会社 Resistor

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