JP2009087982A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that a large number of manufacturing steps possibly causes an increase in manufacturing cost in a conventional manufacturing method of a semiconductor device. <P>SOLUTION: This manufacturing method of a semiconductor device has: a step of preparing a substrate having a convex portion forming region and an element isolation layer forming region; a step of forming a mask pattern for covering the convex portion forming region on the surface of the substrate; a first etching step of etching the element isolation layer forming region; a first impurity implanting step of implanting a first impurity into the convex portion forming region; a second etching step of forming a convex portion having an upper surface and side surfaces on the convex portion forming region by etching the element isolation layer forming region; a step of removing the mask pattern; a second impurity implanting step of implanting a second impurity of the same type as the first impurity into the convex portion; a step of forming gate insulating films on the upper surface and the side surfaces of the convex portion; and a step of forming a gate electrode on each of the gate insulating films of the convex portion. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a Fin-type semiconductor device.

    In integrated circuit technology, miniaturization of transistors is required. As one of the miniaturization means, a Fin type field effect transistor which is a kind of three-dimensional structure type field effect transistor has been proposed. The Fin-type field effect transistor has a structure in which a convex portion is formed on a substrate and a gate electrode is formed to cover a side surface and an upper surface of the convex portion. In the Fin-type field effect transistor, a channel is formed not only on the top surface of the convex portion but also on the side surface, so that the effective channel width of the transistor can be increased as compared with a transistor in which a channel is formed only on the top surface. it can.

  Further, a structure of a field effect transistor which is a kind of a three-dimensional structure type field effect transistor and has a pentagonal structure instead of a convex structure is also known (see Patent Document 1).

JP 2005-203798 A

  However, in the Fin-type field effect transistor, a channel is easily formed at a corner portion connecting the upper surface and the side surface before the upper surface and the side surface. Therefore, ideal transistor characteristics cannot be obtained in the Fin-type field effect transistor. Moreover, in order to make it a pentagon type structure like patent document 1, there existed a possibility that the manufacturing process might increase and it might lead to the increase in manufacturing cost.

  Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device that improves transistor characteristics without significantly increasing the manufacturing cost.

  The method of manufacturing a semiconductor device according to claim 1, comprising: preparing a substrate having a convex portion forming region and an element isolation layer forming region surrounding the convex portion forming region; and forming the convex portion on the surface of the substrate. A step of forming a mask pattern covering the formation region; a first etching step of etching the element isolation layer formation region of the substrate from the substrate surface side after forming the mask pattern; and after the first etching step A first impurity implantation step of implanting a first impurity from the substrate surface side into the convex portion formation region of the substrate; and after the first impurity implantation step, the element isolation layer formation region of the substrate is defined as the substrate surface A second etching step of forming a convex portion having an upper surface and a side surface in the convex portion forming region of the substrate by etching from the side; and after the second etching step, on the convex portion Removing the mask pattern formed on the substrate, and after removing the mask pattern, implanting a second impurity of the same type as the first impurity into the convex portion of the substrate from the substrate surface side And a step of forming a gate insulating film on an upper surface and a side surface of the convex portion, and a step of forming a gate electrode on the gate insulating film of the convex portion.

  According to the manufacturing method of the semiconductor device according to claim 1, since the first etching step, the first impurity implantation step, the second etching step, and the second impurity implantation step are performed in this order, The impurity concentration becomes higher than the impurity concentration on the upper surface excluding the corners and the exposed side surface. Thus, a channel can be prevented from being formed from the corner first, and a semiconductor device that can improve transistor characteristics can be manufactured.

  Further, since the etching process and the impurity implantation process are the first and second etching processes and the first and second impurity implantation processes, respectively, and the manufacturing method does not increase the mask, the manufacturing cost is greatly increased. The above-described semiconductor device can be manufactured without increasing it.

  The method of manufacturing a semiconductor device according to claim 7, wherein the protrusion forming region has a line shape having a first direction as a long side direction and a second direction that is a direction perpendicular to the first direction as a short side direction. And a step of preparing a substrate having an element isolation layer forming region surrounding the protruding portion forming region, covering the protruding portion forming region on the surface of the substrate, and setting the first direction as a long side direction. Forming a mask pattern having a line shape with the direction of the short side, and etching the element isolation layer forming region of the substrate on which the mask pattern is formed from the substrate surface side, thereby A first etching step of forming a convex portion having an upper surface and a side surface in the convex portion formation region; and etching the mask pattern after the first etching step, whereby the mask pattern A second etching step for narrowing a pattern width in two directions; a first impurity implantation step for implanting the first impurity from the substrate surface side into the convex portion of the substrate after the second etching step; A step of removing the mask pattern after the first impurity implantation step; and a step of implanting a second impurity of the same type as the first impurity from the substrate surface side into the convex portion of the substrate after removing the mask pattern. And a step of forming a gate insulating film on an upper surface and a side surface of the convex portion, and a step of forming a gate electrode on the gate insulating film of the convex portion.

  According to the method for manufacturing a semiconductor device according to claim 7, since the first impurity implantation step and the second impurity implantation step are performed after the first etching step and the second etching step, the corner portions of the convex portions are formed. The impurity concentration becomes higher than the impurity concentration on the upper surface excluding the corners and the exposed side surface. Thus, a channel can be prevented from being formed from the corner first, and a semiconductor device that can improve transistor characteristics can be manufactured.

  Further, since the etching process and the impurity implantation process are the first and second etching processes and the first and second impurity implantation processes, respectively, and the manufacturing method does not increase the mask, the manufacturing cost is greatly increased. The above-described semiconductor device can be manufactured without increasing it.

  According to the present invention, a semiconductor device with improved transistor characteristics can be manufactured without significantly increasing manufacturing costs.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  A semiconductor device 100 of the present invention will be described with reference to FIGS. 1A, 1B, and 1C. 1A is a top view of the semiconductor device 100 according to the first embodiment, FIG. 1B is a cross-sectional view taken along the line BB ′ of FIG. 1A, and FIG. 1C is a cross-sectional view taken along the line CC ′ of FIG. .

  As shown in FIGS. 1A, 1B, and 1C, the semiconductor device 100 includes a substrate 110 on which a convex portion 111 is formed. The substrate 110 is made of silicon, for example.

  The convex portion 111 has a line shape in which the first direction 101 is the long side direction and the second direction 102, which is a direction perpendicular to the first direction 101, is the short side. The pattern width of the convex portion 111 in the second direction 102, that is, the length of the convex portion 111 in the second direction 102 is, for example, 100 nm.

  An element isolation layer 120 surrounding the convex portion 111 is formed around the convex portion 111. The element isolation layer 120 is made of, for example, a silicon oxide film. The film thickness of the element isolation layer 120 is, for example, 200 nm. A part of the side surface of the convex portion 111 surrounded by the element isolation layer 120 is exposed from the element isolation layer 120. The height from the upper surface of the element isolation layer 120 to the upper surface of the protrusion 111 is, for example, 100 nm. Here, the side surface is a surface of the convex portion 111 that extends along the first direction 101 and whose direction perpendicular to the surface is the vertical direction of the first direction 101.

  A gate insulating film 130 is formed on the convex portion 111. The gate insulating film 130 is made of, for example, a silicon oxide film.

  A gate electrode 140 is formed on the gate insulating film 130 and the element isolation layer 120. The gate electrode 140 is made of, for example, polysilicon. The gate electrode 140 is formed along the second direction 102 and is formed so as to cover the gate insulating film 130 and the element isolation layer 120 formed on the convex portion 111.

  An extension region 150 and source / drain regions 151 are formed on the upper surface of the protrusion 111 and the side surface exposed from the element isolation layer 120. A sidewall 160 is formed on the extension region 150.

  Next, the convex part 111 is demonstrated using FIG. 2 which is an enlarged view of FIG. 1B. For convenience of explanation, the gate insulating film 130 and the gate electrode 140 are not shown.

The protrusion 111 has an upper surface and a side surface 113 exposed from the element isolation layer 120. Here, the exposed side surface 113 is exposed from the element isolation layer 120, extends along the first direction 101 of the convex portion 111, and the direction perpendicular to the surface is the first direction 101. It is the surface of the convex part 111 which becomes a perpendicular direction. For example, a P-type first impurity layer 114 is formed at a corner near the connecting line that connects the upper surface 112 and the exposed side surface 113. For example, the first impurity layer 114 is formed to have a thickness of 20 nm from the connection line connecting the upper surface 112 and the exposed side surface 113 in the direction of the upper surface 112 and the side surface 113. The first impurity layer 114 is formed with an impurity concentration of, for example, about 6 × 10 ¹⁷ atoms / cm ³ .

Further, the upper surface 112 excluding the corners and the exposed side surface 113 have a lower concentration than the impurity concentration of the first impurity layer 114 formed at the corners, and the second impurity layer 115 of the same type as the first impurity layer 114. Is formed. The second impurity layer 115 is, for example, a P-type impurity layer, and is formed with an impurity concentration of, for example, about 2 × 10 ¹⁷ atoms / cm ³ . That is, the impurity concentration of the first impurity layer 114 at the corner is, for example, about three times the impurity concentration of the second impurity layer 115 formed on the upper surface 112 excluding the corner and the exposed side surface 113.

  Here, as a comparative example, a Fin-type semiconductor device in which the impurity concentration of the impurity layer at the corner and the impurity concentration of the impurity layer formed on the upper surface and the exposed side surface excluding the corner are the same as in the present invention, The transistor characteristics of the semiconductor device 100 with the impurity concentration of the first impurity layer 114 at the corner portion higher than the impurity concentration of the second impurity layer 115 formed on the upper surface 112 excluding the corner portion and the exposed side surface 113 are respectively shown. explain.

  First, in the semiconductor device of the comparative example, when a voltage is applied to the gate electrode, the electron concentration of the impurity layer at the corner portion is higher than the impurity layer on the upper surface and the side surface. This is because, in the Fin-type semiconductor device, the electric field tends to concentrate at the corners of the protrusions. As a result, when the applied voltage is increased, a channel is formed in the corner impurity layer first, so that a current flows between the source and drain only through the corner impurity layer. When the applied voltage is further increased, a channel is formed in the impurity layer on the upper surface of the convex portion and the impurity layer on the side surface. In other words, since the channel is formed in the corner impurity layer before the upper and side impurity layers, the semiconductor device of the comparative example does not have ideal transistor characteristics and may cause hump characteristics. .

  On the other hand, in the semiconductor device 100 of the present invention, when a voltage is applied to the gate electrode 140, the upper surface 112 excluding the corners before the first impurity layer 114 at the corners and the second impurity layer 115 on the exposed side surface 113 are exposed. The electron concentration of This is because the first impurity layer 114 at the corner has an impurity concentration at which a channel is less likely to be formed than the second impurity layer 115 on the upper surface 112 excluding the corner and the exposed side surface 113. This is because the impurity concentration is about three times as high as that of the two impurity layers 115. As a result, when the applied voltage is increased, a channel is formed in the second impurity layer 115 first, so that a current flows between the source and drain only through the second impurity layer 115. Further, when the applied voltage is increased, a channel is formed in the first impurity layer 114.

  The second impurity layer 115 has a much larger cross-sectional area than the first impurity layer 114, that is, the second impurity layer 115 has a much larger amount of current than the first impurity layer 114. The formation of a channel in the layer 115 is dominant over the transistor characteristics of the semiconductor device 100. That is, in the semiconductor device 100 of the present invention, a channel is first formed in the second impurity layer 115 dominant over the transistor characteristics, and then a channel is formed in the first impurity layer 114. Then, unlike the comparative example, the influence of the hump characteristics is reduced, and the transistor characteristics can be improved.

  Next, a method for manufacturing the semiconductor device of this example will be described with reference to FIGS. 3A to 13A are top views in the respective steps, FIGS. 3B to 13B are cross-sectional views taken along the line BB ′ of FIGS. 3A to 13A, and FIGS. 3C to 13C are C in FIGS. 3A to 13A. It is sectional drawing in a -C 'cut line.

  First, as shown in FIGS. 3A, 3B, and 3C, a substrate 110 is prepared. The substrate 110 has a convex portion forming region 103 and an element isolation layer forming region 104 surrounding the convex portion forming region 103. The substrate 110 is made of silicon, for example. The convex portion formation region 103 has a line shape in which the first direction 101 is the long side direction and the second direction 102, which is a direction perpendicular to the first direction 101, is the short side direction. The pattern width of the convex portion forming region 103 in the second direction 102, that is, the length of the convex portion forming region 103 in the second direction 102 is, for example, 100 nm.

  Next, as shown in FIGS. 4A, 4B, and 4C, a mask pattern 105 is formed on the surface of the substrate 110. The mask pattern 105 is formed so as to cover the convex portion forming region 103 and expose the element isolation layer forming region 104. The mask pattern 105 is made of, for example, a silicon nitride film.

  Next, as shown in FIGS. 5A, 5B, and 5C, the element isolation layer forming region 104 is etched from the substrate surface side (first etching step). Etching is performed by anisotropic etching. Etching is terminated when the depth reaches, for example, 20 nm. That is, at this time, the substrate of the convex portion formation region 103 has a side surface of 20 nm.

Next, as shown in FIGS. 6A, 6B, and 6C, a first impurity is implanted from the substrate surface side (first impurity implantation step). The first impurity is, for example, a P-type impurity. The first impurity implantation step is performed, for example, by implanting boron (B) ions at an acceleration voltage of 15 keV and a dose amount of 8 × 10 ¹¹ atoms / cm ² . The first impurities are not incident on the substrate 110 perpendicularly, but are obliquely incident on the substrate surface. That is, the incident angle θ of the first impurity with respect to the substrate 110 is 0 ° <θ. This is because the first impurity is implanted into the side surface of the substrate 110 of the protrusion forming region 103 exposed by the first etching process. At this time, since the mask pattern 105 is formed, the first impurity is not implanted into the substrate surface of the convex portion formation region 103.

  Next, as shown in FIGS. 7A, 7B, and 7C, the element isolation formation region 104 is etched from the substrate surface side (second etching step). Etching is performed by anisotropic etching. The etching depth is larger than the etching depth in the first etching step. The etching is terminated when the depth reaches, for example, 300 nm. At this time, the impurity is implanted only in the corner portion of the convex portion formation region 103, that is, only in the first impurity formation region 106. By the second etching process, the convex portion 111 having the upper surface and the side surface is formed in the convex portion forming region 103.

  Next, as shown in FIGS. 8A, 8B, and 8C, the element isolation layer 120 is formed in the element isolation layer formation region 104. First, an insulating layer is deposited on the substrate 110 from the substrate surface side. This insulating layer is, for example, a silicon oxide film. Next, the insulating layer is etched until the mask pattern 105 is exposed. This etching is performed, for example, by CMP (Chemical Mechanical Polishing). Next, anisotropic etching is performed on the insulating layer. The anisotropic etching is performed until the thickness of the insulating layer in the element isolation layer formation region 104 becomes, for example, 200 nm. Through the above process, the element isolation layer 120 can be formed in the element isolation layer formation region 104, and the side surface of the convex portion 111 is exposed by, for example, 100 nm from the upper surface. Note that since the mask pattern 105 also functions as a mask for anisotropic etching, the surface of the convex portion formation region 104 is prevented from being damaged by etching.

  Next, as shown in FIGS. 9A, 9B, and 9C, the mask pattern 105 that covers the upper surface of the convex portion formation region 103 is removed.

Next, as shown in FIGS. 10A, 10B, and 10C, a second impurity of the same type as the first impurity is implanted from the substrate surface side (second impurity implantation step). The second impurity is, for example, a P-type impurity. The second impurity implantation step is formed, for example, by implanting boron (B) ions at an acceleration voltage of 15 keV and a dose of 4 × 10 ¹¹ atoms / cm ² . The second impurity is incident on the substrate surface from an oblique direction. That is, the incident angle θ of the second impurity with respect to the substrate 110 is 0 ° <θ. The second impurities are implanted into the corners of the convex portions into which the first impurities are implanted, the side surfaces of the convex portions that are exposed, and the upper surfaces of the convex portions that are exposed by removing the mask pattern 105.

After the second impurity implantation step, thermal diffusion is performed to form the first impurity layer 114 at the corners of the protrusions, and the second type of the same type as the first impurity layer 114 on the upper surface excluding the corners and the exposed side surfaces. An impurity layer 115 is formed. The first impurity layer 114 has been implanted with impurities by the first impurity implantation step and the second impurity implantation step, and the second impurity layer has been implanted with impurities by the second impurity implantation step. The impurity layer 114 is a higher concentration impurity layer than the second impurity layer 115. The first impurity layer 114 is, for example, a P-type impurity layer, and has an impurity concentration of, for example, about 6 × 10 ¹⁷ atoms / cm ³ . The second impurity layer 115 is, for example, a P-type impurity layer, and has an impurity concentration of, for example, about 2 × 10 ¹⁷ atoms / cm ³ . That is, the impurity concentration of the first impurity layer 114 is, for example, about three times the impurity concentration of the second impurity layer 115.

  Next, as shown in FIGS. 11A, 11B, and 11C, a gate insulating film 130 is formed on the upper surface and the exposed side surface of the convex portion 111. The gate insulating film 130 is made of, for example, a silicon oxide film, and is formed by a thermal oxidation method.

  Next, as shown in FIGS. 12A, 12B, and 12C, the gate electrode 140 is formed on the gate insulating film 130 and the element isolation layer 120. The gate electrode 140 is made of, for example, polysilicon, and is formed by depositing polysilicon on a substrate and then patterning. By removing the gate insulating film 130 other than the gate insulating film 130 formed immediately below the gate electrode 140, the protrusion 111 of the element isolation layer formation region 103 is exposed. The gate electrode 140 is formed along the second direction 102 and is formed so as to cover the convex portion 111 and the element isolation layer 120.

  Next, as shown in FIGS. 13A, 13B, and 13C, an extension region 150 is formed on the upper surface and the exposed side surface of the convex portion 111. Further, after the sidewalls 160 are formed on the protrusions 111, source / drain regions 151 are formed on the upper surface and the exposed side surfaces of the protrusions 111. The semiconductor device 100 is manufactured through the above steps.

  In the method of manufacturing the semiconductor device 100 according to the present embodiment, the first impurity is implanted into the convex portion forming region 103 after the first etching step, and the second impurity is implanted into the convex portion forming region 103 after the second etching step. Therefore, the impurity concentration of the first impurity layer 114 formed at the corner of the convex portion 111 is higher than the impurity concentration of the second impurity layer 115 formed on the upper surface and the exposed side surface excluding the corner. Become. Thus, a channel can be prevented from being formed from the corner first, and a semiconductor device that can improve transistor characteristics can be manufactured.

  In addition, a semiconductor device in which the impurity concentration of the impurity layer at the corner is higher than the impurity concentration of the upper surface excluding the corner and the impurity layer of the exposed side surface is etched in the first and second etching steps, respectively. Since the first and second impurity implantation steps and only two steps can be performed without increasing the number of masks, it becomes possible to manufacture the semiconductor device without significantly increasing the manufacturing cost.

  Next, the manufacturing method of Example 2 which is another manufacturing method of the semiconductor device 100 is demonstrated using FIGS. 14A to 24A are top views in the respective steps, FIGS. 14B to 24B are cross-sectional views taken along the line BB ′ in FIGS. 14A to 24A, and FIGS. 14C to 24C are C in FIGS. 14A to 24A. It is sectional drawing in a -C 'cut line.

  First, as shown in FIGS. 14A, 14B, and 14C, a substrate 110 is prepared. The substrate 110 has a convex portion forming region 103 and an element isolation layer forming region 104 surrounding the convex portion forming region 103. The substrate 110 is made of silicon, for example. The convex portion formation region 103 has a line shape in which the first direction 101 is the long side direction and the second direction 102, which is a direction perpendicular to the first direction 101, is the short side direction. The pattern width of the convex portion forming region 103 in the second direction 102, that is, the length of the convex portion forming region 103 in the second direction 102 is, for example, 100 nm.

  Next, as shown in FIGS. 15A, 15B, and 15C, a mask pattern 107 is formed on the surface of the substrate 110. The mask pattern 107 is formed so as to cover the convex portion forming region 103 and expose the element isolation layer forming region 104. The mask pattern 107 is made of, for example, a silicon nitride film. The mask pattern 107 has a line shape in which the first direction 101 is the long side direction and the second direction 102 is the short side direction. The pattern width in the second direction 102 of the mask pattern 107, that is, the length of the mask pattern 107 in the second direction 102 is, for example, 100 nm.

  Next, as shown in FIGS. 16A, 16B, and 16C, the element isolation formation region 104 is etched from the substrate surface side (first etching step). Etching is performed by anisotropic etching. By the first etching step, the convex portion 111 having the upper surface and the side surface is formed in the convex portion forming region 103.

  Next, as shown in FIGS. 17A, 17B, and 17C, the element isolation layer 120 is formed in the element isolation layer formation region 104. First, an insulating layer is deposited on the substrate 110 from the substrate surface side. This insulating layer is, for example, a silicon oxide film. Next, the insulating layer is etched until the mask pattern 107 is exposed. This etching is performed, for example, by CMP (Chemical Mechanical Polishing).

  Next, anisotropic etching is performed on the insulating layer. The anisotropic etching is performed until the thickness of the insulating layer in the element isolation layer formation region 104 becomes, for example, 200 nm. Through the above process, the element isolation layer 120 can be formed in the element isolation layer formation region 104, and the side surface of the convex portion 111 is exposed by, for example, 100 nm from the upper surface. Note that since the mask pattern 107 also functions as a mask for anisotropic etching, the surface of the convex portion formation region 104 is prevented from being damaged by etching.

  Next, as shown in FIGS. 18A, 18B, and 18C, the mask pattern 107 is etched (second etching step). Etching is performed by isotropic etching. In the etching, the pattern width of the mask pattern 107 is reduced, that is, the length of the mask pattern 107 in the second direction 102 is reduced, thereby exposing the end portion of the upper surface of the convex portion 111. By etching, for example, the mask pattern 107 having a width of 100 nm is made to have a width of 60 nm, and the end portions of the upper surface of the convex portion 111 are exposed by 20 nm each.

Next, as shown in FIGS. 19A, 19B, and 19C, a first impurity is implanted from the substrate surface side (first impurity implantation step). The first impurity is, for example, a P-type impurity. The first impurity implantation step is performed, for example, by implanting boron (B) ions at an acceleration voltage of 15 keV and a dose amount of 8 × 10 ¹¹ atoms / cm ² . The first impurity is incident on the substrate 110 perpendicularly and is injected into the substrate. Of the upper surface of the convex portion 111, the first impurity is implanted into the exposed upper surface, that is, the end of the upper surface where the mask pattern 107 is not formed, and the convex portion 111 where the mask pattern 107 is formed is formed. This is because the first impurity is not implanted into the upper surface and the side surface of the exposed convex portion. At this time, the impurity is implanted only in the corner portion of the convex portion formation region 103, that is, only in the first impurity formation region 106. Here, normal incidence means that even if the incident angle is 0 to 2 °, the final transistor characteristics are hardly affected. It shall also include those that are ˜2 °.

  Next, as shown in FIGS. 20A, 20B, and 20C, the mask pattern 107 that covers the upper surface of the convex portion formation region 103 is removed.

Next, as shown in FIGS. 21A, 21B, and 21C, a second impurity of the same type as the first impurity is implanted from the substrate surface side (second impurity implantation step). The second impurity is, for example, a P-type impurity. The second impurity implantation step is formed, for example, by implanting boron (B) ions at an acceleration voltage of 15 keV and a dose of 4 × 10 ¹¹ atoms / cm ² . The second impurity is incident on the substrate surface from an oblique direction. That is, the incident angle θ of the second impurity with respect to the substrate 110 is 0 ° <θ. The second impurities are implanted into the corners of the convex portions into which the first impurities are implanted, the side surfaces of the convex portions that are exposed, and the upper surfaces of the convex portions that are exposed by removing the mask pattern 107.

After the second impurity implantation step, thermal diffusion is performed to form the first impurity layer 114 at the corners of the protrusions, and the second type of the same type as the first impurity layer 114 on the upper surface excluding the corners and the exposed side surfaces. An impurity layer 115 is formed. The first impurity layer 114 has been implanted with impurities by the first impurity implantation step and the second impurity implantation step, and the second impurity layer has been implanted with impurities by the second impurity implantation step. The impurity layer 114 is a higher concentration impurity layer than the second impurity layer 115. The first impurity layer 114 is, for example, a P-type impurity layer, and has an impurity concentration of, for example, about 6 × 10 ¹⁷ atoms / cm ³ . The second impurity layer 115 is, for example, a P-type impurity layer, and has an impurity concentration of, for example, about 2 × 10 ¹⁷ atoms / cm ³ . That is, the impurity concentration of the first impurity layer 114 is, for example, about three times the impurity concentration of the second impurity layer 115.

  Next, as shown in FIGS. 22A, 22B, and 22C, a gate insulating film 130 is formed on the upper surface and the exposed side surface of the convex portion 111. The gate insulating film 130 is made of, for example, a silicon oxide film, and is formed by a thermal oxidation method.

  Next, as shown in FIGS. 23A, 23B, and 23C, the gate electrode 140 is formed on the gate insulating film 130 and the element isolation layer 120. The gate electrode 140 is made of, for example, polysilicon, and is formed by depositing polysilicon on a substrate and then patterning. By removing the gate insulating film 130 other than the gate insulating film 130 formed immediately below the gate electrode 140, the protrusion 111 of the element isolation layer formation region 103 is exposed. The gate electrode 140 is formed along the second direction 102 and is formed so as to cover the convex portion 111 and the element isolation layer 120.

  Next, as shown in FIGS. 24A, 24B, and 24C, the extension region 150 is formed on the upper surface and the exposed side surface of the convex portion 111. Further, after the sidewalls 160 are formed on the protrusions 111, source / drain regions 151 are formed on the upper surface and the exposed side surfaces of the protrusions 111. The semiconductor device 100 is manufactured through the above steps.

  In the manufacturing method of the semiconductor device 100 of the present embodiment, the first impurity implantation step and the second impurity implantation step are performed after the first etching step and the second etching step. The impurity concentration of the first impurity layer 114 is higher than the impurity concentration of the second impurity layer 115 formed on the upper surface excluding the corners and the exposed side surface. Thus, a channel can be prevented from being formed from the corner first, and a semiconductor device that can improve transistor characteristics can be manufactured.

  In addition, a semiconductor device in which the impurity concentration of the impurity layer at the corner is higher than the impurity concentration of the upper surface excluding the corner and the impurity layer of the exposed side surface is etched in the first and second etching steps, respectively. Since the first and second impurity implantation steps and only two steps can be performed without increasing the number of masks, it becomes possible to manufacture the semiconductor device without significantly increasing the manufacturing cost.

In the first and second embodiments, the first impurity is described as a P-type impurity, but the first impurity may be an N-type impurity.

1 is a diagram illustrating a structure of a semiconductor device 100. FIG. 1 is a diagram illustrating a structure of a semiconductor device 100. FIG. 6 is a diagram illustrating a method for manufacturing the semiconductor device 100 of Example 1. FIG. 6 is a diagram illustrating a method for manufacturing the semiconductor device 100 of Example 1. FIG. 6 is a diagram illustrating a method for manufacturing the semiconductor device 100 of Example 1. FIG. 6 is a diagram illustrating a method for manufacturing the semiconductor device 100 of Example 1. FIG. 6 is a diagram illustrating a method for manufacturing the semiconductor device 100 of Example 1. FIG. 6 is a diagram illustrating a method for manufacturing the semiconductor device 100 of Example 1. FIG. 6 is a diagram illustrating a method for manufacturing the semiconductor device 100 of Example 1. FIG. 6 is a diagram illustrating a method for manufacturing the semiconductor device 100 of Example 1. FIG. 6 is a diagram illustrating a method for manufacturing the semiconductor device 100 of Example 1. FIG. 6 is a diagram illustrating a method for manufacturing the semiconductor device 100 of Example 1. FIG. 6 is a diagram illustrating a method for manufacturing the semiconductor device 100 of Example 1. FIG. It is a figure explaining the manufacturing method of the semiconductor device 100 of Example 2. FIG. It is a figure explaining the manufacturing method of the semiconductor device 100 of Example 2. FIG. It is a figure explaining the manufacturing method of the semiconductor device 100 of Example 2. FIG. It is a figure explaining the manufacturing method of the semiconductor device 100 of Example 2. FIG. It is a figure explaining the manufacturing method of the semiconductor device 100 of Example 2. FIG. It is a figure explaining the manufacturing method of the semiconductor device 100 of Example 2. FIG. It is a figure explaining the manufacturing method of the semiconductor device 100 of Example 2. FIG. It is a figure explaining the manufacturing method of the semiconductor device 100 of Example 2. FIG. It is a figure explaining the manufacturing method of the semiconductor device 100 of Example 2. FIG. It is a figure explaining the manufacturing method of the semiconductor device 100 of Example 2. FIG. It is a figure explaining the manufacturing method of the semiconductor device 100 of Example 2. FIG.

Explanation of symbols

100 Semiconductor Device 110 Substrate 111 Projection 114 First Impurity Layer 115 Second Impurity Layer 120 Element Isolation Layer 130 Gate Insulating Film 140 Gate Electrode 150 Extension Region 151 Source / Drain Region 160 Side Wall

Claims (13)

Preparing a substrate having a convex portion forming region and an element isolation layer forming region surrounding the convex portion forming region;
Forming a mask pattern on the surface of the substrate to cover the convex formation region;
A first etching step of etching the element isolation layer forming region of the substrate from the substrate surface side after forming the mask pattern;
After the first etching step, a first impurity injection step of injecting a first impurity from the substrate surface side into the convex portion forming region of the substrate;
After the first impurity implantation step, the element isolation layer forming region of the substrate is etched from the substrate surface side to form a convex portion having an upper surface and a side surface in the convex portion forming region of the substrate. 2 etching steps;
After the second etching step, removing the mask pattern formed on the upper surface of the convex portion;
After removing the mask pattern, a second impurity implantation step of implanting a second impurity of the same type as the first impurity from the substrate surface side into the convex portion of the substrate;
Forming a gate insulating film on an upper surface and a side surface of the convex portion;
Forming a gate electrode on the convex gate insulating film;
A method for manufacturing a semiconductor device, comprising:   The convex portion forming region has a line shape in which a first direction is a long side direction and a second direction which is a direction perpendicular to the first direction is a short side direction. The manufacturing method of the semiconductor device of description. Forming an element isolation layer in the element isolation formation region of the substrate after the second etching step and before removing the mask pattern;
The method of manufacturing a semiconductor device according to claim 2, further comprising:   4. The method of manufacturing a semiconductor device according to claim 3, wherein the gate electrode extends in the second direction and is formed on the gate insulating film of the convex portion and the element isolation layer. 5.   The method for manufacturing a semiconductor device according to claim 1, wherein the step of forming the gate insulating film is performed after the second impurity implantation step.   6. The method of manufacturing a semiconductor device according to claim 5, wherein after forming the gate electrode, a source / drain region is formed in the convex portion of the substrate. A convex portion forming region having a line shape having a first direction as a long side direction and a second direction that is a direction perpendicular to the first direction as a short side direction, and an element isolation layer forming region surrounding the convex portion forming region. Preparing a substrate having:
Forming a mask pattern on the surface of the substrate, the mask pattern having a line shape that covers the convex portion forming region, has the first direction as a long side direction, and the second direction as a short side direction;
First etching for forming a convex portion having an upper surface and a side surface in the convex portion forming region of the substrate by etching the element isolation layer forming region of the substrate on which the mask pattern is formed from the substrate surface side. Process,
A second etching step for narrowing a pattern width in the second direction of the mask pattern by etching the mask pattern after the first etching step;
After the second etching step, a first impurity implantation step of injecting the first impurity from the substrate surface side into the convex portion of the substrate;
Removing the mask pattern after the first impurity implantation step;
After removing the mask pattern, a second impurity implantation step of implanting a second impurity of the same type as the first impurity from the substrate surface side into the convex portion of the substrate;
Forming a gate insulating film on an upper surface and a side surface of the convex portion;
Forming a gate electrode on the convex gate insulating film;
A method for manufacturing a semiconductor device, comprising: Forming an element isolation layer in the element isolation layer forming region of the substrate after the first etching step and before the second etching step;
The method of manufacturing a semiconductor device according to claim 7, further comprising:   9. The method of manufacturing a semiconductor device according to claim 8, wherein the gate electrode extends in the second direction and is formed on the gate insulating film of the convex portion and the element isolation layer. .   The method for manufacturing a semiconductor device according to claim 7, wherein the step of forming the gate insulating film is performed after the second impurity implantation step.   11. The method of manufacturing a semiconductor device according to claim 10, wherein after forming the gate electrode, a source / drain region is formed in the convex portion of the substrate.   The method of manufacturing a semiconductor device according to claim 7, wherein the second etching step is performed by isotropic etching.   13. The method of manufacturing a semiconductor device according to claim 7, wherein in the first impurity implantation step, the first impurity is implanted by being perpendicularly incident on the substrate.

Images