JP2009081261A - Semiconductor package, and package-on-package structure using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a compact semiconductor package excellent in connection reliabilities, and to provide a package-on-package structure using the same. <P>SOLUTION: The semiconductor package has external connection terminals on the surface and the rear surface, and the package-on-package structure has the semiconductor package with at least not less than one external connection terminals formed in the semiconductor element mounting region of each surface and a plurality of semiconductor packages vertically laminated and electrically connected. The external connection terminal provided on the lower surface of the upper side semiconductor package and the external connection terminal provided on the upper surface of the lower side semiconductor package are electrically connected through soldering, and at least not less than one external connection terminal is formed in the semiconductor element mounting region of each vertical surface. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a small semiconductor package that can be mounted in multiple layers and a package-on-package structure using the same.

The development of the information society in recent years has been remarkable, and consumer devices have been reduced in size, weight, performance, and functionality, such as personal computers and mobile phones. Industrial equipment includes wireless base stations, optical communication devices, and servers. In addition, there is a demand for improvement in function in the same way, regardless of whether it is large or small, such as routers and other network-related devices.
In addition, with the increase in the amount of information transmitted, the frequency of signals handled tends to increase year by year, and high-speed processing and high-speed transmission technology are being developed.

  With regard to mounting relations, the development of system-on-chip (SoC), system-in-package (SiP), etc., as new high-density mounting technologies, as well as higher-speed and higher-performance LSIs such as CPUs, DSPs, and various types of memory are actively developed. Has been done. In particular, the system-in-package is a multi-layered mounting of a plurality of semiconductor elements in a two-dimensional or three-dimensional manner, as represented by a stacked CSP, and is already mass-produced mainly in memory. Progressing.

  However, there are many restrictions on the types of semiconductor elements to be combined, the size of each semiconductor element, and the like, which is a problem when multilayered. As a technique that can alleviate these restrictions, package on package (PoP) in which thin semiconductor packages are mounted in multiple layers has been proposed.

  As a conventional technique of PoP, a semiconductor package structure as shown in Patent Document 1 has been proposed. This is because a thin semiconductor package as shown in FIG. 6 is manufactured, and as shown in FIG. 7, a plurality of semiconductor packages are melted on the external connection terminals formed outside the semiconductor element mounting region. It is characterized by a structure that connects and multi-layers.

  In the conventional PoP structure, the external connection terminals are formed outside the semiconductor element mounting region. For this reason, there is a problem that the semiconductor package becomes larger than the semiconductor element and cannot be downsized.

  In addition, since the external connection terminals are formed only outside the semiconductor chip mounting region, the external connection terminals cannot be made large in a multi-pin semiconductor package, and there is a problem that the connection reliability between the semiconductor packages is inferior.

JP-A-11-330306

  An object of the present invention is to provide a small semiconductor package having excellent connection reliability and a package-on-package structure using the semiconductor package.

In order to achieve the above object, the present invention provides a semiconductor package having external connection terminals on an upper surface and a lower surface, wherein at least one external connection terminal is formed in a semiconductor element mounting region on each surface. The basic structure is a PoP structure formed by multilayering a plurality of semiconductor packages. That is, the present invention relates to the following matters.
(1) A semiconductor package having external connection terminals on an upper surface and a lower surface, wherein at least one external connection terminal is formed in a semiconductor element mounting region on each surface.

  (2) An electrode for wire bonding connection and an electrode for flip chip connection are provided only on one surface of the semiconductor element, and the flip chip connection electrode is connected to the outer edge of the semiconductor element for the wire bonding connection. A first wiring board disposed on an opposite side of the semiconductor element; and a second wiring board disposed on a surface of the semiconductor element having the electrode, and a first wiring board disposed on an opposite side of the semiconductor element. The wiring board includes a wiring pattern in which a wire bonding terminal and an external connection terminal are part of the wiring, and the wire bonding terminal is provided on a wiring outside a region where the semiconductor element is mounted, and the external connection The terminal is provided in a region where the semiconductor element is mounted, and the wire bonding terminal and the wire bonding connection electrode are connected via a wire, and The second wiring board includes a wiring pattern in which a flip chip terminal and an external connection terminal are part of the wiring, and the plip chip terminal is provided on the wiring inside the region where the semiconductor element is mounted. The semiconductor package according to (1), wherein the external connection terminal is provided inside the flip chip terminal, and the flip chip connection electrode of the semiconductor element and the flip chip terminal are flip chip connected.

  (3) A package-on-package structure in which a plurality of semiconductor packages are stacked one above the other and are electrically connected, and provided on the upper surface of the lower semiconductor package and the external connection terminal provided on the lower surface of the upper semiconductor package A package-on-package structure in which one or more external connection terminals are electrically connected via solder, and at least one of the external connection terminals is formed in a semiconductor element mounting region on each of upper and lower surfaces.

  (4) The semiconductor package has an electrode for wire bonding connection and an electrode for flip chip connection on only one surface of the semiconductor element, and the electrode for flip chip connection is connected to the outer edge of the semiconductor element with the wire. A second wiring board disposed on the surface having the electrodes of the semiconductor element, and a first wiring board disposed on the opposite side of the semiconductor element, the inner side being formed inside the electrode for bonding connection; The first wiring board includes a wiring pattern in which a wire bonding terminal and an external connection terminal are part of the wiring, and the wire bonding terminal is provided on a wiring outside a region where the semiconductor element is mounted. The external connection terminal is provided in a region where the semiconductor element is mounted, and the wire bonding terminal and the electrode for wire bonding connection are wires. The second wiring board includes a wiring pattern in which a flip chip terminal and an external connection terminal are part of the wiring, and the flip chip terminal is provided in a region where the semiconductor element is mounted. The package according to (3), wherein the package is provided on an inner wiring, the external connection terminal is provided inside the flip chip terminal, and the flip chip connection electrode of the semiconductor element and the flip chip terminal are flip chip connected. On-package structure.

(5) The package-on-package structure according to (3) or (4), wherein an upper surface of the uppermost semiconductor package among the plurality of stacked semiconductor packages has no external connection terminal.
(6) The package-on-package according to (3), (4), or (5), wherein a solder ball is provided on an external connection terminal of a lowermost semiconductor package among a plurality of semiconductor packages stacked vertically Structure.

  According to the present invention, it is possible to manufacture a semiconductor package and a PoP structure that are small in size and excellent in connection reliability.

The best mode for carrying out the invention will be described below with reference to the drawings.
(Semiconductor package structure)
1 and 2 show an example of a cross-sectional view of a semiconductor package of the present invention. FIG. 1 is a configuration example of a semiconductor package in which two wiring boards are arranged on a face surface (electrode formation surface) and a back surface of a semiconductor element, and FIG. 2 shows a wafer level CSP on which wire bonding connection electrodes are formed and its back surface. It is the example of a structure which has arrange | positioned the wiring board.

  In the example of FIG. 1, the electrode for wire bonding and the electrode for flip chip connection are provided only on one surface of the semiconductor element, and the electrode for flip chip connection is an electrode for wire bonding connection with respect to the outer edge of the semiconductor element. The one formed inside is used. In the structure of the semiconductor package, the second wiring substrate is bonded to the surface having the electrodes of the semiconductor element, and the first wiring substrate is bonded to the opposite surface of the semiconductor element with an adhesive.

  The first wiring board includes a wiring pattern in which a wire bonding terminal and an external connection terminal are part of the wiring, and the wire bonding terminal is provided on the wiring outside the region where the semiconductor element is mounted, The external connection terminal is provided in a region where the semiconductor element is mounted. The wire bonding terminal of the second wiring board and the electrode for wire bonding connection of the semiconductor element are electrically connected by a wire.

  The second wiring board includes a wiring pattern in which a flip chip terminal and an external connection terminal are part of the wiring, and the flip chip terminal is provided on the wiring inside the region where the semiconductor element is mounted. The external connection terminal is provided inside the flip chip terminal. The flip chip connection electrode of the semiconductor element and the flip chip terminal of the second wiring substrate are flip chip connected by a bump or the like.

In the example of FIG. 2, a wafer level CSP in which an electrode for wire bonding connection is formed on the periphery of a semiconductor element is bonded to a wiring board with an adhesive on the reverse surface on which external connection terminals are formed. The wiring board includes a wiring pattern in which a wire bonding terminal and an external connection terminal are part of the wiring, and the wire bonding terminal is provided on the wiring outside the region where the semiconductor element is mounted, and the external connection terminal Is provided in a region where the semiconductor element is mounted. The wire bonding terminal of the wiring board and the electrode for wire bonding connection of the semiconductor element are electrically connected by a wire.
1 and 2 show an example in which all external connection terminals are arranged in the semiconductor element mounting region, but they can be arranged outside the wire bonding terminals as necessary.

(PoP structure)
FIG. 3 shows an example of a cross-sectional view of the PoP structure of the present invention. The semiconductor package shown in FIG. 1 or FIG. 2 has a structure in which a plurality of semiconductor packages are mounted via solder balls. FIG. 3 shows an example in which the semiconductor package of FIG. 1 is multilayered. However, as long as the arrangement of external connection terminals connected by solder balls is the same, it is possible to mix them and Different semiconductor packages can be multi-layered to form a PoP structure.

  Further, FIG. 3 shows an example in which the external connection terminals are also formed on the upper surface of the uppermost semiconductor package. However, the uppermost semiconductor package is a semiconductor package having no external connection terminals on the upper surface like a conventional CSP. A multilayer structure is preferable because the insulation reliability can be improved. In addition, it is preferable to provide solder balls on the external connection terminals on the lower surface of the lowermost semiconductor package in order to improve mountability on the mother board.

(Wiring board)
As the wiring board used in the present invention, a general semiconductor element mounting board can be used. However, in order to reduce the thickness of the semiconductor package, it is preferable that the wiring board to be used is thin. A wiring substrate having one wiring layer using a polyimide film as shown in FIG.

  FIG. 5 shows an example of a plan view of a wire bonding type wiring board. As shown in the drawing, the wiring is formed as a wiring pattern including an external connection terminal, a wire bonding terminal, and a developed wiring.

  The external connection terminals are arranged in the semiconductor element mounting area, the wire bonding terminals are arranged outside the semiconductor element mounting area, and both terminals are connected by the developed wiring. The flip chip type substrate is different in that the flip chip terminal is formed in the semiconductor element mounting region, but can have the same configuration.

(Method for manufacturing a wiring board)
An example of a method for manufacturing a wiring board will be described with reference to FIG. An adhesive (not shown) is formed on the side of the insulating substrate on which the wiring is formed (FIG. 4A), and an opening is formed at a position where the external connection terminal is formed by a drill, a punch, or the like (FIG. 4B). )). At this point, the opening is a through hole. Next, the copper foil is bonded to the surface on which the adhesive is formed by pressing or laminating (FIG. 4C), and the copper foil is etched using an existing etching method to form a wiring. Finally, nickel and gold plating (not shown) is applied to the surface of the wiring (FIG. 4D).

(Manufacturing method of semiconductor package and PoP structure)
An example of a semiconductor package manufacturing method will be described with reference to FIG. A first wiring board and a second wiring board manufactured by the above method are prepared, and a semiconductor element with bumps is mounted on the second wiring board using an adhesive. At this time, the flip chip connection electrode of the semiconductor element and the flip chip terminal of the second wiring board are electrically flip chip connected via the bumps.

  Next, a semiconductor element in which the second wiring board is bonded to the first wiring board is mounted using an adhesive. Thereafter, the wire bonding connection electrode of the semiconductor element and the wire bonding terminal of the first wiring board are wire-bonded using a gold wire and electrically connected.

  Thereafter, the wiring board on which the semiconductor element is mounted is loaded into a sealing mold, resin-sealed by a trestle mold, and then solder balls are melted to the external connection terminals on the lower surface of the semiconductor package to complete the semiconductor package. Further, a plurality of semiconductor packages are stacked, the solder balls are melted, and the semiconductor packages are connected to complete the PoP structure.

Hereinafter, examples of the present invention will be described with reference to the drawings, but the present invention is not limited thereto.
Example 1
A semiconductor package and a PoP structure to which the present invention was applied were produced as follows.
(Manufacture of wiring boards)
First and second wiring boards were manufactured by the process shown in FIG. Specifically, polyimide adhesive: N4 (manufactured by Hitachi Chemical Co., Ltd., trade name) was applied to 0.075 mm thick polyimide film: Kapton 300EN (trade name, manufactured by Toray DuPont Co., Ltd.). Then, it dried and N4 was made into the B stage state (FIG. 4 (a)).

  Next, an opening (through hole) is formed at a position where an external connection terminal is formed using a drill having a diameter of 0.4 mm (FIG. 4B), and an electrolytic copper foil having a thickness of 18 μm: SLP is added to N4 of Kapton 300EN. The surface coated with was adhered by pressing (FIG. 4C).

  Thereafter, a photosensitive dry film resist: Photec HN340 (trade name, manufactured by Hitachi Chemical Co., Ltd.) was laminated, and the wiring pattern was exposed and developed to form an etching resist. Subsequently, the copper foil was etched, the resist was peeled off, and a wiring pattern was formed. Then, electroless nickel, palladium, and gold plating were sequentially applied to the surface of the wiring.

  As described above, the number of external connection terminals: 100 pins, external connection terminal pitch 0.8 mm, external connection terminal opening diameter 0.4 mm, substrate size 11.5 mm square wire bonding type first wiring board and number of external connection terminals A second flip-chip type wiring substrate having 100 pins, an external connection terminal pitch of 0.8 mm, an external connection terminal opening diameter of 0.4 mm, and a substrate size of 9.5 mm square was manufactured.

(Manufacturing method of semiconductor package and PoP structure)
A semiconductor package was manufactured by the process shown in FIG. The first wiring board and the second wiring board manufactured by the above-described method were prepared (FIG. 8A), and 100 pins each of the wire bonding connection electrode and the flip chip connection electrode with bumps were formed. A 10 mm square semiconductor element was mounted on a second wiring board using a flip chip adhesive film with a flip chip bonder (FIG. 8B). At this time, the flip chip connection electrode of the semiconductor element and the flip chip terminal of the second wiring board are electrically flip chip connected via the bumps.

  Next, a semiconductor element in which the second wiring board is bonded to the first wiring board is mounted using a die bond film: DF-402 (trade name, manufactured by Hitachi Chemical Co., Ltd.), and then a gold wire The electrode for wire bonding connection of the semiconductor element and the wire bonding terminal of the first wiring substrate were wire-bonded and electrically connected with each other (FIG. 8C).

  Next, the wiring board on which the semiconductor element is mounted is loaded into a sealing mold, and resin sealing is performed by a transfer molding method using a sealing resin: CEL-9200 (trade name, manufactured by Hitachi Chemical Co., Ltd.). (FIG. 8D), a 11.5 mm square semiconductor package was manufactured.

Thereafter, lead / tin eutectic solder balls having a diameter of 0.45 mm were melted on the external connection terminals on the lower surface of the semiconductor package by using an N ₂ reflow apparatus. Further, three semiconductor packages were stacked, solder balls were melted using an IR reflow apparatus, and each semiconductor package was electrically connected to produce the PoP structure shown in FIG.

(Example 2)
A wire bonding type wiring board having the number of external connection terminals: 100 pins, an external connection terminal pitch of 0.8 mm, an external connection terminal opening diameter of 0.4 mm, and a substrate size of 11.5 mm square was manufactured in the same manner as in Example 1.

  Also, a 10 mm square wafer level CSP in which 100 pins for wire bonding connection, the number of external connection terminals: 100 pins, an external connection terminal pitch of 0.8 mm, and an external connection terminal opening diameter of 0.4 mm are formed is manufactured separately. A wafer level CSP was mounted on a wiring board using a die bond film: DF-402 (trade name, manufactured by Hitachi Chemical Co., Ltd.).

  Thereafter, the wire bonding connection electrode of the wafer level CSP and the wire bonding terminal of the wiring substrate were wire-bonded using a gold wire, and were electrically connected. Next, the wiring board on which the wafer level CSP is mounted is loaded into a sealing mold, and resin sealing is performed by a transfer mold method using a sealing resin: CEL-9200 (trade name, manufactured by Hitachi Chemical Co., Ltd.). 11.5 mm square size semiconductor package was manufactured.

Next, a lead / tin eutectic solder ball having a diameter of 0.45 mm was melted on the external connection terminal on the lower surface of the semiconductor package using an N ₂ reflow apparatus. Further, three semiconductor packages were stacked, solder balls were melted using an IR reflow apparatus, and each semiconductor package was electrically connected to produce a PoP structure.

(Comparative Example 1)
(Manufacture of wiring boards)
Laminate with double-sided copper foil of thickness 0.2 mm: MCL-E-679F (manufactured by Hitachi Chemical Co., Ltd., product name) is drilled with holes for interlayer connection, electroless copper plating and electrolytic copper plating Sequential application was performed to form an interlayer connection.

  Next, photosensitive dry film resist: Photec HN340 (trade name, manufactured by Hitachi Chemical Co., Ltd.) is laminated on both sides, the wiring pattern is exposed and developed, an etching resist is formed, and then the copper foil is etched. Then, after the resist was peeled off and a wiring pattern was formed, a solder resist was formed on a necessary portion of the substrate surface.

  Thereafter, electroless nickel, palladium, and gold plating were sequentially applied to the surface of the wiring, and a device hole having a size of 10.5 mm square was formed by a router at a location where the semiconductor element of the wiring board was mounted.

  Finally, an adhesive tape is applied from the lower surface side of the wiring board, and the number of external connection terminals is 100 pins, the external connection terminal pitch is 0.5 mm, the external connection terminal opening diameter is 0.25 mm, and the board size is 14 mm square. Manufactured.

(Manufacturing method of semiconductor package and PoP structure)
A wiring board manufactured by the method described above is prepared, a 10 mm square semiconductor element on which 100 pins for wire bonding connection are formed is attached to an adhesive tape in a device hole portion, and a wire of the semiconductor element is used using a gold wire. The electrode for bonding connection and the wire bonding terminal of the wiring board were wire-bonded and electrically connected.

  Next, the wiring board on which the semiconductor element is mounted is loaded into a sealing mold, and resin sealing is performed by a transfer molding method using a sealing resin: CEL-9200 (trade name, manufactured by Hitachi Chemical Co., Ltd.). did.

Then, after peeling off the adhesive tape, a lead / tin eutectic solder ball having a diameter of 0.3 mm was melted to the external connection terminal on the lower surface of the semiconductor package by using an N ₂ reflow apparatus, and the 14 mm square size shown in FIG. A semiconductor package was manufactured.
Further, three semiconductor packages were stacked, solder balls were melted using an IR reflow apparatus, and each semiconductor package was electrically connected to produce the PoP structure shown in FIG.

(PoP structure connection reliability test)
Each of the 22 PoP structures manufactured in Examples 1 and 2 and Comparative Example 1 was mounted on a 0.8 mm thick motherboard, and a temperature cycle test was performed under the conditions of −55 ° C., 30 minutes to 125 ° C., 30 minutes. The connection reliability of the solder balls was examined every 200 cycles. The results are shown in Table 1.

  As shown in Table 1, from the results of the temperature cycle test, in the PoP structures of Examples 1 and 2 to which the present invention is applied, the external connection terminal diameter can be designed to 0.4 mm, and excellent solder It is clear that ball connection reliability can be obtained.

  On the other hand, in Comparative Example 1, since the external connection terminal diameter was as small as 0.25 mm, the solder ball was broken. Even when the same 10 mm square semiconductor element was mounted, the semiconductor package size in Example 1 and Example 2 was 11.5 mm square, but in Comparative Example 1, it was 14 mm square.

It is sectional drawing of the semiconductor package which becomes one Embodiment of this invention. It is sectional drawing of the semiconductor package which becomes one Embodiment of this invention. It is sectional drawing of the PoP structure which becomes one Embodiment of this invention. It is sectional drawing of the manufacturing process of the wiring board used for this invention. It is a top view of the wiring board used for this invention. It is sectional drawing of the semiconductor package of a prior art. It is sectional drawing of the PoP structure of a prior art. It is sectional drawing of the manufacturing process of the PoP structure which becomes one Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Insulation base material 3 Wiring 4 Solder resist 5 Sealing resin 6 Gold wire 7 Wire bonding terminal 8 External connection terminal 9 Bump

10 Solder balls 11 Openings 12 Adhesive (die bonding material)
13 Wiring Board 14 Insulating Base Material 16 Wire Bonding Terminal 17 Die Bond Film Adhesive Area (Wire Bond Type)
18 Semiconductor device mounting area (wire bond type)
19 External connection terminal

20 Development wiring 21 Flip chip terminal 23 Wiring board 24 First wiring board 25 Second wiring board 26 Wafer level CSP
27 Interlayer connection portion 28 Upper surface of semiconductor package 29 Lower surface of semiconductor package 30 Copper foil 31 Semiconductor package

Claims (6)

  A semiconductor package having external connection terminals on an upper surface and a lower surface, wherein at least one of the external connection terminals is formed in a semiconductor element mounting region on each surface.   An electrode for wire bonding connection and an electrode for flip chip connection are provided only on one surface of the semiconductor element, and the flip chip connection electrode is located inside the wire bonding connection electrode with respect to the outer edge of the semiconductor element. A second wiring board disposed on the surface having the electrodes of the semiconductor element and a first wiring board disposed on the opposite surface of the semiconductor element, wherein the first wiring board comprises: A wiring pattern having a wire bonding terminal and an external connection terminal as a part of the wiring, wherein the wire bonding terminal is provided on a wiring outside a region where the semiconductor element is mounted, and the external connection terminal is Provided in a region where a semiconductor element is mounted, the wire bonding terminal and the electrode for wire bonding connection are connected via a wire, and the first The wiring board includes a wiring pattern in which a flip chip terminal and an external connection terminal are part of the wiring, and the flip chip terminal is provided on the wiring inside the region where the semiconductor element is mounted, The semiconductor package according to claim 1, wherein a connection terminal is provided inside the flip chip terminal, and the flip chip connection electrode of the semiconductor element and the flip chip terminal are flip chip connected.   A package-on-package structure in which a plurality of semiconductor packages are stacked one above the other and are electrically connected, and external connection terminals provided on the lower surface of the upper semiconductor package and external devices provided on the upper surface of the lower semiconductor package A package-on-package structure in which connection terminals are electrically connected via solder, and at least one of the external connection terminals is formed in a semiconductor element mounting region on each of upper and lower surfaces.   The semiconductor package has an electrode for wire bonding connection and an electrode for flip chip connection only on one surface of the semiconductor element, and the electrode for flip chip connection is used for the wire bonding connection with respect to an outer edge of the semiconductor element. A second wiring board disposed on the surface having the electrodes of the semiconductor element and a first wiring board disposed on the opposite surface of the semiconductor element, and the first wiring board The wiring board includes a wiring pattern in which a wire bonding terminal and an external connection terminal are part of the wiring, and the wire bonding terminal is provided on a wiring outside an area where the semiconductor element is mounted, The connection terminal is provided in a region where the semiconductor element is mounted, and the wire bonding terminal and the wire bonding connection electrode are connected via a wire. The second wiring board includes a wiring pattern in which a flip chip terminal and an external connection terminal are part of the wiring, and the plip chip terminal is located inside a region where the semiconductor element is mounted. 4. The package-on-package structure according to claim 3, wherein the external connection terminal is provided inside the flip chip terminal, and the flip chip connection electrode of the semiconductor element and the flip chip terminal are flip chip connected. body.   5. The package-on-package structure according to claim 3, wherein no external connection terminal is provided on an upper surface of the uppermost semiconductor package among a plurality of semiconductor packages stacked vertically.   The package-on-package structure according to claim 3, 4 or 5, wherein a solder ball is provided on an external connection terminal of a lowermost semiconductor package among a plurality of semiconductor packages stacked vertically.

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