JP2009080126A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of surely performing a continuity test between all terminals en bloc and capable of rationally and effectively performing a continuity test at the inter-chip connection terminals in the case of a plurality of semiconductor chips mounted on one package without depending on the number of terminals of the semiconductor device. <P>SOLUTION: The semiconductor device is mounted with a first semiconductor chip and a second semiconductor chip which are provided with a plurality of inter-chip connecting terminals respectively in the interior of one package, wherein between each inter-chip terminal of the first semiconductor chip and the second semiconductor chip are connected through a wire one by one. A plurality of switch elements are provided between the adjacent wires on the first semiconductor chip side and the second semiconductor chip side alternately. A continuity test terminals provided with at an end of serial connection body of the switch elements and at the other end of the same, and a switch control terminal for controlling the plurality of all switch elements en bloc. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device in which one or more semiconductor chips are mounted in one package, and particularly relates to a technique for simply and reliably conducting a continuity test.

  Generally, a semiconductor device has a plurality of terminals for transferring signals between a system outside the semiconductor device and an internal circuit integrated in the semiconductor device. In recent years, in the test of semiconductor devices, the test time has greatly increased with the increase in the scale of internal circuits integrated on a semiconductor chip, and there is a concern about an increase in test cost. In order to suppress this test cost, it is important to discriminate defective products without spending as much time as possible. In order to suppress the increase in the test cost, various special test functions are incorporated in the semiconductor device, and a device for shortening the test time is required.

  The test items are roughly classified into a DC test for checking the power supply current and an AC test for checking the function and access time of the internal circuit system. Before performing these characteristic assurance tests, make sure that all the terminals of the semiconductor device under test are securely connected to the test device, and that the terminals inside the semiconductor device under test are connected inside the semiconductor device under test. Check that there is no disconnection failure or short-circuit failure with another terminal. On the premise of this confirmation, a DC test and an AC test are performed. Conventionally, the continuity test as described above is generally performed as follows.

  Each terminal is connected to a diffusion layer of the opposite type to the substrate, and is electrically connected to a diode. The current flowing by biasing the diode in the forward direction confirms the connection between the test apparatus and the semiconductor device to be measured and that there is no disconnection failure between the terminal to be tested and the internal circuit. At that time, confirm that there is no short-circuit failure between the terminal under test and the terminal adjacent to the terminal under test by fixing the terminal adjacent to the terminal under test at a potential opposite to that of the terminal under test. . This test is repeated for each terminal.

  In the past, the number of terminals was not large, so even when conducting a continuity test on all of these terminals, the time was relatively short. However, the number of terminals has increased with the recent increase in circuit systems integrated in semiconductor devices. Since the test time of the continuity test increases in proportion to the number of terminals, the test time and test cost cannot be ignored.

  FIG. 13 shows a general example of the semiconductor device described above. In FIG. 13, 001 is a semiconductor chip, 002 is an internal circuit integrated on the semiconductor chip 001, 003 to 008 are terminals for passing signals between the internal circuit 002 and an external system of the semiconductor chip 001, and 009 to 014 are The diodes are respectively connected to the terminals 003 to 008 and are formed in the forward direction with respect to the power supply potential (VDD) and in the reverse direction with respect to the ground potential (VSS).

  Here, an example of a continuity test method for the terminals 003 to 008 will be described. When conducting the continuity test of the terminal 003, a potential exceeding {power supply potential (VDD) + the threshold voltage Vt of the diode 009} is applied to the terminal under test 003, and the current flowing through the terminal under test 003 is measured simultaneously. If a certain amount of current is flowing, it is determined to be conductive. On the other hand, when the current value is 0, it means that the terminal under test 003 is not conducting. At that time, the same potential as the ground potential (VSS) is applied to the terminals 004 to 008 other than the terminal 003 to be tested. If an abnormal overcurrent flows through the terminal under test 003, it can be confirmed that a short circuit fault has occurred between the terminal under test 003 and the other terminals 004 to 008. The above procedure is similarly carried out for each of the terminals 003 to 008 one by one.

  In the related art having such a configuration, as a countermeasure against the above-described problems, a switch element that is conductive / non-conductive in accordance with a potential applied to each terminal is provided, and the switch elements are connected in series, and one end of the switch element is connected. Whether or not a constant power supply current flows when all the terminals under test are set to potentials at which the switch elements are made conductive by connecting to the power supply potential (VDD) and the other end to the ground potential (VSS). A method of performing a collective test of all the terminals under test by detecting the above has been proposed (see, for example, Patent Document 1).

  The above example is generally an example of a semiconductor device in which one semiconductor chip is mounted in one package. Hereinafter, a semiconductor device to which a technique for mounting a plurality of semiconductor chips in one package that has been attracting attention in recent years will be described.

  The set system was realized by connecting a plurality of semiconductor devices on a printed circuit board in order to configure it. However, the set system has been downsized every year, and has conventionally been configured with a plurality of semiconductor devices. System LSIs that implement a system on a single semiconductor chip are now mainstream. Such a system LSI often requires a DRAM, a FLASH memory, or the like, and as a result, it is required to incorporate a memory device into the system LSI and mount it as a single chip. However, when these memory devices are mixedly mounted, it becomes necessary to add a memory process to a system LSI that can be conventionally manufactured by a pure CMOS process. As a result, the yield is lowered, the limit of miniaturization, the manufacturing period is increased. New issues such as an increase in

  Under such circumstances, attention has been paid to a technique for realizing a system LSI by sealing a plurality of semiconductor chips having different diffusion processes in one package. Although the form is various, it can be roughly divided into three types. The first is a method in which the surface of a chip to be bonded (hereinafter referred to as a child chip) is connected to the surface of a base semiconductor chip (hereinafter referred to as a parent chip) using bumps. The second is a method in which the back surface of the child chip is bonded onto the parent chip, and the respective chips are directly connected via wires. The third method is a method in which a plurality of chips are two-dimensionally arranged in a package, and a portion requiring connection between the chips is directly connected by a wire.

  FIG. 14 shows the second example in the case where a plurality of semiconductor chips are mounted in one package described above. 101 is a base semiconductor chip (hereinafter referred to as a parent chip), 102 is an internal circuit integrated in the parent chip 101, and 103 to 108 are for transferring signals between the internal circuit 102 and an external system of the parent chip 101. , 109 to 114 are diodes connected to the terminals 103 to 108, 115 is a semiconductor chip (hereinafter referred to as a child chip) stacked on the parent chip 101, 116 is an internal circuit integrated on the child chip 115, 117 to Reference numeral 120 denotes an inter-chip connection terminal for passing a signal between the internal circuit 116 and the internal circuit 102 on the parent chip 101. Reference numerals 121 to 124 denote diodes connected to the inter-chip connection terminals 117 to 120. 125 to 128. Is used to exchange signals between the internal circuit 102 on the parent chip 101 and the internal circuit 116 on the child chip 115. Inter-chip connection terminals, 129-132 is diode connected inter-chip connection terminals 125 to 128, 133-136 is a wire connecting inter-chip connection terminals 117 to 120 and inter-chip connection terminals 125 to 128.

  The continuity test method for the terminals 103 to 108 is the same as the continuity test method for a semiconductor device in which one semiconductor chip is mounted in one package described above. Here, a conventional method will be described as a continuity test method for the inter-chip connection terminals 117 to 120 and the inter-chip connection terminals 125 to 128.

  By controlling and observing the terminals 103 to 108 on the parent chip 101 from outside the package, a function test of the internal circuit 116 of the child chip 115 is performed via the internal circuit 102 of the parent chip 101, thereby indirectly between the chips. Conduction tests of the connection terminals 117 to 120 and 125 to 128 and the wires 133 to 136 are performed. However, in order to comprehensively test for disconnection faults and short-circuit faults between inter-chip connection terminals, it is necessary to consider the combination of inter-chip connection terminal states at the time of the functional test. However, there is a problem that it takes a lot of man-hours.

Therefore, a rational and effective test method is required as a continuity test method for the inter-chip connection terminal portion. In the above example, a semiconductor device having a configuration in which two semiconductor chips are stacked in one package and the two semiconductor chips are directly connected by a wire has been described. However, when a plurality of chips are mounted, Alternatively, a plurality of semiconductor chips are mounted in one package regardless of whether the semiconductor chip is mounted in a stacked / two-dimensional layout, or the connection form of the plurality of semiconductor chips is a wire / bump. The same problems as described above apply to all semiconductor devices having a configuration in which the components are directly connected to each other. This will be described in detail below.
JP-A-4-152277 (page 3-5, FIGS. 1 and 2)

  In order to conduct a continuity test of terminals that exchange signals with the outside of the semiconductor device, it is necessary to perform a test for each terminal in the conventional method. Therefore, the continuity is proportional to the number of terminals that are increasing year by year. There was a problem that the test time required for the test increased and the test cost increased.

  In this problem, the invention described in Patent Document 1 has been made as a configuration of a semiconductor device for performing a continuity test for all terminals at once. However, a voltage is applied to a plurality of terminals under test to conduct continuity. Even if a part of the terminal under test is disconnected from the test equipment for inspection, voltage is supplied from the short-circuit fault to the terminal under test if there is a short-circuit fault between adjacent terminals. There was a problem that it was erroneously determined to be normal. Further, in order to perform the above test, there is a problem that the continuity test cannot be performed unless a relatively high-grade test apparatus that measures current while applying a voltage to a terminal under test.

  In addition, in a semiconductor device in which a plurality of semiconductor chips are mounted in one package and the semiconductor chips are directly connected inside the package, the continuity test of the inter-chip connection terminals, that is, the disconnection failure and the short-circuit failure are covered. In order to conduct a test, it is necessary to conduct a function test of the semiconductor chip via the location under test and to consider the combination of the state of the inter-chip connection terminals during the function test. There is a problem that it takes a lot of man-hours to create a test pattern. That is, there is a fundamental problem that there is no rational and effective test method as a continuity test method for the inter-chip connection terminal portion.

  The present invention solves such problems in the prior art, and can reliably execute a continuity test for all the terminals collectively without depending on the number of terminals of the semiconductor device to be measured. Provided is a semiconductor device capable of significantly reducing the time required for testing, and also provides a semiconductor device capable of rationally and effectively conducting a continuity test at inter-chip connection terminals when a plurality of semiconductor chips are mounted in one package. The purpose is to do.

  In order to solve the above problems, the present invention takes the following measures.

  As a first solution, a semiconductor device according to the present invention (Claim 1) includes a first semiconductor chip and a second semiconductor chip each having a plurality of inter-chip connection terminals in one package, A semiconductor device in which each of the inter-chip connection terminals on the first semiconductor chip and each of the inter-chip connection terminals on the second semiconductor chip are connected one by one via a wire, and are adjacent to each other. A switching element interposed between the wires in an alternating state on the first semiconductor chip side and the second semiconductor chip side, one end of a series connection body of the series of the switching elements, and others A continuity test terminal connected to each end; and a switch control terminal for collectively controlling the plurality of switch elements.

  Here, the first semiconductor chip may be called a parent chip, and the second semiconductor chip may be called a child chip. A plurality of switch elements are connected in series in series, but adjacent switch elements are alternately arranged on the first semiconductor chip side and the second semiconductor chip side. That is, it is a series of serially connected bodies of wire-switch element-wire-switch element... In the first solving means, the resistive element is included in each series connection body in order to prevent the excessive current from flowing if the resistive element is not provided. In the first solution, the resistance element is not particularly required because the wire is a resistance element.

  The effect | action by this structure is as follows. All switch elements are conducted during a continuity test, and the value of a current flowing between both continuity test terminals is measured by applying a potential difference between the continuity test terminals at both ends. In a normal state in which there is no failure in all the inter-chip connection terminals, a current flows between both continuity test terminals. However, if the inter-chip connection terminal on the first semiconductor chip and the inter-chip connection on the second semiconductor chip are connected. When a disconnection failure has occurred in the wire connecting the terminals, the measured current value is 0 because both continuity test terminals are in a high impedance state. Therefore, it is possible to detect whether or not a disconnection failure has occurred based on the measured current value. That is, it is possible to collectively detect a disconnection failure of wires connected between chips, which conventionally has not had an effective test method.

  As a second solution, a semiconductor device according to the present invention (Claim 2) is the first solution, wherein a resistance element is connected in series to each of the plurality of switch elements.

  The effect | action by this structure is as follows. All switch elements are conducted during a continuity test, and the value of a current flowing between both continuity test terminals is measured by applying a potential difference between the continuity test terminals at both ends. In a normal state in which all the inter-chip connection terminals are free of failure, the value of the flowing current is (potential difference) / (total resistance value of all resistance elements). If the inter-chip connection terminals on the first semiconductor chip are When a disconnection failure has occurred in the wire connecting the inter-chip connection terminal on the second semiconductor chip, the measured current value is 0 because both continuity test terminals are in a high impedance state. Therefore, it is possible to detect whether or not a disconnection failure has occurred based on the measured current value. In addition, if a short-circuit failure occurs between adjacent inter-chip connection terminals, the resistance elements connected to both ends of the short-circuit failure location are bypassed, and the measured current value increases. The difference in current value can also detect that a short-circuit failure has occurred between adjacent inter-chip connection terminals.

  As a third solution, a semiconductor device according to the present invention (Claim 3) is obtained by weighting individual resistance values of the plurality of resistance elements in the second solution. According to this, since the resistance value is weighted, the measured current value shows a constant and unique value according to the short-circuit location, and the short-circuit failure location can also be specified.

  As a fourth solution, a semiconductor device according to the present invention (Claim 4) includes a first semiconductor chip and a second semiconductor chip each having a plurality of inter-chip connection terminals in one package. A semiconductor device in which each of the inter-chip connection terminals on the first semiconductor chip and each of the inter-chip connection terminals on the second semiconductor chip are connected one by one through the wire, A switch element interposed between each of the plurality of inter-chip connection terminals and the continuity test terminal on the semiconductor chip side, and switch control means for selectively on / off controlling the plurality of switch elements; A diode connected in a forward direction with respect to a power supply potential or in a reverse direction with respect to a ground potential at a plurality of the inter-chip connection terminals on the second semiconductor chip side; and the first semiconductor Tsu comprises a line switching device interposed in a plurality of said lines of inter-chip connection terminal on the side of the flop, and said line terminal continuity test connected to the on / off control terminal of the switch element.

  The effect | action by this structure is as follows. At the time of the continuity test, the line switch element is turned off by the continuity test terminal, and only one switch element is turned on by the switch control means, and exceeds {power supply potential (VDD) + diode threshold voltage Vt} at the continuity test terminal. An electric potential is applied and the flowing current value is measured. In a normal state in which there is no failure in the corresponding inter-chip connection terminal, a current flows. However, if the inter-chip connection terminal on the first semiconductor chip is connected to the inter-chip connection terminal on the second semiconductor chip, When a disconnection failure has occurred, the measured current value is 0 because the connection terminals between both chips are in a high impedance state. By sequentially performing the above measurement on all the inter-chip connection terminals, it is possible to detect whether or not a disconnection failure has occurred for each of the wires connecting the inter-chip connection terminals. Further, since the second semiconductor chip is concentrated on the first semiconductor chip side, no design change such as addition of a switch element or a resistance element for the continuity test is required for the second semiconductor chip. This is particularly effective when using semiconductor chips obtained from other companies.

  Here, when the switch element is composed of an N-type MOS transistor, the potential applied to the terminal for measuring the current during the continuity test is {power supply potential (VDD) + diode threshold voltage Vt}. Since the gate potential of the MOS transistor is VDD, a potential higher than VDD cannot be propagated, and a potential difference for flowing a forward current to both ends of the diode cannot be obtained. Accordingly, a power supply potential (VDD1) to be supplied to the first semiconductor chip and a power supply potential (VDD2) to be supplied to the second semiconductor chip are separately supplied so that VDD1> VDD2 to measure current during a continuity test. On the other hand, a continuity test can be performed because a forward current can be passed through the diode by applying a potential equal to or higher than VDD1 without applying a potential higher than VDD1 (Claim 5). .

  Further, when the switch element is composed of a P-type MOS transistor, the first semiconductor is used even when the continuity test is performed by applying a potential equal to or lower than VSS to the terminal for measuring the current during the continuity test. The ground potential (VSS1) to be supplied to the chip and the ground potential (VSS2) to be supplied to the second semiconductor chip are separately supplied, and VSS1 <VSS2 is set to VSS1 <VSS2 or less with respect to a terminal for measuring current at the continuity test. Even if no potential is applied, that is, by applying the same potential as VSS1, a forward current can be passed through the diode, so that a continuity test can be performed.

  As a fifth solution, a semiconductor device according to the present invention (Claim 7) includes a first semiconductor chip and a second semiconductor chip each having a plurality of inter-chip connection terminals in one package. A semiconductor device in which each of the inter-chip connection terminals on the first semiconductor chip and each of the inter-chip connection terminals on the second semiconductor chip are connected one by one via a wire, and are adjacent to each other. A series connection body of a switch element and a resistance element, interposed between the wires in an alternating state between the first semiconductor chip side and the second semiconductor chip side, and a series of the series A power supply potential side switch element for connecting one end of the connection body to the power supply potential; a ground potential side switch element for connecting the other end of the series connection body to the ground potential; Sui A switch control terminal that collectively controls the entire element, a resistance dividing resistance element connected in series for resistance division with respect to a resistance element group in the series connection body, the series connection body and the resistance division A logic element for detecting that the potential at the resistance dividing point with the resistance element exceeds a predetermined value, and a continuity test terminal connected to the output side of the logic element. In this case, a series of serially connected bodies of wire- (switch element + resistance element) -wire- (switch element + resistance element)...

  The effect | action by this structure is as follows. During the continuity test, all switch elements are turned on and the output potential of the logic element is measured. When all the inter-chip connection terminals are in a normal state with no failure, the potential divided by the series connected body and the resistance dividing resistance element is within a predetermined range, and the logic element outputs a predetermined value. . On the other hand, when a short-circuit failure occurs between adjacent inter-chip connection terminals, the resistive element connected between the short-circuit failure inter-chip connection terminals is bypassed, so the divided potential is Outside the predetermined range, the logic element outputs the inverted value of the normal state. That is, it is possible to detect whether or not a short-circuit failure has occurred between adjacent inter-chip connection terminals based on the output value of the logic element.

  As a sixth solution, a semiconductor device according to the present invention (Claim 8) includes a first semiconductor chip and a second semiconductor chip each having a plurality of inter-chip connection terminals in one package, A semiconductor device in which each of the inter-chip connection terminals on the first semiconductor chip and each of the inter-chip connection terminals on the second semiconductor chip are connected one by one via a wire, and are adjacent to each other. A series connection body of a switch element and a resistance element, interposed between the wires in an alternating state between the first semiconductor chip side and the second semiconductor chip side, and a series of the series A power supply potential side switch element for connecting one end of the connection body to the power supply potential; a ground potential side switch element for connecting the other end of the series connection body to the ground potential; Sui A switch control terminal that collectively controls the entire element, a resistance dividing resistance element connected in series for resistance division with respect to a resistance element group in the series connection body, the series connection body and the resistance division A logic element for detecting that a potential at a resistance dividing point with the resistance element is lower than a predetermined value, and a continuity test terminal connected to the output side of the logic element. The difference from the fifth solving means described above is the difference between being above or below a predetermined value.

  The effect | action by this structure is as follows. When a disconnection failure occurs in the wire connecting the inter-chip connection terminal and the second inter-chip connection terminal on the first semiconductor chip, the divided potential is out of the predetermined range, and the logic element is in a normal state. The inverted value of is output. That is, it is possible to detect whether or not a disconnection failure has occurred based on the output value of the logic element.

  As a seventh solution, a semiconductor device according to the present invention (Claim 9) includes a first semiconductor chip and a second semiconductor chip each having a plurality of inter-chip connection terminals in one package. A semiconductor device in which each of the inter-chip connection terminals on the first semiconductor chip and each of the inter-chip connection terminals on the second semiconductor chip are connected one by one via a wire, and are adjacent to each other. A series connection body of a switch element and a resistance element, interposed between the wires in an alternating state between the first semiconductor chip side and the second semiconductor chip side, and a series of the series A power supply potential side switch element for connecting one end of the connection body to the power supply potential; a ground potential side switch element for connecting the other end of the series connection body to the ground potential; Sui A switch control terminal that collectively controls the entire element, a resistance dividing resistance element connected in series for resistance division with respect to a resistance element group in the series connection body, the series connection body and the resistance division A first logic element that detects that a potential at a resistance dividing point with the resistive element exceeds a predetermined value, and a potential at a resistance dividing point between the series connected body and the resistance dividing resistive element has a predetermined value. A second logic element for detecting the lowering and a continuity test terminal connected to the output side of each of the first and second logic elements. This corresponds to a combination of the fifth solving means and the sixth solving means.

  The effect | action by this structure is as follows. In the continuity test, all the switch elements are turned on, and the output potentials of the first and second logic elements are measured. When all the inter-chip connection terminals are in a normal state with no failure, the potential divided by the series connected body and the resistance dividing resistance element is within a predetermined range, and the first and second logic elements are Each outputs a predetermined value. On the other hand, when a short-circuit failure has occurred between adjacent terminals, the resistive element connected between the terminals of the short-circuit failure is bypassed, so that the divided potential is outside the predetermined range, The logic element 1 outputs the inverted value of the normal state. That is, it is possible to detect whether or not a short-circuit failure has occurred between adjacent terminals due to inversion of the output value of the first logic element. In addition, when a disconnection failure occurs in the wire connecting the inter-chip connection terminal and the second inter-chip connection terminal on the first semiconductor chip, the divided potential is out of a predetermined range, and the second The logic element outputs the inverted value of the normal state. That is, it is possible to detect whether or not a disconnection failure has occurred due to the inversion of the output value of the second logic element. Overall, it is possible to detect both short-circuit faults and disconnection faults.

  In each of the above solutions, the switching element or the resistance element can be constituted by an N-type, P-type, or N-type and P-type MOS transistor, respectively, and the configuration can be simplified.

  According to the present invention, it is possible to collectively detect a disconnection failure of wires connected between chips, which has not been available in the prior art.

  Further, according to the present invention, in addition to the effect of detecting the disconnection failure of the inter-chip connection wires in a lump, by determining the difference in the current value, the inter-chip connection terminals between which there has been no effective test method conventionally The effect of being able to detect even a short-circuit failure at once is obtained.

  In addition, according to the present invention, an effect of identifying a short-circuit fault location with respect to a short-circuit fault between inter-chip connection terminals is obtained.

  Further, according to the present invention, in addition to the effect of detecting the disconnection failure of the wire connected between the chips, the second semiconductor chip does not require any design change such as addition of a switch element or a resistance element for the continuity test. Therefore, it is effective for obtaining from other companies (claim 4).

  Further, according to the present invention, it is possible to detect a short circuit failure between the inter-chip connection terminals at once by inverting the output value of the logic element. Furthermore, since the test can be carried out only by measuring the voltage level, a comparatively high-grade test device for measuring current while applying a voltage as in the prior art becomes unnecessary, and the effect of simplifying the test device can be obtained. 7, 8). Moreover, both a short circuit failure and a disconnection failure can be detected.

  Embodiments of a semiconductor device according to the present invention will be described below with reference to the drawings.

(Reference Example 1)
FIG. 1 is a block circuit diagram showing a configuration of a semiconductor device in Reference Example 1 of the present invention. In FIG. 1, 001 is a semiconductor chip, 002 is an internal circuit integrated on the semiconductor chip 001, 003 to 008 are terminals for passing signals between the internal circuit 002 and an external system of the semiconductor chip 001, and 009 to 014 are The diodes are respectively connected to the terminals 003 to 008 and are formed in the forward direction with respect to the power supply potential (VDD) and in the reverse direction with respect to the ground potential (VSS). 015 and 016 are continuity test terminals, and 050 is a switch control terminal, which are used when conducting continuity tests on the terminals 003 to 008 collectively. Reference numerals 017 to 021 and 022 to 026 denote a switch element and a resistance element connected in series between terminals 003 to 008. The switch elements 017 to 021 are turned on when a power supply potential (VDD) is applied to the switch control terminal 050. When ground potential (VSS) is applied, it becomes non-conductive. A series connection body is formed by connecting one switch element and one resistance element in series. The whole of the plurality of series connection bodies is a series of series connection bodies.

  The operation of the semiconductor device of this reference example configured as described above will be described below. When the power supply potential (VDD) is applied to the continuity test terminal 015 and the switch control terminal 050, and the ground potential (VSS) is applied to the continuity test terminal 016, the switch elements 017 to 021 become conductive. When the terminals 003 to 008 are in a normal state with no failure, the current flowing between the VDD continuity test terminal 015 and the VSS continuity test terminal 016 is {(VDD−VSS) / (resistance elements 022 to 026). Sum of resistance values)}. However, if a short-circuit failure occurs between the terminal 005 and the terminal 006, {(VDD−VSS) / (sum of resistance values of resistance elements 022, 023, 025, 026)} Terminal short-circuit faults can be tested at once with a single measurement.

(Reference Example 2)
FIG. 2 is a block circuit diagram showing a configuration of a semiconductor device in Reference Example 2 of the present invention. In FIG. 2, the same reference numerals as those in FIG. 1 of Reference Example 1 indicate the same components, and thus detailed description thereof is omitted. The difference from the reference example 1 is resistance elements 022a to 026a, and each resistance value is weighted twice.

  The operation of the semiconductor device of this reference example configured as described above will be described below. The basic operation is the same as in the case of Reference Example 1, and short-circuit faults of a plurality of terminals under test can be collectively tested with a single measurement. Furthermore, each of the resistance elements 022a to 026a has a resistance value that is twice as large, so that the measured current value is constant and shows a unique value depending on the short circuit location. As a result, it is possible to specify a short-circuit fault location.

  Note that the weighting of the resistance values of the plurality of resistance elements is not necessarily doubled, and k may be an arbitrary real number and may be multiplied by k. Furthermore, it is not necessary to use weighting having regularity of constant multiples such as k times, and it is only necessary that the resistance values of the plurality of resistance elements are different from each other.

(Reference Example 3)
FIG. 3 is a block circuit diagram showing a configuration of a semiconductor device according to Reference Example 3 of the present invention. In FIG. 3, the same reference numerals as those in FIG. 1 of Reference Example 1 indicate the same components, and thus detailed description thereof is omitted. The difference from the reference example 1 is a power supply potential side switch element 027, a ground potential side switch element 028, a resistance dividing resistance element 029, and a logic element 030. A power supply potential side switch element 027 is connected between the terminal 003 and the power supply potential (VDD). Between the terminal 008 and the ground potential (VSS), a series connection body of a ground potential side switch element 028 and a resistance dividing resistance element 029 is connected. Similarly to the switch elements 017 to 021, the power supply potential side switch element 027 and the ground potential side switch element 028 are turned on when the power supply potential (VDD) is applied to the switch control terminal 050 and are turned off when the ground potential (VSS) is applied. It becomes. The logic element 030 is interposed between the continuity test terminal 016 and the ground potential side switch element 028. The total resistance value of the resistance elements 022 to 026 connected in series between the input portion of the logic element 030 and the power supply potential (VDD) and the series connection between the input portion of the logic element 030 and the ground potential (VSS). The potential divided by the resistance value of the resistance dividing resistance element 029 is set to be lower than the input threshold level of the logic element 030.

  The operation of the semiconductor device of this reference example configured as described above will be described below. The basic operation is the same as in Reference Example 1, and short-circuit faults at a plurality of terminals can be collectively tested with a single measurement. Further, when a power supply potential (VDD) is applied to the switch control terminal 050, the switch elements 017 to 021, 027, and 028 are turned on. When the terminals 003 to 008 are in a normal state with no failure, the divided potential is lower than the threshold value of the logic element 030, so that the logic element 030 outputs a predetermined value. On the other hand, when a short-circuit failure has occurred between the terminals 005 to 006, the resistance element 024 connected between the terminals 005 to 006 is bypassed, so that the divided potential is greater than the threshold value of the logic element 030. And the output of the logic element 030 outputs the inverted value of the normal state. Therefore, it is possible to test a short circuit failure of a plurality of terminals at once by a single measurement based on the output value of the logic element 030. Furthermore, since the detection is performed by logic inversion, a relatively high-grade test apparatus that measures current while applying a voltage is not required, and the test apparatus can be simplified.

  Note that the connection point of the logic element 030 may be changed between the ground potential side switching element 028 and the resistance dividing resistance element 029 instead of P1. Further, instead of connecting the resistance dividing resistance element 029 to the ground potential side switching element 028, a resistance dividing resistance element is connected in series with the power supply potential side switching element 027 between the power supply potential (VDD) and the point Q1. A logic element and a continuity test terminal may be connected to the point Q1. This concept of deformation can also be applied to the following embodiments.

(Embodiment 1)
FIG. 4 is a block circuit diagram showing a configuration of the semiconductor device according to the first embodiment (corresponding to claim 1) of the present invention. In FIG. 4, 101 is a base semiconductor chip (hereinafter referred to as a parent chip), 102 is an internal circuit integrated in the parent chip 101, and 103 to 108 are signals of signals between the internal circuit 102 and an external system of the parent chip 101. Terminals for delivery, 109 to 114 are diodes connected to the terminals 103 to 108, 115 is a semiconductor chip (hereinafter referred to as a child chip) stacked on the parent chip 101, and 116 is an internal integrated on the child chip 115. Circuits 117 to 120 are inter-chip connection terminals for passing signals between the internal circuit 116 and the internal circuit 102 on the parent chip 101, and 121 to 124 are diodes connected to the inter-chip connection terminals 117 to 120. , 125 to 128 receive signals between the internal circuit 102 on the parent chip 101 and the internal circuit 116 on the child chip 115. Inter-chip connection terminals for performing the operation, 129 to 132 are diodes connected to the inter-chip connection terminals 125 to 128, and 133 to 136 are wires connecting the inter-chip connection terminals 117 to 120 and the inter-chip connection terminals 125 to 128. It is. Reference numerals 137 and 138 denote continuity test terminals, and 150 denotes a switch control terminal, which is used when conducting continuity tests on the wires 133 to 136 at once. Reference numeral 139 denotes a switch element connected in series between the inter-chip connection terminals 117 to 118, 140 denotes a switch element connected in series between the inter-chip connection terminals 126 to 127, and 141 denotes the inter-chip connection terminals 119 to 120. The switch elements are connected in series between them, and become conductive when a power supply potential (VDD) is applied to the continuity test terminal 150 and become nonconductive when a ground potential (VSS) is applied.

  The operation of the semiconductor device of the present embodiment configured as described above will be described below. When the power supply potential (VDD) is applied to the continuity test terminal 137 and the switch control terminal 150 and the ground potential (VSS) is applied to the continuity test terminal 138, the switch elements 139 to 141 are conducted. When the wires 133 to 136 are in a normal state with no failure, a current flows between the continuity test terminal 137 and the continuity test terminal 138. However, even at one location, a disconnection failure occurs in the inter-chip connection terminal between the parent and child chips. When this occurs, current does not flow, so that a disconnection failure of wires connecting a plurality of inter-chip connection terminals can be collectively tested with a single measurement.

(Embodiment 2)
FIG. 5 is a block circuit diagram showing a configuration of the semiconductor device according to the second embodiment (corresponding to claim 2) of the present invention. In FIG. 5, the same reference numerals as those in FIG. 4 of the first embodiment indicate the same components, and detailed description thereof will be omitted. The difference from the first embodiment is that the resistance element 142 connected in series to the switch element 139 between the inter-chip connection terminals 117 to 118 and the switch element 140 in series between the inter-chip connection terminals 126 to 127. They are the connected resistance element 143 and the resistance element 144 connected in series with the switch element 141 between the inter-chip connection terminals 119 to 120.

  The operation of the semiconductor device of the present embodiment configured as described above will be described below. The basic operation is the same as that of the first embodiment. When a power supply potential (VDD) is applied to the continuity test terminal 137 and the switch control terminal 150, and a ground potential (VSS) is applied to the continuity test terminal 138. The switch elements 139 to 141 are conducted. When the wires under test 133 to 136 are in a normal state with no failure, the current flowing between the continuity test terminal 137 and the continuity test terminal 138 is {(VDD−VSS) / (resistance value of the resistance elements 142 to 144). )}. However, if a disconnection failure occurs in the wire connecting the inter-chip connection terminals between the parent and child chips even at one location, the current stops flowing, so the wires connecting the plurality of inter-chip connection terminals between the test pins It is possible to test for disconnection faults at once with a single measurement. In addition, if a short-circuit failure occurs between adjacent inter-chip connection terminals, the resistance elements connected to both ends of the short-circuit failure location are bypassed, and the measured current value increases. The fact that a short-circuit failure has occurred between adjacent chip connection terminals due to the difference in current value can also be tested in a batch with a single measurement.

(Embodiment 3)
FIG. 6 is a block circuit diagram showing a configuration of the semiconductor device according to the third embodiment (corresponding to claim 3) of the present invention. In FIG. 6, since the same reference numerals as those in FIG. 5 of the second embodiment indicate the same components, detailed description thereof will be omitted. The difference from the second embodiment is resistance elements 142a to 144a, and each resistance value is weighted twice.

  The operation of the semiconductor device of the present embodiment configured as described above will be described below. The basic operation is the same as in the case of the second embodiment, and it is possible to collectively detect a disconnection failure of a wire connecting a plurality of inter-chip connection terminals and a short-circuit failure between adjacent inter-chip connection terminals in one measurement. Can be tested. Furthermore, each of the resistance elements 142a to 144a has a resistance value that is twice as large, so that the measured current value is constant and shows a unique value depending on the short circuit location. As a result, it is possible to specify a short-circuit fault location.

  Note that the weighting of the resistance values of the plurality of resistance elements is not necessarily doubled, and k may be an arbitrary real number and may be multiplied by k. Furthermore, it is not necessary to use weighting having regularity of constant multiples such as k times, and it is only necessary that the resistance values of the plurality of resistance elements are different from each other.

(Reference Example 4)
FIG. 7 is a block circuit diagram showing a configuration of a semiconductor device in Reference Example 4 of the present invention. In FIG. 7, the same reference numerals as those in FIG. 5 of the second embodiment indicate the same components, and detailed description thereof will be omitted. The difference from the second embodiment is the switch elements 139b and 141b and the resistance elements 142b and 144b. The series connection body of the switch element 139b and the resistance element 142b and the series connection body of the switch element 141b and the resistance element 144b are respectively the series connection body of the switch element 139 and the resistance element 142 and the switch element 141 and the resistance element in FIG. This corresponds to the arrangement position of the serially connected body with 144 shifted from the child chip 115 to the parent chip 101.

  The operation of the semiconductor device of this reference example configured as described above will be described below. When the power supply potential (VDD) is applied to the continuity test terminal 137 and the switch control terminal 150 and the ground potential (VSS) is applied to the continuity test terminal 138, the switch elements 139 to 141 are conducted. When the wires 133 to 136 are in a normal state with no failure, the current flowing between the continuity test terminal 137 and the continuity test terminal 138 is {(VDD−VSS) / (resistance value of the resistance elements 142a, 143, and 144a). )}. However, if a short-circuit failure occurs between adjacent inter-chip connection terminals, the resistance elements connected to both ends of the short-circuit failure location are bypassed, and the measured current value increases. The fact that a short-circuit failure has occurred between adjacent chip connection terminals due to the difference in current value can also be tested in a batch with a single measurement. Furthermore, since it is concentrated on the parent chip 101 side, the child chip 115 does not require any design change such as addition of a switch element or a resistance element for the continuity test, and the child chip 115 was obtained from another company. A semiconductor chip can be used.

(Embodiment 4)
FIG. 8 is a block circuit diagram showing a configuration of the semiconductor device according to the fourth embodiment (corresponding to claim 4) of the present invention. In FIG. 8, since the same reference numerals as those in FIG. 4 of the first embodiment indicate the same components, detailed description thereof will be omitted. The difference from the first embodiment is the switch control means 200, the switch elements 201 to 204, the line switch elements 205 to 208, and the continuity test terminals 137a and 138a. The switch elements 201 to 204 are connected in series between the inter-chip connection terminals 125 to 128 and the continuity test terminal 137a, respectively. The switch control means 200 controls the switch elements 201 to 204 to be conducted one by one during the continuity test. The line switch elements 205 to 208 are connected in series between the inter-chip connection terminals 125 to 128 and the diodes 129 to 132, respectively.

  The operation of the semiconductor device of the present embodiment configured as described above will be described below. In advance, the continuity test terminal 138a blocks the current path to the diodes 129 to 132 by setting the line switch elements 205 to 208 in a non-conduction state. When conducting the continuity test of the wire 133, the switch control means 200 controls only the switch 201 to be in a conductive state, and switches 202 to 204 are controlled to be in a non-conductive state, so that the power supply potential (VDD) + diode is applied to the continuity test terminal 137a. A potential exceeding the threshold voltage Vt} of 121 is applied, and at the same time, a current flowing through the continuity test terminal 137a is measured. Here, when the wire 133 is in a normal state with no failure, a forward current with respect to the power supply potential (VDD) flows through the diode 121, so that it can be determined that the wire 133 is conductive. On the other hand, when the current value is 0, it is possible to detect that the wire 133 is broken. The disconnection failure of all the wires 133 to 136 can be detected by carrying out the above procedure for all the inter-chip connection terminals 125 to 128 one by one. Furthermore, since it is concentrated on the parent chip 101 side, the child chip 115 does not require any design change such as addition of a switch element or a resistance element for the continuity test, and the child chip 115 was obtained from another company. A semiconductor chip can be used.

(Embodiment 5)
FIG. 9 is a block circuit diagram showing a configuration of the semiconductor device according to the fifth embodiment (corresponding to claim 7) of the present invention. In FIG. 9, the same reference numerals as those in FIG. 4 of the first embodiment indicate the same components, and detailed description thereof will be omitted. The difference from the first embodiment is a power supply potential side switch element 145, a ground potential side switch element 146, a resistance dividing resistance element 147, and a logic element 148. A power supply potential side switch element 145 is connected between the inter-chip connection terminal 125 and the power supply potential (VDD). A series connection body of a ground potential side switch element 146 and a resistance dividing resistance element 147 is connected between the inter-chip connection terminal 128 and the ground potential (VSS). Similarly to the switch elements 139 to 141, the power supply potential side switch element 145 and the ground potential side switch element 146 are turned on when the power supply potential (VDD) is applied to the switch control terminal 150, and are turned off when the ground potential (VSS) is applied. It becomes. The logic element 148 is interposed between the continuity test terminal 138 and the ground potential side switch element 146. The total resistance value of the resistance elements 142 to 144 connected in series between the input part of the logic element 148 and the power supply potential (VDD) and the series connection between the input part of the logic element 148 and the ground potential (VSS). The potential divided by the resistance value of the resistance dividing resistance element 147 is set to be lower than the input threshold level of the logic element 148.

  The operation of the semiconductor device of the present embodiment configured as described above will be described below. The basic operation is the same as that in the first embodiment, and the power supply potential (VDD) is applied to the switch control terminal 150 and the switch elements 139 to 141, 145, and 146 are turned on. In the normal state where no voltage is present, the divided potential is lower than the threshold value of the logic element 148, so that the logic element 148 outputs a predetermined value. On the other hand, when a short circuit failure occurs between the wires 135 to 136, the resistive element 144 connected between the inter-chip connection terminals 119 to 120 is bypassed, so that the divided potential is the logic element 148. The output of the logic element 148 outputs the inverted value of the normal state. Therefore, a short circuit failure of a plurality of inter-chip connection terminals can be collectively tested by one measurement based on the output value of the logic element 148. Furthermore, since the detection is performed by logic inversion, a relatively high-grade test apparatus that measures current while applying a voltage is not required, and the test apparatus can be simplified.

(Embodiment 6)
FIG. 10 is a block circuit diagram showing a configuration of the semiconductor device according to the sixth embodiment (corresponding to claim 8) of the present invention. In FIG. 10, the same reference numerals as those in FIG. 9 of the fifth embodiment indicate the same components, and thus detailed description thereof is omitted. A difference from the fifth embodiment is a logic element 149. The total resistance value of the resistance elements 142 to 144 connected in series between the input portion of the logic element 149 and the power supply potential (VDD), and the connection between the input portion of the logic element 148 and the ground potential (VSS) in series. The potential divided by the resistance value of the resistance dividing resistance element 147 is set to be higher than the input threshold level of the logic element 148. The logic of the operation of the logic element 149 is opposite to that of the logic element 148 in the fifth embodiment.

  The operation of the semiconductor device of the present embodiment configured as described above will be described below. The basic operation is the same as in the case of the fifth embodiment. A power supply potential (VDD) is applied to the continuity test terminal 137 and the switch elements 139 to 141, 145 and 146 are turned on. In the normal state with no failure, the divided potential is higher than the threshold value of the logic element 149, so that the logic element outputs a predetermined value. On the other hand, when a disconnection failure has occurred in any of the wires 133 to 136, the divided potential becomes lower than the threshold value of the logic element 149, so that the output of the logic element 149 is the inverted value of the normal state. Is output. Therefore, the disconnection failure of the wires connecting the plurality of chip-to-chip connection terminals can be collectively tested by one measurement according to the output value of the logic element 149. Furthermore, since the detection is performed by logic inversion, a relatively high-grade test apparatus that measures current while applying a voltage is not required, and the test apparatus can be simplified. The disconnection failure and the short-circuit failure are the differences between the present embodiment and the fifth embodiment.

(Embodiment 7)
FIG. 11 is a block circuit diagram showing the configuration of the semiconductor device according to the seventh embodiment (corresponding to claim 9) of the present invention. The seventh embodiment corresponds to a combination of the fifth embodiment and the sixth embodiment. In FIG. 11, the same reference numerals as those in FIGS. 9 and 10 of the fifth and sixth embodiments indicate the same components, and detailed description thereof will be omitted. A first logic element 148a similar to the logic element 148 in FIG. 9 and a second logic element 149a similar to the logic element 149 in FIG. 10 are provided. According to this, both a short circuit failure and a disconnection failure can be detected.

(Reference Example 5)
FIG. 12 is a block circuit diagram showing a configuration of a semiconductor device according to Reference Example 5 of the present invention. In FIG. 12, since the same reference numerals as those in FIG. 9 of the fifth embodiment indicate the same components, detailed description thereof will be omitted. The difference from the fifth embodiment is switch elements 139b and 141b and resistance elements 142b and 144b. The series connection body of the switch element 139b and the resistance element 142b and the series connection body of the switch element 141b and the resistance element 144b are respectively the series connection body of the switch element 139 and the resistance element 142, and the switch element 141 and the resistance element in FIG. This corresponds to the arrangement position of the serially connected body with 144 shifted from the child chip 115 to the parent chip 101.

  The operation of the semiconductor device of this reference example configured as described above will be described below. The basic operation is the same as in the case of the fifth embodiment. A power supply potential (VDD) is applied to the continuity test terminal 137 and the switch elements 139 to 141, 145 and 146 are turned on. In the normal state with no failure, the divided potential is lower than the threshold value of the logic element 148, so that the logic element outputs a predetermined value. On the other hand, when a short circuit failure has occurred between the wires 133 to 135, the resistive element 143b connected between the inter-chip connection terminals 126 to 127 is bypassed, so that the divided potential is the logic element 148. Therefore, the output of the logic element 148 outputs the inverted value of the normal state. Therefore, a short circuit failure of a plurality of inter-chip connection terminals can be collectively tested by one measurement based on the output value of the logic element 148. Furthermore, since the detection is performed by logic inversion, a relatively high-grade test apparatus that measures current while applying a voltage is not required, and the test apparatus can be simplified. In addition, since it is concentrated on the parent chip 101 side, the child chip 115 does not require any design change such as addition of a switch element or a resistance element for the continuity test, and the child chip 115 is obtained from another company. It is possible to use the semiconductor chip.

  In each of the embodiments and reference examples described above, a switch element or a pair of a switch element and a resistor can be easily configured by an N-type, P-type, or N-type and P-type MOS transistor.

The block circuit diagram which shows the structure of the semiconductor device in the reference example 1 of this invention The block circuit diagram which shows the structure of the semiconductor device in the reference example 2 of this invention The block circuit diagram which shows the structure of the semiconductor device in the reference example 3 of this invention 1 is a block circuit diagram showing a configuration of a semiconductor device in Embodiment 1 of the present invention. Block circuit diagram showing a configuration of a semiconductor device according to a second embodiment of the present invention Block circuit diagram showing a configuration of a semiconductor device according to a third embodiment of the present invention The block circuit diagram which shows the structure of the semiconductor device in the reference example 4 of this invention Block circuit diagram showing a configuration of a semiconductor device according to a fourth embodiment of the present invention Block circuit diagram showing a configuration of a semiconductor device according to a fifth embodiment of the present invention Block circuit diagram showing a configuration of a semiconductor device according to a sixth embodiment of the present invention Block circuit diagram showing a configuration of a semiconductor device according to a seventh embodiment of the present invention The block circuit diagram which shows the structure of the semiconductor device in the reference example 5 of this invention Block circuit diagram showing the configuration of a semiconductor device in the prior art Block circuit diagram showing a configuration of a semiconductor device in another conventional technique

Explanation of symbols

001: Semiconductor chips 002, 102, 116: Internal circuits 003-008, 103-108: Terminals 009-014, 109-114, 121-124, 129-132: Diodes 015, 016, 137, 137a, 138, 138a: Terminals for continuity test 017-021, 139-141, 139b, 141b, 201-204: switch elements 022-026, 142-144, 142b, 144b: resistance elements 022a-026a, 142a-144a: resistance values are weighted Resistance elements 027, 145: Power supply potential side switching elements 028, 146: Ground potential side switching elements 029: Resistance dividing resistance elements 030, 148, 149: Logic elements 050, 150: Switch control terminals 101: Parent chip 115: Child chips 117-120, 125-128 Inter-chip connection terminals 133 to 136: Wire 148a: first logic element 149a: second logic element 200: switch control means 205 to 208: line switch element

Claims (11)

A first semiconductor chip and a second semiconductor chip each having a plurality of inter-chip connection terminals are mounted inside one package, and each of the inter-chip connection terminals on the first semiconductor chip and the second semiconductor are mounted. A semiconductor device in which each of the inter-chip connection terminals on the chip is connected one by one through a wire,
A switch element inserted between a plurality of adjacent wires on the first semiconductor chip side and the second semiconductor chip side alternately, and a series connection body of the series of the switch elements A semiconductor device comprising: a continuity test terminal connected to one end and the other end of the switch; and a switch control terminal for collectively controlling the plurality of switch elements.   2. The semiconductor device according to claim 1, wherein a resistance element is connected in series to each of the plurality of switch elements.   3. The semiconductor device according to claim 2, further comprising weighted individual resistance values of the plurality of resistance elements. A first semiconductor chip and a second semiconductor chip each having a plurality of inter-chip connection terminals are mounted inside one package, and each of the inter-chip connection terminals on the first semiconductor chip and the second semiconductor are mounted. A semiconductor device in which each of the inter-chip connection terminals on the chip is connected one by one through a wire,
A switch element interposed between each of the plurality of inter-chip connection terminals and a continuity test terminal on the first semiconductor chip side, and a switch for selectively on / off controlling the plurality of switch elements Control means, a diode connected in the forward direction with respect to the power supply potential or in the reverse direction with respect to the ground potential at the plurality of inter-chip connection terminals on the second semiconductor chip side, and the first semiconductor chip And a continuity test terminal connected to an on / off control terminal of the line switch element.   5. The semiconductor device according to claim 4, wherein a power supply potential supplied to the first semiconductor chip and a power supply potential supplied to the second semiconductor chip are separately supplied.   5. The semiconductor device according to claim 4, wherein a ground potential supplied to the first semiconductor chip and a ground potential supplied to the second semiconductor chip are separately supplied. A first semiconductor chip and a second semiconductor chip each having a plurality of inter-chip connection terminals are mounted inside one package, and each of the inter-chip connection terminals on the first semiconductor chip and the second semiconductor are mounted. A semiconductor device in which each of the inter-chip connection terminals on the chip is connected one by one through a wire,
A series connection body of a switch element and a resistance element, which is inserted between a plurality of adjacent wires in an alternating state on the first semiconductor chip side and the second semiconductor chip side, A power supply potential side switch element that connects one end of the series connection body to a power supply potential; and a ground potential side switch element that connects the other end of the series connection body to a ground potential; A switch control terminal for collectively controlling a plurality of the switch elements, a resistance dividing resistance element connected in series for resistance division with respect to a resistance element group in the series connected body, and the series connection in series A semiconductor device comprising: a logic element that detects that a potential at a resistance dividing point between a body and the resistance dividing resistance element exceeds a predetermined value; and a continuity test terminal connected to an output side of the logic element. A first semiconductor chip and a second semiconductor chip each having a plurality of inter-chip connection terminals are mounted inside one package, and each of the inter-chip connection terminals on the first semiconductor chip and the second semiconductor are mounted. A semiconductor device in which each of the inter-chip connection terminals on the chip is connected one by one through a wire,
A series connection body of a switch element and a resistance element, which is inserted between a plurality of adjacent wires in an alternating state on the first semiconductor chip side and the second semiconductor chip side, A power supply potential side switch element that connects one end of the series connection body to a power supply potential; and a ground potential side switch element that connects the other end of the series connection body to a ground potential; A switch control terminal for collectively controlling the whole of the plurality of switch elements, a resistance element for resistance division connected in series for resistance division with respect to a resistance element group in the series of series connection bodies, and the series of series connections A semiconductor device comprising: a logic element that detects that a potential at a resistance dividing point between a body and the resistance dividing resistance element is below a predetermined value; and a continuity test terminal connected to an output side of the logic element. A first semiconductor chip and a second semiconductor chip each having a plurality of inter-chip connection terminals are mounted inside one package, and each of the inter-chip connection terminals on the first semiconductor chip and the second semiconductor are mounted. A semiconductor device in which each of the inter-chip connection terminals on the chip is connected one by one through a wire,
A series connection body of a switch element and a resistance element, which is inserted between a plurality of adjacent wires in an alternating state on the first semiconductor chip side and the second semiconductor chip side, A power supply potential side switch element that connects one end of the series connection body to a power supply potential; and a ground potential side switch element that connects the other end of the series connection body to a ground potential; A switch control terminal for collectively controlling the whole of the plurality of switch elements, a resistance element for resistance division connected in series for resistance division with respect to a resistance element group in the series of series connection bodies, and the series of series connections A first logic element for detecting that a potential at a resistance dividing point between a body and the resistance dividing resistance element exceeds a predetermined value; and a resistance dividing point between the series connected body and the resistance dividing resistance element. Potential is a predetermined value Second and logic elements, a semiconductor device and a respectively connected continuity test terminal to the output side of the first and second logic element for detecting the below.   10. The semiconductor device according to claim 1, wherein the switch element includes an N-type, a P-type, or an N-type and a P-type MOS transistor.   7. The semiconductor device according to claim 1, wherein the resistance element is an N-type, P-type, or N-type and P-type MOS transistor.

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