JP2009075030A - 半導体テスタ - Google Patents
半導体テスタ Download PDFInfo
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- JP2009075030A JP2009075030A JP2007246407A JP2007246407A JP2009075030A JP 2009075030 A JP2009075030 A JP 2009075030A JP 2007246407 A JP2007246407 A JP 2007246407A JP 2007246407 A JP2007246407 A JP 2007246407A JP 2009075030 A JP2009075030 A JP 2009075030A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000012360 testing method Methods 0.000 claims abstract description 31
- 238000004891 communication Methods 0.000 claims description 20
- 238000012546 transfer Methods 0.000 abstract description 13
- 230000002238 attenuated effect Effects 0.000 abstract description 3
- 230000003139 buffering effect Effects 0.000 abstract description 2
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 230000001360 synchronised effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 12
- 230000005540 biological transmission Effects 0.000 description 7
- 238000000926 separation method Methods 0.000 description 5
- 230000006866 deterioration Effects 0.000 description 4
- 238000007689 inspection Methods 0.000 description 4
- 238000009434 installation Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
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Abstract
【解決手段】中継モジュール5は、ハーネス4のペアケーブルを伝送される差動信号を中継するリタイミング回路50と、リタイミング回路50に外部クロックを与えるクロック60と、を備える。リタイミング回路50は、テストヘッド2からの差動入力信号を受けるとともに、ハーネス4の周波数特性により減衰した高周波成分を強調して波形の補償を行うイコライザ51と、イコライザ51の出力信号より、信号パタンに埋め込まれたクロック成分を復調するとともに、クロック60からの外部クロックに同期して信号およびクロック成分をリタイミングして出力するリクロッカ52と、リクロッカ52の出力信号をバッファして出力するケーブルドライバ53とを具備する。
【選択図】図1
Description
この半導体テスタによれば、通信回路の周波数特性を補償して出力する中継装置を挿入したので、コストを抑制しつつ、転送データの情報量を増大できる。
5 中継モジュール
51 イコライザ
52 リクロッカ
70 電源・信号分離回路
80 電源・信号重畳回路
Claims (5)
- テストヘッドと本体架とを互いに通信経路で接続して構成された半導体テスタにおいて、
前記通信経路の途中に挿入され、前記通信経路の周波数特性を補償して出力する中継装置を備えることを特徴とする半導体テスタ。 - 前記中継装置には、前記通信回路の周波数特性を補償するイコライザが設けられることを特徴とする請求項1に記載の半導体テスタ。
- 前記中継装置には、出力される信号のタイミングを整えるリクロッカが設けられることを特徴とする請求項1または2に記載の半導体テスタ。
- 前記通信経路を介して前記中継装置へ電源供給され、前記中継装置には、前記通信経路の信号と電源電圧とを分離する回路が設けられることを特徴とする請求項1〜3のいずれか1項に記載の半導体テスタ。
- 前記中継装置には、供給された電源電圧を信号に重畳させて前記通信経路に送出する回路が設けられることを特徴とする請求項4に記載の半導体テスタ。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP2007246407A JP4947371B2 (ja) | 2007-09-25 | 2007-09-25 | 半導体テスタ |
Applications Claiming Priority (1)
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JP2007246407A JP4947371B2 (ja) | 2007-09-25 | 2007-09-25 | 半導体テスタ |
Publications (2)
Publication Number | Publication Date |
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JP2009075030A true JP2009075030A (ja) | 2009-04-09 |
JP4947371B2 JP4947371B2 (ja) | 2012-06-06 |
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JP2007246407A Active JP4947371B2 (ja) | 2007-09-25 | 2007-09-25 | 半導体テスタ |
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05102892A (ja) * | 1991-10-09 | 1993-04-23 | Mitsubishi Electric Corp | バイパス装置 |
JP2000304821A (ja) * | 1999-04-22 | 2000-11-02 | Advantest Corp | データ取込制御装置、データ取込制御方法、及び試験装置 |
JP2004320291A (ja) * | 2003-04-15 | 2004-11-11 | Nippon Hoso Kyokai <Nhk> | ビデオジャック装置 |
JP2005136905A (ja) * | 2003-10-31 | 2005-05-26 | Maspro Denkoh Corp | インターホンシステム及び信号中継装置 |
JP2006180443A (ja) * | 2004-11-26 | 2006-07-06 | Fujitsu Component Ltd | 遠隔ユニット、遠隔システム、中継器及び自動調整方法 |
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2007
- 2007-09-25 JP JP2007246407A patent/JP4947371B2/ja active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05102892A (ja) * | 1991-10-09 | 1993-04-23 | Mitsubishi Electric Corp | バイパス装置 |
JP2000304821A (ja) * | 1999-04-22 | 2000-11-02 | Advantest Corp | データ取込制御装置、データ取込制御方法、及び試験装置 |
JP2004320291A (ja) * | 2003-04-15 | 2004-11-11 | Nippon Hoso Kyokai <Nhk> | ビデオジャック装置 |
JP2005136905A (ja) * | 2003-10-31 | 2005-05-26 | Maspro Denkoh Corp | インターホンシステム及び信号中継装置 |
JP2006180443A (ja) * | 2004-11-26 | 2006-07-06 | Fujitsu Component Ltd | 遠隔ユニット、遠隔システム、中継器及び自動調整方法 |
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