JP2009071246A - Drawing device and data processing method of drawing data - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a drawing device for restraining the delay of countermeasure against erroneous determination and abnormal operation of timeout error. <P>SOLUTION: A drawing device 100 in one aspect includes a master control computer 110 for making the device execute data processing for each processing unit while dividing drawing data 12 to each processing unit; a slave control computer 130 for executing the data processing by receiving an execution instruction; and a drawing part 150 for drawing on a specimen 101 using an electron beam 200 a pattern based on the drawing data of a predetermined processing unit for which the data processing has been completed normally. The master control computer 110 or the slave control computer 130 computes predicted processing time required for the data processing of each processing unit for each processing unit of drawing data. The slave control computer 130 completes the data processing as error when the data processing has not been completed within the predicted processing time. In accordance with the present invention, it is possible to determine timeout error in predicted processing time matching data scale. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a drawing apparatus and a data processing method for drawing data, and for example, relates to timeout error control in data processing of drawing data used for electron beam drawing or laser drawing.

  Lithography technology, which is responsible for the progress of miniaturization of semiconductor devices, is an extremely important process for generating a pattern among semiconductor manufacturing processes. In recent years, with the high integration of LSIs, circuit line widths required for semiconductor devices have been miniaturized year by year. In order to form a desired circuit pattern on these semiconductor devices, a highly accurate original pattern (also referred to as a reticle or a mask) is required. Here, the electron beam (electron beam) drawing technique has an essentially excellent resolution, and is used for producing a high-precision original pattern. Similarly, laser drawing technology is used to produce highly accurate original picture patterns. Hereinafter, an electron beam drawing technique will be described as an example.

FIG. 13 is a conceptual diagram for explaining the operation of a conventional variable shaping type electron beam drawing apparatus.
In a first aperture 410 in a variable shaping type electron beam drawing apparatus (EB (Electron beam) drawing apparatus), a rectangular, for example, rectangular opening 411 for forming the electron beam 330 is formed. Further, the second aperture 420 is formed with a variable shaping opening 421 for shaping the electron beam 330 having passed through the opening 411 of the first aperture 410 into a desired rectangular shape. The electron beam 330 irradiated from the charged particle source 430 and passed through the opening 411 of the first aperture 410 is deflected by the deflector, passes through a part of the variable shaping opening 421 of the second aperture 420, and passes through a predetermined range. The sample is irradiated on a stage that moves continuously in one direction (for example, the X direction). That is, the drawing area of the sample 340 mounted on the stage in which the rectangular shape that can pass through both the opening 411 of the first aperture 410 and the variable shaping opening 421 of the second aperture 420 is continuously moved in the X direction. Drawn on. A method of creating an arbitrary shape by passing both the opening 411 of the first aperture 410 and the variable shaping opening 421 of the second aperture 420 is referred to as a variable shaping method.

  In performing such electron beam drawing, first, a layout of a semiconductor integrated circuit is designed, and layout data (design data) in which a pattern layout is defined is generated. Then, the layout data is converted by an external apparatus, and drawing data that can be input to the electron beam drawing apparatus is generated. Then, the drawing data is batch-transferred and input to the electron beam drawing apparatus. Based on the drawing data in the electron beam drawing apparatus, the data is converted into the format data in the electron beam drawing apparatus after the data processing by parallel processing or the like. The image is converted and drawn (see, for example, Patent Document 1).

With the recent high integration of LSI, the drawing data to be processed and input to the electron beam drawing apparatus is increasing. Here, with respect to the data processing of the drawing data in the electron beam drawing apparatus, if the data processing is not completed within a predetermined time, it is treated as a time-out error assuming that some abnormality has occurred. Conventionally, the set value (time) of this timeout error is a fixed value uniquely set for each apparatus. Therefore, the following problems have occurred. First, on the other hand, a pattern composed of a large amount of data is erroneously determined as a timeout error because the process is not completed within the set time even though normal processing is ongoing. There was a problem. In order to solve this problem, if the set value is lengthened, the pattern composed of a small amount of data on the other hand is not determined to be abnormal until the set time elapses even if the abnormal operation is started within a short time. Problems arise. Therefore, there has been a problem that countermeasures against such abnormal operations are delayed.
JP 2007-103923 A

  As described above, since the set value of the timeout error is a unique value uniquely set for each apparatus, there has been a problem that erroneous determination of the timeout error and a delay in countermeasures for abnormal operation are caused. Also, laser mask drawing has the same problem as electron beam drawing.

  Therefore, an object of the present invention is to provide a data processing method and a drawing apparatus that overcome such problems and suppress delays in countermeasures against erroneous determination of timeout errors and abnormal operations.

The drawing device of one embodiment of the present invention includes:
A storage unit for storing drawing data for drawing a predetermined pattern on the sample;
A main computer that divides drawing data into processing units and executes data processing of each processing unit;
A slave computer that receives an execution instruction from the master computer and executes data processing of a predetermined processing unit;
A drawing unit for drawing a predetermined pattern on the sample based on drawing data of a predetermined processing unit in which data processing has been normally completed;
With
Either the primary computer or the slave computer calculates the expected processing time for data processing of each processing unit for each processing unit of drawing data,
The slave computer ends data processing as an error when data processing of a predetermined processing unit does not end within the expected processing time.

  By calculating the expected processing time for data processing for each processing unit of drawing data, it is possible to obtain the expected processing time corresponding to each data scale. Then, this estimated processing time is set to the timeout error setting value.

  In particular, when the progress management of processing by data communication is regularly performed between the main computer and the slave computer, the following configuration is preferable.

First, the slave computer transmits a predetermined signal to the master computer if the expected processing time has not yet elapsed when the data processing of the predetermined processing unit is not completed within the first period,
As long as the master computer receives a predetermined signal within the second period, the data processing of the slave computer is normal even if the data processing of the predetermined processing unit is not completed within the first period. It is preferable that the configuration is determined.

  The expected processing time is preferably defined by a function based on at least one of the data type, the data amount, the number of cells, the number of arranged cells, the CPU performance for data processing, the number of CPUs, and the memory amount. .

A drawing apparatus according to another aspect of the present invention includes:
A storage unit for storing drawing data for drawing a predetermined pattern on the sample;
An execution command part that transmits an execution command for executing data processing of each processing unit for each processing unit of drawing data;
For each processing unit of drawing data, a time prediction unit that calculates an expected processing time for data processing of each processing unit;
An execution unit that receives an execution instruction and executes data processing of a predetermined processing unit;
A drawing unit for drawing a predetermined pattern on the sample based on drawing data of a predetermined processing unit in which data processing is completed within an expected processing time;
It is provided with.

The drawing data processing method according to one aspect of the present invention includes:
Dividing drawing data for drawing a predetermined pattern on a sample for each processing unit, and transmitting an execution command for executing data processing of a predetermined processing unit;
Calculating an expected processing time for data processing of a predetermined processing unit;
Receiving an execution instruction and executing data processing of a predetermined processing unit;
A step of determining a time-out error when data processing of a predetermined processing unit does not end within the expected processing time, and outputting the result;
It is provided with.

  According to the present invention, it is possible to determine a time-out error with an expected processing time corresponding to the data scale. Therefore, it is possible to suppress delays in countermeasures against erroneous determination of timeout errors and abnormal operations.

  Hereinafter, in each embodiment, a configuration using an electron beam will be described as an example of a charged particle beam. However, the charged particle beam is not limited to an electron beam, and a beam using charged particles such as an ion beam may be used. As an example of the charged particle beam apparatus, a charged particle beam drawing apparatus, particularly, a variable shaping type electron beam drawing apparatus will be described. Hereinafter, an electron beam drawing apparatus will be described as an example, but the present invention is not limited to this, and the same applies to a laser mask drawing apparatus.

Embodiment 1 FIG.
FIG. 1 is a conceptual diagram illustrating a configuration of a drawing apparatus according to the first embodiment.
In FIG. 1, the drawing apparatus 100 includes a drawing unit 150 and a control unit 160. The drawing apparatus 100 is an example of a charged particle beam drawing apparatus. The drawing apparatus 100 draws a predetermined pattern on the sample 101. The drawing unit 150 includes a drawing chamber 103 and an electronic lens barrel 102 disposed on the upper portion of the drawing chamber 103. In the electron column 102, an electron gun 201, an illumination lens 202, a first aperture 203, a projection lens 204, a deflector 205, a second aperture 206, an objective lens 207, and a deflector 208 are provided. An XY stage 105 is arranged in the drawing chamber 103, and a sample 101 to be drawn is arranged on the XY stage 105. Examples of the sample 101 include a wafer on which a semiconductor device is formed and an exposure mask that transfers a pattern to the wafer. Further, this mask includes, for example, mask blanks on which no pattern is formed. The control unit 160 includes magnetic disk devices 109 and 170, a main (parent) control computer 110, a plurality of slave (child) control computers 130 (a to k), and a control circuit 172. In the parent control computer 110, a distribution unit 112, an activation unit 114, a time prediction unit 116, a command unit 118, a determination unit 120, and a parameter calculation unit 122 are arranged. In the plurality of child control computers 130, a plurality of arithmetic units (CPUs) 132 that execute data processing, a plurality of memories 134, and a control unit 136 are arranged. The CPU 132 is an example of an execution unit. The components of the control unit 160 are connected to each other via a bus (not shown). Here, in FIG. 1, each configuration in the parent control computer 110 is described as being configured by hardware using an electric circuit, but the configuration is not limited to this, and may be implemented by software. That is, the parent control computer 110 may be a computer. The parent control computer 110, which is an example of a computer, may execute processing of each function such as the distribution unit 112, the activation unit 114, the time prediction unit 116, the command unit 118, the determination unit 120, and the parameter calculation unit 122. I do not care. Or you may make it implement by the combination of the hardware and software by an electrical circuit. Alternatively, a combination of such hardware and firmware may be used. Further, in the case of implementation by software or in combination with software, information input to the parent control computer 110 or information during and after the arithmetic processing is stored in the memory 124 each time. The control unit 136 in the child control computer 130 may be a computer. The control unit 136, which is an example of a computer, may execute processing of each function described later. Or you may make it implement by the combination of the hardware and software by an electrical circuit. Alternatively, a combination of such hardware and firmware may be used. Further, in the case of implementation by software or in combination with software, information input to the child control computer 130 or information during and after the arithmetic processing is stored in one of the memories 134 each time. In FIG. 1, description of components other than those necessary for describing the first embodiment is omitted. Needless to say, the drawing apparatus 100 may normally include other necessary configurations.

  In performing electron beam drawing, first, a layout of a semiconductor integrated circuit is designed, and layout data (design data) in which a pattern layout is defined is generated. Then, the layout data is converted by an external conversion device, and drawing data 12 that can be input to the drawing device 100, which is an example of an electron beam drawing device, is generated. The drawing data 12 for drawing a predetermined pattern on the sample is stored in a magnetic disk device 109 as an example of a storage unit. In the drawing apparatus 100, the data is further converted into format data in the drawing apparatus 100 after a plurality of stages of conversion processing. The parent control computer 110 distributes these data processes to a plurality of child control computers 130. Then, the data is processed by the plurality of child control computers 130 while the parent control computer 110 controls. Then, the drawing unit 150 draws a predetermined pattern on the sample 101 using the data that has been processed.

FIG. 2 is a diagram illustrating an example of a hierarchical structure of drawing data according to the first embodiment.
In the drawing data 12, the drawing area is the layer of the chip 10, the layer of the frame 14 obtained by virtually dividing the chip area into a strip shape, for example, in the y direction, the layer of the block 16 obtained by dividing the frame 14, and at least one figure. And a layer of a plurality of internal structural units such as a layer of a cell 18 constituted by and a layer of a graphic 19 constituting the cell 18. In general, a plurality of layers of the chip 10 are laid out with respect to the drawing region of one sample 101. Here, the chip area of the frame 14 is divided into strips in the y direction (predetermined direction), but this is an example, and the chip area is divided in the x direction that is parallel to the drawing surface and orthogonal to the y direction. It is possible that Alternatively, other directions parallel to the drawing surface may be used.

FIG. 3 is a diagram illustrating an example of drawing data according to the first embodiment.
When a pattern is drawn by the drawing apparatus, for example, the frame 14 is drawn as a drawing unit. In FIG. 3, as an example, data located in a frame area identified by a number “n” in a certain chip 10 will be described. Then, cell arrangement data, link data, and cell pattern data are created as the drawing data 12 for the frame. In FIG. 3, the drawing data 12 includes a cell arrangement data file 22, a link data file 24, and a cell pattern data file 26 as an example. These files are created for each frame. The drawing data 12 further includes a chip configuration file 20 that defines configuration information of each frame, parameters common to the entire chip, and the like for a chip configured with one or more frames. Further, FIG. 3 shows an example of a correspondence relationship between each data in the cell arrangement data file 22, the link data file 24, and the cell pattern data file 26. When a desired pattern is drawn on a sample, the mask is composed of one or more chips 10 for one mask. In such a case, there are a plurality of chip data composed of these files, and has layout information for arranging them on the mask.

  The cell arrangement data file 22 includes arrangement data (arrangement information) for arranging the cells 18 corresponding to the pattern data of a certain chip 10 included in the design data. The cell arrangement data file 22 includes arrangement data for arranging any of the arranged cells 18 for each block area, for example. In FIG. 3, as an example, arrangement data for arranging any of the cells (i) to (l) that are a part of the arranged cells 18 is shown. The cell arrangement data is indicated by coordinates indicating the arrangement position of the reference point of the cell 18. In FIG. 3, a cell arrangement data file 22 is followed by a block (0, 0) header, cell arrangement data (p), cell arrangement data (q), and cells arranged in the block (0, 0). Arranged data (r), block (0, 1) header, cell arrangement data (s) arranged in block (0, 1), block (1, 0) header, arranged in block (1, 0) The cell arrangement data (t) is defined (stored). Other arrangement data is further stored.

  Next, the cell pattern data file 26 includes each pattern data of a plurality of cells 18 arranged in the nth frame 14 of a certain chip 10. In FIG. 3, each pattern data of the cells (i) to (l) is shown as an example. Here, the cell pattern data file 26 includes, as part thereof, a pattern data segment (0), cell pattern data (i) indicating pattern data of the cell (i), and cell pattern indicating pattern data of the cell (j). Data (j) is stored once in order. Subsequently, cell pattern data (k) indicating the pattern data segment (1) and the pattern data of the cell (k) is stored. Further, other data is stored, and thereafter, pattern data segment (4) and cell pattern data (l) indicating the pattern data of cell (l) are stored.

  The link data file 24 includes link information for referring to each cell pattern data from each cell arrangement data and operation information to the cell pattern data. In FIG. 3, the link data file 24 includes, as a part thereof, relation data (a) for associating cell arrangement data (p) with cell pattern data (i), and cell arrangement data (q) as cell pattern data. Relation data (b) for relating to (j), Relation data (c) for relating cell arrangement data (r) to cell pattern data (i), and cell arrangement data (s) to cell pattern data (k) ) And relation data (e) for associating the cell arrangement data (t) with the cell pattern data (l) are stored together with other data.

  In the first embodiment, when the parent control computer 110 and the child control computer 130 do not perform close communication, or when communication is performed, a counter indicating a data processing status such as a watchdog counter is not functioning. The case will be described. Here, as an example, a case will be described in which data processing is distributed to the child control computer 130 in units of frames 14 as processing units of drawing data.

FIG. 4 is a flowchart showing the main steps of the processing flow of the parent control computer and the child control computer in the first embodiment.
In S <b> 102, as a frame selection step, the distribution unit 112 selects a frame to be distributed to each child control computer 130.

In S104, as a parameter calculation step, the parameter calculating unit 122 calculates a parameter for calculating the estimated processing time T ₁ of the next step. Expected processing time T ₁ can be expected as a function of the parameters characterizing the data of a certain frame to be input. Examples of parameters include data type, data amount, number of cells, number of cell arrangements, and the like. In addition, it is preferable to consider the configuration of hardware resources. Examples of parameters when considering hardware resources include CPU performance, the number of CPUs, the amount of memory, or disk I / O (input / output) performance.

(Case 1)
In Case 1, and calculates the expected processing time _{T 1} based on the amount of data _{V total} and the coefficient _{k 1} of the frame data to be input. In that case, the expected processing time T ₁ can be defined by the following equation (1).
(1) T ₁ = k ₁ · V _total

In case 1, the parameter calculation unit 122 calculates the data amount V _total of the frame data input. Alternatively, it is acceptable to measure the data processing time corresponding to the advance amount of data for the coefficients k _1, it is sufficient to seek its coefficients by fitting (approximation) of the measurement results. At that time, since the data processing time varies depending on the type of device such as a memory or a logic, it may be measured in each case. This allows the data type to be considered as a parameter. Here, the expected processing time T ₁ is not limited to Equation (1). For example, it is also preferable to define the expected processing time T ₁ as follows.

(Case 2)
In Case 2, it calculates the expected processing time _{T 1} based on the number of cells of the frame data _{N cell} and the coefficient _{k 2} to be inputted. In that case, the expected processing time T ₁ can be defined by the following equation (2).
(2) T ₁ = k ₂ · N _cell

In case 2, the parameter calculation unit 122 calculates the number N _cells of frame data to be input. Alternatively, it is acceptable to measure the data processing time corresponding to the advance number of cells for the coefficients k _2, it is sufficient to seek its coefficients by fitting (approximation) of the measurement results. At that time, since the data processing time varies depending on the type of device such as a memory or a logic, it may be measured in each case. This allows the data type to be considered as a parameter. Here, the expected processing time T ₁ is, in addition to the equation (2), for example, it is also preferable to define the expected processing time T ₁ as follows.

(Case 3)
In Case 3, it calculates the expected processing time _{T 1} based on the amount of data _{V cell-i} and coefficient _{k 4} cells arrangement number _{N cell-ref} and the coefficient _{k 3} and cell i of the frame data input. In that case, the expected processing time T ₁ can be defined by the following equation (3).
(3) T ₁ = k ₃ · N _cell-ref + k ₄ · ΣV _cell-i

In case 3, the parameter calculation unit 122 calculates the cell arrangement number N _{cell-ref of the} frame data and the data amount V _cell-i of the _{cell i} . As for the coefficient k ₃ , the data processing time corresponding to the number of cell arrangements is measured in advance, and the coefficient is obtained by fitting (approximate) the measurement result. Similarly, for the coefficient k ₄ , the data processing time corresponding to the cumulative addition value of the data amount of the cell i is measured in advance, and the coefficient is obtained by fitting (approximate) the measurement result. At that time, since the data processing time varies depending on the type of device such as a memory or a logic, it may be measured in each case. This allows the data type to be considered as a parameter. Here, the expected processing time T ₁ is, in addition to the equation (3), for example, it is also preferable to define the expected processing time T ₁ as follows.

(Case 4)
In Case 4, it calculates the expected processing time _{T 1} by considering the further CPU number _{N CPU} to equation (1). In that case, the expected processing time T ₁ can be defined by the following equation (4).
(4) T ₁ = k ₅ · V _total / N _CPU

In case 4, the parameter calculation unit 122 further acquires the number of CPUs 132 arranged in the child control computer 130 that is the distribution destination. Alternatively, it is acceptable to measure the data processing time was considered previously CPU number N _CPU for coefficient k _5, it is sufficient to seek its coefficients by fitting (approximation) of the measurement results. Here, the expected processing time T ₁ is, in addition to the equation (4), for example, it is also preferable to define the expected processing time T ₁ as follows.

(Case 5)
In the case 5, the CPU performance, for example, the clock constant F _CPU , the processing data amount R per unit time corresponding to the memory amount, or the disk I / O constant S _{i / o} is further considered in the expression (4). calculates the expected processing time _{T 1.} Here, the expected processing time T ₁ is calculated in consideration of the clock constant F _CPU , the processing data amount R per unit time, and the disk S / O constant S _{i / o} . In that case, the expected processing time T ₁ can be defined by the following equation (4).
(5) T ₁ = k ₆ · V _total / (F _CPU · R · S _{i / o} · N _CPU )

In case 5, the parameter calculation unit 122 further processes the data amount R per unit time according to the memory amount of the memory 134 arranged in the child control computer 130 of the distribution destination, the clock constant F _{CPU of the CPU} 132, the magnetic disk The I / O constant S _{i / o} of the device 109 is further calculated or acquired. As for the coefficient k ₆ , the data processing time in consideration of the processing data amount R per unit time, the clock constant F _{CPU of the CPU} 132, and the I / O constant S _{i / o} of the magnetic disk device 109 is measured in advance. The coefficient may be obtained by fitting (approximate) the measurement result. Moreover, although all of these are added in Formula (5), not only this but at least one may be added. Since the processing speed differs between the clock value of the CPU 132 of 1 GHz and 2 GHz, the clock constant F _CPU may be set according to the clock value. In addition, since the processing speed differs between the input / output speed of the magnetic disk device 109 of 100 MB / s and 200 MB / s, the constant S _{i / o} can be set according to the I / O performance of the magnetic disk device 109. That's fine.

FIG. 5 is a diagram illustrating an example of the relationship between the memory usage amount and the processing data amount per unit time in the first embodiment. As shown in FIG. 5, the data processing amount vol / t per unit time rapidly increases from the processing data amount R ₁ to R ₂ per unit time until the memory usage exceeds a predetermined memory usage. To drop. Therefore, it is preferable to change the processing data amount R according to the memory amount of the memory 134 arranged in the child control computer 130.

  Here, in cases 4 and 5, new parameters are added to the equation (1), but it is also preferable to add them to the equation (2) or the equation (3) instead of the equation (1). Of the above-described parameters, those relating to input frame data are preferably obtained together with the frame data as attribute data of the frame data instead of being calculated by the parameter calculation unit 122.

In S <b> 106, as the data processing time prediction step, the time prediction unit 116 calculates an estimated processing time T <b> ₁ for data processing of each processing unit for each processing unit of the drawing data 12. Time anticipator 116 may be computing the expected processing time T ₁ by any of the calculation methods of the case 1 to 5 described above. Instead of using a fixed set time for each apparatus regardless of the data amount, data type, etc. as in the prior art, in the first embodiment, a time for determining the timeout for each processing unit of the drawing data 12 is predicted. . This makes it possible to obtain the expected processing time T ₁ commensurate with the data size.

  In S <b> 108, as the execution instruction process, the instruction unit 118 transmits an execution instruction for executing data processing of each processing unit to the child control computer 130 for each processing unit of drawing data. The command unit 118 is an example of an execution command unit. Here, the execution command notification is transmitted, but the child control computer 130 may be activated instead of the execution command notification. In that case, the activation unit 114 may activate the child control computer 130 instead of the instruction unit 118. Alternatively, the instruction unit 118 may transmit an execution instruction notification to the child control computer 130 after the activation unit 114 has activated the child control computer 130 in advance.

In S110, as the data processing step, when the child control computer 130 receives the execution command notification, first, the control unit 136 inputs data relating to a processing unit frame allocated from the magnetic disk device 109. Then, the CPU 132 executes data processing for the allocated processing unit. Then, the control unit 136 transmits an end notification to the parent control computer 110 when the data processing is completed. As shown in FIG. 4, the normal termination when the time until the master control computer 110 receives the end notification from the transmission of the execution command notification does not exceed the expected processing time T _1. On the other hand, a timeout error occurs in the following cases.

FIG. 6 is a flowchart illustrating a part of the process flow of the parent control computer and the child control computer when a timeout error occurs in the first embodiment.
In S112, as a judging step, the determination unit 120 until the master control computer 110 has reached the expected processing time T ₁ from the transmission of the execution instruction notification, come signal indicating that entering from the slave control computer 130 to the abnormality processing If it is determined that there is no end notification, it is determined that an abnormal state has been entered. In other words, it is determined as a timeout. Then, the determination unit 120 transmits an end command notification to the child control computer 130. As a result, the control unit 136 forcibly terminates the data processing being executed by the CPU 132. And the determination part 120 outputs the result determined to be timeout. The output result is displayed on a monitor (not shown) or output to the outside. The output result may be stored in the magnetic disk device 170.

  As described above, the time for determining the timeout for each processing unit of the drawing data 12 on the parent control computer 110 side is predicted. Further, since the timeout is determined based on the expected time for each processing unit, it is possible to suppress the erroneous determination of the timeout error and the delay of the countermeasure for the abnormal operation.

The drawing unit 150, using the electron beam 200, the predetermined pattern data processing based on the drawing data processing unit ended the expected processing time T ₁ to draw the sample 101. Specifically, it is as follows. The drawing data of each processing unit for which data processing has been completed within the expected processing time T ₁ is stored in the magnetic disk device 170 as shot data in a format unique to the device. The drawing unit 150 controlled by the control circuit 172 draws a predetermined pattern based on the shot data on the sample 101 as follows.

  An electron beam 200 emitted from an electron gun 201 that is an example of an irradiation unit illuminates the entire first aperture 203 having a rectangular hole, for example, a rectangular hole, by an illumination lens 202. Here, the electron beam 200 is first formed into a rectangle, for example, a rectangle. Then, the electron beam 200 of the first aperture image that has passed through the first aperture 203 is projected onto the second aperture 206 by the projection lens 204. The position of the first aperture image on the second aperture 206 is deflection-controlled by the deflector 205, and the beam shape and size can be changed. As a result, the electron beam 200 is shaped. Then, the electron beam 200 of the second aperture image that has passed through the second aperture 206 is focused by the objective lens 207 and deflected by the deflector 208. As a result, the desired position of the sample 101 on the XY stage 105 is irradiated. The operation of the XY stage 105 is performed by continuous movement or step-and-repeat movement. That is, the drawing apparatus 100 performs drawing while the XY stage 105 continuously moves. Alternatively, the drawing apparatus 100 performs drawing while the XY stage 105 is stopped while performing step-and-repeat movement. As described above, a desired pattern can be drawn at a highly accurate position based on data that has been successfully processed.

Embodiment 2. FIG.
In the first embodiment, the predicted expected processing time T ₁ parent control computer 110 side is not limited to this. In the second embodiment, the case of predicting the expected processing time T ₁ at the child control computer 130.

FIG. 7 is a conceptual diagram illustrating a configuration of a drawing apparatus according to the second embodiment.
7 is the same as FIG. 1 except that a parameter calculation unit 138 and a time prediction unit 140 are added in each child control computer 130. Here, in FIG. 7, as in FIG. 1, each configuration in the parent control computer 110 is described as being configured by hardware using an electric circuit, but this is not a limitation, and the configuration is implemented by software. It doesn't matter. That is, the parent control computer 110 may be a computer. The parent control computer 110, which is an example of a computer, may execute processing of each function such as the distribution unit 112, the activation unit 114, the time prediction unit 116, the command unit 118, the determination unit 120, and the parameter calculation unit 122. I do not care. Or you may make it implement by the combination of the hardware and software by an electrical circuit. Alternatively, a combination of such hardware and firmware may be used. Further, in the case of implementation by software or in combination with software, information input to the parent control computer 110 or information during and after the arithmetic processing is stored in the memory 124 each time. In FIG. 7, the control unit 136, the parameter calculation unit 138, and the time prediction unit 140 in the child control computer 130 are described as being configured by hardware using an electric circuit. However, the present invention is not limited to this. The software may be used. That is, the processing of each function of the control unit 136, the parameter calculation unit 138, and the time prediction unit 140 may be executed by a computer. Or you may make it implement by the combination of the hardware and software by an electrical circuit. Alternatively, a combination of such hardware and firmware may be used. Further, in the case of implementation by software or in combination with software, information input to the child control computer 130 or information during and after the arithmetic processing is stored in one of the memories 134 each time. In FIG. 7, the description is omitted except for the components necessary for explaining the second embodiment. Needless to say, the drawing apparatus 100 may normally include other necessary configurations.

FIG. 8 is a flowchart showing the main steps of the processing flow of the parent control computer and the child control computer in the second embodiment.
In S <b> 202, as the activation process, the activation unit 114 activates each child control computer 130. In S204, each child control computer 130 is activated.

  In S206, as a frame selection step, the distribution unit 112 selects a frame to be distributed to each child control computer 130.

In S208, as a parameter calculation step, the parameter calculating unit 122, the parameters for calculating the estimated expected time t ₁ until the calculation of the expected processing time T ₁ according to the data processing of the frame data slave control computer 130 are distributed Calculate. The estimated estimated time t ₁ can be estimated as a function of parameters characterizing the data of a certain input frame. Any one of the above-described cases 1 to 5 may be used. At that time, as for the coefficient of each equation, the calculation time corresponding to the parameter to be used is measured in advance, and the coefficient is obtained by fitting (approximate) the measurement result.

In S210, as estimated time expected process, up to the time anticipator 116, for each processing unit of the drawing data 12, and calculates the expected processing time T ₁ according to the data processing of each processing unit each slave control computer 130 are distributed The estimated calculation time t ₁ is calculated. The time prediction unit 116 may calculate the estimated trial time t ₁ by using any one of the above-described calculation formulas of cases 1 to 5 with different coefficients. If a processing error occurs while calculating the estimated processing time T ₁ according to the data processing of the frame data slave control computer 130 is distributed also. Also, come or different times for calculating the T ₁ expected processing time by the data size to be processed. Therefore, by calculating the estimated calculation time t ₁ , it is possible to calculate the period for calculating the estimated processing time T ₁ corresponding to the estimated calculation scale.

In S212, as expected processing time T ₁ calculated instruction step, the instruction unit 118, for each processing unit of the drawing data, and transmits the calculated command for calculating each estimated processing time T ₁ to the slave control computer 130.

In S214, as a parameter calculation step, the parameter calculating unit 138 calculates a parameter for calculating the estimated processing time T ₁ according to the data processing of the frame data to be distributed. Method of calculating the estimated processing time T _1, as in the first embodiment, may be used any of the formulas case 1-5 described above. Therefore, the parameter calculation unit 138 may calculate or acquire the parameter of any one of the selected cases 1 to 5.

In S <b> 216, as the data processing time prediction step, the time prediction unit 140 calculates an estimated processing time T <b> ₁ for data processing of each processing unit for each processing unit of the drawing data 12. Time anticipator 140 may be computing the expected processing time T ₁ by any of the calculation methods of the case 1 to 5 selected. In the second embodiment, a time for determining the timeout for each processing unit of the drawing data 12 is predicted on the child control computer 130 side. This makes it possible to obtain the expected processing time T ₁ commensurate with the data size. Then, the control unit 136, calculation of the estimated process time T ₁ is to transmit the predicted processing time T ₁ when finished to the parent control computer 110. As shown in FIG. 8, if the time from when the parent control computer 110 transmits the predicted processing time T ₁ calculation command notification until receiving the predicted processing time T ₁ does not exceed the estimated predicted time t ₁ The process proceeds to the previous execution instruction process. On the other hand, a timeout error occurs in the following cases.

FIG. 9 is a flowchart illustrating a part of the process flow of the parent control computer and the child control computer when a timeout error occurs in the second embodiment.
In S218, as a judging step, the determination unit 120 until the master control computer 110 has reached the estimated expected time t ₁ from the transmission of the T ₁ calculated command notification expected processing time, entered from the slave control computer 130 to the abnormality processing If signal indicating that came, or determines that the expected processing time T ₁ of the notification enters the abnormal state when not come. In other words, it is determined as a timeout. Then, the determination unit 120 transmits an end command notification to the child control computer 130. As a result, the control unit 136 forcibly terminates the calculation process being executed by the parameter calculation unit 138 or the time prediction unit 140. And the determination part 120 outputs the result determined to be timeout. The output result is displayed on a monitor (not shown) or output to the outside. The output result may be stored in the magnetic disk device 170.

Thus, to predict the estimated time for computing the estimated processing time T ₁ of the order to determine the time-out for each processing unit of the drawing data 12 on the parent control computer 110 side. Since the timeout is determined at the estimated estimated time t ₁ predicted for each processing unit, the erroneous determination of the timeout error and the delay of the countermeasures against the abnormal operation can be suppressed here.

  In S220, when a time-out error has not occurred in the previous process as an execution command process, the command unit 118 sends an execution command for executing data processing of each processing unit for each processing unit of drawing data to the child control computer. To 130. The command unit 118 is an example of an execution command unit.

In S222, as the data processing step, when the child control computer 130 receives the execution command notification, first, the control unit 136 inputs data relating to the processing unit frame allocated from the magnetic disk device 109. Then, the CPU 132 executes data processing for the allocated processing unit. Then, the control unit 136 transmits an end notification to the parent control computer 110 when the data processing is completed. As shown in FIG. 8, a normal termination when the time until the master control computer 110 receives the end notification from the transmission of the execution command notification does not exceed the expected processing time T _1. On the other hand, until the parent control computer 110 has reached the expected processing time T ₁ from the transmission of the execution instruction notification, if the came signal indicating that entering from the slave control computer 130 to the error processing, or if the end notification is not come Timeout error.

Here, when the timeout error occurs in the second embodiment, the processing flow of the parent control computer and the child control computer is as follows when S108 in FIG. 6 is replaced with S220, S110 with S222, and S112 with S224. It is the same. That is, in S224, as a determination step, the determination unit 120 until the master control computer 110 has reached the expected processing time T ₁ from the transmission of the execution command notification signal indicating that entered from the slave control computer 130 to the abnormality processing It is determined that an abnormal state has been entered when no notification is received. In other words, it is determined as a timeout. Then, the determination unit 120 transmits an end command notification to the child control computer 130. As a result, the control unit 136 forcibly terminates the data processing being executed by the CPU 132. And the determination part 120 outputs the result determined to be timeout. The output result is displayed on a monitor (not shown) or output to the outside. The output result may be stored in the magnetic disk device 170.

  As described above, the time for determining the timeout for each processing unit of the drawing data 12 is predicted on the child control computer 130 side. Further, since the timeout is determined based on the expected time for each processing unit, it is possible to suppress the erroneous determination of the timeout error and the delay of the countermeasure for the abnormal operation.

The drawing unit 150, using the electron beam 200, the predetermined pattern data processing based on the drawing data processing unit ended the expected processing time T ₁ to draw the sample 101. Others are the same as in the first embodiment.

Embodiment 3 FIG.
In the first embodiment or the second embodiment, a case has been described in which the parent control computer 110 and the child control computer 130 do not function a counter indicating a data processing state such as a watchdog counter. In the third embodiment, a case where a counter indicating a data processing status such as a watch dog counter is functioning will be described.

FIG. 10 is a conceptual diagram illustrating a configuration of a drawing apparatus according to the third embodiment.
10, except that the time prediction unit 116 and the parameter calculation unit 122 are deleted from the parent control computer 110, and a counter check unit 142, a determination unit 144, and a counter 146 are added to each child control computer 130. Is the same as FIG. Here, in FIG. 10, as in FIGS. 1 and 7, it is described that each configuration in the parent control computer 110 is configured by hardware based on an electric circuit, but this is not a limitation, and it is implemented by software. It does n’t matter. That is, the parent control computer 110 may be a computer. The parent control computer 110, which is an example of a computer, may execute processing of each function such as the distribution unit 112, the activation unit 114, the command unit 118, and the determination unit 120. Or you may make it implement by the combination of the hardware and software by an electrical circuit. Alternatively, a combination of such hardware and firmware may be used. Further, in the case of implementation by software or in combination with software, information input to the parent control computer 110 or information during and after the arithmetic processing is stored in the memory 124 each time. In FIG. 10, the control unit 136, the parameter calculation unit 138, the time prediction unit 140, the counter check unit 142, the determination unit 144, and the counter 146 in the child control computer 130 are configured by hardware using an electric circuit. However, the present invention is not limited to this, and may be implemented by software. That is, the processing of each function of the control unit 136, the parameter calculation unit 138, the time prediction unit 140, the counter check unit 142, the determination unit 144, and the counter 146 may be executed by a computer. Or you may make it implement by the combination of the hardware and software by an electrical circuit. Alternatively, a combination of such hardware and firmware may be used. Further, in the case of implementation by software or in combination with software, information input to the child control computer 130 or information during and after the arithmetic processing is stored in one of the memories 134 each time. In FIG. 10, the description of components other than those necessary for describing the third embodiment is omitted. Needless to say, the drawing apparatus 100 may normally include other necessary configurations.

In performing data processing of distributed frame data, when a watchdog counter is operated to manage a time-out error, control is performed as follows. First, check the counter value at a predetermined period t ₀ child control computer 130 has been set in advance, and transmits if the counter value is increased to a parent control computer 110 side-alive (ALIVE) signal (predetermined signal) . The counter value is incremented by one, for example, every time data processing for each cell is completed. On the other hand, when the parent control computer 110 does not receive an ALIVE signal within a predetermined time limit T ₀ set in advance, it is determined that a timeout has occurred. Here, the time limit T _{0 with} which the counter value must be counted up is finite. Therefore, depending on the design of the software or the data to be processed, the counter value does not change even though the process is actually continued normally, so the ALIVE signal is not transmitted to the parent control computer 110 side and an abnormal state ( Timeout error) may be detected erroneously.

  Here, it is also conceivable to avoid a timeout by changing the processing unit for increasing the counter value from a cell unit to a graphic unit having a smaller data amount. However, since the number of counter checks increases, this is not preferable because the processing time itself of the drawing data increases significantly. Therefore, in the third embodiment, the above-described erroneous detection is avoided by configuring as follows.

FIG. 11 is a flowchart showing the main steps of the processing flow of the parent control computer and the child control computer in the third embodiment.
In S300, as the time limit T ₀ setting step, setting the time limit T ₀ the counter value must be incremented to a parent control computer 110. Similarly, in S302, as the period _{t 0} setting step, setting the period _{t 0} to check the counter value to each child control computer 130.

  In S304, as a frame selection step, the distribution unit 112 selects a frame to be distributed to each child control computer 130.

  In S <b> 306, as an execution instruction process, the instruction unit 118 transmits an execution instruction for executing data processing of each processing unit to the child control computer 130 for each processing unit of drawing data. The command unit 118 is an example of an execution command unit. Here, the execution command notification is transmitted, but the child control computer 130 may be activated instead of the execution command notification. In that case, the activation unit 114 may activate the child control computer 130 instead of the instruction unit 118. Alternatively, the instruction unit 118 may transmit an execution instruction notification to the child control computer 130 after the activation unit 114 has activated the child control computer 130 in advance.

  In S308, as a counter reset process, the counter check unit 142 resets the value of the counter 146 to “0”.

In S310, as the data processing time prediction step, the time prediction unit 140 calculates the expected processing time T _1i required for the data processing of the processing unit in which the counter value is counted up. For example, a cell arranged in a frame in the distributed frame data is a processing unit to be counted up. In this case, the counter value is counted up every time data processing is performed in cell units. Therefore, here, it calculates the expected processing time T ₁₁ according to the data processing of the cell A _1. First, the parameter calculation unit 138 calculates a parameter for calculating the expected processing time T ₁ required for the data processing of the cell A ₁ . As in the first embodiment, the method for calculating the expected processing time T _1i may use any one of the cases 1, 4 and 5 described above. However, it goes without saying that the data amount V _total in the equations (1), (4), and (5) is the data amount of the corresponding cell A _i . Therefore, the parameter calculation unit 138 may calculate or acquire the parameter of the selected formula in any of cases 1, 4 and 5. Then, the time prediction unit 140 calculates an expected processing time T _1i for data processing of each processing unit for each cell unit. The time prediction unit 140 may calculate the predicted processing time T _1i by any one of the calculation methods of the selected cases 1, 4, and 5. In the third embodiment, a time for determining a timeout for each cell unit on the child control computer 130 side is predicted. As a result, it is possible to obtain the expected processing time T _1i corresponding to the data scale.

In step S312, when the child control computer 130 receives an execution command notification as a data processing step, first, the control unit 136 inputs data relating to a processing unit frame allocated from the magnetic disk device 109. Then, the CPU 132 executes data processing of cell unit data arranged in the frame in the allocated frame data. Here, it executes data processing of the cell A _1.

In S314, as a counter checking step, the count checking unit 142 checks the value of the counter 146 in period t _0, which is set after receiving the execution command notification.

In S316, as a judging step, the determination unit 144 determines whether the time from the calculation of the expected processing time T ₁₁ until the time of checking the value of the counter 146 exceeds the expected processing time T _11. As a result of the determination, even if not before the counter value in step up, yet, but before the expected processing time T ₁₁ elapses, the control unit 136, a parent controls the dummy ALIVE signal (predetermined signal) Send to computer 110. That is, if the data processing in units of cells is not completed within the period t ₀ (first period), and if the expected processing time T ₁₁ has not yet elapsed, the control unit 136 may use a dummy ALIVE signal (predetermined signal). ) Is transmitted to the parent control computer 110. FIG. 11 shows the case where the data processing of the data of the cell A ₁ has not been completed yet and the counter value has not increased. However, if the estimated processing time T ₁₁ has not yet elapsed, the previous process ( If the counter value has increased in S <b> 314), the control unit 136 transmits an actual (real) ALIVE signal to the parent control computer 110. Then, as long as the parent control computer 110 receives the ALIVE signal regardless of whether it is dummy or real within the set time limit T ₀ (second period), the data processing for each cell is completed within the period t ₀ . Even if not, it is determined that the data processing of the child control computer 130 is normal. The data processing of the cell A ₁ is advanced as it is.

In S318, as a counter checking step, the count checking unit 142 checks the value of the counter again 146 further period _{t 0} from the previous count checking.

In S320, as a judging step, the determination unit 144 determines whether the time up to the time of checking the value of the counter 146 in the previous step (S318) after computing the expected processing time _{T 11} exceeds the expected processing time _{T 11} Determine. As a result of the determination, even if the previous count value at step (S318) is not raised, yet, but before the expected processing time _{T 11} elapses, the control unit 136, as before, a dummy ALIVE signal Transmit to the parent control computer 110. The data processing of the cell A ₁ advances, the value of the data processing is completed counter 146 is incremented by one.

In S322, as the data processing time predicted process time anticipator 140 calculates the expected processing time _{T 12} according to the data processing of the next cell _{A 2.} The calculation method is the same as in the case of cell A ₁ .

In S324, as the data processing step, CPU 132 executes the data processing of the cell _{A 2.} Then, the data processing of the cell A ₂ proceeds, and when the data processing is completed, the value of the counter 146 is newly added by 1 to “2”.

In S326, as the data processing time predicted process time anticipator 140 calculates the expected processing time _{T 13} according to the data processing of the next cell _{A 3.} The calculation method is the same as in the case of cell A ₁ .

In S328, as the data processing step, CPU 132 executes the data processing of the cell _{A 3.}

In S330, as a counter checking step, the count checking unit 142 checks the value of the counter again 146 further period _{t 0} from the previous count checking.

In S332, as a judging step, the determination unit 144 determines whether the time up to the time of checking the value of the counter 146 in the previous step (S330) after computing the expected processing time _{T 13} exceeds the expected processing time _{T 13} Determine. As a result of the determination, yet, but before the expected processing time _{T 11} elapses, even if the previous step (S330) the counter value is not raised, the control unit 136, as before, a dummy ALIVE signal Transmit to the parent control computer 110. Alternatively, still, but before the expected processing time _{T 11} elapses, the control unit 136 if the previous counter value in step (S330) is increased transmits the ALIVE signal real parent control computer 110. Here, since the counter value has increased from “0” to “2”, a real ALIVE signal is transmitted to the parent control computer 110.

As described above, the process in cell units is advanced, operates similarly to the data processing of the cell A _n is completed in S360. The data processing of the last cell A _n in the frame sorted data upon completion, control unit 136 transmits a completion notification to the parent control computer 110. As shown in FIG. 11, as long as the parent control computer 110 receives the ALIVE signal regardless of whether it is dummy or real within the set time limit T ₀ , the data processing for each cell is completed within the period t ₀ . Even if not, it is determined that the data processing of the child control computer 130 is normal. Then, the normal termination when the data processing of the last cell A _n is completed. On the other hand, a timeout error occurs in the following cases.

FIG. 12 is a flowchart illustrating a part of the process flow of the parent control computer and the child control computer when a timeout error occurs in the third embodiment.
In FIG. 12, for example, the expected processing time _{T 1k} cell _{A k} is calculated in S340, it shows a case where data processing of the cell _{A k} is running in S342. Further, k is 1 ≦ k ≦ n.

In S344, as a counter checking step, the count checking unit 142 checks the value of the counter again 146 further period _{t 0} from the previous count checking.

In S346, as a judging step, the determination unit 144 determines whether the time up to the time of checking the value of the counter 146 in the previous step (S344) after computing the expected processing time _{T 1k} exceeds the expected processing time _{T 1k} Determine. As a result of the determination, when the processing of the cell A _k despite the expected processing time T _1k has elapsed has not ended, regardless of whether previous counter value in step (S330) is up, the control unit 136 Sends an error notification to the parent control computer 110. Then, the control unit 136 forcibly ends the data processing of the cell _Ak . When the parent control computer 110 transmits the execution command notification, the determination unit 120 does not receive the ALIVE signal regardless of whether it is dummy or real within the set time limit T ₀ , or when the error notification is received. Judged as having entered an abnormal state. In other words, it is determined as a timeout. When the error notification is received, the data processing in the child control computer 130 is forcibly terminated. However, when the ALIVE signal is not received within the time limit T ₀ , the data processing in the child control computer 130 is not performed. Since it may be executed in an abnormal state, in this case, the determination unit 120 transmits an end command notification to the child control computer 130. As a result, the control unit 136 forcibly terminates the data processing being executed by the CPU 132. And the determination part 120 outputs the result determined to be timeout. The output result is displayed on a monitor (not shown) or output to the outside. The output result may be stored in the magnetic disk device 170.

  As described above, even when managed by the watchdog counter, it is possible to determine the timeout with the expected processing time corresponding to the data scale. Therefore, it is possible to suppress delays in countermeasures against erroneous determination of time-out errors and abnormal operations.

The drawing unit 150, using the electron beam 200, the predetermined pattern data processing based on the drawing data processing unit ended the expected processing time T ₁ to draw the sample 101. Others are the same as in the first embodiment.

  In the above description, what is described as “to part” or “to process” can be configured by a computer-operable program. Or you may make it implement by not only the program used as software but the combination of hardware and software. Alternatively, a combination of hardware and firmware may be used. When configured by a program, the program is recorded on a recording medium such as a magnetic disk device 109, a magnetic tape device (not shown), FD, CD, DVD, MO, or ROM.

  The embodiments have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, in each of the embodiments described later, the predicted time is set as the timeout time, and when the timeout occurs, the abnormal termination process is immediately performed. However, the present invention is not limited to this. Instead, it is also preferable to perform a retry process when a timeout occurs. In that case, when calculating the expected time of data processing, the entire target processing data is divided into a plurality of steps. And it is good to store the record of the processing completion ratio in a step. According to this configuration, when the processing is actually halfway, it is possible to calculate the processing time at the time of retrying by comparing with information on how far the data processing has progressed. When data is partially created, the expected end time may be obtained based on the data amount. It is also preferable to set a correction coefficient for the expected processing time at the time of retrying N times in advance and retry the corrected time as a timeout time. For example, at the second retry, the time is set to twice the original expected processing time. At the time of the third retry, the time is set to four times the original expected processing time. At the time of the fourth retry, the time is set to five times the original expected processing time. Thus, it is preferable to set a timeout time and retry.

  In addition, although descriptions are omitted for parts and the like that are not directly required for the description of the present invention, such as a device configuration and a control method, a required device configuration and a control method can be appropriately selected and used. For example, although the description of the control unit configuration for controlling the drawing apparatus 100 is omitted, it goes without saying that the required control unit configuration is appropriately selected and used.

  In addition, all charged particle beam drawing apparatuses, charged particle beam drawing methods, and drawing data processing methods that include elements of the present invention and that can be appropriately modified by those skilled in the art are included in the scope of the present invention.

1 is a conceptual diagram illustrating a configuration of a drawing apparatus according to Embodiment 1. FIG. 6 is a diagram illustrating an example of a hierarchical structure of drawing data according to Embodiment 1. FIG. 6 is a diagram illustrating an example of drawing data according to Embodiment 1. FIG. FIG. 3 is a flowchart diagram illustrating a main process of a processing flow of a parent control computer and a child control computer in the first embodiment. 6 is a diagram illustrating an example of a relationship between a memory usage amount and a processing data amount per unit time in Embodiment 1. FIG. FIG. 10 is a flowchart illustrating a part of a process flow of a parent control computer and a child control computer when a timeout error occurs in the first embodiment. 6 is a conceptual diagram illustrating a configuration of a drawing apparatus according to Embodiment 2. FIG. FIG. 10 is a flowchart showing the main steps of the processing flow of the parent control computer and the child control computer in the second embodiment. FIG. 10 is a flowchart illustrating a part of a process flow of a parent control computer and a child control computer when a timeout error occurs in the second embodiment. FIG. 10 is a conceptual diagram illustrating a configuration of a drawing apparatus according to a third embodiment. FIG. 10 is a flowchart showing the main steps of the processing flow of the parent control computer and the child control computer in the third embodiment. FIG. 20 is a flowchart illustrating a part of the process flow of the parent control computer and the child control computer when a timeout error occurs in the third embodiment. It is a conceptual diagram for demonstrating operation | movement of the conventional variable shaping type | mold electron beam drawing apparatus.

Explanation of symbols

10 chip 12 drawing data 14 frame 16 block 18 cell 19 figure 20 chip configuration file 22 cell arrangement data file 24 link data file 26 cell pattern data file 100 drawing apparatus 101, 340 sample 102 electron column 103 drawing room 105 XY stage 109, 170 Magnetic disk device 110 Parent control computer 112 Distribution unit 114 Start unit 116, 140 Time prediction unit 118 Command unit 120, 144 Judgment unit 122, 138 Parameter calculation unit 124, 134 Memory 130 Child control computer 132 CPU
136 Control unit 142 Counter check unit 146 Counter 150 Drawing unit 160 Control unit 172 Control circuit 200 Electron beam 201 Electron gun 202 Illumination lenses 203 and 410 First aperture 206 and 420 Second aperture 204 Projection lens 205 and 208 Deflector 207 Objective lens 330 Electron beam 411 Aperture 421 Variable shaping aperture 430 Charged particle source

Claims (5)

A storage unit for storing drawing data for drawing a predetermined pattern on the sample;
A main computer that divides the drawing data into processing units and executes data processing of each processing unit;
A slave computer that receives an execution instruction from the master computer and executes data processing of a predetermined processing unit;
A drawing unit for drawing a predetermined pattern on the sample based on the drawing data of the predetermined processing unit in which data processing has been normally completed;
With
Either one of the main computer and the slave computer calculates the expected processing time for data processing of each processing unit for each processing unit of the drawing data,
The slave computer terminates data processing as an error when data processing of the predetermined processing unit does not end within the expected processing time. The slave computer transmits a predetermined signal to the master computer if the expected processing time has not yet elapsed when the data processing of the predetermined processing unit is not completed within the first period,
As long as the main computer receives the predetermined signal within the second period, even if the data processing of the predetermined processing unit is not completed within the first period, the data processing of the slave computer The drawing apparatus according to claim 1, wherein the image is determined to be normal.   The expected processing time is defined by a function based on at least one of a data type, a data amount, a cell number, a cell arrangement number, a CPU performance for data processing, a CPU number, and a memory amount. The drawing apparatus according to claim 1 or 2. A storage unit for storing drawing data for drawing a predetermined pattern on the sample;
An execution command unit that transmits an execution command for executing data processing of each processing unit for each processing unit of the drawing data;
For each processing unit of the drawing data, a time prediction unit that calculates an expected processing time for data processing of each processing unit;
An execution unit that receives the execution instruction and executes data processing of a predetermined processing unit;
A drawing unit for drawing a predetermined pattern on the sample based on drawing data of the predetermined processing unit in which data processing is completed within the expected processing time;
A drawing apparatus comprising: Dividing drawing data for drawing a predetermined pattern on a sample for each processing unit, and transmitting an execution command for executing data processing of a predetermined processing unit;
Calculating an expected processing time for data processing of the predetermined processing unit;
Receiving the execution instruction and executing data processing of a predetermined processing unit;
When the data processing of the predetermined processing unit does not end within the expected processing time, determining a timeout error and outputting the result;
A data processing method for drawing data, comprising:

Images