JP2009070737A - Method for manufacturing display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a display device, which enables a display panel in which a protective film is formed on an electrode layer of a light-emitting element, to have an improved passivation based on the protective film while suppressing the occurrence of interlayer peeling and cracks of the electrode layer. <P>SOLUTION: A transparent insulating passivation film 19 is formed to cover all over an insulating substrate 11 including display pixels PIX, and then the passivation film 19 is subjected to heating processing in a nitrogen gas atmosphere under a predetermined condition so as to perform a stress relaxing treatment for relaxing internal stress of the film 19. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a display device, and more particularly to a method for manufacturing a display device including a display panel in which a plurality of self-luminous elements such as organic electroluminescence elements are arranged as display pixels.

  2. Description of the Related Art In recent years, a display panel (organic EL display panel) in which organic electroluminescence elements (hereinafter abbreviated as “organic EL elements”), which are self-luminous elements, are two-dimensionally arranged as display devices for electronic devices such as mobile phones and portable music players. ) Is known. In particular, in an organic EL display panel to which an active matrix driving system is applied, the display response speed is faster and the viewing angle dependency is smaller than that of a liquid crystal display device. Therefore, it is possible to further reduce the thickness and weight. Therefore, application to various electronic devices is expected in the future.

  As is well known, an organic EL element is roughly an anode (anode) electrode, an organic EL layer composed of a hole transport layer, a light emitting layer and an electron transport layer, and a cathode (cathode) electrode on one side of a glass substrate or the like. And a positive voltage injected into the organic EL layer by applying a positive voltage to the anode electrode and a negative voltage to the cathode electrode so as to exceed the light emission threshold value. Light (excitation light) is emitted based on the energy generated when the holes and electrons recombine.

  Here, the uppermost layer of the substrate on which the organic EL element is formed (that is, the upper layer of the cathode electrode of the organic EL element) is provided with a protective film or a sealing substrate, so that moisture or oxygen can enter from the outside. Etc. is prevented, and the quality of the display panel (organic EL element) is maintained well over a long period of time. Note that a display panel in which a protective film (passivation film) or a sealing substrate is provided as the uppermost layer is described in, for example, Patent Document 1 and the like.

JP 2005-011793 A (Page 8, Page 11, FIG. 1)

  As described above, in a display panel (display device) in which a protective film is formed on the uppermost layer of a substrate on which an organic EL element is formed, in order to improve the passivation property for preventing moisture and oxygen from entering from the outside. When the protective film is formed thicker than a certain thickness, the electrode layer (for example, cathode electrode) that forms the organic EL element and the protective film are laminated in close contact with each other with internal stress remaining. As a result, peeling and cracks occur in the electrode layer, resulting in deterioration of element characteristics and a decrease in the reliability of the display device.

  Therefore, in view of the above-described problems, the present invention provides a display panel in which a protective film is formed on an electrode layer of a light emitting element (organic EL element), while improving the passivation property of the protective film and delamination of the electrode layer. Another object of the present invention is to provide a method for manufacturing a display device that can suppress the generation of cracks.

The invention according to claim 1 includes a step of forming a light emitting element on one surface side of the substrate, a step of forming an insulating protective film so as to cover the one surface side of the substrate including the light emitting element, and the protective film. And a heat treatment in an atmospheric gas under a predetermined condition after the film formation.
According to a second aspect of the present invention, in the method for manufacturing a display device according to the first aspect, the step of heat-treating the protective film is performed in an inert gas atmosphere.
According to a third aspect of the present invention, in the method for manufacturing a display device according to the second aspect, in the step of heat-treating the protective film, the pressure of the atmospheric gas is set to approximately 0.2 atm or more. To do.
According to a fourth aspect of the present invention, in the method for manufacturing a display device according to the second or third aspect, in the step of heat-treating the protective film, the heating temperature is set in a range of approximately 60 to 140 ° C. It is characterized by being.
According to a fifth aspect of the present invention, in the method for manufacturing a display device according to any one of the second to fourth aspects, the step of heat-treating the protective film has a heating time set to approximately 10 minutes or more. Features.
According to a sixth aspect of the present invention, in the method for manufacturing a display device according to any one of the first to fifth aspects, the light emitting element includes an electrode layer made of a transparent conductive metal oxide film, and the protective film Is made of a transparent insulating film formed on the electrode layer.

  According to the method for manufacturing a display device of the present invention, in a display panel in which a protective film is formed on an electrode layer of a light emitting element (organic EL element), delamination of the electrode layer is improved while improving the passivation property of the protective film. And the generation of cracks can be suppressed.

Hereinafter, a method for manufacturing a display device according to the present invention will be described in detail with reference to embodiments.
(Display panel)
First, a display panel (organic EL panel) and display pixels applicable to the display device according to the present invention will be described.

  FIG. 1 is a schematic plan view showing an example of a pixel arrangement state of a display panel applicable to the display device according to the present invention, and FIG. 2 is a diagram of each two-dimensional array on the display panel of the display device according to the present invention. It is an equivalent circuit diagram which shows an example of a circuit structure of a display pixel (a display element and a pixel drive circuit). In the plan view shown in FIG. 1, for convenience of explanation, the arrangement of pixel electrodes and the arrangement of wiring layers provided in each display pixel (color pixel) when the display panel (insulating substrate) is viewed from the view side. In order to drive only the organic EL elements (light emitting elements) of each display pixel to emit light, the display of the transistors and the like in the pixel driving circuit shown in FIG. 2 provided in each display pixel is omitted. In FIG. 1, hatching is shown for convenience in order to clarify the arrangement of the pixel electrode and each wiring layer.

  As shown in FIG. 1, a display device (display panel 10) according to the present invention includes a plurality of supply voltage lines arranged in a column direction (vertical direction in the drawing) on one surface side of an insulating substrate 11 such as a glass substrate. A region that includes (for example, an anode line) La and a plurality of common voltage lines (for example, cathode lines) Lc arranged in the row direction (left and right in the drawing) and includes the intersections of the supply voltage line La and the common voltage line Lc. Each display pixel PIX (sub-pixels PXr, PXg, PXb) is arranged.

  Here, when the display device provided with the display panel 10 is compatible with color display, for example, sub-pixels of three colors of red (R), green (G), and blue (B) (hereinafter referred to as convenience). PXr, PXg, and PXb are repeatedly arranged in the row direction (horizontal direction in the drawing), and a plurality of color pixels PXr, PXg, and PXb of the same color are arranged in the column direction (vertical direction in the drawing). Is done. In this case, the RGB three-color pixels PXr, PXg, and PXb adjacent in the row direction (left and right in the drawing) are combined into one display pixel PIX. In the case of a display device provided with a display panel (monocolor display panel) that emits only single color light, one color pixel becomes one display pixel PIX.

  In addition, pixel electrodes (for example, anode electrodes) 15 are formed in the formation regions of the respective color pixels PXr, PXg, and PXb of the display pixel PIX, and in the column direction (vertical direction in the drawing) in parallel with the supply voltage line La. In addition, a data line Ld is arranged, and a selection line Ls is arranged in the row direction (left and right direction in the drawing) in parallel with the common voltage line Lc.

  A specific circuit configuration of each color pixel PXr, PXg, PXb of the display pixel PIX is, for example, as shown in FIG. 2, a pixel driving circuit (or an amorphous silicon thin film transistor, etc.) on an insulating substrate 11 (or an amorphous silicon thin film transistor). A pixel circuit) DC, and an organic EL element (light-emitting element) OEL that emits light when a light emission drive current generated by the pixel drive circuit DC is supplied to the pixel electrode 15.

  For example, as shown in FIG. 2, the pixel drive circuit DC includes a transistor (select transistor) Tr11 having a gate terminal connected to the selection line Ls, a drain terminal connected to the data line Ld, and a source terminal connected to the contact N11, and a gate terminal. Includes a transistor (drive transistor) Tr12 having a drain terminal connected to the supply voltage line La, a source terminal connected to the contact N12, and a capacitor Cs connected between the gate terminal and the source terminal of the transistor Tr12. I have.

  Here, n-channel field effect transistors (thin film transistors) are applied to the transistors Tr11 and Tr12. Note that if the transistors Tr11 and Tr12 are p-channel transistors, the source terminal and the drain terminal are opposite to each other. The capacitor Cs is a parasitic capacitance formed between the gate and the source of the transistor Tr12, an auxiliary capacitance additionally provided between the gate and the source, or a capacitance component composed of these parasitic capacitance and auxiliary capacitance. It is. Therefore, if the transistor Tr12 is a p-channel type, one of the capacitors Cs is connected not to the organic EL element OLED side but to the power supply voltage line Lv side.

  The organic EL element OLED has an anode terminal (pixel electrode 15 serving as an anode electrode) connected to the contact N12 of the pixel drive circuit DC and a cathode terminal (counter electrode 17 serving as a cathode electrode) connected to a common voltage line Lc. Yes. Here, the counter electrode 17 serving as the cathode electrode is a single electrode layer (solid) so as to face each pixel electrode 15 of the plurality of display pixels PIX two-dimensionally arranged on the insulating substrate 11. Electrode). Details will be described later.

  The selection line Ls shown in FIGS. 1 and 2 is connected to a selection driver (not shown), and a plurality of display pixels PIX (color pixels PXr, PXg) arranged in the row direction of the display panel 10 at a predetermined timing. , PXb) is applied with a selection signal Ssel for setting the selected state, and the data line Ld is connected to a data driver (not shown), and the display data is converted to the display data at a timing synchronized with the selected state of the display pixel PIX. A corresponding gradation signal Vpix is applied. Here, the gradation signal Vpix is a voltage signal for setting the light emission luminance gradation of the organic EL element OLED.

  The supply voltage line La is connected directly or indirectly to a predetermined high potential power source, for example, and display data is displayed on the pixel electrode 15 of the organic EL element OLED provided in each display pixel PIX (color pixels PXr, PXg, PXb). A predetermined high voltage (supply voltage Vdd) having a potential higher than the common voltage Vcom applied to the counter electrode 17 of the organic EL element OLED is applied in order to flow a light emission drive current according to the voltage, and the common voltage line Lc. Are connected directly or indirectly to a predetermined low potential power source, for example, and a predetermined low voltage (common voltage Vcom; for example, ground potential Vgnd) is commonly applied to the plurality of organic EL elements OLED.

  That is, in the pixel drive circuit DC shown in FIG. 2, both ends of the set of the transistor Tr12 and the organic EL element OLED connected in series in each display pixel PIX (the drain terminal of the transistor Tr12 and the cathode terminal of the organic EL element OLED). A high supply voltage Vdd and a constant common voltage Vcom are respectively applied to the organic EL element OLED so that a forward bias is applied to the organic EL element OLED so that the organic EL element OLED can emit light. Further, according to the gradation signal Vpix Thus, the current value of the light emission drive current flowing through the organic EL element OLED is controlled.

  In the drive control operation in the display pixel PIX having such a circuit configuration, first, a selection signal Ssel of a selection level (on level; for example, high level) is applied to a selection line Ls from a selection driver (not shown). As a result, the transistor Tr11 is turned on and set to the selected state. In synchronization with this timing, control is performed so that a gradation signal Vpix having a voltage value corresponding to display data is applied to the data line Ld from a data driver (not shown). As a result, a potential corresponding to the gradation signal Vpix is applied to the contact N11 (that is, the gate terminal of the transistor Tr12) via the transistor Tr11.

  In the pixel drive circuit DC having the circuit configuration shown in FIG. 2, the current value of the drain-source current of the transistor Tr12 (that is, the light emission drive current flowing through the organic EL element OLED) is the potential difference between the drain-source and the gate. -Determined by the potential difference between the sources. Here, since the supply voltage Vdd applied to the drain terminal (drain electrode) of the transistor Tr12 and the common voltage Vcom applied to the cathode terminal (cathode electrode) of the organic EL element OLED are fixed values, the drain of the transistor Tr12 The potential difference between the sources is fixed beforehand by the supply voltage Vdd and the common voltage Vcom. Since the potential difference between the gate and source of the transistor Tr12 is uniquely determined by the potential of the gradation signal Vpix, the current value of the current flowing between the drain and source of the transistor Tr12 is controlled by the gradation signal Vpix. be able to.

  Thereby, the transistor Tr12 is turned on in a conductive state corresponding to the potential of the contact N11 (that is, a conductive state corresponding to the gradation signal Vpix), and the transistor Tr12 and the organic EL element OLED are switched from the supply voltage Vdd on the high potential side. Since a light emission driving current having a predetermined current value flows through the low potential side common voltage Vcom (ground potential Vgnd), the organic EL element OLED has a luminance gradation corresponding to the gradation signal Vpix (that is, display data). Lights up. At this time, charges are accumulated (charged) in the capacitor Cs between the gate and the source of the transistor Tr12 based on the gradation signal Vpix applied to the contact N11.

  Next, by applying a selection signal Ssel of a non-selection level (off level; for example, low level) to the selection line Ls, the transistor Tr11 of the display pixel PIX is turned off and set to a non-selection state, and the data line Ld and the pixel The drive circuit DC (specifically, the contact N11) is electrically disconnected. At this time, the charge accumulated in the capacitor Cs is held, so that the voltage corresponding to the gradation signal Vpix is held at the gate terminal of the transistor Tr12 (that is, the potential difference between the gate and the source is held). It becomes a state.

  Accordingly, similarly to the light emission operation in the selected state, a predetermined light emission drive current flows from the supply voltage Vdd to the organic EL element OLED via the transistor Tr12, and the light emission operation state is continued. This light emitting operation state is controlled so as to continue, for example, for one frame period until the next gradation signal Vpix is applied (written). Then, such a drive control operation is sequentially executed for every row, for example, for all the display pixels PIX (each color pixel PXr, PXg, PXb) two-dimensionally arranged on the display panel 10, thereby obtaining desired image information. An image display operation to be displayed can be executed.

  In FIG. 2, as the pixel drive circuit DC provided in the display pixel PIX, the light emission drive that flows through the organic EL element OLED by adjusting (specifying) the voltage value of the gradation signal Vpix to be written according to the display data. Although the circuit configuration corresponding to the voltage-designated gradation control method for controlling the current value of the current to emit light at a predetermined luminance gradation is shown, the current value of the current supplied (written) according to the display data By adjusting (specifying), the current value of the light emission drive current that flows to the organic EL element OLED is controlled to have a circuit configuration of a current designation type gradation control system that performs light emission operation at a predetermined luminance gradation. There may be.

  Further, in the pixel driving circuit DC shown in FIG. 2, a circuit configuration in which two n-channel transistors Tr11 and Tr12 are applied is shown, but the display panel according to the present invention is not limited to this. It may have another circuit configuration to which three or more transistors are applied, a circuit configuration to which only a p-channel transistor is applied, or both n-channel and p-channel channels A transistor having polarity may be mixed.

  Here, as shown in FIG. 2, when only an n-channel transistor is applied as the pixel driving circuit DC, the operation characteristics are stabilized by using the amorphous silicon semiconductor manufacturing technology that has already been established. A transistor can be easily manufactured, and a pixel driving circuit in which variation in light emission characteristics of the display pixel is suppressed can be realized.

(Device structure of display pixel)
Next, a specific device structure (planar layout and cross-sectional structure) of the display pixel (light emission drive circuit and organic EL element) having the circuit configuration as described above will be described.
FIG. 3 is a plan layout diagram showing an example of display pixels applicable to the display panel according to the present invention. Here, an example of a planar layout of one specific color pixel among the red (R), green (G), and blue (B) color pixels PXr, PXg, and PXb of the display pixel PIX shown in FIG. Show. In FIG. 3, the layer in which each transistor, wiring layer, and the like of the pixel driving circuit DC are formed is shown in the center, and hatching is made for convenience in order to clarify the arrangement and planar shape of each wiring layer and each electrode. This is shown. 4 and 5 are respectively the IVA-IVA line (in this specification, the symbol corresponding to the Roman numeral “4” shown in FIG. 3) in the display pixel PIX having the planar layout shown in FIG. And “V” (for convenience, “V” is used as a symbol corresponding to the Roman numeral “5” shown in FIG. 3 in this specification). It is a schematic sectional drawing which shows the cross section along.

  Specifically, the display pixels PIX (color pixels PXr, PXg, or PXb) shown in FIG. 2 are pixel formation regions (organic pixels in the color pixels PXr, PXg, and PXb) set on one surface side of the insulating substrate 11. In the EL element formation region (Rpx), for example, the selection line Ls and the common voltage line Lc are arranged so as to extend in the row direction (horizontal direction in the drawing) in the upper and lower edge regions of the planar layout shown in FIG. In addition, the data line Ld and the supply voltage line La are arranged so as to extend in the column direction (vertical direction in the drawing) in the left and right edge regions of the above-described planar layout, orthogonal to these lines Ls and Lc. It is installed. Further, the right edge region of the planar layout extends in the column direction (vertical direction in the drawing) and overlaps the above-described transistors Tr11 and Tr12 and the supply voltage line La in a substantially planar manner. A bank BKy serving as a boundary with the adjacent display pixel PIX is disposed on the right side. The bank BKy and the bank BKx formed integrally with the common voltage line Lc will be described in detail later.

  Here, for example, as shown in FIGS. 3 to 5, the selection line Ls is formed on the insulating substrate 11, and a gate metal layer for forming the gate electrodes Tr11g and Tr12g of the transistors Tr11 and Tr12 is patterned. Thus, the gate electrode Tr11g is formed in the same process as the gate electrodes Tr11g and Tr12g and integrally with the gate electrode Tr11g of the transistor Tr11.

  The signal line layer Ldx that protrudes in the row direction from the data line Ld and the data line Ld is provided above the selection line Ls and the gate electrodes Tr11g and Tr12g, and the source electrodes Tr11s and Tr12s of the transistors Tr11 and Tr12, By patterning the source and drain metal layers for forming the drain electrodes Tr11d and Tr12d, the source electrodes Tr11s and Tr12s and the drain electrodes Tr11d and Tr12d are formed in the same process and integrally with the source electrode Tr11s of the transistor Tr11. Is done. At this time, the drain electrode Tr11d of the transistor Tr11 is connected to the gate electrode Tr12g of the transistor Tr12 through the contact hole CH11 provided in the gate insulating film 12.

  The supply voltage line La is provided above the data line Ld (including the signal wiring layer Ldx), the source electrodes Tr11s and Tr12s, and the drain electrodes Tr11d and Tr12d, and is provided on the protective insulating film 13 and the planarizing film 14. It is buried in the formed wiring trench and is electrically connected to the upper surface of the drain electrode Tr12d. Further, the common voltage line Lc is provided on the upper layer side of the supply voltage line La and on the interlayer insulating film 18b formed on the planarizing film 14 so as to continuously protrude from the surface of the insulating substrate 11. ing.

  Thus, as shown in FIGS. 4 and 5, the display pixel PIX includes a plurality of transistors Tr11 and Tr12 and capacitors of the pixel drive circuit DC (see FIG. 2) provided in the display pixel PIX on the insulating substrate 11. Various wiring layers including Cs, the selection line Ls, and the data line Ld are provided, and the upper layers thereof are provided via the protective insulating film 13 and the planarization film 14 which are sequentially formed so as to cover the transistors Tr11 and Tr12 and the wiring layer. Further, a pixel electrode (for example, an anode electrode; a lower electrode) 15 connected to the pixel driving circuit DC and supplied with a predetermined light emission driving current, at least a hole transport layer (carrier transport layer), a light emitting layer, and an electron transport layer (carrier) An organic EL element OLED composed of an organic EL layer 16 composed of a transport layer) and a counter electrode (for example, cathode electrode) 17 to which a common voltage Vcom is applied is formed. To have.

  In the present embodiment, in particular, a transparent insulating passivation film 19 is formed so as to cover the entire area of the insulating substrate 11 including the display pixels PIX, and the passivation film 19 is at least after the film formation. It has a film characteristic in which residual stress is relaxed by heat treatment in an atmosphere gas of a predetermined condition. A specific method for manufacturing the passivation film 19 applied to this embodiment will be described in detail later.

  4 and 5, two insulating films, a protective insulating film 13 and a planarizing film 14, are provided between the transistors Tr11 and Tr12 and the wiring layer and the upper organic EL element OLED (pixel electrode 15). However, the present invention is not limited to this, and for example, it may be composed of only one planarization film having a function as a protective insulating film, or three layers. It may have a multilayer structure including the above insulating films.

  More specifically, the pixel drive circuit DC is formed, for example, as shown in FIG. 3, by projecting in the row direction from the selection line Ls (or the data line Ld) in which the transistor Tr11 shown in FIG. 2 is arranged in the row direction. Are arranged so that the channel width direction extends along the signal wiring layer Ldx), and the transistor Tr12 is arranged so that the channel width direction extends along the supply voltage line La arranged in the column direction. ing.

  Here, each of the transistors Tr11 and Tr12 has a well-known field effect type thin film transistor structure, and each of the gate electrodes Tr11g and Tr12g formed on the insulating substrate 11 and the gate electrode through the gate insulating film 12. A semiconductor layer SMC formed in a region corresponding to Tr11g and Tr12g, and a reverse having source electrodes Tr11s and Tr12s and drain electrodes Tr11d and Tr12d formed so as to extend to both ends of a channel of the semiconductor layer SMC It has a staggered structure.

  Note that, on the channel of the semiconductor layer SMC in which the source electrodes Tr11s and Tr12s of the transistors Tr11 and Tr12 and the drain electrodes Tr11d and Tr12d are arranged to face each other, in order to prevent etching damage to the semiconductor layer SMC in the manufacturing process. A channel protective layer (block layer) BL of silicon oxide or silicon nitride is formed, and the semiconductor layer SMC on both sides of the channel of the semiconductor layer SMC where the source electrodes Tr11s, Tr12s and the drain electrodes Tr11d, Tr12d are in contact An impurity layer OHM for realizing ohmic connection between the layer SMC and the source electrodes Tr11s and Tr12s and the drain electrodes Tr11d and Tr12d is formed. The impurity layer OHM is an amorphous silicon layer containing n-type impurity ions.

  Then, to correspond to the circuit configuration of the pixel drive circuit DC shown in FIG. 2, the transistor Tr11 has a gate electrode Tr11g formed integrally with the selection line Ls as shown in FIGS. The electrode Tr11s is formed integrally with the data line Ld via the signal wiring layer Ldx.

  3 to 5, the transistor Tr12 is connected to the drain electrode Tr11d of the transistor Tr11 through a contact hole CH11 provided in the gate insulating film 12, and the drain electrode Tr12s is connected to the transistor Tr12. The source electrode Tr12d is connected to the supply voltage line La, and is connected to the pixel electrode 15 of the organic EL element OLED through the contact metal MTL embedded in the contact hole CH12 formed in the protective insulating film 13 and the planarizing film 14. ing.

  Here, the supply voltage line La (anode line) has a thick film wiring structure embedded in a wiring groove formed in the protective insulating film 13 and the planarizing film 14, as shown in FIGS. For example, it is formed in the same process as the contact metal MTL buried in the contact hole CH12.

  Then, on the planarization film 14 in each pixel formation region Rpx, as shown in FIGS. 4 and 5, for example, a pixel electrode 15 that becomes an anode electrode, an organic layer that includes at least a hole transport layer, a light emitting layer, and an electron transport layer. An organic EL element is provided which is composed of an EL layer 16 and a solid electrode, and is formed by sequentially laminating a counter electrode 17 serving as a cathode electrode, for example. Here, in the present embodiment, the pixel electrode 15 has at least light reflection characteristics, and the counter electrode 17 has a top emission type light emitting structure having light transmittance.

  Further, between each pixel formation region Rpx (a boundary region between the formation regions of the organic EL elements OLED of each display pixel PIX), a formation region of the organic EL elements OLED (strictly, a formation region of the organic EL layer 16) is provided. Banks (partition walls) BKx and BKy for definition are provided so as to continuously protrude from the upper surface of the planarization film 14.

  For example, as shown in FIGS. 3 and 4, the bank BKy is formed in the column direction of the display panel 10 (insulating substrate 11) and insulates the pixel electrodes 15 formed in the pixel formation region Rpx of each display pixel PIX. It has a laminated structure including an interlayer insulating film 18a to be formed and an insulating bank portion 18c formed in the column direction of the display panel 10 on the interlayer insulating film 18a. Further, for example, as shown in FIGS. 3 and 5, the bank BKx is formed in the row direction of the display panel 10 (insulating substrate 11), and the pixel electrodes 15 formed in the pixel formation region Rpx of each display pixel PIX. And a conductive bank portion 18d formed in the row direction of the display panel 10 on the interlayer insulating film 18b. Here, the conductive bank portion 18d corresponds to the above-described common voltage line Lc.

More specifically, the banks BKx and BKy are formed on the pixel electrode 15 of the organic EL element OLED from the upper surface of the planarizing film 14 exposed in the vicinity of the boundary region between the display pixels PIX (pixel electrodes 15) adjacent to each other. Interlayer insulating films 18a and 18b made of a silicon nitride film (SiN), a silicon oxide film (SiO ₂ ) or the like are provided so as to partially extend, and on the interlayer insulating films 18a and 18b, for example, photosensitive The insulating bank portion 18c made of a resin material and the like, and the conductive bank portion 18d having at least a surface made of a metal material, for example, are stacked so as to protrude in the thickness direction.

  As shown in FIGS. 4 and 5, the counter electrode 17 provided in common to each display pixel PIX is provided so as to extend not only on each pixel formation region Rpx but also on the banks BKx and BKy. Furthermore, it is joined so as to be electrically connected to the conductive bank portion 18d made of a metal material or the like. As a result, the conductive bank portion 18d forming the bank BKx can also be used as a common voltage line (for example, cathode line) Lc.

  In the display panel 10 shown in FIG. 1, as shown in FIGS. 3 to 5, by arranging the banks BKx and BKy having the laminated structure so as to have a planar pattern of a fence shape or a lattice shape, A pixel formation region Rpx of each display pixel PIX (that is, a region in which the organic EL layer 16 of the organic EL element OLED is formed in each pixel formation region Rpx) is defined.

  In the panel structure of the display device according to the present embodiment, as shown in FIGS. 4 and 5, on the insulating substrate 11 on which the pixel driving circuit DC, the organic EL element OLED, and the banks BKx and BKy are formed. Although the panel structure in which only the transparent passivation film 19 is formed is shown, the present invention is not limited to this, and a glass substrate or the like is provided so as to face the insulating substrate 11 with the passivation film 19 interposed therebetween. The sealing substrate which consists of may be further joined.

  In such a display panel 10, each circuit element such as the transistors Tr11 and Tr12 provided in the lower layer of the display panel 10 (the layer on the insulating substrate 11 side of the organic EL element OLED), the selection line Ls and the data line. In the pixel driving circuit DC including wiring layers such as Ld and supply voltage line (anode line) La, the pixel driving circuit DC has a predetermined current value based on the gradation signal Vpix corresponding to the display data supplied through the data line Ld. A light emission driving current flows between the source and drain of the transistor Tr12 and is supplied from the transistor Tr12 (source electrode Tr12s) to the pixel electrode 15 of the organic EL element OLED through the contact hole CH12 (contact metal MTL). Organic E of each display pixel PIX (each color pixel PXr, PXg, PXb) Element OLED emit light at a desired luminance gradation corresponding to the display data.

  At this time, in the display panel 10 shown in the present embodiment, the pixel electrode 15 has light reflection characteristics (high reflectance with respect to visible light), and the counter electrode 17 has light transmittance (with respect to visible light). By having a high transmittance, light emitted from the organic EL layer 16 of each display pixel PIX (each color pixel PXr, PXg, PXb) passes through the counter electrode 17 having optical transparency (FIG. 4, The light is directly emitted to the upper part of FIG. 5, reflected by the pixel electrode 15 having light reflection characteristics, and emitted to the visual field side through the counter electrode 17.

  Thus, since the display panel 10 according to the present embodiment has a top emission type light emitting structure, each circuit element and wiring layer of the pixel driving circuit DC formed on the insulating substrate 11 are The organic EL element OLED formed on the protective insulating film 13 and the planarizing film 14 can be disposed so as to overlap in a plane. Accordingly, it is possible to increase the pixel aperture ratio, reduce power consumption and extend the panel life, and increase the degree of freedom in layout design of the pixel drive circuit.

(Manufacturing method of display device)
Next, a method for manufacturing the above-described display device (display panel) will be described.
6 to 9 are process cross-sectional views illustrating an example of a method for manufacturing a display device (display panel) according to the present embodiment. Here, a part of the panel structure of the IVA-IVA cross section shown in FIG. 4 and the VB-VB cross section shown in FIG. In addition, as a light-emitting element provided in a display pixel, an organic EL element having an organic EL layer formed by applying a solution (organic compound-containing liquid) containing a high molecular or low molecular organic material is applied. explain. FIG. 10 is a schematic view showing an example of the element structure of the organic EL element OLED formed in the display device (display panel) according to the present embodiment.

  In the manufacturing method of the display device (display panel) described above, first, as shown in FIG. 6A, display pixels PIX (each color) set on one surface side (the upper surface side in the drawing) of the insulating substrate 11 such as a glass substrate. In the pixel pixel PXr, PXg, PXb) formation region (pixel formation region) Rpx, the above-described pixel drive circuit (see FIGS. 2 and 3) DC transistors Tr11, Tr12, capacitor Cs, selection line Ls, data line Ld (signal) A wiring layer such as a wiring layer Ldx) is formed (pixel drive circuit forming step).

  Specifically, on the insulating substrate 11, the same gate metal layer is patterned on the gate electrodes Tr11g and Tr12g and the selection line Ls (see FIG. 5) formed integrally with the gate electrode Tr11g. Then, a gate insulating film 12 is formed over the entire area of the insulating substrate 11.

  Next, in a region corresponding to each of the gate electrodes Tr11g and Tr12g on the gate insulating film 12, a semiconductor layer SMC made of, for example, amorphous silicon or polysilicon, and a channel protective layer (block layer) made of silicon oxide, silicon nitride, or the like. BL is formed, and source electrodes Tr11s and Tr12s and drain electrodes Tr11d and Tr12d are formed on both ends of the semiconductor layer SMC via an impurity layer OHM for ohmic connection.

  At this time, the data line Ld and the signal wiring layer Ldx (see FIGS. 3 to 5) connected to the source electrode Tr11s are simultaneously formed by patterning the same source and drain metal layers. Further, the drain electrode Tr11d of the transistor Tr11 is connected to the gate electrode Tr12g of the transistor Tr12 through a contact hole CH11 formed in the gate insulating film 12.

  Note that the source electrodes Tr11s and Tr12s and the drain electrodes Tr11d and Tr12d, the selection line Ls, and the data line Ld (including the signal wiring layer Ldx) of the transistors Tr11 and Tr12 described above reduce wiring resistance and migration. For the purpose, for example, it may have a laminated wiring structure composed of an aluminum alloy layer and a transition metal layer.

  Next, as shown in FIG. 6B, protection made of silicon nitride (SiN) or the like so as to cover the entire area of one surface of the insulating substrate 11 including the transistors Tr11 and Tr12, the selection line Ls, and the data line Ld. After sequentially forming the insulating film 13 and the planarizing film 14 made of a photosensitive organic material, the planarizing film 14 is exposed and developed and patterned, and the protective insulating film 13 is used using the planarizing film 14 as a mask. Are etched to form a contact hole CH12 in which the upper surface of the source electrode Tr12s of the transistor Tr12 is exposed, and an upper surface of the drain electrode Tr12d of the transistor Tr12, and a wiring groove CH13 corresponding to the wiring pattern of the supply voltage line La. Form at the same time.

  Next, as shown in FIG. 6C, a metal material is embedded in the contact hole CH12 and the wiring groove CH13 by using a plating method, etc., and a contact metal MTL is formed in the contact hole CH12, and a thick film is formed in the wiring groove CH13. A supply voltage line La having a wiring structure is formed.

  Here, in FIGS. 6B and 6C, a metal material is embedded in the contact hole CH12 and the wiring trench CH13 opened in the protective insulating film 13 and the planarizing film 14 stacked on the insulating substrate 11. In the above description, the contact metal MTL and the supply voltage line La are formed. However, when such a manufacturing method is used, the flatness of the upper surface of the planarization film 14 cannot be sufficiently ensured. A manufacturing method may be applied. For example, a metal layer is formed by sputtering or the like on the entire surface of the insulating substrate 11 in which the protective insulating film 13 and the planarizing film 14 are not formed, and wiring patterns of the contact metal MTL and the supply voltage line La are formed. After patterning so as to correspond to the above, a manufacturing method of forming a planarizing film (corresponding to the protective insulating film 13 and the planarizing film 14) by a spin coating method or a dry film may be applied.

In the manufacturing process shown in FIGS. 6B and 6C, a non-photosensitive insulating material may be used as the planarizing film 14, and in this case, for example, the planarizing film 14 is used. A metal film made of aluminum (Al), chromium (Cr), or the like is formed thereon by sputtering or the like, and then the metal film is patterned using photolithography to form a mask (metal mask), and a planarization film 14 and the protective insulating film 13 may be etched using a dry etching method to form the contact hole CH12 and the wiring trench CH13, and then the mask may be removed by a wet etching method.
Furthermore, in the manufacturing process shown in FIGS. 6B and 6C, the case where two insulating layers including the protective insulating film 13 and the planarizing film 14 are stacked on the insulating substrate 11 has been described. It may be composed of only one planarization film, or may be a laminate of a plurality of three or more layers.

  Next, after the contact metal MTL and the supply voltage line La are embedded in the contact hole CH12 and the wiring trench CH13 formed in the planarizing film 14 and the protective insulating film 13, as shown in FIG. For each region Rpx, the pixel electrode 15 electrically connected to the contact metal MTL is formed (pixel electrode forming step).

  Here, the pixel electrode 15 is specifically a reflective metal film having light reflection characteristics such as aluminum (Al), chromium (Cr), silver (Ag), palladium silver (AgPd) based alloy by sputtering or the like. Is formed into a thin film and patterned into a predetermined shape using a photolithography method to form a lower reflective metal layer 15a electrically connected to the contact metal MTL.

Thereafter, tin-doped indium oxide (ITO) or zinc-doped indium oxide (Indium) is coated by sputtering or the like so as to cover the reflective metal layer 15a.
A conductive metal oxide film (having light transmission characteristics) made of a transparent electrode material such as Zinc Oxide (IZO) is formed as a thin film and patterned so as not to expose the upper surface and end surface of the reflective metal layer 15a. Metal oxide layer (hole injection layer) 15b is formed.

  Thus, when patterning the upper metal oxide film, the battery reaction between the metal oxide film (ITO, etc.) and the reflective metal layer 15a is prevented by preventing the lower reflective metal layer 15a from being exposed. It is possible to prevent this from occurring, and it is possible to prevent the reflective metal layer 15a on the lower layer side from being over-etched or subjected to etching damage.

  Here, the reflective metal layer 15a under the pixel electrode 15 is not limited to the panel structure formed on the planarization film 14 as shown in the present embodiment, and the planarization film 14 or the protective insulating film 13 is not limited thereto. It may be formed in the lower layer. In this case, due to the film thickness and optical characteristics (refractive index, etc.) of the flattening film 14, a deviation occurs in the path (optical axis) of light emitted from the organic EL layer 16 described later, Since parallax may occur in the image information, it is preferable to form each layer of the pixel electrode 15 on the planarizing film 14 as shown in FIG.

  Next, a chemical vapor deposition method (CVD method) or the like is used to cover, for example, silicon oxide so as to cover the entire area of one surface side of the insulating substrate 11 including the pixel electrode 15 including the reflective metal layer 15a and the metal oxide layer 15b. After forming an insulating layer made of an inorganic insulating material such as a film or a silicon nitride film, patterning is performed using a photolithography method, so that as shown in FIGS. 4, 5, and 7 (b), An interlayer insulating film 18b which is a boundary region between the pixel electrodes 15 formed in each adjacent pixel forming region Rpx and is a lower layer of the bank BKx extending in the row direction of the display panel 10 (insulating substrate 11) is formed. At the same time, an interlayer insulating film 18 a is formed as a lower layer of the bank BKy extending in the column direction of the display panel 10. As a result, the upper surface of the pixel electrode 15 (metal oxide layer 15b) of each display pixel PIX is located in a region surrounded by the interlayer insulating films 18a and 18b (that is, an opening formed by the interlayer insulating films 18a and 18b). Exposed.

  Next, as shown in FIG. 8A, an insulating bank portion 18c made of, for example, photosensitive polyimide resin or novolac resin is formed on the interlayer insulating film 18a in the column direction of the display panel 10 to form a laminated structure. On the other hand, on the interlayer insulating film 18b, for example, at least the surface is made of copper (Cu), silver (Au), or a metal having a low resistance such as a single metal or an alloy mainly composed of these. Bank portions 18d are formed in the row direction of the display panel 10 to form a bank BKx having a stacked structure (partition wall forming step).

  Specifically, the insulating bank portion 18c performs exposure and development processing on the photosensitive polyimide film formed so as to cover the entire area of the one surface side of the insulating substrate 11 including the interlayer insulating film 18a. The insulating film 18a is formed by patterning so as to remain with a predetermined pattern. Further, the conductive bank portion 18d specifically includes a metal film such as copper formed by using a plating method or the like so as to cover the entire area of the one surface side of the insulating substrate 11 including the interlayer insulating film 18b. It is formed by patterning so as to remain with a predetermined pattern on the interlayer insulating film 18b by using a photolithography method.

  Here, the insulating bank 18c and the conductive bank 18d may be formed first. Further, as described above, the conductive bank portion 18d forming the bank BKx is also used as the common voltage line Lc for applying the common voltage Vcom to the display pixels PIX that are two-dimensionally arranged on the display panel 10.

  Thereby, the pixel formation region Rpx (strictly speaking, the formation region of the organic EL layer 16 of the organic EL element OLED) of each display pixel PIX arranged in the display panel 10 is defined by being surrounded by the banks BKx and BKy. Therefore, when forming a light emitting layer (electron transporting light emitting layer 16b) that forms the organic EL layer 16 described later, the pixel forming region Rpx of the display pixel PIX (organic EL element OLED) of other colors is separated. Even when the solution or dispersion liquid (organic compound-containing liquid) of the light emitting material is applied, the light emitting material is not mixed between the adjacent display pixels PIX (color pixels PXr, PXg, PXb), and adjacent to each other. Color mixing between color pixels can be prevented.

  In the present embodiment, as the bank BKx arranged in the row direction of the display panel 10, a stacked structure including the interlayer insulating film 18 b and the conductive bank portion 18 d is applied, and in the column direction of the display panel 10. As the bank BKy to be disposed, a panel structure in which a laminated structure including the interlayer insulating film 18a and the insulating bank portion 18c is applied is shown, but the present invention is not limited to this, and for example, the bank BKx is an interlayer insulating film. A laminated structure composed of a film and an insulating bank part may be applied, and a laminated structure composed of an interlayer insulating film and a conductive bank part may be applied as the bank BKy, or both the banks BKx and BKy may be used as an interlayer insulating film. And a conductive bank portion to be a common voltage line Lc arranged on the insulating substrate 11 in a lattice shape. , It may be to define a pixel formation region Rpx of each display pixel PIX of the display panel 10.

  Furthermore, both of the banks BKx and BKy are formed by a laminated structure including an interlayer insulating film and an insulating bank portion, and the insulating substrate 11 is not substantially provided with the common voltage line Lc on the insulating substrate 11. A predetermined common voltage Vcom may be directly applied to the counter electrode 17 formed as a planar electrode (solid electrode) over the entire area. Such a panel structure that does not have the common voltage line Lc is, for example, in a display panel in which a plurality of display pixels PIX are arranged, when the amount of current required during the light emission driving operation of each display pixel (light emitting element) is small. Can be applied well.

  Next, a solution (organic compound-containing liquid) containing, for example, a polymer organic material is applied to the pixel formation region Rpx (formation region of the organic EL element OLED) of each display pixel PIX defined by the banks BKx and BKy. The organic EL layer 16 including at least a hole transport layer, a light emitting layer, and an electron transport layer is formed by applying and drying by heating (carrier transport layer forming step). In the present embodiment, as shown in FIG. 8B, a case will be described in which an organic EL layer 16 composed of two layers of a hole transport layer 16a and an electron transport light emitting layer 16b is formed.

  First, as an organic compound-containing liquid containing an organic polymer-based hole transport material (carrier transport material), for example, polyethylene dioxythiophene / polystyrene sulfonic acid aqueous solution (PEDOT / PSS; polyethylene dioxythiophene PEDOT which is a conductive polymer) And a dispersion liquid in which polystyrene sulfonate PSS as a dopant is dispersed in an aqueous solvent) is applied on the pixel electrode 15 (metal oxide layer 15b) by applying an inkjet method or a nozzle printing method, and then heated. By performing a drying process and removing the solvent, an organic polymer hole transport material is fixed on the pixel electrode 15 to form a hole transport layer 16a as a carrier transport layer.

  Next, as an organic compound-containing liquid containing an organic polymer-based electron transporting light emitting material (carrier transporting material), for example, a light emitting material containing a conjugated double bond polymer such as polyparaphenylene vinylene or polyfluorene is used as tetralin. Then, a solution dissolved in water or an organic solvent such as tetramethylbenzene, mesitylene, xylene, etc. is applied onto the hole transport layer 16a by applying an ink jet method or a nozzle printing method in the same manner as described above, and then dried by heating. By performing the treatment to remove the solvent, the organic polymer electron transporting light emitting material is fixed on the hole transporting layer 16a to form the electron transporting light emitting layer 16b which is the carrier transporting layer and also the light emitting layer. To do.

  In the present embodiment, the case where the organic EL layer 16 has an element structure including two layers of the hole transport layer 16a and the electron transporting light emitting layer 16b has been described, but the present invention is not limited thereto. For example, it may be composed of only one layer of a hole transporting / electron transporting light emitting layer, may be composed of a hole transporting light emitting layer and an electron transporting layer, You may consist of a positive hole transport layer, a light emitting layer, and an electron carrying layer. Furthermore, for example, as shown in FIG. 10, an interlayer 103b having an electron blocking property may be interposed between the hole transport layer 103a and the light emitting layer (or electron transporting light emitting layer) 103c. It may have a laminated structure having other intervening layers between the layers forming the organic EL layer 16. In the schematic diagram shown in FIG. 10, 101 corresponds to the planarization film 14, 102 corresponds to the pixel electrode 15, 103 corresponds to the organic EL layer 16, and 104 corresponds to an electron injection layer described later. 105 corresponds to a counter electrode 17 described later, 106 corresponds to a passivation film 19, 107 corresponds to a sealant described later, and 108 corresponds to a sealing substrate such as a glass substrate.

  Prior to the formation of the hole transport layer 16a, the surface of the pixel electrode 15 (metal oxide layer 15b) exposed in the pixel formation region (formation region of the organic EL element OLED) Rpx of each display pixel PIX To be lyophilic with an organic compound-containing liquid of a transport material or an electron-transporting luminescent material (in order to be sufficiently familiar and easy to spread), for example, subjected to lyophilic treatment by oxygen plasma treatment, UV ozone treatment, etc. Furthermore, the surface of the banks BKx and BKy may be fluorine (so as to repel) the organic compound-containing liquid such as a hole transporting material or an electron transporting light emitting material. A liquid-repellent treatment may be performed by forming a film of a compound of the series.

  Thereafter, as shown in FIG. 9A, a light-transmissive conductive layer (transparent electrode layer) is formed on the insulating substrate 11 including at least each pixel formation region Rpx, and the organic EL layer 16 (holes) is formed. A common counter electrode (for example, a cathode electrode) 17 facing each pixel electrode 15 is formed through the transport layer 16a and the electron transport light emitting layer 16b) (counter electrode forming step).

  Specifically, as shown in the schematic diagram of FIG. 10, for example, a metal material (such as barium (Ba), magnesium (Mg), or lithium fluoride (LiF)) that becomes the electron injection layer 104 by an evaporation method, a sputtering method, or the like. After forming a thin film made of an alkali or alkaline earth metal), in the facing target sputtering method using ITO, tungsten-zinc doped indium oxide (IWZO) or the like as an upper layer, an atmosphere at the time of sputtering Argon (Ar) was used as a gas, the pressure was set to 100 mPa, and a counter electrode 105 (17) composed of a transparent electrode layer formed with a film thickness of 50 nm (500 mm) was laminated and transparent in the thickness direction. A film structure can be applied.

  As shown in FIG. 9A, the counter electrode 17 includes not only the region facing the pixel electrode 15 but also the banks BKx and BKy that define each pixel formation region Rpx (formation region of the organic EL element OLED). It is formed as a single conductive layer (solid electrode) extending up to the top and joined so as to be electrically connected to the conductive bank portion 18d forming the bank BKx. Accordingly, the conductive bank portion 18d can be applied as a common voltage line (cathode line) Lc commonly connected to each display pixel PIX. In this manner, by disposing the conductive bank portion 18d having the same potential as that of the counter electrode 17 between the display pixels PIX (organic EL elements OLED), the sheet resistance of the entire cathode is reduced, and the entire display panel 10 is reduced. Uniform display characteristics can be realized.

  Next, after the counter electrode 17 is formed, as shown in FIG. 9B, a transparent passivation film made of a silicon oxide film, a silicon nitride film, or the like is formed on one side of the insulating substrate 11 by using a CVD method or the like. (Protective film) 19 is formed (protective film forming step). Specifically, a passivation film 19 made of a silicon nitride film is formed with a film thickness of 600 nm (6000 mm) using a CVD method or the like.

  Next, a heat treatment (annealing) is performed in a dry nitrogen atmosphere under an atmospheric pressure (1 atm) at a temperature of 100 ° C. for 1 hour to perform stress relaxation processing of the passivation film 19 (stress relaxation processing step), FIG. The display panel 10 having a cross-sectional structure as shown in FIG. 5 is completed. As shown in the schematic diagram of FIG. 10, in the panel structure as shown in FIGS. 4 and 5, in addition to the passivation film 106 (19), a UV curable or thermosetting adhesive (sealing agent 107). ), And a sealing substrate 108 such as a metal cap (sealing lid) or glass may be bonded so as to face the insulating substrate 11.

  As described above, the manufacturing method of the display device according to the present embodiment applies the stress applied to the electron transporting light emitting layer 16b and the counter electrode 17 due to the internal stress generated when the passivation film 19 is formed. In order to relieve or cancel, heat treatment is performed in an atmospheric gas under a predetermined condition to relieve (reduce) the internal stress of the passivation film 19.

  In the above-described embodiment, the panel structure of the display panel 10 (organic EL element OLED) is such that the light emitted from the organic EL layer 16 is emitted to the view side without passing through the insulating substrate 11. Although the case of having an emission type light emitting structure has been described, the present invention is not limited to this, and has an element structure in which a passivation film is formed on a carrier transport layer and an electrode layer forming an organic EL element OLED. As long as it has a bottom emission type light emitting structure in which the light emitted from the organic EL layer 16 is emitted to the visual field side through the insulating substrate 11, it can be applied satisfactorily.

  In this embodiment, the pixel electrode 15 is an anode electrode and the counter electrode 17 is a cathode electrode. However, the present invention is not limited to this, and the pixel electrode 15 is a cathode electrode and the counter electrode 17 is an anode electrode. It may be a thing. In this case, in the organic EL layer 16, the carrier transport layer in contact with the pixel electrode 15 may be an electron transport layer.

(Verification of effects)
Next, functions and effects unique to the manufacturing method of the display device having the above-described features will be described in detail.
FIG. 11 is experimental data showing the operational effect (stress relaxation effect) in the manufacturing method according to the present embodiment.

Here, as a manufacturing method according to the present embodiment, in the stress relaxation treatment step after the formation of the passivation film 19, in a dry nitrogen (N ₂ ) atmosphere, atmospheric pressure (1 atm) and a temperature condition of 80 ° C. for 1 hour. A display panel subjected to heat treatment (annealing) (referred to as “panel 1” for the sake of convenience), and a display panel subjected to heat treatment for 1 hour under the same temperature condition of 120 ° C. (referred to as “panel 2” for convenience). As a comparative example, a display panel (for the sake of convenience, “Comparative Example 1”) subjected to a heat treatment at a temperature of 100 ° C. for one hour in a stress relaxation treatment step after the formation of the passivation film 19 under a vacuum condition. In addition, each measurement data of current efficiency (light emission efficiency) with respect to light emission luminance in a display panel (for convenience, described as “Comparative Example 2”) having no passivation film 19 (not shown). Make a comparison verification shows.

In the panel 1 and panel 2 has been applied a production method according to the present embodiment, as shown as a characteristic line S1, S2 in FIG. 11, generally approximately 1,800 cd / ^{m 2} order of 50 cd / ^{m 2} about a relatively low brightness A high current efficiency of approximately 10 cd / A or higher, or around 10 cd / A, was observed over almost the entire range up to high luminance.

On the other hand, in Comparative Example 1, as shown by the characteristic line S3 in FIG. 11, in a substantially entire range from a low luminance of about 500 cd / m ² to a high luminance of about 1400 cd / m ² , A current efficiency of about 8 cd / A was observed, and a current efficiency of less than 8 cd / A was observed in a luminance range of approximately 500 cd / m ² or less.

That is, in Comparative Example 1, the current efficiency (luminous efficiency) is about 8 cd / A in almost the entire range from low luminance to high luminance, and from panel 1 and panel 2 to which the manufacturing method according to this embodiment is applied. It was also found that stable current efficiency (luminous efficiency) cannot be obtained in a luminance range of about 20% lower and approximately 500 cd / m ² or less.

On the other hand, when the current efficiency with respect to the light emission luminance is measured for the display panel having no passivation film (Comparative Example 2), the luminance is relatively low (approximately 50 cd / m ² ) as shown by the characteristic line S4 in FIG. Although there was some variation, a high current efficiency of about 10 cd / A was observed over almost the entire range up to a luminance of about 1800 cd / m ² .

  Here, since the comparative example 2 is a display panel in which the passivation film is not formed on the light emitting element (organic EL element), in other words, the influence of the internal stress of the passivation film is exerted on the display panel on which the passivation film is formed. It can be considered that there is no state at all, or is equivalent to a state in which the influence is extremely small and suppressed.

From this, according to the panel 1 and the panel 2 to which the manufacturing method according to this embodiment described above is applied, the influence of the internal stress of the passivation film is suppressed, and light emission efficiency substantially equal to that in the comparative example 2 is obtained. Turned out to be. In particular, in the luminance range of about 1000 cd / m ² or less, in addition to obtaining current efficiency (luminous efficiency) substantially equal to that in Comparative Example 2, in the luminance range of about 1000 cd / m ² or more, in Comparative Example 2. The current efficiency (luminous efficiency) higher than the case was obtained, and the fluctuation of the current efficiency (luminous efficiency) with respect to the luminous intensity was small and stable in almost the entire range from low luminance to high luminance compared to the case of Comparative Example 2. It has been found that luminescent properties can be obtained. Needless to say, if there is no passivation film as in Comparative Example 2, the penetration of water or oxygen into the light-emitting element is promoted, and the light emission lifetime of the light-emitting element is remarkably shortened.

Such a function effect (stress relaxation effect) of the manufacturing method according to the present embodiment is presumably due to the following mechanism.
That is, the silicon nitride film applied as the above-described passivation film 106 (19) becomes porous (porous film quality) due to film formation conditions, material composition ratio, and the like. Volume change occurs when moisture in the atmosphere enters the part and hydroxyl groups are bonded to unreacted groups of silicon nitride molecules. Here, since the ITO film (electrode layer) formed as the counter electrode 17 serving as the cathode electrode or the like is very thin as 50 nm (500 mm) as described above, the passivation film in the above state is used. When a thermal stress is applied, a tensile stress is applied to the ITO film (electrode layer) to reduce the adhesion between the counter electrode 105 (17) made of ITO and the electron injection layer 104, resulting in delamination and cracks. As described above, it is considered that the current efficiency (light emission efficiency) is lowered. Such a phenomenon becomes more prominent as the passivation film is formed thicker in order to improve the passivation of the display panel.

Therefore, in the present invention, as shown in the above-described embodiment, immediately after the passivation film is formed, the passivation film is heated at 80 to 120 ° C. for about 1 hour in a nitrogen gas atmosphere of 1 atm. An annealing process is performed in which nitrogen penetrates into the vacancy portion and nitrogen is bonded to unreacted groups of silicon nitride molecules forming the passivation film to form a complete silicon nitride (Si ₃ N ₄ ). Thus, even when exposed to the outside air, moisture intrusion into the passivation film (that is, bonding of hydroxyl groups to unreacted groups of silicon nitride molecules) is suppressed, and generation of internal stress in the passivation film is suppressed. be able to.

  Therefore, according to the manufacturing method of the display device according to the present invention, the internal stress of the passivation film formed on the display panel in which the light emitting elements (organic EL elements) are two-dimensionally arranged can be relaxed or reduced. Generation of delamination and cracks between the electrode layer and the electron injection layer due to thermal stress can be suppressed (in other words, heat resistance can be improved), and in addition, the thickness of the passivation film is relatively thick. Since it can be formed, sufficient passivation can be ensured, and a display device having favorable light emission characteristics and reliability can be realized.

  In the verification of the effects described above, the experimental results are shown and described for the case where a silicon nitride film is applied as the passivation film, but the present invention is not limited to this, and a silicon oxide film is applied. Alternatively, an insulating film made of a mixture of silicon nitride and silicon oxide (SiNO) may be used.

  Further, in the verification of the above-described effects, the heat treatment (annealing) is performed for 1 hour at 80 ° C. or 120 ° C. under atmospheric pressure (1 atm) in a dry nitrogen atmosphere as the treatment conditions of the stress relaxation treatment step. Although the experimental results have been shown for the case where the atmospheric gas is used, the atmospheric gas may be other inert gas such as argon or hydrogen in addition to nitrogen, and the atmospheric gas pressure may be approximately 0.2 atm or more. The heating temperature may be in the range of approximately 60 to 140 ° C., and the heating time may be approximately 10 minutes or more. Here, when the heating temperature is 60 ° C. or lower, the reaction due to annealing is not promoted, so that the stress relaxation effect is small. When the heating temperature is 140 ° C. or higher, the organic EL layer (electron) formed below the electrode layer (counter electrode 17). Since the film characteristics change by reaching the melting point (polymer melting temperature Tg) of the transporting light emitting layer 16b, etc., the stress relaxation effect is reduced. As a result of various experiments, the inventor of the present application has confirmed that according to the processing conditions having such a numerical range, substantially the same effect (stress relaxation effect) as that shown in FIG. 11 can be obtained.

It is a schematic plan view which shows an example of the pixel arrangement state of the display panel applicable to the display apparatus which concerns on this invention. It is an equivalent circuit diagram showing an example of a circuit configuration of each display pixel (display element and pixel driving circuit) two-dimensionally arranged on the display panel of the display device according to the present invention. It is a plane layout figure which shows an example of the display pixel applicable to the display panel which concerns on this invention. It is a schematic sectional drawing which shows the cross section along the IVA-IVA line | wire in the display pixel which has the planar layout which concerns on this embodiment. It is a schematic sectional drawing which shows the cross section along VB-VB in the display pixel which has the planar layout which concerns on this embodiment. It is process sectional drawing (the 1) which shows an example of the manufacturing method of the display apparatus (display panel) which concerns on this embodiment. It is process sectional drawing (the 2) which shows an example of the manufacturing method of the display apparatus (display panel) which concerns on this embodiment. It is process sectional drawing (the 3) which shows an example of the manufacturing method of the display apparatus (display panel) which concerns on this embodiment. It is process sectional drawing (the 4) which shows an example of the manufacturing method of the display apparatus (display panel) which concerns on this embodiment. It is a schematic diagram which shows an example of the element structure of the organic EL element OLED formed in the display apparatus (display panel) which concerns on this embodiment. It is experimental data which shows the effect (stress relaxation effect) in the manufacturing method which concerns on this embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Display panel 11 Insulating substrate 15 Pixel electrode 16 Organic EL layer 17, 105 Counter electrode 18a, 18b Interlayer insulating film 18c Insulating bank part 18d Conductive bank part 19, 106 Passivation film PIX Display pixel Rpx Pixel formation area BKx, BKy bank

Claims (6)

Forming a light emitting element on one side of the substrate;
Forming an insulating protective film so as to cover one surface side of the substrate including the light emitting element;
A step of performing heat treatment in an atmospheric gas under a predetermined condition after the formation of the protective film;
A method for manufacturing a display device, comprising: The method for manufacturing a display device according to claim 1, wherein the heat treatment of the protective film is performed in an inert gas atmosphere. 3. The method of manufacturing a display device according to claim 2, wherein in the step of heat-treating the protective film, the pressure of the atmospheric gas is set to approximately 0.2 atm or more. The method for manufacturing a display device according to claim 2, wherein the step of heat-treating the protective film has a heating temperature generally set in a range of 60 to 140 ° C. 5. 5. The method for manufacturing a display device according to claim 2, wherein in the step of heat-treating the protective film, a heating time is set to approximately 10 minutes or more. 6. The light-emitting element has an electrode layer made of a transparent conductive metal oxide film, and the protective film is made of a transparent insulating film formed on the electrode layer. The manufacturing method of the display apparatus in any one of.

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