JP2009069332A - Liquid crystal display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display panel which is equipped with a means for preventing image burn-in caused by a voltage applied to a scanning line and which brings about no deterioration in excellent display characteristics of a lateral electric field mode. <P>SOLUTION: The liquid crystal display panel 100 is equipped with: a plurality of scanning lines 101 and common wires 103 formed on a substrate 132 in parallel to each other; signal lines 102; common electrodes 104 and pixel electrodes 105 formed in respective pixel regions partitioned with the scanning lines 101 and the signal lines 102; and a plurality of shield electrode layers 150 which extend in a direction identical to that of the scanning line 101, which are electrically connected to the common wires 103 on the outside of an active display region comprising pixel regions, and which are composed of a conductive material. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

The present invention provides an IPS (In-Plane Switching) mode or FFS (
The present invention relates to a horizontal electric field type liquid crystal display panel such as a fringe field switching mode, and more particularly to a liquid crystal display panel provided with means for preventing image sticking caused by a voltage applied to a scanning line and means for preventing orientation failure.

In recent years, electronic devices equipped with a liquid crystal display unit such as an electronic dictionary and a mobile phone have been required to have high definition, small size, and wide viewing angle, and accordingly, an active matrix type which has been conventionally adopted as a general driving method. Instead of the vertical electric field method, a liquid crystal display panel of a horizontal electric field method excellent in wide viewing angle has been proposed.

A vertical electric field type liquid crystal display panel is configured by sealing liquid crystal between a substrate on which a thin film transistor and a pixel electrode are formed and a substrate on which a color filter and a common electrode are formed. Then, by applying a voltage between the opposing pixel electrode and the common electrode to form a vertical electric field between the opposing substrates, and rotating the liquid crystal molecules sandwiched between the pixel electrode and the common electrode, light transmittance is achieved. Various images are displayed by changing. Such a vertical electric field type liquid crystal display panel includes a TN (Twisted Nematic) mode and a VA (Vertical Ali).
There is a problem that the vertical electric field type liquid crystal display panel has a narrow viewing angle in any mode.

In order to solve the viewing angle problem in the vertical electric field type liquid crystal display panel, a horizontal electric field type liquid crystal display panel that generates a horizontal electric field in the in-plane direction with respect to the substrate has been proposed. A horizontal electric field type liquid crystal display panel rotates various liquid crystal molecules in a plane parallel to the substrate by a horizontal electric field generated in the in-plane direction with respect to the substrate, thereby changing the light transmittance and displaying various images. indicate. At this time, the movement of the liquid crystal molecules in the horizontal electric field type liquid crystal display panel is limited to the in-plane direction of the substrate, and the major axis of the liquid crystal molecules is in the plane of the substrate as in the vertical electric field type liquid crystal display panel. There is no change from the parallel direction to the vertical direction. For this reason, the horizontal electric field type liquid crystal display panel has very good viewing angle characteristics with no significant difference in birefringence depending on the viewing angle.

In addition, an IPS (In Plane Switchin) is used for a horizontal electric field type liquid crystal display panel.
g) mode and FFS (Fringe-Field Switching) mode. The FFS mode is a liquid crystal display panel in which the aperture ratio is improved by further improving the IPS technology.

9 to 11 are diagrams showing an operation principle of an IPS mode liquid crystal display panel 600 which is one of the horizontal electric field methods, and FIG. 9 is a pixel region formed on the array substrate 630 of the IPS mode liquid crystal display panel 600. 10 is a cross-sectional view taken along line EE ′ of FIG. 9, and FIG. 11 is a cross-sectional view taken along line FF ′ of FIG. 10 and 11 are enlarged for the sake of explanation, the pixel region of the liquid crystal display panel 600 shown in FIG. 9 is enlarged, and the liquid crystal molecules constituting the liquid crystal layer 640 are schematically shown to explain the movement of the liquid crystal molecules. ing.

As shown in FIGS. 9 to 11, the IPS mode liquid crystal display panel 600 includes an array substrate 63.
A liquid crystal layer 640 is sealed between 0 and the color filter substrate 620. And
The array substrate 630 includes a plurality of scanning lines 601 and a common wiring 603 on the surface of the glass substrate 632.
Are formed in parallel, and a plurality of signal lines 602 extending in a direction orthogonal to the scanning lines 601 and the common wiring 603 are formed. Note that the signal line 602 is formed so as to be orthogonal to the scanning line 601 and the common wiring 603 via an insulating layer, and these are insulated from each other.

In each pixel region, a comb-like common electrode 6 electrically connected to the common wiring 603 is used.
04 and a comb-like pixel electrode 605 are also provided so as to surround the common electrode 604. The surface of the pixel electrode 605 is covered with, for example, a protective insulating film 633 made of silicon nitride and an alignment film 634 made of polyimide or the like.

A TFT as a switching element is located near the intersection of the scanning line 601 and the signal line 602.
(Thin Film Transistor: thin film field effect transistor) 610 is formed. In this TFT 610, the semiconductor layer 609 is disposed on the scanning line 601, and the extending portion that extends from the signal line 602 and overlaps the upper portion of the semiconductor layer 609 is the source electrode 6 of the TFT 610.
06, and the scanning line 601 portion below the semiconductor layer 609 constitutes the gate electrode 607. In addition, a part of the pixel electrode 605 that overlaps with a part of the semiconductor layer 609 forms the drain electrode 6.
08 is constituted.

Further, the color filter substrate 620 is formed on the surface of the glass substrate 622 with the color filter layer 623.
An overcoat layer 625 and an alignment film 624 are provided. And the array substrate 63
The array substrate 630 and the color filter substrate 620 are opposed so that the pixel electrode 605 and the common electrode 604 of 0 and the color filter layer 623 side of the color filter substrate 620 face each other, and the liquid crystal 640 is sealed therebetween, and both substrates Polarizer 62 on the outside of each
The IPS mode liquid crystal display panel 600 is formed by arranging 1 and 631 such that the polarization directions are orthogonal to each other.

In the IPS mode liquid crystal display panel 600, an electric field (in FIG. 10, an electric field line is indicated by an arrow emitted from the pixel electrode 605 and incident on the common electrode 604) between the pixel electrode 605 and the common electrode 604 is formed. Then, the molecules of the liquid crystal 640 that have been aligned in the horizontal direction rotate in the horizontal direction. As a result, the transmission amount of the incident light (the white arrow in FIGS. 10 and 11) from the backlight incident on the liquid crystal display panel 600 from below the array substrate 630 is controlled and emitted above the color filter substrate 620. Can do. However, the IPS mode liquid crystal display panel 600 has the advantages of having a wide viewing angle and excellent contrast.
4 is formed of the same metal material as the common wiring 603 or the scanning line 601, there are problems that the aperture ratio and the transmittance are low and there is a color change depending on the viewing angle.

Therefore, in recent years, in order to solve the problems of the low aperture ratio and the low transmittance of the IPS mode liquid crystal display panel 600, the IPS mode liquid crystal display panel 600 has been further improved to provide an FFS.
A mode liquid crystal display panel 700 has been proposed. 12 to 14 are diagrams showing an operation principle of an FFS mode liquid crystal display panel 700 which is one of the horizontal electric field methods, and FIG. 12 is a schematic diagram showing a pixel region on the array substrate 730 in the FFS mode liquid crystal display panel 700. 13 is a plan view, FIG. 13 is a cross-sectional view taken along line GG ′ of FIG. 10, and FIG. 14 is a cross-sectional view taken along line HH ′ of FIG.
It is sectional drawing along a line. 13 and FIG. 14 are explanatory diagrams for explaining the movement of the liquid crystal molecules by enlarging the pixel region of the liquid crystal display panel 700 shown in FIG. 12 and schematically showing the liquid crystal molecules constituting the liquid crystal layer 740. .

As shown in FIGS. 12 to 14, in the FFS mode liquid crystal display panel 700, liquid crystal is sealed between an array substrate 730 and a color filter substrate 720 to form a liquid crystal layer 740. In the array substrate 730, a plurality of scanning lines 701 and common wirings 703 are formed in parallel on the surface of the glass substrate 732, and a plurality of signal lines 702 are formed in a direction perpendicular to the scanning lines 701 and common wirings 703. . Note that the signal line 702 is formed so as to be orthogonal to the scanning line 701 and the common wiring 703 via an insulating layer, and these are in an insulated state.

Here, in each pixel region defined by the scanning line 701 and the signal line 702, the scanning line 7.
ITO (Indium Ti) so as to cover the common wiring 703 provided along the line 01
n Oxide) or the like is provided with a common electrode 704 formed of a transparent material, and a pixel electrode 705 is provided on the surface of the common electrode 704 with insulating layers 733 and 735 interposed therebetween. The pixel electrode 705 is made of a transparent material such as ITO, and a plurality of slits 705a are formed in a stripe shape. The surfaces of the pixel electrode 705 and the plurality of slits 705a are covered with an alignment film 734.

A TF as a switching element is located near the intersection of the scanning line 701 and the signal line 702.
T710 is formed, and in this TFT 710, a semiconductor layer 709 is disposed between the scanning line 701 and the signal line 702. Here, the semiconductor layer 709 is formed so as to cover a part of the extended scanning line 701, and the extended part of the scanning line 701 overlapping the lower part of the semiconductor layer 709 constitutes the gate electrode 707, and the semiconductor layer The signal line 70 covers a part of the upper surface of the 709.
2 extends to form a source electrode 706 of the TFT 710, and the semiconductor layer 709
A part of the pixel electrode 705 that overlaps a part of the drain electrode 708 constitutes the drain electrode 708.

Further, the color filter substrate 720 has a color filter layer 72 on the surface of the glass substrate 722.
3, an overcoat layer 725 and an alignment film 724 are provided. And the array substrate 7
The array substrate 730 and the color filter substrate 720 are opposed to each other so that the 30 pixel electrodes 705 and the common electrode 704 and the color filter layer 723 of the color filter substrate 720 are opposed to each other, and liquid crystal is sealed therebetween to form a liquid crystal layer 740. In addition, the FFS mode liquid crystal display panel 700 is formed by disposing the polarizing plates 721 and 731 on the outer sides of both substrates so that the polarization directions thereof are orthogonal to each other.

As shown in FIGS. 13 and 14, in the FFS mode liquid crystal display panel 700, when a voltage is applied between the pixel electrode 705 and the common electrode 704, the pixel electrode 705 moves toward the common electrode 704 using the slit 705a. An electric field (in the figure, an electric line of force is indicated by an arrow emitted from the pixel electrode 705) can be generated. At this time, the electric field is directed from both sides of the pixel electrode 705 toward the common electrode 704 formed below, but together with the electric field in the horizontal direction, the pixel electrode 7
An electric field component is also generated in the direction perpendicular to the array substrate 730 near the edge of 05. Accordingly, not only the liquid crystal molecules existing on the slit 705a but also the liquid crystal molecules existing on the pixel electrode 705 can be driven. In addition, since the pixel electrode 705 and the common electrode 704 are formed of a transparent material such as ITO, the FFS mode liquid crystal display panel 700 is more than the IPS mode liquid crystal display panel 600 by making these electrode portions contribute to display. Also, the pixel aperture ratio can be designed to be large. Similarly to the IPS mode liquid crystal display panel 600, the FFS mode liquid crystal display panel 700 has a wide viewing angle and high contrast, and further has a feature that a bright display is possible because of high transmittance. In addition, the FFS mode liquid crystal display panel 700 has a pixel electrode 7 in a plan view as compared with the IPS mode liquid crystal display panel 600.
05 and the common electrode 704 have a large overlapping area, so that a larger storage capacity is generated as a secondary effect, and there is an advantage that it is not necessary to separately provide an auxiliary capacity line.

Note that in the FFS mode liquid crystal display panel 700, the rubbing direction is preferably orthogonal to the signal line 702 in terms of display characteristics, as in the case of the IPS mode liquid crystal display panel 600, and the pixel electrode 705 and the rubbing direction are Because it is better to provide a slight angle of inclination,
A stripe-shaped slit 705a provided in the pixel electrode 705 is inclined with respect to the scanning line 701 or the common wiring 703. Similarly, in order to prevent a color change from being observed depending on the viewing angle, FIG. FFS mode liquid crystal display panel 700 shown
As described above, a dual-domain structure is also formed by arranging striped slits provided in the pixel electrode 705 in a “<” shape.

Further, in order to prevent the black matrix of the color filter substrate 720 provided in the portion facing the signal line 702 from being linear, and to make the black matrix suitable for image display in which the black matrix is not conspicuous, the signal line 702 is changed to the scanning line 701. A plurality of common electrodes 704 and pixel electrodes 705 can also be arranged in a delta arrangement by providing them in a crank shape in a direction perpendicular to the direction.

In the IPS mode liquid crystal display panel 600 shown in FIG.
Similar to the liquid crystal display panel in the mode, the rubbing direction of the alignment films 624 and 634 is orthogonal to the signal line 602 as in the IPS mode liquid crystal display panel 600 shown in FIG.
In addition, display quality is improved by providing a slight angle of inclination between the common electrode 604 and the rubbing direction. In addition, the pixel electrode 605 and the common electrode 604 are arranged to be inclined in different directions on the right and left in the extending direction to form a dual domain, so that the color change can be prevented from being recognized depending on the viewing angle. Also, such an IPS mode liquid crystal display panel 60.
As in the case of 0, a plurality of pixel electrodes 605 and common electrodes 604 can be arranged in a delta arrangement so that a black matrix is not noticeable.

15 is a modification of the FFS mode liquid crystal display panel 700 shown in FIG. 12, and the IPS mode liquid crystal display panel 600 shown in FIG. 16 is an IPS mode liquid crystal display panel 700 shown in FIG. Since this is an example of the mode liquid crystal display panel 600, the same components as those of the liquid crystal display panel in each mode are denoted by the same reference numerals, and detailed description thereof is omitted.

By the way, it is known that when the liquid crystal display panel is used for a long time, a burn-in phenomenon occurs, and this is the same in the case of the liquid crystal display panel 600 in the IPS mode and the liquid crystal display panel 700 in the FFS mode. However, the conventional FF as described above
In the S-mode liquid crystal display panel 700, it has been found that this burn-in phenomenon appears greatly compared to the conventional IPS-mode liquid crystal display panel 600. The inventors
The reason why the burn-in phenomenon appears larger in the S-mode liquid crystal display panel 700 than in the IPS-mode liquid crystal display panel 600 is that the generated electric field affects the alignment of liquid crystal molecules in the vicinity. The path of the electric lines of force toward the layers is symmetric in the case of the liquid crystal display panel 600 in the IPS mode, whereas the liquid crystal display panel 7 in the FFS mode.
In the case of 00, it was estimated that the asymmetrical factor contributed to this.

That is, in the liquid crystal display device panel of the IPS mode and the FFS mode, the voltage applied to the scanning line is about −10 V in a non-selected state of a predetermined pixel, and is about +15 V in a selected state. Since the time for which a pixel is selected is very short, it is about -10V.
The DC voltage is applied for a long time. Here, the liquid crystal display panel 600 in the IPS mode.
In this case, as is apparent from the description of FIG. 11, the electric field from the pixel electrode 605 toward the scanning line 601 (in the figure, the electric lines of force are indicated by the arrows emitted from the pixel electrode 605 and entering the scanning line 601).
Enters the liquid crystal layer 640 from the pixel electrode 605 through the protective insulating film 633 and the alignment film 634, and reaches the scanning line 601 from the liquid crystal layer 640 through the alignment film 634 and the protective insulating film 633. As described above, the path of the electric lines of force from the pixel electrode 605 to the liquid crystal layer 640 and the path of the electric lines of force from the liquid crystal layer 640 to the scanning line 601 are symmetric.

On the other hand, in the case of the FFS mode liquid crystal display panel 700, as shown in FIG. 14, an electric field (from the pixel electrode 705 in FIG.
1 enters the liquid crystal layer 740 from the pixel electrode 705 through the alignment film 734, and from the liquid crystal layer 740 through the alignment film 734 and the protective insulating film 733 to the scanning line 701.
Has reached. As described above, the path of electric lines of force from the pixel electrode 705 to the liquid crystal layer 740 and the path of electric lines of force from the liquid crystal layer 740 to the scanning line 701 are asymmetric. Therefore, the FFS mode liquid crystal display panel 700 is an IPS mode liquid crystal display panel 6.
The pixel electrode 705 or the alignment film 734 on the surface of the pixel electrode 705 is more easily irreversibly affected by a DC electric field caused by a signal applied to the scanning line 701 than in the case of 00. And this is FFS
It is presumed that the mode liquid crystal display panel 700 causes the image sticking phenomenon to appear larger than the IPS mode liquid crystal display panel 600.

However, conventionally, sufficient countermeasures have not been studied for the burn-in of the liquid crystal display panel that occurs in the vicinity of the scanning line. As an invention of a horizontal electric field type liquid crystal display panel, the IPS mode described in Patent Document 1 is used. In general, a liquid crystal display panel is intended to improve viewing angle, high transparency, and high image quality.

JP 2005-338256 A

However, the present inventor has conducted various studies to reduce the image sticking problem of the FFS mode liquid crystal display panel, and as a result, the path of electric lines of force from the pixel electrode to the liquid crystal layer and the scanning line from the liquid crystal layer. It is difficult to make the path of the electric lines of force to reach the point of view from the operation principle of the liquid crystal display panel of the FFS mode, but the DC electric field based on the high voltage signal applied to the scanning line is It is found that not only the image sticking phenomenon of the FFS mode liquid crystal display panel can be reduced by preventing the liquid crystal from being applied to the liquid crystal, but also the image sticking can be reduced in the IPS mode liquid crystal display panel. It came to.

The present invention has been made in order to solve the above-described problems, and an object of the present invention is to provide a means for preventing burn-in caused by a voltage applied to a scanning line and to provide an excellent display of a lateral electric field method. An object of the present invention is to provide a liquid crystal display panel that does not deteriorate the characteristics.

In order to achieve the above object, a liquid crystal display panel according to a first aspect of the present invention includes a plurality of scanning lines and common lines formed in parallel on a substrate, and a plurality of lines extending in a direction orthogonal to the scanning lines and common lines. Signal lines, common electrodes and pixel electrodes formed in each pixel area partitioned by the scanning lines and the signal lines, and extending in the same direction as the scanning lines, outside the active display area constituted by the pixel areas And a plurality of shield electrode layers made of a conductive material electrically connected to the common wiring.

In the liquid crystal display panel according to the first aspect, as described above, the shield electrode layer made of a conductive material extending in the same direction as the scanning line is formed, so that a high voltage signal applied to the scanning line is used. The generated lines of electric force from the pixel electrode to the scanning line are blocked by the shield electrode layer before reaching the scanning line from the pixel electrode. Therefore, the electric field component from the scanning line applied to the liquid crystal positioned above the shield electrode layer can be minimized, and the image sticking phenomenon of the liquid crystal display panel based on the high voltage signal applied to the scanning line is greatly reduced. Can be reduced.

In addition, when the shield electrode is in a floating state, the potential of the shield electrode layer becomes unstable. However, in the liquid crystal display panel according to the present invention, the shield electrode layer and the common wiring are electrically connected to stabilize the potential of the shield electrode layer. It has become. Thereby, the image sticking phenomenon of the liquid crystal display panel based on the high voltage signal applied to the scanning line can be further reduced.

In the liquid crystal display panel according to the present invention, the shield electrode layer and the common wiring are electrically connected outside the active matrix region. Usually, when the shield electrode layer and the common wiring are electrically connected in each pixel region partitioned by the scanning line and the signal line, a notch is formed in a part of the pixel electrode in the structure and manufacturing process of the liquid crystal display panel. It is necessary to provide a contact hole in the notch to ensure conduction between the shield electrode layer and the common wiring. For this reason, the problem that the manufacturing process of a liquid crystal display panel becomes complicated arises. In addition, since a notch is provided in a part of the pixel electrode, the liquid crystal molecules existing above the notch cannot be driven. Therefore, even when the shield electrode layer is formed of a transparent material such as ITO, this notch cannot be contributed to display, and the pixel aperture ratio of the liquid crystal display panel is lowered.

However, in the liquid crystal display panel according to the present invention, since the shield electrode layer and the common wiring are electrically connected outside the active display region, it is not necessary to provide a notch in each pixel region. It does not narrow the formation area. Therefore, the shield electrode layer can be formed without reducing the pixel aperture ratio. Further, in order to achieve high definition of the active display area, it is necessary to reduce the size of each pixel area and increase the number of pixels in the display area. Therefore, the potential of the shield electrode layer may not be stabilized. However, when the shield electrode layer and the common wiring are electrically connected outside the active display region as in the liquid crystal display panel according to the present invention, this electrical connection region Can be secured sufficiently. For this reason, the electrical connection between the shield electrode layer and the common wiring does not affect the high definition of the display area.

In the liquid crystal display panel according to the first aspect, the shield electrode layer is preferably formed through an insulating layer so as to cover the scanning line. Accordingly, the electric field from the pixel electrode can be effectively cut off, and the image sticking phenomenon of the horizontal electric field type liquid crystal display panel based on the high voltage signal applied to the scanning line can be further reduced.

In the liquid crystal display panel according to the first aspect, the shield electrode layer is preferably formed in a continuous band shape. Thereby, the formation of the shield electrode layer can ensure the pixel aperture ratio without narrowing the pixel electrode formation region. Further, since the shield electrode layers are connected together, the potential of the shield electrode layer in the active display region can be stabilized only by electrically connecting the common wiring and the shield electrode layer outside the active display region.

In the liquid crystal display panel according to the first aspect, the end of the common wiring is preferably formed in a comb shape. Thereby, the connection part of a common wiring and a shield electrode layer can be provided widely, and the electric potential of a shield electrode layer can be stabilized more.

In the liquid crystal display panel according to the first aspect, the shield electrode layer is preferably electrically connected to both ends of the common wiring and the outside of the active display area. Thereby, the connection part of a common wiring and a shield electrode layer can be provided widely, and the electric potential of a shield electrode layer can be stabilized more.

As described above, according to the present invention, it is possible to easily provide a liquid crystal display panel that includes a burn-in preventing unit due to a voltage applied to a scanning line and has a predetermined pixel aperture ratio.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments embodying the present invention will be described in detail with reference to the drawings. However, the embodiment described below exemplifies a lateral electric field type FFS mode liquid crystal display panel as a liquid crystal display panel for embodying the technical idea of the present invention. The present invention is not limited to a display panel, and can be equally applied to other embodiments included in the scope of claims such as an IPS mode liquid crystal display panel.

(First embodiment)
FIG. 1 is a circuit configuration diagram of a driving system of an FFS mode liquid crystal display panel 100 according to a first embodiment of the present invention. 2 to 5 show the operation principle of one pixel of the FFS mode liquid crystal display panel 100 which is one of the horizontal electric field systems, and FIG. 2 shows the FF according to the first embodiment of the present invention.
4 is a schematic plan view showing a pixel region on an array substrate 130 that is seen through a color filter substrate 120 in an S mode liquid crystal display panel 100. FIG. 3 is a cross-sectional view taken along the line AA ′ of the liquid crystal display panel 100 according to the first embodiment shown in FIG. 2, and FIG.
FIG. 5 is a cross-sectional view taken along line -B ′, and FIG. 5 is a cross-sectional view taken along line CC ′ of FIG. In addition,
3 and 4, for the sake of explanation, the pixel region of the liquid crystal display panel 100 shown in FIG. 2 is enlarged, and the movement of the liquid crystal molecules is illustrated by schematically showing the liquid crystal molecules constituting the liquid crystal layer 140.

As shown in FIG. 1, in the liquid crystal display panel 100 according to the first embodiment of the present invention, a plurality of scanning lines 101 and common wirings 103 are formed in parallel on an array substrate 130, respectively. A plurality of signal lines 102 are formed in a direction perpendicular to the line. In addition, a plurality of pixel areas defined by the plurality of scanning lines 101 and signal lines 102 are arranged to form an active display area 180 of the liquid crystal display panel 100. In FIG. 1, only a part of the pixel region is shown for the sake of explanation, and other regions are omitted.

Here, the scanning line 101 extends to the scanning electrode driving circuit 10 provided at the end of the array substrate 130 outside the active display region 180 and is connected thereto. Further, the signal line 10
2 extends to the signal electrode drive circuit 20 provided at the end of the array substrate 130 outside the active display region 180 and is connected thereto. Further, a common electrode line 31 having a low resistance value is provided outside the active display region 180 along the outer periphery of the display region 180, and the common electrode line 31 is provided outside the active display region 180 and at the end of the array substrate 130. Connected to the common electrode driving circuit 30. Further, the common wiring 103 is an active display area 180.
It extends to the outside to the left and right and is connected to the common electrode line 31. Although not shown in FIG. 1, a band-shaped shield electrode layer 150 is formed on the scanning line 101 via an insulating film, and is electrically connected to the common wiring and the common electrode line outside the active display region 180. It is connected. Each of these drive circuits is controlled by a display control device (not shown). In FIG. 1, an equivalent circuit corresponding to an electrode structure is shown in one pixel region constituting the active display region 180. Further, although the scan electrode driving circuit 10 is provided at one end of the array substrate 130, the array substrate 1 can be connected to both ends of one scan line 101 according to the screen size or the like.
The scanning electrode driving circuit 10 may be provided at both ends of the power supply 30 to supply power to the scanning line 101 from both the left and right sides. Further, instead of the scanning electrode driving circuit 10 connected to the scanning line 101 and the signal electrode driving circuit 20 connected to the signal line 102, a signal can be supplied to either the signal line 102 or the scanning line 101. A drive circuit may be arranged. At this time, both ends of each scanning line 101 extending outside the active display region 180 are drawn out to one pole outside the active display region 180,
By connecting to the driving circuit together with the signal line 102, the number of driving circuits can be reduced and an extra space outside the active display region 180 can be omitted. Thereby, size reduction of the liquid crystal display panel 100 can be achieved. At this time, the cost can be reduced by reducing the number of necessary drive circuits. The connection structure between the common electrode line 31 and the common wiring 103 will be described later.

As shown in FIGS. 2 to 5, each pixel area constituting the active display area 180 is an area partitioned by the scanning lines 101 and the signal lines 102 formed in parallel. Also, the scanning line 101
Are formed in parallel, and the signal line 102 is formed in a direction orthogonal to the scanning line 101 and the common wiring 103. Here, in each pixel region defined by the scanning line 101 and the signal line 102, a transparent material made of ITO (Indium Tin Oxide) or the like is formed so as to cover the common wiring 103 provided along the scanning line 101. A common electrode 104 is provided. Further, the insulating layer 133 is formed on the surface of the common electrode 104.
, 135, and a strip-shaped shield electrode layer 150 is provided via insulating layers 133, 135 so as to cover the scanning line 101. The pixel electrode 105 and the shield electrode layer 150 are made of a transparent material such as ITO, and the pixel electrode 105 has a plurality of slits 105a formed in a stripe shape. The surfaces of the pixel electrode 105, the plurality of slits 105a, and the shield electrode layer 150 are covered with an alignment film 134.

In the FFS mode liquid crystal display panel 100 according to the first embodiment of the present invention, as shown in FIG. 3, an electric field (from the pixel electrode 105 to the common electrode 104) near the center of the pixel region away from the scanning line 101 (see FIG. 3). Of the common electrode 104 formed downward from both sides of the pixel electrode 105.
Head in the direction. Further, the array substrate 1 near the edge of the pixel electrode 105 together with the horizontal electric field component.
Since an electric field component is also generated in a direction perpendicular to 30, not only the liquid crystal molecules existing on the slit 105 a but also the liquid crystal molecules existing on the pixel electrode 105 can be driven.

Further, in the pixel region adjacent to the scanning line 101, as shown in FIG.
The electric field generated in the direction of the scanning line 101 out of the electric field generated from the pixel electrode 105 (in the figure, the direction of the electric field is indicated by the lines of electric force indicated by the arrows emitted from the pixel electrode 105 in the figure) is from the pixel electrode 105 to the alignment film 134.
After entering the liquid crystal layer 140, the shield electrode layer 150 blocks the liquid crystal layer 140 on the way to the scanning line 101. Therefore, in the FFS mode liquid crystal display panel 100 according to the first embodiment of the present invention, the pixel electrodes 105 or the alignment film 134 are arranged on the scanning lines 101 as compared with the conventional FFS mode liquid crystal display panel having no shield electrode layer 150. Irreversible influences caused by a DC electric field caused by an applied signal can be suppressed. Shield electrode layer 1
The electric field component applied to the liquid crystal positioned on the upper part of 50 can be minimized, and the scanning line 1
The image sticking phenomenon in the vicinity of 01 can be greatly reduced.

Further, since the potential becomes unstable when the shield electrode layer 150 is in a floating state,
It is necessary to stabilize the potential of the shield electrode layer 150 by being electrically connected to the common wiring 103. However, as shown in FIG. 6, the shield electrode layer 150 and the common electrode 1 in the pixel region.
04 is connected to the pixel electrode 1 in view of the structure and manufacturing process of the FFS mode liquid crystal display panel.
It is necessary to provide a cutout portion in a part of 05 and provide a contact hole 173 in the cutout portion to ensure conduction between the shield electrode layer 150 and the common wiring 103. For this reason, the problem that the manufacturing process of the liquid crystal display panel 100 becomes complicated arises. Further, since a notch is provided in a part of the pixel electrode 105, the liquid crystal molecules existing above the notch cannot be driven. Therefore, even when the shield electrode layer 150 is formed of a transparent material such as ITO, this notch cannot be contributed to display, and the liquid crystal display panel 1
The pixel aperture ratio of 00 will decrease. FIG. 6 is a modification of the FFS mode liquid crystal display panel 100 of the first embodiment in which the shield electrode layer 150 is formed on the scanning line 101, and is the same as the FFS mode liquid crystal display panel 100 of the first embodiment. Parts are denoted by the same reference numerals.

In contrast, in the FFS mode liquid crystal display panel 100 according to the first embodiment of the present invention, the shield electrode 150 is electrically connected to the common wiring 103 outside the active display region 180. Therefore, as shown in FIG. 2, the shield electrode layer 150 is formed in a strip shape on the scanning line 101 to secure the formation region of the pixel electrode 104 and the pixel electrode 10.
There is no need to provide notches in the four objects. Accordingly, it is possible to stabilize the potential of the shield electrode layer 150 and to suppress a decrease in the pixel aperture ratio.

The shield electrode layer 150 is preferably provided as wide as possible in order to block the electric field generated from the pixel electrode 105 in the direction of the scanning line 101. However, when the shield electrode is formed wide, the formation region of the pixel electrode 105 The pixel aperture ratio may be reduced. Therefore, in the FFS mode liquid crystal display panel 100 according to the first embodiment of the present invention, the shield electrode layer 150 is formed in a strip shape with a predetermined width necessary to suppress the burn-in phenomenon on the scanning line 101.

In order to increase the definition of the active display region 180, it is necessary to reduce the area in each pixel region and increase the number of pixels in the active display region 180. At this time, in the case of the liquid crystal display panel 100 as shown in FIG. 6, the shield electrode layer 150 provided in the pixel region.
The contact hole 173 that electrically connects the common electrode 104 and the common electrode 104 also needs to be miniaturized.

FIG. 7 is a schematic plan view showing a part of the outer periphery of the active display region 180 of the FFS mode liquid crystal display panel 100 according to the first embodiment of the present invention, and FIG. 8 is a cross section taken along the line DD ′ of FIG. FIG. As shown in FIG. 7, the common wiring 103 extends to the outside of the active display region 180 and is electrically connected to the shield electrode layer 150 via the contact hole 171. At this time, the end portions of the common wiring 103 are formed in a comb-teeth shape and connected via a plurality of contact holes 171. With this configuration, the shield electrode layer 150 and the common wiring 1
It is possible to stabilize the potential of the shield electrode layer 160 by keeping the resistance value of the electrical connection portion 03 low. The plurality of common wirings 103 are all connected to the common electrode line 31 having a low resistance value, and finally connected to the common electrode driving circuit 30 via the common electrode line 31 (see FIG. 1).
. At this time, in the FFS mode liquid crystal display panel 100 according to the first embodiment of the present invention, a portion extending from the common electrode line 31 in a comb shape is electrically connected to the shield electrode layer 150 via the contact hole 172. ing. With this configuration, the common wiring 103 is electrically connected to the common electrode line 31 through the shield electrode layer 150. Further, the extended portion of the common electrode line 31 is formed in a comb shape, and the common electrode line 31 and the shield electrode layer 150 are electrically connected through a plurality of contact holes 172. With this configuration, the resistance value of the electrical connection portion between the shield electrode layer 150 and the common electrode line 131 can be kept low, and the common wiring 103 and the common electrode line 31 can be stably connected. Further, the potential of the shield electrode layer 150 is further stabilized.

Note that the connection portion of the common wiring 103, the shield electrode layer 150, and the common electrode line 31 is not limited to being provided at one end of the matrix display region 180, and may be provided at both ends of the matrix display region 180. At this time, the potential of the shield electrode layer 150 can be further stabilized.

Next, the configuration of the FFS mode liquid crystal display region 100 according to the first embodiment of the present invention will be described in detail. As shown in FIG. 5, the array substrate 130 is a transparent substrate 13 such as a glass substrate.
The scanning line 101 and the common wiring 103 formed on the substrate 2 are formed by forming a two-layer film having a lower part made of Al metal and a surface made of Mo metal over the entire surface of the transparent substrate 132, and then a photolithography method and an etching method. This is a Mo / Al two-layer wiring formed by M
The o / Al two-layer wiring has the advantage that aluminum has a small resistance value,
On the other hand, it is easy to corrode and has high defects such as high contact resistance with ITO. Such a defect can be improved by forming a multilayer structure in which aluminum is covered with molybdenum. Further, although an example in which the common wiring 103 is provided along the scanning line 101 is shown here, the common wiring 103 may be provided in the middle of the adjacent scanning lines 101.

The common electrode 104 is formed of a transparent material made of ITO so as to cover the common wiring 103 in each pixel region defined by the scanning line 101 and the signal line 102.
In this method, once the transparent electrode layer made of ITO is coated over the entire surface of the transparent substrate 132 on which the scanning lines 101 and the common wiring 103 are formed, unnecessary transparent electrode layers are removed by a photolithography method and an etching method. Is formed. In the pixel area,
The common electrode 104 is electrically connected to the common wiring 103 but is not connected to the scanning line 101 or the gate electrode 107.

Further, after forming the common electrode 104, the gate insulating film 133 made of a silicon nitride layer or silicon oxide is covered over the entire transparent substrate 132 including the scanning line 101, the common wiring 103, and the common electrode 104.

Further, a TF as a switching element is located near the intersection of the scanning line 101 and the signal line 102.
T110 is formed, and the semiconductor layer 109 is disposed between the scanning line 101 and the signal line 102 in the TFT 110. At this time, the semiconductor layer 109 is formed on a predetermined region extending from the scanning line 101, and the extending part of the scanning line 101 overlapping the lower part of the semiconductor layer 109 constitutes the gate electrode 107 and the upper surface of the semiconductor layer 109. A part of the signal line 102 is extended so as to cover a part to constitute the source electrode 106 of the TFT 110, and a part of the pixel electrode 105 overlapping with a part of the semiconductor layer 109 constitutes the drain electrode 108.

The TFT 110 is first formed of, for example, amorphous silicon (hereinafter referred to as “a” by CVD).
-Si ") layer is applied over the entire surface of the gate insulating film 133, and then the unnecessary a-Si layer is removed by a photolithography method and an etching method to extend the scanning line 101, which is the TFT 110 formation region. A semiconductor layer 109 made of an a-Si layer is formed. Then M
A conductive layer having a three-layer structure of o / Al / Mo is coated from the upper surface of the semiconductor layer 109 to the entire surface of the transparent substrate 132, and unnecessary portions are removed by the photolithography method and the etching method to remove the signal line 102. The source electrode 106 and the drain electrode 108 are formed, and the common electrode line 31 is formed along the outer periphery of the active display region 180. Here, a part of the signal line 102 extends so as to partially overlap with a part of the upper surface of the semiconductor layer 109, and an extension part of the signal line 102 that partially overlaps with the upper surface of the semiconductor layer 109 is formed. Source electrode 1 of TFT 110
06. Similarly, the drain electrode 108 is also formed so as to partially overlap a part of the surface of the semiconductor layer 109.

The drain electrode 108 has an IT in which a plurality of slits 105a are formed in a stripe shape.
The pixel electrode 105 made of O is electrically connected. This manufacturing process starts with the signal line 10.
2. After forming the source electrode 106 and the drain electrode 108, the entire surface of the substrate is covered with a source insulating film 135 made of a silicon nitride layer, and a contact hole 170 is formed in the source insulating film 135 at a position corresponding to the drain electrode 108. To expose part of the drain electrode. Thereafter, a transparent conductive layer made of ITO is covered over the entire surface, and the pixel electrode 105 in which a plurality of slits 105a are formed in a stripe shape by the photolithography method and the etching method is used as the scanning line 101 and the signal line. It is formed on the source insulating film 135 in the pixel region surrounded by 102. At this time, the pixel electrode 105 is electrically connected to the drain electrode 108 through the contact hole 170.

At this time, the pixel electrode 105 having the slit 105 a is formed, and the shield electrode layer 150 is formed on the surface of the source insulating film 135 on the scanning line 101. As shown in FIG. 8, the shield electrode layer 150 is connected to the common wiring 1 outside the active display region 180.
03 and the common electrode line 31 through contact holes 171 and 172, respectively, to stabilize the potential. This is because the signal line 102, the source electrode 106 and the drain electrode 108 are formed to cover the source insulating film 135, and then contacted to the source insulating film 135 at a predetermined position corresponding to the common electrode line 31 outside the active display region 180. Hall 17
2 to expose a part of the common electrode line 31, and a contact hole 171 is formed in the source insulating film 135 and the gate insulating film 133 at predetermined positions corresponding to the common wiring 103 to form the shield electrode layer 150. A transparent conductive layer is covered and formed. At this time, the shield electrode layer 150 is electrically connected to the common wiring 103 and the common electrode line 31 through the contact holes 171 and 172.

In order not to affect the operating characteristics of the TFT 110, the shield electrode layer 15
0 should not cover the surface of the semiconductor layer 109. Therefore, in the FFS mode liquid crystal display region 100 according to the first embodiment of the present invention, a notch is provided in a part of the pixel electrode 105, and the TFT 110 is provided in this part. The shield electrode 150 may be formed of a conductive metal such as aluminum instead of ITO. The surface of the pixel electrode 105, the plurality of slits 105a, and the shield electrode layer 150 is covered with an alignment film 134.

On the other hand, the color filter substrate 120 is made of a glass substrate 122 as shown in FIG.
A color filter layer 123, an overcoat layer 125, and an alignment film 124 are provided on the surface. Then, the array substrate 130 and the color filter substrate 120 are opposed so that the pixel electrode 105 and the common electrode 104 of the array substrate 130 and the color filter layer 123 of the color filter substrate 120 are opposed to each other, and liquid crystal is sealed between them. The FFS mode liquid crystal display panel 1 is formed by forming the layer 140 and disposing the polarizing plates 121 and 131 on the outer sides of the substrates 120 and 130 so that the polarization directions are perpendicular to each other.
00 is formed.

In the first embodiment, an example in which the slit provided in the pixel electrode 105 is tilted in one direction has been shown. However, as a conventional example, the pixel electrode as in the FFS mode liquid crystal display panel shown in FIG. The stripe-shaped slits 105a provided in 105 may be arranged in a “<” shape to form a dual domain. In this case, in order to reduce viewing angle anisotropy, the number of slits 105 a provided on both sides of the common wiring 103 is preferably the same on each side, and the slits on both sides closest to the common wiring 103 are also provided. The end of 105a is preferably connected on the common wiring. Further, although not shown in the figure, in order to make the black matrix of the color filter substrate 120 provided in the portion facing the signal line 102 not linear, the signal is suitable for image display in which the black matrix is not conspicuous. The lines 102 may be provided in a crank shape in a direction orthogonal to the scanning lines 101 so that the plurality of common electrodes 104 and the pixel electrodes 105 have a delta arrangement.

In addition, the configuration of the FFS mode liquid crystal display panel 100 described in the first embodiment, particularly the configuration related to the shield electrode, can be easily applied to the IPS mode liquid crystal display panel 600 as shown in FIG. Here, in order to avoid duplication of explanation, the IPS shown as the conventional example is applied to the liquid crystal display panel 600 of the IPS mode applied to the configuration of the present invention.
As in the liquid crystal display panel 600 in the mode, the pixel electrode and the counter electrode and the alignment film are rubbed in the rubbing direction so as to form a dual domain, and the pixel electrode and the counter electrode are arranged in a delta arrangement. Obviously, it is possible to

1 is a circuit configuration diagram of a driving system of an FFS mode liquid crystal display panel according to a first embodiment of the present invention. FIG. FIG. 2 is a schematic plan view showing a pixel region on an array substrate constituting the FFS mode liquid crystal display panel according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view taken along line A-A ′ in the pixel region of the FFS mode liquid crystal display panel according to the first embodiment of the present invention shown in FIG. 2. FIG. 3 is a cross-sectional view taken along line B-B ′ in the pixel region of the FFS mode liquid crystal display panel according to the first embodiment of the present invention shown in FIG. 2. FIG. 3 is a cross-sectional view taken along line C-C ′ in the pixel region of the FFS mode liquid crystal display panel according to the first embodiment of the present invention shown in FIG. 2. FIG. 5 is a schematic plan view illustrating a modification example in a pixel region of the FFS mode liquid crystal display panel according to the first embodiment of the present invention illustrated in FIG. 2. FIG. 2 is a schematic plan view showing the outside of an active display area on an array substrate constituting the FFS mode liquid crystal display panel according to the first embodiment of the present invention. FIG. 8 is a cross-sectional view taken along line D-D ′ outside the active display region of the FFS mode liquid crystal display panel according to the first embodiment of the present invention shown in FIG. 7. It is the model top view which showed the pixel area | region of the array substrate which comprises the liquid crystal display panel of the conventional IPS mode. FIG. 10 is a cross-sectional view taken along line E-E ′ in the pixel region of the conventional IPS mode liquid crystal display panel shown in FIG. 9. FIG. 10 is a cross-sectional view taken along line F-F ′ in the pixel region of the conventional IPS mode liquid crystal display panel shown in FIG. 9. It is the model top view which showed the pixel area | region of the array substrate which comprises the conventional liquid crystal display panel of FFS mode. FIG. 13 is a cross-sectional view taken along line G-G ′ in the pixel region of the conventional FFS mode liquid crystal display panel shown in FIG. 12. FIG. 13 is a cross-sectional view taken along line H-H ′ in the pixel region of the conventional FFS mode liquid crystal display panel shown in FIG. 12. FIG. 16 is a schematic plan view showing a modification of the pixel region of the conventional FFS mode liquid crystal display panel shown in FIG. 12. FIG. 10 is a schematic plan view showing a modification of the pixel region of the conventional IPS mode liquid crystal display panel shown in FIG. 9.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Scan electrode drive circuit 20 Signal electrode drive circuit 30 Common electrode drive circuit 31 Common electrode line 100 Liquid crystal display panel 101, 601, 701 Scan line 102, 602, 702 Signal line 103, 603, 703 Common wiring 104 Common electrode 105 Pixel electrode 105a Slit 106 Source electrode 107 Gate electrode 108 Drain electrode 109 Semiconductor layer 110 TFT
120 Color filter substrate 130 Array substrate 140 Liquid crystal layer 150 Shield electrode layer 170 Contact hole

Claims (5)

A plurality of scanning lines and common lines formed in parallel on the substrate;
A plurality of signal lines extending in a direction orthogonal to the scanning lines and the common lines;
A common electrode and a pixel electrode formed in each pixel region partitioned by the scanning line and the signal line;
A plurality of shield electrode layers made of a conductive material extending in the same direction as the scanning line and electrically connected to the common wiring outside the active display region constituted by the pixel region;
A liquid crystal display panel comprising: The liquid crystal display panel according to claim 1, wherein the shield electrode layer is formed through an insulating layer so as to cover the scanning line. 2. The shield electrode layer is formed in a continuous band shape.
Or the liquid crystal display panel of Claim 2. The liquid crystal display panel according to claim 1, wherein an end portion of the common wiring is formed in a comb shape. 5. The liquid crystal display panel according to claim 1, wherein the shield electrode layer is electrically connected to the common line at both ends outside the active display area. 6.

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