JP2009064980A - Method of manufacturing imaging apparatus, imaging apparatus, and imaging system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing an imaging apparatus which can fine a surrounding area, reducing a noise component of a signal read out from an imaging area, and to provide an imaging apparatus and an imaging system. <P>SOLUTION: The method is a process for manufacturing the imaging apparatus having a semiconductor substrate which includes the imaging area with a plurality of pixels are located and the surrounding area with a control circuit located to control a plurality of pixels in the surrounding of the imaging area. The process includes a first step which forms in the surrounding area a first STI type element isolation portion to electrically isolate a plurality of elements contained in the control circuit, and second step which forms in the imaging area a second LOCOS type element isolation portion to electrically isolate a plurality of elements contained in each of a plurality of pixels. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an imaging device manufacturing method, an imaging device, and an imaging system.

  An imaging device such as a MOS sensor has a semiconductor substrate including an imaging region in which a plurality of pixels are arranged and a peripheral region in which a control circuit for controlling the plurality of pixels is arranged around the imaging region. The element separation unit that separates the plurality of elements included in each of the plurality of pixels in the imaging region and the element separation unit that separates the plurality of elements included in the control circuit in the peripheral region have the same element isolation structure. It is common.

  Here, if an STI (Shallow Trench Isolation) type element isolation portion is formed in the peripheral region and the imaging region, the entire area can be miniaturized, so that the chip area of the imaging device can be reduced. In the case of forming an STI type element isolation portion, a groove is formed, and an insulating film is buried in the groove. Here, when the trench is formed, etching damage (for example, plasma damage) may be given to the semiconductor substrate, or the semiconductor substrate may be stressed by the insulating film buried in the trench.

On the other hand, in the technique of Patent Document 1, when forming the element isolation portion in the imaging region of the semiconductor substrate, a groove having a shallower depth than the peripheral region is formed, and an insulating film is embedded in the shallow groove. Thus, an element isolation portion is formed. According to Patent Document 1, this can reduce the occurrence of crystal lattice distortion, crystal defects, and the like in the imaging region of the semiconductor substrate as compared to the peripheral region.
JP 2005-347325 A

  However, in the technique of Patent Document 1, when forming the element isolation portion, the semiconductor substrate is etched in the imaging region to form a groove on the surface thereof. As a result, the pixels included in the imaging region may be subjected to etching damage (for example, plasma damage), or metal impurities may be mixed into the pixels. As a result, a dark current or the like may occur, so that a noise component in a signal read from a pixel in the imaging region may increase.

  In the technique of Patent Document 1, since an insulating film is embedded in a groove formed on the surface of the semiconductor substrate when the element isolation portion is formed, stress may be applied to the semiconductor substrate by the embedded insulating film. . As a result, a dark current or the like may occur, so that a noise component in a signal read from a pixel in the imaging region may increase.

  On the other hand, if the LOCOS (LOCal Oxidation of Silicon) type element isolation part is formed in the peripheral region and the imaging region, the above-described problem can be avoided. In this case, it becomes difficult to reduce the size as a whole.

  Here, as a result of examination, the present inventor has reached the following view.

  In the imaging area, it is necessary to read out a minute analog signal, whereas in the peripheral area, an amplified signal and a digital signal are handled. That is, the above-described problems such as etching damage are not so much a problem in the peripheral area as compared with the imaging area.

  Further, in the peripheral region, it is required to increase the speed, multifunction, and power consumption of the control circuit. That is, the necessity for miniaturizing elements is higher in the peripheral region than in the imaging region.

  An object of the present invention is to provide an image pickup apparatus manufacturing method, an image pickup apparatus, and an image pickup system capable of miniaturizing a peripheral area while reducing a noise component in a signal read from the image pickup area.

  The manufacturing method of the imaging device according to the first aspect of the present invention includes an imaging region in which a plurality of pixels are arranged, and a peripheral region in which a control circuit that controls the plurality of pixels is arranged around the imaging region. A manufacturing method of an imaging device having a semiconductor substrate, wherein a first STI-type element isolation portion for electrically isolating a plurality of elements included in the control circuit is formed in the peripheral region. And a second step of forming, in the imaging region, a LOCOS-type second element isolation portion for electrically isolating a plurality of elements included in each of the plurality of pixels. Features.

  STI is an abbreviation for Shallow Trench Isolation. LOCOS is an abbreviation for LOCal Oxidation of Silicon.

  An imaging apparatus according to a second aspect of the present invention includes a semiconductor substrate including an imaging region in which a plurality of pixels are arranged and a peripheral region in which a control circuit that controls the plurality of pixels is arranged in the periphery of the imaging region. In the imaging apparatus, the peripheral region includes a control circuit that controls the plurality of pixels, and an STI-type first element isolation unit that electrically isolates the plurality of elements included in the control circuit. In the imaging region, a plurality of pixels and a LOCOS-type second element isolation unit that electrically isolates a plurality of elements included in each of the plurality of pixels are arranged, and the first region The height of the element isolation part from the surface of the semiconductor substrate is lower than the height of the second element isolation part from the surface of the semiconductor substrate.

  An imaging system according to a third aspect of the present invention processes an imaging device according to the second aspect of the present invention, an optical system that forms an image on the imaging surface of the imaging device, and a signal output from the imaging device. And a signal processing unit for generating image data.

  According to the present invention, the peripheral area can be miniaturized while reducing the noise component of the signal read from the imaging area.

  The present invention relates to an imaging apparatus used for a digital still camera, a digital video camera, and the like, and a manufacturing method thereof.

  A schematic configuration of an imaging apparatus 200 according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a diagram illustrating a circuit configuration of an imaging apparatus 200 according to an embodiment of the present invention. FIG. 2 is a diagram illustrating a cross-sectional configuration of the imaging apparatus 200 according to the embodiment of the present invention. In the description of the present embodiment and each drawing, the detailed description of the contact, wiring layer, color filter, microlens, and the like is omitted for the sake of simplicity.

  The imaging device 200 includes a semiconductor substrate SB. The semiconductor substrate SB includes an imaging region 220, a peripheral region 210, and a boundary region 230 between them.

  In the imaging region 220, a plurality of pixels P and a second element isolation unit 221 are arranged. The plurality of pixels P are arranged in the row direction and the column direction. The pixel P includes a reset transistor 225, a photodiode 226, a transfer gate 227, a floating diffusion (hereinafter referred to as FD) 228, and an amplification transistor 229. The reset transistor 225 resets the FD 228. The photodiode 226 photoelectrically converts incident light and accumulates electric charges (signals). The transfer gate 227 transfers the charge (signal) accumulated by the photodiode 226 to the FD 228. The FD 228 converts the electric charge (signal) into a voltage (signal). The amplification transistor 229 amplifies the signal input from the FD 228 and outputs the amplified signal to the column signal line RL. In this way, a signal is read from the pixel P.

  Here, if there is etching damage, metal impurities, crystal lattice distortion, crystal defects, or the like in the vicinity of the photodiode 226 of the pixel P, a dark current may be generated. In this case, the noise component in the signal read from the pixel P may increase.

  In the imaging region 220, a well region 240 (see FIG. 2) is formed around the pixel P. The second element isolation unit 221 is a LOCOS type element isolation unit, and a plurality of elements (225, 226, 227, 228, 229, etc.) included in each of the plurality of pixels P by the LOCOS method, The pixel is electrically separated.

  Here, in the imaging region 220, the second element isolation part 221 is formed by a method that does not include a step of etching the semiconductor substrate SB. Thereby, in the imaging region 220, it is possible to reduce the etching damage of the pixel P and the mixing of metal impurities into the pixel P, so that the noise component in the signal read from the pixel P can be suppressed.

  The peripheral area 210 is located around the imaging area 220. In the peripheral region 210, a control circuit and a first element isolation unit 211 are arranged. The control circuit includes a circuit for controlling a plurality of pixels P and a circuit for outputting signals from the pixels P. The control circuit includes, for example, a vertical scanning circuit VSR for scanning a row of a plurality of pixels P, a reading circuit RC for reading signals from the pixels P in each column, and a horizontal scanning circuit HSR for scanning the columns of the reading circuits. including. The readout circuit includes, for example, a circuit for amplifying a signal from the pixel P, an output line for output, and a switch. The first element isolation unit 211 is an STI type element isolation unit that electrically isolates a plurality of elements and circuits (VSR, RC, HSR, etc.) included in the control circuit by the STI method.

  Here, in the peripheral region 210, the circuit scale tends to increase, and it is required to miniaturize the element. On the other hand, the first element isolation part 211 is formed by filling an insulating film in a groove formed in a semiconductor substrate. For this reason, since the difference between the dimension of the element isolation part to be designed and the dimension of the element isolation part actually formed can be eliminated, the element spacing can be made fine in the peripheral region 210, and the circuit can be made fine.

  On the other hand, the imaging area 220 has a smaller circuit scale than the peripheral area 210, so that the necessity for miniaturizing the element is small. That is, if only the elements in the peripheral region 210 are miniaturized, the chip area of the imaging device 200 can be sufficiently reduced.

  The boundary area 230 is located at the boundary between the imaging area 220 and the peripheral area 210. The boundary region 230 may include an active region 231 in which the well region 240 around the photodiode 226 extends from the imaging region 220. In this case, a well contact (not shown) for supplying a voltage to the well region 240 may be formed in the active region 231. Thereby, since the potential of the well region 240 can be stabilized, the charge accumulation operation of the photodiode 226 can be stabilized.

  When the boundary region 230 is not provided, the second element isolation portion 221 may be disposed between the imaging region 220 and the peripheral region 210 in order to reduce etching damage to the imaging region 220.

  Here, the second element isolation unit 221 in the imaging area 220 and the first element isolation unit 211 in the peripheral area 210 will be compared.

  The height H1 of the second element isolation part 221 from the surface of the semiconductor substrate SB is lower than the height H2 of the first element isolation part 211 from the surface of the semiconductor substrate SB. As will be described later, this feature is that the step of forming the second element isolation portion 221 (first step) is performed before the step of forming the first element isolation portion 211 (second step). It is due to that.

  Next, a method for manufacturing the imaging device 200 according to the embodiment of the present invention will be described with reference to FIGS. 3 to 9 are process cross-sectional views illustrating the method for manufacturing the imaging device 200 according to the embodiment of the present invention.

  In the step (first step) shown in FIG. 3, the pad oxide film 214 is formed by oxidizing the surface of the silicon substrate SB so as to extend to the imaging region 220 and the peripheral region 210. The thickness of this pad oxide film 214 is, for example, 5 to 20 nm.

  Next, a first silicon nitride film 215 is formed on the pad oxide film 214 by CVD or the like so as to extend to the imaging region 220 and the peripheral region 210. The thickness of the first silicon nitride film 215 is, for example, 100 to 200 nm.

  In the process shown in FIG. 4 (groove formation step of the first step), a groove (trench) 216 is formed on the surface of the semiconductor substrate SB by etching the surface of the semiconductor substrate SB in part of the peripheral region 210. Form.

  Specifically, a resist pattern is formed in the peripheral region 210 using a photolithography technique, and the silicon substrate SB is anisotropically etched using the resist pattern as a mask. Thereby, a groove 216 is formed in the silicon substrate SB. The groove 216 is a groove formed by the STI method, and is formed with a large aspect ratio (depth / width). The depth of the groove 216 is, for example, 250 to 400 nm. The angle formed between the side wall of the groove 216 and the normal to the surface of the semiconductor substrate SB is, for example, 0 to 20 °.

  Next (embedding step of the first step), the first insulating film 211 is embedded in the trench 216 in the peripheral region 210. Specifically, after oxidizing the surface of the trench 216 to a thickness of, for example, 5 to 50 nm, an insulating film is embedded in the trench by HDP (high density plasma) method.

  After that (first planarization step), the surface of the first insulating film 211 is planarized by CMP or the like. Here, the first silicon nitride film 215 serves as a stopper when the surface is flattened by a CMP method or the like (see FIG. 5).

  Further, (a heat treatment step of the first step), a heat treatment is performed to bake the first insulating film 211 embedded in the trench 216 (see FIG. 4). Thereby, the crystal defects of the silicon substrate SB are reduced, and the crystallinity is recovered. Here, the temperature of the heat treatment for baking the first insulating film 211 is higher than the temperature for thermally oxidizing the semiconductor substrate SB in order to form the second element isolation portion 221 in a later step. In addition, the atmosphere when the first insulating film 211 is heat-treated is an inert atmosphere such as an inert gas or a vacuum.

  As described above, the peripheral region 210 can be further miniaturized by using an STI type element isolation portion formed by embedding and baking an insulating film in a trench having a high aspect ratio (depth / width).

  Next, in the step shown in FIG. 6 (second step), a second silicon nitride film 218 is formed on the first silicon nitride film 215 by CVD or the like. The thickness of the second silicon nitride film 218 is, for example, 50 to 200 nm.

  In the process shown in FIG. 7 (second step), a resist pattern is formed in the imaging region 220 using a photolithography technique, and the second silicon nitride film 218 and the first silicon nitride film 215 are formed using the resist pattern as a mask. Perform anisotropic etching. As a result, an opening 222 is formed in the second silicon nitride film 218 and the first silicon nitride film 215, and a part of the pad oxide film 214 is exposed. Here, the upper portion of the pad oxide film 214 is etched to such an extent that the surface of the semiconductor substrate SB is not exposed. That is, by stopping the etching in the middle of the pad oxide film 214, the pixel P in the imaging region 220 of the semiconductor substrate SB is not easily damaged by etching (plasma damage), and metal impurities are not easily mixed into the pixel P.

  In the step (second step) shown in FIG. 8, in the imaging region 220, the region exposed in the opening 222 in the pad oxide film 214 is selectively thermally oxidized. As a result, the second insulating film grows and the second element isolation portion 221 is formed. The second element separation unit 221 is a film for electrically separating a plurality of elements (225, 226, 227, 228, 229, etc.) included in each of the plurality of pixels P and pixels from each other by the LOCOS method. is there. The thickness of the second element isolation part 221 is, for example, 300 to 500 nm. The angle formed between the side surface of the second element isolation part 221 and the normal to the surface of the semiconductor substrate SB is, for example, 55 to 75 °. Here, the temperature at which the semiconductor substrate SB is thermally oxidized in order to form the second element isolation part 221 is lower than the temperature for heat-treating the first element isolation part 211. The atmosphere when the second element isolation part 221 is heat-treated is an oxidizing atmosphere such as oxygen.

In the step shown in FIG. 9, the first silicon nitride film 215 and the second silicon nitride film 218 are removed by hot phosphoric acid or the like. Further, the pad oxide film 214 is removed with buffered hydrofluoric acid. Thereafter, a photodiode 226, a wiring layer (not shown), a color filter layer (not shown), a microlens (not shown), and the like are formed.

  As described above, in the imaging region 220, a LOCOS-type element isolation portion that does not include the step of etching the semiconductor substrate SB is formed. Thereby, in the imaging region 220, the pixel P can be made less susceptible to etching damage, and metal impurities can be made less likely to be mixed into the pixel P, so that crystal lattice distortion and crystal defects in the pixel P can be reduced. Furthermore, since the insulating film is not embedded in the trench, the stress exerted on the pixel P by the element isolation portion (insulating film) can be reduced. As a result, crystal lattice distortion, crystal defects, and the like in the pixel P can be reduced. As a result, generation of dark current or the like can be reduced, so that noise components in signals read from the pixels P in the imaging region 220 can be suppressed.

  In the peripheral region 210, an STI-type element isolation portion suitable for miniaturization is formed. Thereby, the element can be miniaturized in the peripheral region 210.

  Therefore, according to the present embodiment, it is possible to reduce the size of the peripheral area 210 while reducing the noise component in the signal read from the imaging area 220.

  Further, since the second element isolation portion 221 is formed by the LOCOS method after the first element isolation portion 211 is formed by the STI method, the first element isolation portion 221 is formed in comparison with the case where the second element isolation portion 221 is formed first. It becomes easy to flatten the surface of the element isolation part 211. Thereby, the height H1 of the first element isolation part 211 from the surface of the semiconductor substrate SB can be easily made lower than the height H2 of the second element isolation part 221 from the surface of the semiconductor substrate SB (see FIG. 2). ). As a result, it is possible to reduce problems that occur when the height H2 is greater than the height H1 (for example, a space for forming an element is limited and miniaturization becomes difficult).

  Further, since the LOCOS-type second element isolation part 221 is formed after the formation of the STI-type first element isolation part 211, the second element isolation part 221 is subjected to high temperature heat more than necessary (design). It is possible to reduce expansion (deviation from the value). Further, stress due to high temperature heat applied to the second element isolation portion 221 and thermal diffusion of impurities can be reduced.

  Since the first element isolation part 211 is an STI type and the second element isolation part 221 is a LOCOS type, the inclination angle B of the side surface of the second element isolation part 221 is as shown in FIG. The inclination angle A of the side surface of the first element isolation part 211 is larger.

  Next, an example of an imaging system to which the imaging apparatus of the present invention is applied is shown in FIG.

  As shown in FIG. 11, the imaging system 90 mainly includes an optical system, an imaging device 200, and a signal processing unit. The optical system mainly includes a shutter 91, a photographing lens 92, and a diaphragm 93. The signal processing unit mainly includes an imaging signal processing circuit 95, an A / D converter 96, an image signal processing unit 97, a memory unit 87, an external I / F unit 89, a timing generation unit 98, an overall control / calculation unit 99, and a recording. A medium 88 and a recording medium control I / F unit 94 are provided. The signal processing unit may not include the recording medium 88.

  The shutter 91 is provided in front of the photographic lens 92 on the optical path and controls exposure.

  The photographic lens 92 refracts incident light to form an image of a subject on a pixel array (imaging surface) of the imaging device.

  The diaphragm 93 is provided between the photographing lens 92 and the imaging device 200 on the optical path, and adjusts the amount of light guided to the imaging device 200 after passing through the photographing lens 92.

  The imaging apparatus 200 converts an image of a subject formed in the imaging area 220 into an image signal. The imaging apparatus 200 reads out the image signal from the imaging area 220 and outputs it.

  The imaging signal processing circuit 95 is connected to the imaging device 200 and processes an image signal output from the imaging device 200.

  The A / D converter 96 is connected to the imaging signal processing circuit 95 and converts the processed image signal (analog signal) output from the imaging signal processing circuit 95 into a digital signal.

  The image signal processing unit 97 is connected to the A / D converter 96, and performs various kinds of arithmetic processing such as correction on the image signal (digital signal) output from the A / D converter 96 to generate image data. To do. The image data is supplied to the memory unit 87, the external I / F unit 89, the overall control / calculation unit 99, the recording medium control I / F unit 94, and the like.

  The memory unit 87 is connected to the image signal processing unit 97 and stores the image data output from the image signal processing unit 97.

  The external I / F unit 89 is connected to the image signal processing unit 97. Thus, the image data output from the image signal processing unit 97 is transferred to an external device (such as a personal computer) via the external I / F unit 89.

  The timing generation unit 98 is connected to the imaging device 200, the imaging signal processing circuit 95, the A / D converter 96, and the image signal processing unit 97. Thereby, a timing signal is supplied to the imaging device 200, the imaging signal processing circuit 95, the A / D converter 96, and the image signal processing unit 97. The imaging device 200, the imaging signal processing circuit 95, the A / D converter 96, and the image signal processing unit 97 operate in synchronization with the timing signal.

  The overall control / arithmetic unit 99 is connected to the timing generation unit 98, the image signal processing unit 97, and the recording medium control I / F unit 94, and the timing generation unit 98, the image signal processing unit 97, and the recording medium control I / F. The unit 94 is controlled as a whole.

  The recording medium 88 is detachably connected to the recording medium control I / F unit 94. As a result, the image data output from the image signal processing unit 97 is recorded on the recording medium 88 via the recording medium control I / F unit 94.

  With the above configuration, if a good image signal is obtained in the imaging apparatus 200, a good image (image data) can be obtained.

1 is a diagram illustrating a circuit configuration of an imaging apparatus 200 according to an embodiment of the present invention. The figure which shows the cross-sectional structure of the imaging device 200 which concerns on embodiment of this invention. Process sectional drawing which shows the manufacturing method of the imaging device 200 which concerns on embodiment of this invention. Process sectional drawing which shows the manufacturing method of the imaging device 200 which concerns on embodiment of this invention. Process sectional drawing which shows the manufacturing method of the imaging device 200 which concerns on embodiment of this invention. Process sectional drawing which shows the manufacturing method of the imaging device 200 which concerns on embodiment of this invention. Process sectional drawing which shows the manufacturing method of the imaging device 200 which concerns on embodiment of this invention. Process sectional drawing which shows the manufacturing method of the imaging device 200 which concerns on embodiment of this invention. Process sectional drawing which shows the manufacturing method of the imaging device 200 which concerns on embodiment of this invention. Sectional drawing which shows the structure of an element isolation part. 1 is a configuration diagram of an imaging system to which an imaging apparatus according to an embodiment is applied.

Explanation of symbols

211 First element isolation part 219 Groove 221 Second element isolation part

Claims (7)

A method of manufacturing an imaging device having a semiconductor substrate including an imaging region in which a plurality of pixels are arranged and a peripheral region in which a control circuit for controlling the plurality of pixels is arranged around the imaging region,
A first step of forming an STI-type first element isolation portion for electrically isolating a plurality of elements included in the control circuit in the peripheral region;
A second step of forming, in the imaging region, a LOCOS-type second element isolation portion for electrically isolating a plurality of elements included in each of the plurality of pixels;
An image pickup apparatus manufacturing method comprising: The method of manufacturing an imaging apparatus according to claim 1, wherein the first step is performed before the second step. The first step includes
A groove forming step of forming a groove in the surface of the semiconductor substrate by etching the surface of the semiconductor substrate in a partial region of the peripheral region;
A step of embedding an insulating film in the groove;
A planarization step of planarizing the surface of the insulating film;
The manufacturing method of the imaging device according to claim 2, wherein: 4. The height of the first element isolation part from the surface of the semiconductor substrate is lower than the height of the second element isolation part from the surface of the semiconductor substrate. Manufacturing method of imaging apparatus. The first step further includes a heat treatment step of performing a heat treatment after the embedding step,
4. The image pickup apparatus according to claim 3, wherein the temperature of the heat treatment is higher than a temperature for thermally oxidizing the semiconductor substrate to form the second element isolation portion in the second step. 5. Production method. An imaging apparatus having a semiconductor substrate including an imaging region in which a plurality of pixels are arranged and a peripheral region in which a control circuit that controls the plurality of pixels is arranged around the imaging region,
In the peripheral area,
A control circuit for controlling the plurality of pixels;
An STI-type first element isolation unit that electrically isolates a plurality of elements included in the control circuit;
Is arranged,
In the imaging area,
A plurality of pixels;
A LOCOS-type second element isolation unit that electrically isolates a plurality of elements included in each of the plurality of pixels;
Is arranged,
The height of the said 1st element isolation part from the surface of the said semiconductor substrate is lower than the height from the surface of the said semiconductor substrate of the said 2nd element isolation part, The imaging device characterized by the above-mentioned. An imaging device according to claim 6;
An optical system for forming an image on the imaging surface of the imaging device;
A signal processing unit that processes the signal output from the imaging device to generate image data;
An imaging system comprising:

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