JP2009059805A - Semiconductor device processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a processing method suitable for microfabrication of an device, having a structure which is called a "high-k/metal gate". <P>SOLUTION: A semiconductor device having the electrode structure, wherein, for example, an HfSiON insulating film 12 containing Hf or Zr is formed on an Si substrate 11 and a conductor film 13 containing Ti or Ta and the like, a conductor film 14, consisting principally of W and the like, a cap SiN layer 15, a BARC 16, and resist 17 are formed thereupon is subjected to dry etching processing so that the respective layers 13 to 17, on the insulating film 12, are etched in the horizontal direction, at substantially the same speeds in a pressure region of 1 Pa or lower with a gas that contains at least F. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a processing method of a fine semiconductor element, and particularly relates to a processing method suitable for miniaturization of an element having a structure usually called a high-k / metal gate.

Conventionally, in order to increase the speed and integration of semiconductor elements such as CMOS transistors, an insulating film made of a SiO ₂ film or the like is provided on a Si substrate, and a semiconductor element such as TiN or TaN is formed on the insulating film. Alternatively, there has been proposed a semiconductor device having a metal gate structure in which a metal material film for controlling the work function of n-type is provided, and a gate electrode material made of a material such as W or Mo is further provided on the metal material film.

As a method for processing such a semiconductor element, a method of etching a wiring having a resist / W / TiN / Si (silicon) structure at a pressure of 0.27 Pa using C ₄ F ₈ gas or SF ₆ gas is proposed. (For example, refer nonpatent literature 1).

  This document has a processing size of about 500 nm, and does not describe a method for achieving a processing size of 65 nm or less, which is a processing size (line width) that is currently required.

  On the other hand, when processing such a metal gate semiconductor element, a resist is provided on the above structure as a mask, and etching is performed using this mask. The line width of this mask is about 500 nm, and in order to reduce the line width of this mask to, for example, about 200 nm, a processing method called slimming is known.

  The processing method called slimming is to etch the resist laterally with a gas that has an effect of removing the resist, such as oxygen, before starting the etching of the semiconductor element that is the base material, thereby reducing the size of the resist mask. This is a technique for further reducing the line width from the mask size patterned by lithography. In this slimming method, since the resist is thinned and the thickness is reduced at the same time, there is a problem that the thickness of the resist is insufficient when the base material is etched. If the resist layer is made thick in order to compensate for the insufficient thickness of the resist mask, the thickness direction becomes too large with respect to the line width, and the resist may fall down and become unable to stand on its own. In generations that require a metal gate structure, the miniaturization of the element is 65 nm or less, and the thickness of the resist is becoming thinner accordingly. Therefore, it is difficult to cope with the conventional slimming technique.

A conventional structure of a semiconductor element having a layer structure in which an oxide film layer is present under a work function control metal TiN and a processing method of the semiconductor element will be described with reference to FIG. The substrate of the semiconductor element has an SiO ₂ film 120, a TiN film 13 as a work function control metal, a W film 14 as an electrode material, an SiN film 15 as a cap, and an antireflection film (BARC) 16 on an Si substrate 11. It has a metal gate structure in which a resist layer 17 deposited and patterned thereon is formed (FIG. 8A).

In the etching method of a semiconductor element having such a structure, in mask slimming, the resist 17 is thinned by slimming with oxygen plasma and the BARC 16 is etched (FIG. 8B). Next, the cap SiN layer 15, the electrode W layer 14, and the work function control metal TiN layer 13 are etched using CF ₄ or the like. In this processing method, as shown in FIG. 8C, the resist is etched only in the vertical direction during etching, and the line width cannot be reduced.

An object of the present invention is to perform a fine dry etching process of a semiconductor element called a metal gate, which has been proposed for higher speed transistors. In this structure processing, a metal for controlling the work function such as TiN or TaN is deposited on a gate insulating film (conventional SiO ₂ ), and a refractory metal such as W or Mo is further deposited. The structure is etched using a resist as a mask. Currently required processing size (line width) is 65 nm or less.

  On the other hand, in the slimming processing method, the resist becomes thin and the thickness becomes thin at the same time. Therefore, there is a problem that the thickness of the resist is insufficient when the base material is etched. In generations that require a metal gate structure, the line width (line width) is reduced to 65 nm or less due to miniaturization of the element, and the thickness of the resist becomes thinner accordingly, so it is difficult to cope with the conventional slimming technology. Yes.

In the SiO ₂ film used as an insulating film in the conventional metal gate structure, since the vapor pressure of SiF ₄ is very high, after the etching of the second conductor film is completed and the SiO ₂ film is exposed, the SiO ₂ film is exposed in a very short time. The SiO ₂ film is etched and penetrates, and there is a problem that the element cannot be processed with a gas containing F.
Journal of Vacuum Science and Technology (J.Vac.Sci.Technol.) A 13 1995 810-814 American Vacuum Society (American Vaccum Society)

The present invention provides an electrode structure in which an insulating layer exists under a metal gate structure composed of a first conductor film containing at least W, Ta, Ti, Mo and the like as a main component and a second conductor such as a work function control metal TiN. In a processing method of a semiconductor device having a metal gate structure, a metal gate structure having a structure for preventing penetration of the insulating film after the exposure of the SiO ₂ film, which is a conventional insulating layer, and a metal gate provided under the resist It is an object of the present invention to provide a processing method that enables processing to obtain a narrower line width with the same resist thickness as in the conventional method when performing vertical etching.

  That is, an object of the present invention is to provide a processing method suitable for miniaturization of an element having a structure called a high-k / metal gate.

  In the present invention, in order to further miniaturize an element having a metal gate structure, an oxide or nitride of Hf or Zr whose vapor pressure is relatively low when an insulating film deposited under the metal gate reacts with fluorine. (So-called high-k material) and at the same time while etching the metal gate in the vertical direction by etching under the condition that the etching rate in the horizontal direction of the metal gate material and the mask material is equal during the metal gate etching. Etching is also performed in the horizontal direction to narrow the line width, and thinner lines can be processed with thinner resist thickness.

  That is, the most important point in the present invention is that the metal gate has a first conductor film that forms a reaction product having a high vapor pressure by reaction with F (fluorine), and a semiconductor provided under the first conductor film. It is configured as a second conductor film that controls the threshold of the on / off operating voltage of the element, and a reaction product having a lower vapor pressure than the material constituting the metal gate is formed under the metal gate by reaction with F. An insulating film to be formed is provided. For example, the present invention uses W or Mo as the first conductor film, uses TiN or TaN as the second conductor layer, and has an HfSiON film that is an oxide such as Hf as the insulating film. .

  Further, it is desirable to keep the pressure of the etching gas at 3 Pa or less. If the pressure is higher than this, the collision frequency of the gas particles to the pattern side wall increases, so that the possibility of falling when the line becomes thin increases.

  That is, according to the present invention, the metal constituting the metal gate electrode such as W, Ti, Ta forms a reaction product having a high vapor pressure by F, and the gate insulating film deposited under these metals is F. And a processing method using an oxide or nitride of Hf that forms a reaction product having a relatively low vapor pressure (compared to chlorine). Therefore, a metal gate electrode material such as a metal having the same properties as W, Ti, Ta, for example, an electrode of Mo, or an insulating film having the same properties as the gate insulating film, for example, a combination of Zr, Al oxide, or nitride is the same. An effect is obtained.

  The structure of the electrode is not limited to the structure shown in FIG. 1, and the same effect can be obtained with a laminated film of a compound such as silicide, nitride, or the like of W, Ti, Ta, and Mo.

  Further, the wafer temperature is a temperature range from 0 ° C. to 50 ° C. suitable for equalizing the horizontal etching rate of each substance. The present invention utilizes the fact that Hf oxides or nitrides such as HfSiON are not easily etched by F. To realize this state, the power of the bias power source for accelerating ions is 50 W or less ( It is desirable to keep the output voltage amplitude at about 300 V or less. As the ion energy increases, the physical sputtering rate increases, so the etching rate of the Hf oxide increases and the selection ratio decreases. The amount of thinning is controlled by measuring the etching rate in the horizontal direction in advance and controlling the overetching time.

  In the processing method of the present invention, as shown in FIG. 1D, during etching of the metal gate, the resist, BARC, and metal gate are etched in the horizontal direction as well as in the vertical direction, and then the insulating film is over-etched. Thus, the resist, BARC, and metal gate are etched in the horizontal direction as well as in the vertical direction. On the other hand, in the conventional method, as shown in FIG. 8, the resist is etched only in the vertical direction during the etching. Therefore, in the present invention, a thinner line width can be obtained with the same resist and BARC thickness as compared with the conventional method.

  The present invention relates to a first conductive film that forms a reaction product having a high vapor pressure by reacting a metal gate with F (fluorine), and an on / off operation of a semiconductor element provided under the first conductive film. An insulating film is formed as a second conductor film for controlling the voltage threshold value, and an insulating film for forming a reaction product having a lower vapor pressure than the material constituting the metal gate is formed under the metal gate by reaction with F. Accordingly, the selectivity when etching the metal gate and the insulating film is increased, and the gate metal is etched in the lateral direction while the metal gate material is over-etched, so that the line width can be narrowed.

[Embodiment 1] A semiconductor element processing method by side etch slimming, which is a first embodiment of the present invention, will be described below with reference to FIG. In the semiconductor device of Example 1, the HfSiON film 12 as the gate insulating film, the TiN film 13 as the work function control metal constituting the metal gate, and the W film 14 as the electrode material constituting the metal gate are formed on the Si substrate 11. A high-k / metal gate structure in which a SiN film 15 as a cap and an antireflection film (BARC) 16 are deposited is provided, and a patterned resist 17 is provided on the BARC 16. The thicknesses of the HfSiON film 12 are 2 nm, the TiN film 13 is 10 nm, the W film 14 is 50 nm, the SiN film 15 is 50 nm, the BARC 16 is 80 nm, and the resist 17 is 200 nm.

The semiconductor element processing method according to the present invention will be described below. In the initial state, the resist 17 patterned by lithography is in the uppermost layer. The resist layer is patterned into a shape larger than the final line width (FIG. 1A). Next, in mask slimming, the resist 17 is thinned by slimming with oxygen plasma and the BARC 16 is etched (FIG. 1B). Next, in the cap etching, the cap SiN layer 15 is etched with a mixed gas of SF ₆ gas, CHF ₃ gas, and Ar gas (FIG. 1C). The process up to here is the same as the conventional miniaturization method.

Next, as a gas for etching the electrode W layer 14 and the work function control metal TiN layer 13, the resist 17, BARC 16, SiN layer 15, W layer 14, and TiN layer 13 are etched in the horizontal direction at a substantially equal speed v 1. In addition, a gas system is used in which the W layer 14 and the TiN layer 13 are etched in the vertical direction at a speed v2 that is several times larger than v1 and has a high selectivity with respect to the HfSiON layer 12. As an etching gas having such a function, a mixed gas containing fluorine such as SF ₂ , Cl ₂ , CHF ₃ , and NF ₃ can be used.

  Then, as shown in the slimming at the time of etching, the entire gate line width is narrowed by etching of W and TiN and overetching thereof (etching proceeds only in the horizontal direction while the vertical etching stops in the HfSiON layer 12). Thus, a finer semiconductor element can be processed (FIG. 1D).

Etching conditions for etching and side-etching the electrode W layer 14 and the work function control metal TiN layer 13 having the function of side-etching the resist 17, the BARC 16, and the SIN layer 15 and having selectivity for the HfSiON layer 12 Has been experimentally found to be achieved with a gas containing F such as SF ₆ , NF ₃ , CF ₄ , and CHF ₃ , or a gas obtained by mixing Cl ₂ , N ₂ , a rare gas, or the like with these gases.

As an example, in the structure shown in FIG. 1, SF ₂ gas is 20 ml / min, Cl ₂ gas is 20 ml / min, CHF ₃ gas is 40 ml / min, N ₂ gas is 100 ml / min, pressure is 1 Pa, wafer This can be achieved at a temperature of 30 ° C. According to this method, the initial 100 nm line can be narrowed to 50 nm or less after etching. Details of gas conditions for realizing side etch slimming will be described in Example 2.

[Embodiment 2] A semiconductor device processing method by side etch slimming, which is a second embodiment of the present invention, will be described below. The structure of the semiconductor element to which the processing method according to the present invention is applied and the processing steps will be described with reference to cross-sectional views schematically showing the processing steps of FIG. FIG. 2 is a schematic diagram created based on an SEM (electron microscope) photograph of a longitudinal section of the metal gate portion when the metal gate structure is etched under the conditions shown in Table 1.

  In this embodiment, a 2.5 nm HfSiON film 12, a 10 nm TaSiN film 13, and a 50 nm W film 14 are stacked on a silicon substrate 11 to form a metal gate structure, and an 80 nm SiN film 15 is further formed thereon. , 50 nm BARC 16 and 200 nm resist 17 are stacked (FIG. 2A). In FIG. 2A, the resist 17 is patterned and the initial line width is 100 nm.

First, the BARC 16 is etched under the following conditions. Etching gas species and flow rates are 75 ml / min for Ar, 35 ml / min for HBr, 10 ml / min for O ₂ , pressure 0.8 Pa, bias power 20 W, wafer temperature 30 ° C., until SiN film 15 is reached. Etched. At this time, the upper surface of the resist 17 is etched, but side etching is not performed, and the line width of 100 nm is maintained (FIG. 2B).

Next, the SiN film 15 is etched under the following conditions. The etching gas species and its flow rate are 50 ml / min for Ar, 160 ml / min for CHF _{3 and} 10 ml / min for SF ₆ , reach the W film 14 at a pressure of 1.2 Pa, a bias power of 30 W, and a wafer temperature of 30 ° C. Etched until. At this time, the upper surface of the resist 17 is etched, but the resist 17 and the BARC 16 are not side-etched, and the line width is 100 nm (FIG. 2C).

Next, the W film 14 is etched under the following conditions. The etching gas types and flow rates thereof are as follows: SF ₆ is 30 ml / min, Cl ₂ is 50 ml / min, N ₂ is 110 ml / min, O ₂ is 20 ml / min, pressure 1.0 Pa, bias power 20 W, wafer temperature 30 Etching was performed at a temperature of 15 ° C. for 15 seconds until the TaSiN film 13 was reached. At this time, the etching in the vertical direction proceeds simultaneously with the lateral etching (side etching) of each layer, and the line widths of the resist 17, BARC 16, and SiN film 15 become narrower (FIG. 2D).

Next, the TaSiN film 13 was etched under the same conditions as the etching of the W film 14 until reaching the HfSiON film 12. That is, the etching gas types and the flow rates thereof are SF ₆ for 30 ml / min, Cl ₂ for 50 ml / min, N ₂ for 110 ml / min, O ₂ for 20 ml / min, pressure 1.0 Pa, bias power 20 W, wafer At a temperature of 30 ° C., 29 seconds after the start of W etching, the TaSiN layer 13 is also etched, and the etching is stopped at the underlying HfSiON film 12. At this time, the side etching further proceeds, and the line widths of the resist 17, BARC 16, SiN film 15, and W film 14 are further reduced (FIG. 2E).

  Thereafter, the HfSiON film 12 is over-etched under the same conditions as the W film 14 and the TaSiN film 13 (35 seconds after the start of W etching). As a result, the HfSiON film 12 is hardly etched, but the resist 17, BARC 16, SiN film 15, W film 14, TaSiON film 13 side etching proceeds, and the line width can be reduced to a desired line width, for example, 35 nm. (FIG. 2 (F)).

  In this embodiment, in order to achieve side etch slimming, the amount of fluorine-containing gas is optimized to balance the horizontal etching rate and the vertical etching rate of each layer of resist / BARC / SiN / W / TaSiN. It is necessary to maintain and prevent unevenness between the layers. Furthermore, in order to require a certain amount of fluorine-containing gas, it is necessary to use an insulating film that is difficult to be etched by F as a base.

  In this embodiment, the conventional slimming for narrowing the line width by etching of the resist 17 and the BARC 16 is not performed, but a narrower line width can be realized by using the conventional slimming together.

Next, gas conditions for realizing side etch slimming will be described. The side etch rate of the W layer when the flow rate of SF ₆ is changed under the W / TaSiN layer etching conditions shown in Table 1 will be described with reference to FIG. The flow rates of Cl ₂ , N ₂ , and O ₂ are 50 ml / min, 110 ml / min, and 20 ml / min, respectively, and the pressure is 1 Pa. In FIG. 3, the horizontal axis represents the flow rate of SF ₆ (ml / min), and the vertical axis represents the side etch rate (nm / min) of the W layer. Increasing the flow rate of F increases the side etch rate, where a negative rate means that the shape is tapered. In Example 2, when SF ₆ is flowed at a rate of ₆ ml / min or more, side etching can proceed and the line width can be reduced.

The side etch rate when the flow rates of Cl ₂ , N ₂ , and O ₂ are changed will be described with reference to FIGS. FIG. 4 shows a case where the flow rate of Cl ₂ is changed. The flow rates of N ₂ , O ₂ , and SF ₆ are 110 ml / min, 20 ml / min, and 30 ml / min, respectively, and the pressure is 1 Pa. FIG. 5 shows a case where the flow rate of N ₂ is changed. The flow rates of CI ₂ , O ₂ , and SF ₆ are 50 ml / min, 20 ml / min, and 30 ml / min, respectively, and the pressure is 1 Pa. FIG. 6 shows the case where the flow rate of O ₂ is changed. The flow rates of CI ₂ , N ₂ and SF ₆ are 50 ml / min, 110 ml / min and 30 ml / min, respectively, and the pressure is 1 Pa.

When these gas flow rates are increased, the side etch rate tends to be slow, and the shape can be finely adjusted. Regarding Cl ₂ , since the vapor pressure of the reactive organism WCl ₅ with W is not so high, it has a function of suppressing side etching when deposited on the side wall without ion irradiation. Therefore, side etch slimming cannot be realized with Cl2 alone.

In order to realize side etch slimming, it is necessary to maintain a balance of side etch speeds between different materials so that no step is generated. For this purpose, optimization of the wafer temperature is important. In Example 2, the temperature of the wafer is set to 30 ° C., but if the temperature is different, the balance of the side etching rate is lost and unevenness is generated between the layers. In this case, the gas ratio of SF ₆ or the like may be adjusted again.

In Example 2, SF ₆ is used as the fluorine-containing gas, but the same effect can be obtained with CF ₄ and NF ₃ .

[Embodiment 3] A third embodiment of the present invention will be described with reference to Table 2. Example 3 is an example in which etching of W / TiN as a metal gate material was performed in several steps.

  Under these conditions, the BARC / SiN etching conditions are changed, but this is a change unrelated to slimming.

In the third embodiment, a wafer in which an HfSiON film 12, a TiN film 13, a W film 14, a SiN film 15, a BARC 16, and a resist 17 are stacked on a Si substrate 11 is used. The etching gas species and flow rate of BARC 16 are 75 ml / min for Ar, 35 ml / min for HBr, 10 ml / min for O ₂ , pressure 0.8 Pa, bias power 40 W, wafer temperature 30 ° C., and SiN film 15. Etched until reached.

Next, the SiN film 15 is etched under the following conditions. The etching gas species and its flow rate are 50 ml / min for Ar, 160 ml / min for CHF _{3 and} 20 ml / min for SF ₆ , reach the W film 14 at a pressure of 1.2 Pa, a bias power of 40 W, and a wafer temperature of 30 ° C. Etched until. At this time, the upper surface of the resist 17 is etched, but the resist 17 and the BARC 16 are not side-etched.

Further, the W film 14 and the TiN film 13 were continuously etched under the following conditions. The etching gas and its flow rate are 20 ml / min for CHF ₃ , 20 ml / min for SF ₆ , 50 ml / min for Cl _{2 and} 110 ml / min for N ₂ , pressure 1.0 Pa, bias power 20 W, wafer temperature 30 ° C. Then, etching was performed up to the vicinity of the HfSiON film 12.

Further, the TiN film 13 was over-etched under the following conditions. The etching gas and its flow rate are Cl ₂ of 30 ml / min, HBr of 50 ml / min, a pressure of 0.2 Pa, a bias power of 20 W, and a wafer temperature of 30 ° C. By this over-etching, the shape of the TiN film 13 and the W film 14 can be made more vertical without the HfSiON film 12 being etched.

In Example 3, etching of W / TiN is performed with a mixed gas of SF ₆ / CHF ₃ / Cl ₂ / N ₂ , and even under this condition, the content of SF ₆ is in a region where side etching occurs, and side etch slimming is performed. Can do. Furthermore, after etching W / TiN by side etch slimming, additional etching is performed using HBr / Cl ₂ gas. Under this gas condition, side etch slimming does not occur, but it is finally inserted to make the shape of TiN more vertical.

  As described above, the W / metal layer can be divided into several steps for more precise shape control. In Example 3, the initial resist line width is 100 nm, and the line width after etching is 20 nm or less. When this microfabrication is performed by a conventional slimming method, the resist height is also reduced by 80 nm when the initial resist line width is set to 20 nm, and the remaining 120 nm. When a layer of SiN or less is etched with this resist thickness by the conventional etching method, the resist disappears midway, and a line width of 20 nm cannot be realized.

  In addition to the third embodiment, as an example of dividing the etching into several, the bias voltage can be decreased immediately before the HfSiON is exposed to improve the ratio to HfSiON.

[Embodiment 4] A fourth embodiment of the present invention will be described with reference to Table 3. In the fourth embodiment, the W / metal layer can be etched in the same manner as the resist line width without performing side etch slimming. That is, the etching is performed by setting the amount of SF ₆ at the time of W / TaSiN etching to 5 ml / min at which the side etch rate becomes almost zero. Table 3 shows the etching conditions.

In the fourth embodiment, a wafer in which an HfSiON film 12, a TaSiN film 13, a W film 14, a SiN film 15, a BARC 16, and a resist 17 are stacked on an Si substrate 11 is used. The etching gas species and flow rate of BARC 16 are 75 ml / min for Ar, 35 ml / min for HBr, 10 ml / min for O ₂ , pressure 0.8 Pa, bias power 40 W, wafer temperature 30 ° C., and SiN film 15. Etched until reached.

Next, the SiN film 15 is etched under the following conditions. The etching gas species and its flow rate are 50 ml / min for Ar, 160 ml / min for CHF _{3 and} 20 ml / min for SF ₆ , reach the W film 14 at a pressure of 1.2 Pa, a bias power of 40 W, and a wafer temperature of 30 ° C. Etched until. At this time, the upper surface of the resist 17 is etched, but the resist 17 and the BARC 16 are not side-etched.

Further, the W film 14 and the TaSiN film 13 were continuously etched under the following conditions. The etching gas and its flow rate are 40 ml / min for CHF ₃ , 5 ml / min for SF ₆ , 50 ml / min for Cl _{2 and} 105 ml / min for N ₂ , pressure 1.0 Pa, bias power 20 W, wafer temperature 30 ° C. Then, etching was performed up to the vicinity of the HfSiON film 12.

Further, the TaSiN film 13 was over-etched under the following conditions. The etching gas and its flow rate are Cl ₂ of 30 ml / min, HBr of 50 ml / min, a pressure of 0.2 Pa, a bias power of 20 W, and a wafer temperature of 30 ° C. By this over-etching, the desired line width can be obtained without etching the HfSiON film 12. Thus, when the side etch rate is adjusted to be 0, a vertical shape can be obtained without reducing the line width.

  An example of the entire structure of the etching apparatus for carrying out the present invention will be described with reference to FIG. This etching apparatus is a method called an electron spin resonance (ECR) method, and generates a plasma in a plasma power source 21, an antenna 22 that emits electromagnetic waves into a vacuum chamber, a window 23 that transmits electromagnetic waves, and a wafer 26. A vacuum chamber 24 for etching the wafer, a wafer mounting table 25 for holding the wafer 26, a bias power source 27 for accelerating ions incident on the wafer, and an electromagnetic coil 28 for generating a magnetic field in the chamber 24. Yes.

  The electromagnetic waves emitted from the plasma power source 21 are emitted from the antenna 22 into the vacuum chamber 24 through a window 23 that transmits electromagnetic waves such as quartz. The etching gas is held at a constant pressure in the vacuum chamber 24, and the etching progresses when the gas is turned into plasma by electromagnetic waves and reactive ions are incident on the wafer. A bias power supply 27 for accelerating incident ions is connected to the wafer mounting table 25 that holds the wafer 26.

  In this etching apparatus, a magnetic field is generated in the vacuum chamber 24 by the electromagnetic coil 28. When the magnetic field intensity is set so that the electron spin frequency in the plasma and the frequency of the plasma power source 21 coincide with each other, the electric power is efficiently absorbed into the plasma, and a high plasma density can be maintained at a low pressure. The magnetic field intensity that causes ECR can be set by changing the value of the current flowing through the electromagnetic coil 28. Therefore, an ECR type plasma source is suitable for implementing the present invention requiring a low pressure.

An etching apparatus for carrying out the present invention includes:
In addition to the above, other etching apparatuses such as an inductively coupled (ICP) plasma apparatus, a plasma apparatus using helicon waves, and a parallel plate type plasma apparatus can also be used.

Through the above embodiments, the HfSiON layer is used as the insulating film 12 provided under the first conductor film 14 and the second conductor film 13. However, the insulating film 12 is not limited to this, and HfO ₂ , HfON or An insulating film containing an oxide or nitride of Zr, Gd, La, Pr, Al, such as ZrO ₂ or ZrSiON can be used.

  Further, although the example in which the first conductor film is W has been described, a metal of Ti, Ta, or Mo, or a silicide or nitride of these metals can be used as the first conductor film. In the above description, the second conductor film 13 is an example of TaSiN or TiN. However, the second conductor film 13 is an on-state of a semiconductor element containing Mo or Re in addition to Ti or Ta. Any conductive film that controls the threshold value of the off-operation voltage may be used. The layer structure may be a multilayer structure such as W / TiN / TaSiN / HfSiON. Further, the present invention can be similarly applied even when the mask / cap structure is a so-called multilayer resist including an amorphous carbon layer.

In the present invention, a metal gate material is used as an etching gas, and a gas containing at least one of SF ₆ , NF ₃ , CF ₄ , and CHF ₃ , or a gas containing a mixture of Cl ₂ , N ₂ , O ₂ , and a rare gas is used. be able to. Further, the pressure of the etching gas for the metal gate material is 3 Pa or less, the wafer temperature is 0 ° C. to 50 ° C., the high frequency power applied to the wafer is 50 W or less, and the side etch rate and the vertical etch rate are balanced. The metal gate is processed almost vertically.

  As described above, the present invention insulates under the metal gates 13 and 14 having a structure including the first conductor film 14 and the second conductor film 13 provided under the first conductor film 14. In the processing method of the semiconductor element in which the film 12 is formed, the first conductor film 14 is a conductor film that forms a reaction product having a high vapor pressure by reaction with F, and the second conductor film 13 is A conductive film for controlling a threshold voltage of an on / off operation voltage of a semiconductor element provided under the first conductive film; the insulating film is made of a material constituting the metal gate by a reaction with F; And the metal film after etching the first conductor film 14 and the second conductor film 13 in plasma of an etching gas containing at least F. Over-etching gate material 13 By Rukoto, characterized by side-etching the layers 13 and 14 of the metal gate material on the insulating film 12 at equal horizontal line width.

  According to the present invention, in the semiconductor element processing method, the first conductor film 14 is a metal of any of W, Ti, Ta, and Mo, or a silicide or nitride of these metals, and the second conductor film Reference numeral 13 denotes a conductor containing Ti or Ta, and the main component of the insulating film 12 is an oxide or nitride of Hf, Zr, Gd, La, Pr, Al.

According to the present invention, in the semiconductor element processing method, the etching gas containing F for etching the metal gate materials 14 and 13 includes a gas containing at least one of SF ₆ , NF ₃ , CF ₄ , and CHF ₃ , or Cl ₂ , N ₂ , O ₂ , a rare gas mixed gas, the pressure of the etching gas is 3 Pa or less, the semiconductor temperature is 0 ° C. to 50 ° C., the high frequency power applied to the semiconductor is 50 W or less, While adjusting the amount of F to balance the etching rate in the horizontal direction and the etching rate in the vertical direction, each layer of the metal gate material on the insulating film is side-etched with a line width equal to the horizontal direction and the metal gate is almost vertical. It is characterized by processing.

Sectional drawing explaining the metal gate structure and processing process concerning Example 1 of this invention. Sectional drawing explaining the metal gate structure and processing process concerning Example 2 of this invention. Graph illustrating the relationship between flow rate and side etching rate of SF ₆ in such W etched in Embodiment 2 of the present invention. Graph it is illustrating the relationship between flow rate and side etching rate of Cl ₂ in the W etch according to the second embodiment of the present invention. Diagram for explaining the flow and side etching speed relationship of N ₂ in the W etch according to the second embodiment of the present invention. Diagram for explaining the flow and side etching speed relationship of O ₂ in the W etch according to the second embodiment of the present invention. The figure explaining an example of the structure of the etching apparatus for implementing this invention. Sectional drawing explaining the metal gate structure and processing process in the conventional processing method.

Explanation of symbols

11: Si substrate, 12: HfSiON layer, 120: SiO ₂ layer, 13: TiN layer / TaSiN layer, 14: W layer, 15: SiN layer, 16: antireflection film (BARC), 17: resist, 21: plasma Power supply, 22: Antenna, 23: Window, 24: Vacuum chamber, 25: Wafer mounting table, 26: Wafer, 27: Bias power supply, 28: Electromagnetic coil

Claims (3)

In a processing method of a semiconductor element in which an insulating film is formed under a metal gate having a structure including a first conductor film and a second conductor film provided under the first conductor film,
The first conductor film is a conductor film that forms a reaction product having a high vapor pressure by reaction with F (fluorine),
The second conductor film is a conductor film that controls a threshold value of an on / off operation voltage of a semiconductor element provided under the first conductor film,
The insulating film is an insulating film that forms a reaction product having a lower vapor pressure than the material constituting the metal gate by reaction with F;
Each layer of the metal gate material on the insulating film is etched by etching the first conductor film and the second conductor film in an etching gas plasma containing at least F and then over-etching the metal gate material. A method for processing a semiconductor device, characterized in that side etching is performed with a line width equal to the horizontal direction. The semiconductor device processing method according to claim 1,
The first conductor film is a metal of W, Ti, Ta, or Mo, or a silicide or nitride of these metals,
The second conductor film is a conductor containing Ti or Ta;
A semiconductor element processing method, wherein the insulating film main component is an oxide or nitride of Hf, Zr, Gd, La, Pr, Al. The semiconductor device processing method according to claim 1,
A gas containing at least one of SF ₆ , NF ₃ , CF ₄ , and CHF ₃ as an etching gas containing F for etching the metal gate material, or a gas in which Cl ₂ , N ₂ , O ₂ , and a rare gas are mixed And
The pressure of the etching gas is 3 Pa or less,
The semiconductor temperature is 0 ° C. to 50 ° C.,
The high frequency power applied to the semiconductor is 50 W or less,
While adjusting the amount of F to balance the etching rate in the horizontal direction and the etching rate in the vertical direction, each layer of the metal gate material on the insulating film is side-etched with a line width equal to the horizontal direction and the metal gate is almost A method of processing a semiconductor device, characterized by processing vertically.

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