JP2009054878A - Method of manufacturing integrated circuit, and integrated circuit using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem in which white turbidity arises in an aluminum film formed on a silicon oxide film by high-temperature aluminum sputter method. <P>SOLUTION: Sputter etching using an argon ion is performed toward a silicon oxide film 44. Minute unevenness with the front surface of the silicon oxide film 44 produced in preceding etch-back treatment is smoothed. Then, an aluminum film is deposited on the front surface of the silicon oxide film 44 by the high-temperature aluminum sputter method. Therefore, the white turbidity of the Al film is controlled and the reflection factor of an alignment mark formed thereby is assured. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an integrated circuit manufacturing method and an integrated circuit manufactured using the integrated circuit manufacturing method, and more particularly to a manufacturing method for depositing an aluminum film on a silicon oxide film by high-temperature aluminum sputtering.

  In an integrated circuit formed using a silicon substrate or the like, it is necessary to miniaturize the dimensions of wirings and contacts as the degree of integration increases. As a structure effective for miniaturization, a tungsten plug in which tungsten (W) is buried in a contact hole as a contact material is known.

  FIG. 5 is a cross-sectional view of major steps of a conventional manufacturing method of an integrated circuit having a tungsten plug. After a contact hole 6 is formed in the silicon oxide film 4 laminated on the silicon substrate 2, a tungsten film 8 is deposited on the upper surface of the silicon oxide film 4 and the contact hole 6 (FIG. 5A). The tungsten film 8 deposited on the upper surface of the silicon oxide film 4 is removed by an etch back process, and the tungsten film 8 is selectively left in the contact hole 6. As a result, the tungsten plug 10 embedded in the contact hole 6 is formed (FIG. 5B).

  Thereafter, an aluminum (Al) film 12 is deposited on the upper surface of the silicon oxide film 4 and the tungsten plug 10 (FIG. 5C), and the Al film 12 is patterned to connect the wiring 14 connected to the tungsten plug 10, An alignment mark 16 or the like necessary for the subsequent manufacturing process is formed (FIG. 5D). The alignment mark 16 formed of an Al film has a high reflectance with respect to light, and an alignment apparatus recognizes the shape and position of the alignment mark 16 based on the reflected light image of the alignment mark 16 and performs alignment.

Here, in order to improve the coverage of the aluminum wiring in the contact hole or the like, a high temperature aluminum sputtering method is used. In this high-temperature aluminum sputtering method, when performing sputtering to deposit the lowermost Al film, the substrate temperature is set to a high temperature of 500 ° C. or more, thereby promoting the movement of sputtered Al particles on the substrate. Is improved.
Japanese Patent Laid-Open No. 6-252024

  When an Al film is deposited on the surface of a silicon oxide film by a high temperature aluminum sputtering method, there is a problem that the gloss of the Al film surface is lowered and becomes cloudy. This white turbidity is a state in which the surface of the Al film is rough and scatters and reflects light, and is considered to be caused by the Al film taking over minute roughness (unevenness) on the surface of the underlying silicon oxide film. In addition, in the high temperature aluminum sputtering method, the grain size of aluminum is increased as compared with normal aluminum sputtering performed at a relatively low substrate temperature. Therefore, it is considered that the Al film formed by the high-temperature aluminum sputtering method is difficult to flatten the unevenness of the underlying silicon oxide film, and the surface thereof is easily affected by the unevenness of the silicon oxide film.

  Incidentally, the roughness of the surface of the silicon oxide film can be caused by, for example, an etch back process for removing the tungsten film 8 from the upper surface of the silicon oxide film 4. In particular, when there is a variation in the film thickness of the tungsten film 8 in the wafer, the thinner the silicon oxide film 4 is, the more easily exposed to the etch-back process, and the Al film reflectance varies within the wafer. Can occur.

  The decrease in the reflectance of the alignment mark 16 due to the white turbidity of the Al film lowers the contrast between the alignment mark 16 and its surroundings, making it difficult to detect the alignment mark 16 and making the alignment impossible or the alignment accuracy lowering. was there.

  The present invention has been made to solve the above problems, and provides a method for manufacturing an integrated circuit that suppresses white turbidity of an Al film by high-temperature aluminum sputtering and realizes a uniform gloss in a wafer. The purpose is to provide.

  An integrated circuit manufacturing method according to the present invention includes a smoothing step of smoothing surface roughness of the silicon oxide film by irradiating gas ions toward a silicon oxide film formed on a substrate, and the smoothing And a step of depositing an aluminum film on the surface of the silicon oxide film by a high temperature aluminum sputtering method after the process.

  According to the present invention, the roughness of the silicon oxide film surface is smoothed by irradiation with gas ions. By depositing an Al film by a high-temperature aluminum sputtering method on the surface smoothed by irradiation with gas ions, white turbidity of the Al film is suppressed.

  Hereinafter, embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings. This embodiment relates to an integrated circuit formed on a semiconductor substrate, and in particular, the formation of wiring and alignment marks using a first layer Al film formed by high-temperature aluminum sputtering will be described.

  FIG. 1 is a schematic cross-sectional view of the present integrated circuit, showing a cross section perpendicular to the semiconductor substrate. An impurity diffusion layer 42 is formed in the semiconductor substrate 40. In the silicon oxide film 44 laminated on the surface of the semiconductor substrate 40, a contact hole 46 is formed at a position corresponding to the impurity diffusion layer 42, and a tungsten plug 48 is embedded in the contact hole 46. Also, a first layer of Al film is deposited on the surface of the silicon oxide film 44, and an Al wiring 50 connected to the tungsten plug 48 and an alignment mark 52 are formed using the Al film. The alignment mark 52 is used, for example, as a mark by the chip mounter in an assembly process for attaching the chip on which the integrated circuit is formed to a package or the like. The chip mounter grasps the position of the chip based on the alignment mark 52. And pick up the chip. A laminated structure is further formed on the Al wiring 50 and the alignment mark 52, but the illustration is omitted here.

  2 to 4 are schematic cross-sectional views at main steps of the method of manufacturing the integrated circuit. A silicon oxide film 44 is stacked on the surface of the semiconductor substrate 40. Photoresist (not shown) is applied to the surface of the silicon oxide film 44 and patterned to form an etching mask having an opening at a position where the contact hole 46 is to be formed. Etching is performed using this etching mask to form contact holes 46 in the silicon oxide film 44 (FIG. 2A). The contact hole 46 penetrates the silicon oxide film 44, and the impurity diffusion layer 42 is exposed on the bottom surface.

  After a titanium nitride (TiN) film or the like (not shown) is formed as a barrier layer in the contact hole 46 and on the upper surface of the silicon oxide film 44, a tungsten film 60 is deposited by CVD (Chemical Vapor Deposition). The tungsten film 60 is deposited on the upper surface of the silicon oxide film 44 and also in the contact hole 46, and the contact hole 46 is filled with the tungsten film 60 (FIG. 2B).

  Thereafter, the tungsten film 60 and the like deposited on the upper surface of the silicon oxide film 44 are removed by an etch back process. As a result, a tungsten plug 48 embedded in the contact hole 46 is formed (FIG. 2C).

  Here, the etch back process of the tungsten film 60 and the barrier layer is performed by a method having a selection ratio with respect to the silicon oxide film 44. In this etch back process, an amount of overetching corresponding to the variation in the film thickness and etching rate of the tungsten film 60 in the wafer is performed so that the tungsten film 60 and the like existing on the upper surface of the silicon oxide film 44 are preferably removed. Is done. That is, the portion where the film thickness of the tungsten film 60 is thin is exposed to the etching process even after the silicon oxide film 44 is exposed. Then, minute irregularities may be formed on the surface of the silicon oxide film 44 exposed to the etching. The irregularities are so small that they cannot be represented in FIG. FIG. 3 is a cross-sectional view schematically showing the minute unevenness, and FIG. 3A shows the state of the unevenness 70 on the surface of the silicon oxide film 44 after the etch-back process of the tungsten film 60. FIG. is there.

  In the manufacturing method of the present invention, sputter etching is performed by irradiating argon ions toward the surface of the silicon oxide film 44 (FIGS. 2D and 3B). FIG. 3C shows the state of irregularities 72 on the surface of the silicon oxide film 44 after the sputter etching. By the smoothing by the sputter etching process, the unevenness 72 after the treatment is relaxed compared to the unevenness 70 before the treatment. That is, the unevenness 72 is rounded and rounded as compared with the unevenness 70, and the height difference of the undulation is reduced.

  A first layer Al film 62 is deposited on the surface of the silicon oxide film 44 whose unevenness is relaxed by high temperature aluminum sputtering (FIG. 4A). Corresponding to the relief of the unevenness of the silicon oxide film 44, the unevenness on the surface of the Al film 62 is also relaxed, and the occurrence of white turbidity can be suppressed.

  The Al film 62 is patterned by a photolithography technique to form the first Al wiring 50 and the alignment mark 52 connected to the tungsten plug 48 (FIG. 4B). As described above, the alignment mark 52 formed using the Al film 62 in which white turbidity is suppressed has a high reflectance and a contrast with the surrounding area is ensured, so that the detection is easy and the accuracy is high. Alignment is possible.

  Incidentally, the above-described over-etching on the tungsten film 60 may cause a step 30 between the silicon oxide film 44 outside the contact hole 46 and the upper surface of the tungsten plug 48 inside. The above-described sputter etching of argon ions has a larger etching rate with respect to the silicon oxide film than tungsten, and has an effect of cutting off corners. Therefore, the step 30 is smoothed, the flatness of the inner and outer surfaces of the contact hole 46 is improved, and the coverage of the Al wiring 50 laminated thereon is also improved.

  Note that the sputter etching may be performed using other gas ions capable of smoothing minute irregularities on the surface of the silicon oxide film 44.

1 is a schematic vertical sectional view of an integrated circuit according to an embodiment of the present invention. It is typical sectional drawing in the main processes of the manufacturing method which is embodiment of this invention about the integrated circuit shown in FIG. It is typical sectional drawing in the process regarding the surface treatment of the silicon oxide film in the manufacturing method of embodiment of this invention. It is typical sectional drawing in the main processes of the manufacturing method which is embodiment of this invention about the integrated circuit shown in FIG. It is sectional drawing in the main processes of the conventional manufacturing method.

Explanation of symbols

  40 semiconductor substrate, 42 impurity diffusion layer, 44 silicon oxide film, 46 contact hole, 48 tungsten plug, 50 Al wiring, 52 alignment mark, 60 tungsten film, 62 Al film, 70, 72 unevenness.

Claims (3)

A smoothing step of smoothing the surface roughness of the silicon oxide film by irradiating gas ions toward the silicon oxide film formed on the substrate;
After the smoothing step, depositing an aluminum film on the surface of the silicon oxide film by a high temperature aluminum sputtering method;
An integrated circuit manufacturing method comprising: In the manufacturing method of the integrated circuit of Claim 1,
The method of manufacturing an integrated circuit, wherein the smoothing step includes sputter etching using argon ions. An integrated circuit manufactured using the manufacturing method according to claim 1 or 2,
An integrated circuit comprising an alignment mark formed by patterning the aluminum film and recognized based on reflection of light.

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