JP2009049115A - Semiconductor device, and manufacturing method thereof - Google Patents

Semiconductor device, and manufacturing method thereof Download PDF

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JP2009049115A
JP2009049115A JP2007212651A JP2007212651A JP2009049115A JP 2009049115 A JP2009049115 A JP 2009049115A JP 2007212651 A JP2007212651 A JP 2007212651A JP 2007212651 A JP2007212651 A JP 2007212651A JP 2009049115 A JP2009049115 A JP 2009049115A
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resin
semiconductor chip
semiconductor device
substrate
adhesive
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Toru Fujita
透 藤田
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Seiko Epson Corp
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Seiko Epson Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83909—Post-treatment of the layer connector or bonding area
    • H01L2224/83951—Forming additional members, e.g. for reinforcing, fillet sealant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device structured so as to improve its reliability, and to provide a manufacturing method thereof. <P>SOLUTION: This semiconductor device is equipped with a wiring board 3, a semiconductor chip 1 mounted facedown to the wiring board 3, an adhesive existing between the wiring board 3 and the semiconductor chip 1, and a resin layer 15 in contact with the wiring board 3 and the side face of the semiconductor chip 1, and the concentration of dopant (Cl<SP>-</SP>) contained in the resin layer 15 is not more than 2 mg/L. In such a structure, moisture can be prevented from directly adhering to the adhesive 5, and the amount of the dopant eluting from the resin layer 15 by humidity can be reduced. Thereby, moisture and dopants can be prevented from entering into the inside of the semiconductor device through voids. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof.

図６（ａ）及び（ｂ）は従来例に係る半導体装置９０の構成例を示す断面図と、その一部を拡大した図である。図６（ａ）に示すように、この半導体装置９０はＣＳＰ（Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅ）の一例であり、半導体チップ８１と、配線基板８３と、半導体チップ８１と配線基板８３との間にあるフィルム状の接着剤８５と、配線基板８３の裏面に設けられた複数個の半田ボール８７、とを含んだ構成となっている。半導体チップ８１はその能動面に突起状電極（以下、バンプともいう。）９１を有し、配線基板８３はその表面から裏面にかけて複数の層からなる配線パターン（図示せず）を有する。この半導体装置９０では、半導体チップ８１は配線基板８３にフェースダウンで取り付けられており、半導体チップ８１のバンプ９１は配線基板８３表面の配線パターンに接合されている。このような実装形態は、フリップチップ実装とも呼ばれており、例えば特許文献１に開示されている。
特開２００４−２８１８９９号公報 6A and 6B are a cross-sectional view showing a configuration example of a semiconductor device 90 according to a conventional example, and an enlarged view of a part thereof. As shown in FIG. 6A, the semiconductor device 90 is an example of a CSP (Chip Size Package), and is in the form of a film between the semiconductor chip 81, the wiring substrate 83, and the semiconductor chip 81 and the wiring substrate 83. The adhesive 85 and a plurality of solder balls 87 provided on the back surface of the wiring board 83 are included. The semiconductor chip 81 has a protruding electrode (hereinafter also referred to as a bump) 91 on its active surface, and the wiring substrate 83 has a wiring pattern (not shown) composed of a plurality of layers from the front surface to the back surface. In this semiconductor device 90, the semiconductor chip 81 is attached face-down to the wiring board 83, and the bumps 91 of the semiconductor chip 81 are bonded to the wiring pattern on the surface of the wiring board 83. Such a mounting form is also called flip-chip mounting, and is disclosed in Patent Document 1, for example.
JP 2004-281899 A

ところで、図６（ａ）に示した半導体装置９０を製造する際の、ダイアタッチ工程では、配線基板８３にフィルム状の接着剤８５を配置した後、熱と加重とにより半導体チップ８１を配線基板８３側に押圧する。このとき、接着剤８５は半導体チップ８１下から部分的にはみ出し、このはみ出した部分８５ａからバンプ９１近傍にかけて接着剤８５中に細かなボイド（空隙）ｈが入ってしまうことが多かった。   By the way, in the die attach process when manufacturing the semiconductor device 90 shown in FIG. 6A, after the film-like adhesive 85 is disposed on the wiring board 83, the semiconductor chip 81 is attached to the wiring board by heat and weight. Press to the 83 side. At this time, the adhesive 85 partially protrudes from the bottom of the semiconductor chip 81, and fine voids (voids) h often enter the adhesive 85 from the protruding portion 85 a to the vicinity of the bump 91.

また、図６（ａ）に示すように、接着剤８５のはみ出した部分８５ａは露出しているため、実際の使用環境下ではこの部分８５ａに水分が直接付着する場合がある。ここで、接着剤８５のはみ出した部分８５ａに水分が付着すると、接着剤８５に含まれる不純物が水分と共にボイドｈに入り込み、ボイドｈを伝って半導体装置９０の内部に入り込んでしまうおそれがあった。上記不純物が水分と共にバンプ９１近傍にまで到達すると、半導体チップ８１の腐食を引き起して信頼性を損なうおそれがあった。   Further, as shown in FIG. 6A, since the protruding portion 85a of the adhesive 85 is exposed, moisture may directly adhere to the portion 85a under an actual use environment. Here, if moisture adheres to the protruding portion 85 a of the adhesive 85, impurities contained in the adhesive 85 may enter the void h together with moisture, and may enter the semiconductor device 90 through the void h. . If the impurities reach the vicinity of the bump 91 together with moisture, the semiconductor chip 81 may be corroded to impair reliability.

一方、上記の半導体装置９０では、熱膨張係数の違いなどにより、半導体チップ８１と接着剤８５及び配線基板８３間で応力が発生する。この応力の緩和を目的として、図６（ｂ）に示すように、半導体チップ８１の側面８１ａに沿って樹脂層９５を形成する場合がある。この場合、接着剤８５のはみ出した部分８５ａは樹脂層９５で覆われるので剥き出しとはならず、水分が直接付着することを防ぐことができる。しかしながら、図６（ｂ）では、樹脂層９５中の不純物が湿度により溶け出す場合があり、溶け出した不純物は接着剤８５に到達し、さらに、ボイドｈを伝ってバンプ９１近傍にまで到達するおそれがあった。
そこで、この発明はこのような問題に鑑みてなされたものであって、半導体装置の信頼性を向上できるようにした半導体装置及びその製造方法の提供を目的とする。 On the other hand, in the semiconductor device 90 described above, stress is generated between the semiconductor chip 81, the adhesive 85, and the wiring board 83 due to a difference in thermal expansion coefficient. For the purpose of relaxing the stress, a resin layer 95 may be formed along the side surface 81a of the semiconductor chip 81 as shown in FIG. In this case, the protruding portion 85a of the adhesive 85 is covered with the resin layer 95, so that it is not exposed, and moisture can be prevented from adhering directly. However, in FIG. 6B, the impurities in the resin layer 95 may be dissolved by humidity, and the dissolved impurities reach the adhesive 85 and further reach the vicinity of the bump 91 through the void h. There was a fear.
Accordingly, the present invention has been made in view of such problems, and it is an object of the present invention to provide a semiconductor device and a method for manufacturing the same that can improve the reliability of the semiconductor device.

上記課題を解決するために、発明１の半導体装置は、基板と、第１の面に電極を有する半導体チップであって、前記第１の面が前記基板と対向するように取り付けられた前記半導体チップと、前記基板と前記半導体チップとの間にある第１樹脂と、前記基板と前記半導体チップの側面とに接する第２樹脂と、を備え、前記第２樹脂に含まれる不純物の濃度は２ｍｇ／Ｌ以下であることを特徴とするものである。
ここで、本発明の「第１樹脂」は例えばシート状の接着剤である。「第２樹脂」は例えばエポキシ樹脂であり、当該第２樹脂に含まれる「不純物」は例えば塩素イオン（Ｃｌ-）である。なお、発明１〜４の半導体装置では、第２樹脂は既に硬化後の状態（即ち、固体状態）であり、硬化した状態で不純物濃度が２ｍｇ／Ｌ以下となっている。 In order to solve the above-described problems, a semiconductor device according to a first aspect of the present invention is a semiconductor chip having a substrate and an electrode on a first surface, and the semiconductor is attached so that the first surface faces the substrate. A chip, a first resin between the substrate and the semiconductor chip, and a second resin in contact with the substrate and a side surface of the semiconductor chip, and the concentration of impurities contained in the second resin is 2 mg / L or less.
Here, the “first resin” of the present invention is, for example, a sheet-like adhesive. The “second resin” is, for example, an epoxy resin, and the “impurities” contained in the second resin are, for example, chlorine ions (Cl − ). In the semiconductor devices of the inventions 1 to 4, the second resin is already in a cured state (that is, a solid state), and the impurity concentration is 2 mg / L or less in the cured state.

発明２の半導体装置は、発明１の半導体装置において、前記第１樹脂は前記半導体チップ下からはみ出した部分を有し、当該はみ出した部分を前記第２樹脂が覆っていることを特徴とするものである。
発明３の半導体装置は、発明１又は発明２の半導体装置において、前記半導体チップの側面全体を前記第２樹脂が覆っていることを特徴とするものである。
発明４の半導体装置は、発明１から発明３の何れか一の半導体装置において、前記半導体チップは、前記第１の面とは反対側の第２の面を有し、前記第２樹脂は前記第２の面を覆っていることを特徴とするものである。
発明５の半導体装置は、発明４の半導体装置において、前記第２樹脂は前記第２の面を全て覆っていることを特徴とするものである。 A semiconductor device according to a second aspect of the invention is the semiconductor device according to the first aspect, wherein the first resin has a portion protruding from below the semiconductor chip, and the protruding portion covers the second resin. It is.
A semiconductor device according to a third aspect of the invention is the semiconductor device according to the first or second aspect, wherein the second resin covers the entire side surface of the semiconductor chip.
The semiconductor device according to a fourth aspect is the semiconductor device according to any one of the first to third aspects, wherein the semiconductor chip has a second surface opposite to the first surface, and the second resin is the The second surface is covered.
A semiconductor device according to a fifth aspect of the invention is the semiconductor device according to the fourth aspect of the invention, wherein the second resin covers the entire second surface.

発明６の半導体装置装置は、発明１から発明３の何れか一の半導体装置において、前記不純物は、塩素イオンであることを特徴とするものである。
発明１〜発明６の半導体装置によれば、第１樹脂は、基板と半導体チップとによって断面視で上下方向から挟まれ、且つ、第２樹脂によって側方から封止される。従って、第１樹脂に水分が直接付着することを防ぐことができる。また、第２樹脂に含まれる不純物濃度は２ｍｇ／Ｌ以下であり、湿度により溶け出す不純物量を少なくすることができる。これにより、水分及び不純物がボイドを伝って半導体装置の内部へ入り込むことを防ぐことができ、半導体チップの腐食を防止することができるので、半導体装置の信頼性向上に寄与することができる。 A semiconductor device device of an invention 6 is the semiconductor device according to any one of the inventions 1 to 3, wherein the impurity is a chlorine ion.
According to the semiconductor devices of the inventions 1 to 6, the first resin is sandwiched between the substrate and the semiconductor chip from the top and bottom in the sectional view, and is sealed from the side by the second resin. Therefore, it is possible to prevent moisture from adhering directly to the first resin. Moreover, the impurity concentration contained in 2nd resin is 2 mg / L or less, and the amount of impurities which melt | dissolves with humidity can be decreased. Accordingly, moisture and impurities can be prevented from entering the inside of the semiconductor device through the voids, and corrosion of the semiconductor chip can be prevented, which can contribute to improving the reliability of the semiconductor device.

発明７の半導体装置の製造方法は、第１樹脂を介して、第１の面に電極を有する半導体チップを基板に取り付ける工程であって、前記第１の面が前記基板と対向するように前記半導体チップを前記基板に取り付ける工程と、前記基板と前記半導体チップの側面とに接するように液状の第２樹脂を設ける工程と、前記液状の第２樹脂を硬化させる工程と、を含み、前記液状の第２樹脂を設ける工程では、前記液状の第２樹脂として不純物濃度が２ｍｇ／Ｌ以下の樹脂を使用することを特徴とするものである。   A method of manufacturing a semiconductor device according to a seventh aspect of the present invention is a step of attaching a semiconductor chip having an electrode on a first surface to a substrate via a first resin, wherein the first surface is opposed to the substrate. A step of attaching a semiconductor chip to the substrate; a step of providing a liquid second resin so as to contact the substrate and a side surface of the semiconductor chip; and a step of curing the liquid second resin. In the step of providing the second resin, a resin having an impurity concentration of 2 mg / L or less is used as the liquid second resin.

ここで、発明７の半導体装置の製造方法では、液状の第２樹脂の不純物濃度が２ｍｇ／Ｌ以下となっている。この点は発明１〜６の半導体装置と異なる。即ち、発明１〜６では第２樹脂の固体状態における不純物濃度を２ｍｇ／Ｌ以下に規定しているのに対して、発明７では第２樹脂の液体状態における不純物濃度を２ｍｇ／Ｌ以下に規定している。また、発明７の「液状の第２樹脂」が例えば加熱硬化型の樹脂である場合、「所定処理」は加熱処理である。第２樹脂を硬化させる工程では、加熱処理により液状の第２樹脂に含まれる溶媒成分が揮発するため、液状のときと比べて硬化後では第２樹脂の体積が若干減少することが想定される。従って、液状の第２樹脂の不純物濃度が２ｍｇ／Ｌ以下であっても、硬化後の不純物濃度は２ｍｇ／Ｌを若干上回る可能性がある。   Here, in the manufacturing method of the semiconductor device of the invention 7, the impurity concentration of the liquid second resin is 2 mg / L or less. This point is different from the semiconductor devices of the inventions 1-6. That is, in the inventions 1 to 6, the impurity concentration in the solid state of the second resin is defined as 2 mg / L or less, whereas in the invention 7, the impurity concentration in the liquid state of the second resin is defined as 2 mg / L or less. is doing. Further, when the “liquid second resin” of the invention 7 is, for example, a thermosetting resin, the “predetermined treatment” is a heat treatment. In the step of curing the second resin, the solvent component contained in the liquid second resin volatilizes due to the heat treatment, and therefore it is assumed that the volume of the second resin is slightly reduced after curing compared to the liquid state. . Therefore, even if the impurity concentration of the liquid second resin is 2 mg / L or less, the impurity concentration after curing may slightly exceed 2 mg / L.

発明７の半導体装置の製造方法によれば、第１樹脂に水分が直接付着することを防ぐことができ、また、第２樹脂から溶け出す不純物量を少なくすることができる。従って、水分及び不純物がボイドを伝って半導体装置の内部へ入り込むことを防ぐことができ、半導体チップの腐食を防止することができる。その結果、半導体装置の信頼性向上に寄与することができる。   According to the method for manufacturing a semiconductor device of the seventh aspect, it is possible to prevent moisture from adhering directly to the first resin, and to reduce the amount of impurities that are dissolved from the second resin. Therefore, moisture and impurities can be prevented from entering the inside of the semiconductor device through the void, and corrosion of the semiconductor chip can be prevented. As a result, the reliability of the semiconductor device can be improved.

なお、従来技術では、例えば特許文献１に開示されているように、半導体チップと基板とに挟まれたシート状の接着剤をその側方から樹脂で封止する技術が知られている。しかしながら、従来技術において上記樹脂の不純物濃度は液状で通常５〜６ｍｇ／Ｌであり、これを液状で２ｍｇ／Ｌ以下にわざわざ低減することは今まで行われてこなかった。また、上記樹脂の不純物濃度を液状で２ｍｇ／Ｌ以下にまで低減することのメリットも今まで知られていなかった。   In the prior art, as disclosed in Patent Document 1, for example, a technique is known in which a sheet-like adhesive sandwiched between a semiconductor chip and a substrate is sealed with resin from the side. However, in the prior art, the impurity concentration of the above resin is normally 5 to 6 mg / L in a liquid state, and it has not been performed so far to reduce the impurity concentration to 2 mg / L or less in a liquid state. Moreover, the merit of reducing the impurity concentration of the resin to 2 mg / L or less in a liquid state has not been known so far.

以下、図面を参照しながら、本発明の実施の形態について説明する。
（１）第１実施形態
図１〜図３は本発明の第１実施形態に係る半導体装置１００の製造方法を示す工程図であり、図１（ａ）〜（ｅ）は断面図、図２（ａ）は平面図、図２（ｂ）は図２（ａ）をＸ２−Ｘ´２に沿って切断した断面図、図３（ａ）は平面図、図３（ｂ）は図３（ａ）をＸ３−Ｘ´３に沿って切断した断面図である。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(1) First Embodiment FIGS. 1 to 3 are process diagrams showing a method for manufacturing a semiconductor device 100 according to a first embodiment of the present invention. FIGS. 1 (a) to 1 (e) are cross-sectional views and FIG. 2. 2A is a plan view, FIG. 2B is a cross-sectional view of FIG. 2A cut along X2-X′2, FIG. 3A is a plan view, and FIG. 3B is FIG. It is sectional drawing which cut | disconnected a) along X3-X'3.

図１（ａ）に示すように、まず始めに、半導体チップ１を用意する。この半導体チップ１はウエーハ工程（前工程）で製造されたものであり、回路素子（図示せず）を有し、半導体チップ１の表面に回路素子と電気的に接続されている電極と、回路素子に繋がり、電極上に設けられた複数のバンプ１１とが形成されている。バンプ１１は半導体チップ１の表面に露出しており、例えば金（Ａｕ）からなる。なお、半導体チップ１の表面には、バンプ１１を避けてパッシベーション膜（図示せず）も形成されている。   As shown in FIG. 1A, first, a semiconductor chip 1 is prepared. The semiconductor chip 1 is manufactured in a wafer process (pre-process), has a circuit element (not shown), and is electrically connected to the circuit element on the surface of the semiconductor chip 1 and a circuit. A plurality of bumps 11 connected to the element and provided on the electrode are formed. The bumps 11 are exposed on the surface of the semiconductor chip 1 and are made of, for example, gold (Au). A passivation film (not shown) is also formed on the surface of the semiconductor chip 1 so as to avoid the bumps 11.

次に、図１（ｂ）に示すように、配線基板３を用意する。この配線基板３は例えばインターポーザであり、その表面から裏面にかけて複数の層からなる配線パターン（図示せず）を有する。これら各層の配線パターンは例えばスルーホールによって互いに電気的に接続されている。なお、この配線基板３は、有機系（例えばポリイミド樹脂、エポキシ樹脂）又は無機系（例えばセラミック、ガラス）のいずれの材料であっても良く、これらの複合構造からなるものであっても良い。   Next, as shown in FIG. 1B, a wiring board 3 is prepared. The wiring board 3 is an interposer, for example, and has a wiring pattern (not shown) composed of a plurality of layers from the front surface to the back surface. The wiring patterns of these layers are electrically connected to each other by, for example, through holes. The wiring board 3 may be either organic (for example, polyimide resin, epoxy resin) or inorganic (for example, ceramic or glass) material, or may have a composite structure thereof.

次に、図１（ｂ）に示すように、配線基板３表面の、半導体チップ１が取り付けられる領域（以下、チップ取付け領域ともいう。）にフィルム状の接着剤５を貼り付ける。この接着剤５は、例えばＡＣＦ（Ａｎｉｓｏｔｒｏｐｉｃ Ｃｏｎｄｕｃｔｉｖｅ Ｆｉｌｍ：異方性導電フィルム）又はＮＣＦ（Ｎｏｎ Ｃｏｎｄｕｃｔｉｖｅ Ｆｉｌｍ）である。ＡＣＦは、例えば熱硬化性のエポキシ樹脂に導電性の粒子を分散させた樹脂である。   Next, as shown in FIG. 1B, a film-like adhesive 5 is affixed to an area (hereinafter also referred to as a chip attachment area) where the semiconductor chip 1 is attached on the surface of the wiring substrate 3. The adhesive 5 is, for example, ACF (Anisotropic Conductive Film) or NCF (Non Conductive Film). ACF is, for example, a resin in which conductive particles are dispersed in a thermosetting epoxy resin.

次に、図１（ｃ）に示すように、電極が設けられた面若しくはバンプ１１が設けられた面が配線基板３と対向するように、半導体チップ１を配線基板３に取り付ける（ダイアタッチ工程）。ここでは、ボンディングツール（図示しない）を用いて半導体チップ１の表面を配線基板３の表面に押し当てると共に、これら半導体チップ１と配線基板３との間にあるフィルム状の接着剤５を所定の温度に加熱する。これにより、半導体チップ１の表面と配線基板３の表面とが接着し、半導体チップ１が有するバンプ１１と、配線基板３が有する配線パターンとが接合される。   Next, as shown in FIG. 1C, the semiconductor chip 1 is attached to the wiring substrate 3 so that the surface provided with the electrodes or the surface provided with the bumps 11 faces the wiring substrate 3 (die attach step). ). Here, the surface of the semiconductor chip 1 is pressed against the surface of the wiring board 3 using a bonding tool (not shown), and a film-like adhesive 5 between the semiconductor chip 1 and the wiring board 3 is applied in a predetermined manner. Heat to temperature. Thereby, the surface of the semiconductor chip 1 and the surface of the wiring substrate 3 are bonded, and the bumps 11 included in the semiconductor chip 1 and the wiring pattern included in the wiring substrate 3 are bonded.

なお、ダイアタッチ工程では、加熱により接着剤５は流動性が高くなっているので、接着剤５の一部が半導体チップ１下からはみ出す場合がある。以後、この接着剤５の半導体チップ１下からはみ出した部分を、はみ出し部分５ａとも呼ぶ。また、ダイアタッチ後は、半導体チップ１の裏面（即ち、能動面とは反対側の面）に製品の名称や番号、商標等をレーザ又はインクジェットプリントで記しても良い。   In the die attach process, since the fluidity of the adhesive 5 is increased by heating, a part of the adhesive 5 may protrude from the bottom of the semiconductor chip 1 in some cases. Hereinafter, the portion of the adhesive 5 that protrudes from under the semiconductor chip 1 is also referred to as a protruding portion 5a. In addition, after the die attach, the name, number, trademark, etc. of the product may be written on the back surface of the semiconductor chip 1 (that is, the surface opposite to the active surface) by laser or ink jet printing.

次に、図１（ｄ）に示すように、配線基板３の裏面に半田ボール７を取り付ける。これら半田ボール７は外部（例えば、半導体装置１００が取り付けられるマザーボード）との電気的コンタクトをとるための球状端子である。この取付け工程では、例えば、配線基板３裏面の所定位置に半田ボール７を搭載し、リフロー炉等で半田ボール７を加熱溶融することによって、半田ボール７を配線基板３が有する配線パターンに接合する。   Next, as shown in FIG. 1D, solder balls 7 are attached to the back surface of the wiring board 3. These solder balls 7 are spherical terminals for making electrical contact with the outside (for example, a mother board to which the semiconductor device 100 is attached). In this attachment process, for example, the solder balls 7 are mounted at predetermined positions on the back surface of the wiring board 3 and the solder balls 7 are heated and melted in a reflow furnace or the like, thereby joining the solder balls 7 to the wiring pattern of the wiring board 3. .

次に、図１（ｅ）に示すように、半田ボール７が形成された側にシート９を貼付し、この状態で配線基板３をダイシングして半導体装置１００を個片化する（ダイシング工程）。このダイシング工程では、シート９を切らないように配線基板３のみをダイシングする。その後、個片化されたシート９から半導体装置１００を剥がす。シート９に塗布されている接着剤５が例えば紫外線硬化型の場合、シート９に紫外線を照射することでその接着力を無くすことができ、シート９から個々の半導体装置１００を無理なく剥がすことができる。
図２（ａ）及び（ｂ）は、シートから半導体装置１００を剥離した後の図である。図２（ａ）及び（ｂ）に示すように、半導体チップ１と配線基板３との間にはフィルム状の接着剤５が存在し、この接着剤５の半導体チップ１下からはみ出した部分５ａは露出した状態となっている。 Next, as shown in FIG. 1E, a sheet 9 is affixed to the side on which the solder balls 7 are formed, and in this state, the wiring substrate 3 is diced to separate the semiconductor device 100 (dicing step). . In this dicing process, only the wiring substrate 3 is diced so as not to cut the sheet 9. Thereafter, the semiconductor device 100 is peeled off from the separated sheet 9. In the case where the adhesive 5 applied to the sheet 9 is, for example, an ultraviolet curable type, the adhesive force can be eliminated by irradiating the sheet 9 with ultraviolet rays, and the individual semiconductor devices 100 can be removed from the sheet 9 without difficulty. it can.
2A and 2B are views after the semiconductor device 100 is peeled from the sheet. As shown in FIGS. 2A and 2B, a film-like adhesive 5 exists between the semiconductor chip 1 and the wiring board 3, and a portion 5 a of the adhesive 5 protruding from the bottom of the semiconductor chip 1. Is exposed.

次に、図３（ａ）及び（ｂ）において、例えばディスペンスノズル１３から配線基板３の表面に向けて液状の樹脂１５´を吐出し、これを半導体チップ１の側面１ａと配線基板３の表面とに接するように、半導体チップ１の側面に沿って配線基板３上に塗布する。この液状の樹脂１５´は例えば加熱硬化型のエポキシ樹脂である。また、液状の樹脂１５´には不純物濃度が２ｍｇ／Ｌ以下の樹脂を使用する。不純物とは、例えば塩素イオン（Ｃｌ-）である。 Next, in FIGS. 3A and 3B, for example, a liquid resin 15 ′ is discharged from the dispensing nozzle 13 toward the surface of the wiring substrate 3, and this is discharged to the side surface 1 a of the semiconductor chip 1 and the surface of the wiring substrate 3. It is applied on the wiring substrate 3 along the side surface of the semiconductor chip 1 so as to be in contact with the semiconductor chip 1. This liquid resin 15 'is, for example, a heat-curing type epoxy resin. Further, a resin having an impurity concentration of 2 mg / L or less is used for the liquid resin 15 ′. The impurity is, for example, chlorine ion (Cl − ).

次に、例えば、半導体チップ１を含む配線基板３全体に加熱処理を施して、液状の樹脂１５´を硬化させる。これにより、図３（ａ）及び（ｂ）に示すように、配線基板３と半導体チップ１の側面１ａとに接し、且つ、接着剤５の半導体チップ１下からはみ出している部分５ａを隙間なく覆う形状の樹脂層１５を形成する。ここでは、ディスペンスノズル１３から吐出する樹脂１５´の不純物濃度が２ｍｇ／Ｌ以下であるため、硬化後の樹脂層１５の不純物濃度も２ｍｇ／Ｌ以下、若しくは２ｍｇ／Ｌを若干上回る程度となる。また、硬化後の樹脂層１５は耐熱性を有する。なお、側面１ａは、半導体チップ１の、基板と対向する面と、基板と対向する面とは反対側の面と、を繋ぐ面といっても良い。   Next, for example, the entire wiring substrate 3 including the semiconductor chip 1 is subjected to heat treatment to cure the liquid resin 15 ′. As a result, as shown in FIGS. 3A and 3B, the portion 5 a that is in contact with the wiring substrate 3 and the side surface 1 a of the semiconductor chip 1 and protrudes from the bottom of the semiconductor chip 1 of the adhesive 5 is left without a gap. A covering resin layer 15 is formed. Here, since the impurity concentration of the resin 15 ′ discharged from the dispense nozzle 13 is 2 mg / L or less, the impurity concentration of the cured resin layer 15 is also 2 mg / L or less, or slightly higher than 2 mg / L. Further, the cured resin layer 15 has heat resistance. Note that the side surface 1a may be referred to as a surface connecting the surface of the semiconductor chip 1 facing the substrate and the surface opposite to the surface facing the substrate.

このように、本発明の第１実施形態によれば、図３（ａ）及び（ｂ）に示すように、シート状の接着剤５は、配線基板３と半導体チップ１とによって断面視で上下方向から挟まれ、且つ、樹脂層５１によって側方から封止される。従って、シート状の接着剤５に水分が直接付着することを防ぐことができる。また、ディスペンスノズル１３から吐出される液状の樹脂１５´の不純物濃度は２ｍｇ／Ｌ以下と極めて低濃度であるため、湿度により樹脂層１５から溶け出す不純物量を少なくすることができる。これにより、水分及び不純物が接着剤５中のボイドを伝って半導体装置１００の内部へ入り込むことを防ぐことができ、半導体チップ１の腐食を防止することができるので、半導体装置１００の信頼性を高めることができる。   As described above, according to the first embodiment of the present invention, as shown in FIGS. 3A and 3B, the sheet-like adhesive 5 is vertically moved by the wiring substrate 3 and the semiconductor chip 1 in the sectional view. It is sandwiched from the direction and sealed from the side by the resin layer 51. Therefore, it is possible to prevent moisture from adhering directly to the sheet-like adhesive 5. Further, since the impurity concentration of the liquid resin 15 ′ discharged from the dispense nozzle 13 is as low as 2 mg / L or less, the amount of impurities that are dissolved from the resin layer 15 by humidity can be reduced. As a result, moisture and impurities can be prevented from entering the inside of the semiconductor device 100 through the voids in the adhesive 5, and corrosion of the semiconductor chip 1 can be prevented, so that the reliability of the semiconductor device 100 can be improved. Can be increased.

この第１実施形態では、配線基板３が本発明の「基板」に対応し、フィルム状の接着剤５が本発明の「第１樹脂」に対応している。また、樹脂１５´が本発明の「液状の第２樹脂」に対応し、樹脂層１５が本発明の「（硬化後の）第２樹脂」に対応している。
なお、上記の第１実施形態では、配線基板３をダイシングした後で液状の樹脂１５´を塗布する場合について説明した。しかしながら、樹脂１５´の塗布はダイシング後に限られることはなく、ダイアタッチ以降の工程であれば、どの工程で実施しても良い。また、樹脂１５´の塗布はディスペンスに限らず、真空モールド等、別の方法を用いても良い。ここで、真空モールドとは、例えば、半導体チップ１を含む配線基板３の表面側にキャビティを被せてその内側を減圧し、減圧されたキャビティ内に樹脂１５´を供給する方法のことである。 In the first embodiment, the wiring board 3 corresponds to the “board” of the present invention, and the film adhesive 5 corresponds to the “first resin” of the present invention. The resin 15 ′ corresponds to the “liquid second resin” of the present invention, and the resin layer 15 corresponds to the “(second cured) second resin” of the present invention.
In the first embodiment, the case where the liquid resin 15 ′ is applied after the wiring substrate 3 is diced has been described. However, the application of the resin 15 'is not limited to the process after dicing, and any process may be performed as long as it is a process after die attachment. Further, the application of the resin 15 'is not limited to dispensing, and another method such as vacuum molding may be used. Here, the vacuum mold is, for example, a method in which a cavity is placed on the surface side of the wiring substrate 3 including the semiconductor chip 1 and the inside thereof is decompressed, and the resin 15 ′ is supplied into the decompressed cavity.

（２）その他の実施形態
上記の第１実施形態では、シート状の接着剤５を側方から封止するために、樹脂層１５を半導体チップ１の側面に沿って形成する場合について説明したが、本発明の封止はこれに限られるものではない。この点について、図４及び図５を参照しながら説明する。
図４（ａ）及び（ｂ）は、本発明の第２、第３実施形態に係る半導体装置１００の構成例を示す断面図である。図４（ａ）及び（ｂ）において、図１〜図３と同一の構成及び同一の機能を有する部分には同一の符号を付し、その詳細な説明は省略する。 (2) Other Embodiments In the first embodiment described above, the case where the resin layer 15 is formed along the side surface of the semiconductor chip 1 in order to seal the sheet-like adhesive 5 from the side has been described. The sealing of the present invention is not limited to this. This point will be described with reference to FIGS.
4A and 4B are cross-sectional views showing a configuration example of the semiconductor device 100 according to the second and third embodiments of the present invention. 4A and 4B, parts having the same configuration and the same function as those in FIGS. 1 to 3 are denoted by the same reference numerals, and detailed description thereof is omitted.

例えば、図４（ａ）に示すように、半導体チップ１の裏面（基板と対向する面とは反対側の面）を覆うように樹脂層２５を形成しても良い。このとき、樹脂層２５は、半導体チップ１の裏面全てを覆うように形成しても良い。さらに、図４（ｂ）に示すように、半導体チップ１の側面１ａを完全に覆うと共に、半導体チップ１の裏面を完全に露出するように樹脂層３５を形成しても良い。特に、図４（ｂ）に示すような樹脂層３５を形成する場合は、アンダーフィル剤のような流動性の高い樹脂を使用することで樹脂層３５を効率良く形成することが可能である。   For example, as shown in FIG. 4A, the resin layer 25 may be formed so as to cover the back surface of the semiconductor chip 1 (the surface opposite to the surface facing the substrate). At this time, the resin layer 25 may be formed so as to cover the entire back surface of the semiconductor chip 1. Further, as shown in FIG. 4B, the resin layer 35 may be formed so as to completely cover the side surface 1 a of the semiconductor chip 1 and to completely expose the back surface of the semiconductor chip 1. In particular, when the resin layer 35 as shown in FIG. 4B is formed, the resin layer 35 can be efficiently formed by using a highly fluid resin such as an underfill agent.

アンダーフィル剤を使用して樹脂層３５を形成する場合は、例えば図５（ａ）に示すように、チップ取付け領域を一定距離の余裕を持って囲むことが可能な枠体４１を用意する。この枠体４１は、例えばフッ素樹脂で構成されていることが望ましい。これにより、後の工程で、枠体４１の樹脂層３５からの取り外しが容易となる。次に、図５（ｂ）に示すように、この枠体４１を配線基板３の表面側に被せる。ここでは、枠体４１の中心と、半導体チップ１の中心とが平面視で重なるように、枠体４１の配置を調整しておく。   When the resin layer 35 is formed using an underfill agent, for example, as shown in FIG. 5A, a frame 41 that can surround the chip mounting region with a certain distance is prepared. The frame 41 is preferably made of, for example, a fluororesin. Thereby, the removal from the resin layer 35 of the frame 41 becomes easy at a later step. Next, as shown in FIG. 5B, the frame body 41 is put on the surface side of the wiring board 3. Here, the arrangement of the frame body 41 is adjusted so that the center of the frame body 41 and the center of the semiconductor chip 1 overlap in plan view.

そして、この枠体４１の内側にアンダーフィル剤を塗布する。ここで、アンダーフィル剤は、例えば、一液性加熱硬化型のエポキシ樹脂である。この塗布工程では、気泡の発生を防ぐために空気の抜け道を確保しながらアンダーフィル剤を塗布する。次に、配線基板３上に供給されたアンダーフィル剤を加熱して硬化させる。硬化したアンダーフィル剤が、図４（ｂ）に示した樹脂層３５である。その後、樹脂層３５から枠体４１を取り外す。   Then, an underfill agent is applied to the inside of the frame body 41. Here, the underfill agent is, for example, a one-component thermosetting epoxy resin. In this application step, the underfill agent is applied while ensuring air passage to prevent the generation of bubbles. Next, the underfill agent supplied onto the wiring board 3 is heated and cured. The cured underfill agent is the resin layer 35 shown in FIG. Thereafter, the frame body 41 is removed from the resin layer 35.

この第２、第３実施形態では、不純物濃度が２ｍｇ／Ｌ以下の液状の樹脂又はアンダーフィル剤を使用して、樹脂層２５、３５を形成する。これにより、水分及び不純物がボイドを伝って半導体装置１００の内部へ入り込むことを防ぐことができ、半導体チップ１の腐食を防止することができる。図４（ａ）に示す第２実施形態では樹脂層２５が本発明の「（硬化後の）第２樹脂」に対応し、図４（ｂ）に示す第３実施形態では樹脂層３５が本発明の「（硬化後の）第２樹脂」に対応している。その他の対応関係は図１〜図３に示した第１実施形態と同じである。   In the second and third embodiments, the resin layers 25 and 35 are formed using a liquid resin or an underfill agent having an impurity concentration of 2 mg / L or less. Thereby, moisture and impurities can be prevented from entering the inside of the semiconductor device 100 through the voids, and the corrosion of the semiconductor chip 1 can be prevented. In the second embodiment shown in FIG. 4A, the resin layer 25 corresponds to the “second resin after curing” of the present invention, and in the third embodiment shown in FIG. This corresponds to the “second resin (after curing)” of the invention. The other correspondence is the same as that of the first embodiment shown in FIGS.

（３）実験結果
半導体装置の試験において、「高温高湿バイアス試験」がある。本試験は高温高湿（例：８５℃、８５％湿度）環境において、半導体チップに絶対最大定格の電圧を印加し続けるものである。求められる信頼性の程度により試験条件は異なり、又耐性も異なる。この試験における本発明の優位性を示すデータを表１に記す。 (3) Experimental results A semiconductor device test includes a “high temperature and high humidity bias test”. In this test, the voltage of the absolute maximum rating is continuously applied to the semiconductor chip in a high temperature and high humidity (eg, 85 ° C., 85% humidity) environment. Test conditions vary depending on the degree of reliability required, and resistance varies. Data showing the superiority of the present invention in this test is shown in Table 1.

Figure 2009049115
Figure 2009049115

表１において、「樹脂保護層」とは図１〜図３に示した樹脂層１５のように、半導体チップの側面と配線基板とに接し、シート状の接着剤を側方から封止する樹脂層のことである。また、「Ｃｌ-濃度」は塩素イオン濃度であり、不純物濃度のことである。
また表１において、水準１は樹脂保護層無しのサンプルである。水準２は高不純物濃度の樹脂保護層有りで、樹脂保護層の形成に使用した液状樹脂のＣｌ-濃度が５ｍｇ／Ｌのサンプルである。水準３は低不純物濃度の樹脂保護層有りで、樹脂保護層の形成に使用した液状樹脂のＣｌ-濃度が２ｍｇ／Ｌ以下のサンプルである。このように、水準１はリファレンス、水準２は従来技術、水準３は本発明に係るサンプルである。 In Table 1, the “resin protective layer” is a resin that contacts the side surface of the semiconductor chip and the wiring substrate and seals the sheet-like adhesive from the side, like the resin layer 15 shown in FIGS. It is a layer. The “Cl − concentration” is a chlorine ion concentration, which is an impurity concentration.
In Table 1, Level 1 is a sample without a resin protective layer. Level 2 is a sample having a resin protective layer having a high impurity concentration and a Cl − concentration of 5 mg / L of the liquid resin used for forming the resin protective layer. Level 3 is a sample having a resin protective layer with a low impurity concentration, and the Cl − concentration of the liquid resin used for forming the resin protective layer is 2 mg / L or less. Thus, level 1 is a reference, level 2 is a prior art, and level 3 is a sample according to the present invention.

表１に示すように、実験結果では、水準１では簡単に不良が発生した。また、水準１と比べて、水準２、３では不良の発生数が少なかった。さらに、水準２では不良の発生数はゼロではなかったが、水準３では不良の発生数がゼロだった。
このような実験結果から本発明者は、樹脂保護層に含まれるＣｌ−の濃度（即ち、不純物濃度）の大小によって不良発生率が異なる、ということを見出した。実験結果から、樹脂保護層における不純物濃度は低ければ低いほど優位であると考えられ、液状樹脂における不純物濃度を２ｍｇ／Ｌ以下にすることで、不良発生数を著しく低減することができるということがわかった。
なお、樹脂保護層の不純物濃度は０ｍｇ／Ｌが最も理想的であると考えられるが、有機物である樹脂保護層において不純物濃度０ｍｇ／Ｌを実現することはほぼ不可能である。このような考えから、本発明では不純物濃度の下限を設定せず、上限のみを２ｍｇ／Ｌ以下に設定した。 As shown in Table 1, in the experimental results, defects were easily generated at level 1. In addition, compared with level 1, the number of defects was small at levels 2 and 3. Furthermore, at level 2, the number of defects was not zero, but at level 3, the number of defects was zero.
From such experimental results, the present inventor has found that the defect occurrence rate varies depending on the concentration of Cl − (ie, impurity concentration) contained in the resin protective layer. From the experimental results, it can be considered that the lower the impurity concentration in the resin protective layer is, the more dominant, and the number of defects can be remarkably reduced by setting the impurity concentration in the liquid resin to 2 mg / L or less. all right.
It is considered that the impurity concentration of the resin protective layer is most ideal 0 mg / L, but it is almost impossible to achieve the impurity concentration of 0 mg / L in the organic resin protective layer. From such an idea, the lower limit of the impurity concentration is not set in the present invention, and only the upper limit is set to 2 mg / L or less.

第１実施形態に係る半導体装置１００の製造方法を示す工程図。FIG. 5 is a process diagram illustrating a method for manufacturing the semiconductor device 100 according to the first embodiment. 第１実施形態に係る半導体装置１００の製造方法を示す工程図。FIG. 5 is a process diagram illustrating a method for manufacturing the semiconductor device 100 according to the first embodiment. 第１実施形態に係る半導体装置１００の製造方法を示す工程図。FIG. 5 is a process diagram illustrating a method for manufacturing the semiconductor device 100 according to the first embodiment. 第２、第３実施形態に係る半導体装置１００の構成例を示す図。The figure which shows the structural example of the semiconductor device 100 which concerns on 2nd, 3rd embodiment. 枠体を用いた樹脂層３５の形成方法を示す図。The figure which shows the formation method of the resin layer 35 using a frame. 従来例に係る半導体装置９０の構成例を示す図。The figure which shows the structural example of the semiconductor device 90 which concerns on a prior art example.

符号の説明Explanation of symbols

１ 半導体チップ、３ 配線基板、５ 接着剤、５ａ 接着剤の（半導体チップ下から）はみ出した部分、７ 半田ボール、９ シート、１１ バンプ、１５、２５、３５ （硬化後の）樹脂層、１５´ （液状の）樹脂、４１ 枠体、１００ 半導体装置   DESCRIPTION OF SYMBOLS 1 Semiconductor chip, 3 Wiring board, 5 Adhesive, 5a The part which protruded (from under the semiconductor chip) of the adhesive, 7 Solder ball, 9 Sheet, 11 Bump, 15, 25, 35 Resin layer (after hardening), 15 ′ (Liquid) resin, 41 frame, 100 semiconductor device

Claims (7)

基板と、
第１の面に電極を有する半導体チップであって、前記第１の面が前記基板と対向するように取り付けられた前記半導体チップと、
前記基板と前記半導体チップとの間にある第１樹脂と、
前記基板と前記半導体チップの側面とに接する第２樹脂と、を備え、
前記第２樹脂に含まれる不純物の濃度は２ｍｇ／Ｌ以下であることを特徴とする半導体装置。 A substrate,
A semiconductor chip having an electrode on a first surface, the semiconductor chip attached so that the first surface faces the substrate;
A first resin between the substrate and the semiconductor chip;
A second resin in contact with the substrate and the side surface of the semiconductor chip,
The semiconductor device, wherein the concentration of impurities contained in the second resin is 2 mg / L or less. 前記第１樹脂は前記半導体チップ下からはみ出した部分を有し、当該はみ出した部分を前記第２樹脂が覆っていることを特徴とする請求項１に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the first resin has a portion protruding from below the semiconductor chip, and the second resin covers the protruding portion. 前記半導体チップの側面全体を前記第２樹脂が覆っていることを特徴とする請求項１又は請求項２に記載の半導体装置。   The semiconductor device according to claim 1, wherein the entire side surface of the semiconductor chip is covered with the second resin. 前記半導体チップは、前記第１の面とは反対側の第２の面を有し、
前記第２樹脂は前記第２の面を覆っていることを特徴とする請求項１から請求項３の何れか一項に記載の半導体装置。 The semiconductor chip has a second surface opposite to the first surface,
4. The semiconductor device according to claim 1, wherein the second resin covers the second surface. 5. 前記第２樹脂は前記第２の面を全て覆っていることを特徴とする請求項４に記載の半導体装置。   The semiconductor device according to claim 4, wherein the second resin covers all of the second surface. 前記不純物は、塩素イオンであることを特徴とする請求項１から請求項３の何れか一項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the impurity is a chlorine ion. 第１樹脂を介して、第１の面に電極を有する半導体チップを基板に取り付ける工程であって、前記第１の面が前記基板と対向するように前記半導体チップを前記基板に取り付ける工程と、
前記基板と前記半導体チップの側面とに接するように液状の第２樹脂を設ける工程と、
前記液状の第２樹脂を硬化させる工程と、を含み、
前記液状の第２樹脂を設ける工程では、前記液状の第２樹脂として不純物濃度が２ｍｇ／Ｌ以下の樹脂を使用することを特徴とする半導体装置の製造方法。 A step of attaching a semiconductor chip having an electrode on a first surface to a substrate via a first resin, the step of attaching the semiconductor chip to the substrate such that the first surface faces the substrate;
Providing a liquid second resin in contact with the substrate and the side surface of the semiconductor chip;
Curing the second liquid resin,
In the step of providing the liquid second resin, a semiconductor device manufacturing method using a resin having an impurity concentration of 2 mg / L or less as the liquid second resin.
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